ls1021a-qds.dts (279385) | ls1021a-qds.dts (295436) |
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1/* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * --- 44 unchanged lines hidden (view full) --- 53 54 aliases { 55 enet0_rgmii_phy = &rgmii_phy1; 56 enet1_rgmii_phy = &rgmii_phy2; 57 enet2_rgmii_phy = &rgmii_phy3; 58 enet0_sgmii_phy = &sgmii_phy1c; 59 enet1_sgmii_phy = &sgmii_phy1d; 60 }; | 1/* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * --- 44 unchanged lines hidden (view full) --- 53 54 aliases { 55 enet0_rgmii_phy = &rgmii_phy1; 56 enet1_rgmii_phy = &rgmii_phy2; 57 enet2_rgmii_phy = &rgmii_phy3; 58 enet0_sgmii_phy = &sgmii_phy1c; 59 enet1_sgmii_phy = &sgmii_phy1d; 60 }; |
61 62 sys_mclk: clock-mclk { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <24576000>; 66 }; 67 68 regulators { 69 compatible = "simple-bus"; 70 #address-cells = <1>; 71 #size-cells = <0>; 72 73 reg_3p3v: regulator@0 { 74 compatible = "regulator-fixed"; 75 reg = <0>; 76 regulator-name = "3P3V"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 regulator-always-on; 80 }; 81 }; 82 83 sound { 84 compatible = "simple-audio-card"; 85 simple-audio-card,format = "i2s"; 86 simple-audio-card,widgets = 87 "Microphone", "Microphone Jack", 88 "Headphone", "Headphone Jack", 89 "Speaker", "Speaker Ext", 90 "Line", "Line In Jack"; 91 simple-audio-card,routing = 92 "MIC_IN", "Microphone Jack", 93 "Microphone Jack", "Mic Bias", 94 "LINE_IN", "Line In Jack", 95 "Headphone Jack", "HP_OUT", 96 "Speaker Ext", "LINE_OUT"; 97 98 simple-audio-card,cpu { 99 sound-dai = <&sai2>; 100 frame-master; 101 bitclock-master; 102 }; 103 104 simple-audio-card,codec { 105 sound-dai = <&codec>; 106 frame-master; 107 bitclock-master; 108 }; 109 }; |
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61}; 62 63&dspi0 { 64 bus-num = <0>; 65 status = "okay"; 66 67 dspiflash: at45db021d@0 { 68 #address-cells = <1>; 69 #size-cells = <1>; 70 compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash"; 71 spi-max-frequency = <16000000>; 72 spi-cpol; 73 spi-cpha; 74 reg = <0>; 75 }; 76}; 77 | 110}; 111 112&dspi0 { 113 bus-num = <0>; 114 status = "okay"; 115 116 dspiflash: at45db021d@0 { 117 #address-cells = <1>; 118 #size-cells = <1>; 119 compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash"; 120 spi-max-frequency = <16000000>; 121 spi-cpol; 122 spi-cpha; 123 reg = <0>; 124 }; 125}; 126 |
127&enet0 { 128 tbi-handle = <&tbi0>; 129 phy-handle = <&sgmii_phy1c>; 130 phy-connection-type = "sgmii"; 131 status = "okay"; 132}; 133 134&enet1 { 135 tbi-handle = <&tbi0>; 136 phy-handle = <&sgmii_phy1d>; 137 phy-connection-type = "sgmii"; 138 status = "okay"; 139}; 140 141&enet2 { 142 phy-handle = <&rgmii_phy3>; 143 phy-connection-type = "rgmii-id"; 144 status = "okay"; 145}; 146 |
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78&i2c0 { 79 status = "okay"; 80 81 pca9547: mux@77 { | 147&i2c0 { 148 status = "okay"; 149 150 pca9547: mux@77 { |
151 compatible = "nxp,pca9547"; |
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82 reg = <0x77>; 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 i2c@0 { 87 #address-cells = <1>; 88 #size-cells = <0>; 89 reg = <0x0>; --- 38 unchanged lines hidden (view full) --- 128 reg = <0x57>; 129 }; 130 131 adt7461a@4c { 132 compatible = "adi,adt7461a"; 133 reg = <0x4c>; 134 }; 135 }; | 152 reg = <0x77>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 156 i2c@0 { 157 #address-cells = <1>; 158 #size-cells = <0>; 159 reg = <0x0>; --- 38 unchanged lines hidden (view full) --- 198 reg = <0x57>; 199 }; 200 201 adt7461a@4c { 202 compatible = "adi,adt7461a"; 203 reg = <0x4c>; 204 }; 205 }; |
206 207 i2c@4 { 208 #address-cells = <1>; 209 #size-cells = <0>; 210 reg = <0x4>; 211 212 codec: sgtl5000@2a { 213 #sound-dai-cells = <0>; 214 compatible = "fsl,sgtl5000"; 215 reg = <0x2a>; 216 VDDA-supply = <®_3p3v>; 217 VDDIO-supply = <®_3p3v>; 218 clocks = <&sys_mclk 1>; 219 }; 220 }; |
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136 }; 137}; 138 139&ifc { 140 #address-cells = <2>; 141 #size-cells = <1>; 142 /* NOR, NAND Flashes and FPGA on board */ 143 ranges = <0x0 0x0 0x0 0x60000000 0x08000000 --- 82 unchanged lines hidden (view full) --- 226 227&mdio0 { 228 tbi0: tbi-phy@8 { 229 reg = <0x8>; 230 device_type = "tbi-phy"; 231 }; 232}; 233 | 221 }; 222}; 223 224&ifc { 225 #address-cells = <2>; 226 #size-cells = <1>; 227 /* NOR, NAND Flashes and FPGA on board */ 228 ranges = <0x0 0x0 0x0 0x60000000 0x08000000 --- 82 unchanged lines hidden (view full) --- 311 312&mdio0 { 313 tbi0: tbi-phy@8 { 314 reg = <0x8>; 315 device_type = "tbi-phy"; 316 }; 317}; 318 |
319&sai2 { 320 status = "okay"; 321}; 322 323&sata { 324 status = "okay"; 325}; 326 |
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234&uart0 { 235 status = "okay"; 236}; 237 238&uart1 { 239 status = "okay"; 240}; | 327&uart0 { 328 status = "okay"; 329}; 330 331&uart1 { 332 status = "okay"; 333}; |