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lpc32xx.dtsi (279385) lpc32xx.dtsi (295436)
1/*
2 * NXP LPC32xx SoC
3 *
4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
1/*
2 * NXP LPC32xx SoC
3 *
4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
14#include "skeleton.dtsi"
15
16/ {
17 compatible = "nxp,lpc3220";
18 interrupt-parent = <&mic>;
19
20 cpus {
15
16/ {
17 compatible = "nxp,lpc3220";
18 interrupt-parent = <&mic>;
19
20 cpus {
21 #address-cells = <0>;
21 #address-cells = <1>;
22 #size-cells = <0>;
23
22 #size-cells = <0>;
23
24 cpu {
24 cpu@0 {
25 compatible = "arm,arm926ej-s";
26 device_type = "cpu";
25 compatible = "arm,arm926ej-s";
26 device_type = "cpu";
27 reg = <0x0>;
27 };
28 };
29
30 ahb {
31 #address-cells = <1>;
32 #size-cells = <1>;
33 compatible = "simple-bus";
28 };
29 };
30
31 ahb {
32 #address-cells = <1>;
33 #size-cells = <1>;
34 compatible = "simple-bus";
34 ranges = <0x20000000 0x20000000 0x30000000>;
35 ranges = <0x20000000 0x20000000 0x30000000>,
36 <0xe0000000 0xe0000000 0x04000000>;
35
36 /*
37 * Enable either SLC or MLC
38 */
39 slc: flash@20020000 {
40 compatible = "nxp,lpc3220-slc";
41 reg = <0x20020000 0x1000>;
42 status = "disabled";
43 };
44
45 mlc: flash@200a8000 {
46 compatible = "nxp,lpc3220-mlc";
47 reg = <0x200a8000 0x11000>;
48 interrupts = <11 0>;
49 status = "disabled";
50 };
51
37
38 /*
39 * Enable either SLC or MLC
40 */
41 slc: flash@20020000 {
42 compatible = "nxp,lpc3220-slc";
43 reg = <0x20020000 0x1000>;
44 status = "disabled";
45 };
46
47 mlc: flash@200a8000 {
48 compatible = "nxp,lpc3220-mlc";
49 reg = <0x200a8000 0x11000>;
50 interrupts = <11 0>;
51 status = "disabled";
52 };
53
52 dma@31000000 {
54 dma: dma@31000000 {
53 compatible = "arm,pl080", "arm,primecell";
54 reg = <0x31000000 0x1000>;
55 interrupts = <0x1c 0>;
56 };
57
55 compatible = "arm,pl080", "arm,primecell";
56 reg = <0x31000000 0x1000>;
57 interrupts = <0x1c 0>;
58 };
59
58 /*
59 * Enable either ohci or usbd (gadget)!
60 */
61 ohci@31020000 {
62 compatible = "nxp,ohci-nxp", "usb-ohci";
63 reg = <0x31020000 0x300>;
64 interrupts = <0x3b 0>;
65 status = "disabled";
66 };
60 usb {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 compatible = "simple-bus";
64 ranges = <0x0 0x31020000 0x00001000>;
67
65
68 usbd@31020000 {
69 compatible = "nxp,lpc3220-udc";
70 reg = <0x31020000 0x300>;
71 interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
72 status = "disabled";
66 /*
67 * Enable either ohci or usbd (gadget)!
68 */
69 ohci: ohci@0 {
70 compatible = "nxp,ohci-nxp", "usb-ohci";
71 reg = <0x0 0x300>;
72 interrupts = <0x3b 0>;
73 status = "disabled";
74 };
75
76 usbd: usbd@0 {
77 compatible = "nxp,lpc3220-udc";
78 reg = <0x0 0x300>;
79 interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
80 status = "disabled";
81 };
82
83 i2cusb: i2c@300 {
84 compatible = "nxp,pnx-i2c";
85 reg = <0x300 0x100>;
86 interrupts = <0x3f 0>;
87 #address-cells = <1>;
88 #size-cells = <0>;
89 pnx,timeout = <0x64>;
90 };
73 };
74
91 };
92
75 clcd@31040000 {
93 clcd: clcd@31040000 {
76 compatible = "arm,pl110", "arm,primecell";
77 reg = <0x31040000 0x1000>;
78 interrupts = <0x0e 0>;
79 status = "disabled";
80 };
81
82 mac: ethernet@31060000 {
83 compatible = "nxp,lpc-eth";
84 reg = <0x31060000 0x1000>;
85 interrupts = <0x1d 0>;
86 };
87
94 compatible = "arm,pl110", "arm,primecell";
95 reg = <0x31040000 0x1000>;
96 interrupts = <0x0e 0>;
97 status = "disabled";
98 };
99
100 mac: ethernet@31060000 {
101 compatible = "nxp,lpc-eth";
102 reg = <0x31060000 0x1000>;
103 interrupts = <0x1d 0>;
104 };
105
106 emc: memory-controller@31080000 {
107 compatible = "arm,pl175", "arm,primecell";
108 reg = <0x31080000 0x1000>;
109 #address-cells = <1>;
110 #size-cells = <1>;
111
112 ranges = <0 0xe0000000 0x01000000>,
113 <1 0xe1000000 0x01000000>,
114 <2 0xe2000000 0x01000000>,
115 <3 0xe3000000 0x01000000>;
116 status = "disabled";
117 };
118
88 apb {
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "simple-bus";
92 ranges = <0x20000000 0x20000000 0x30000000>;
93
94 ssp0: ssp@20084000 {
95 compatible = "arm,pl022", "arm,primecell";

--- 17 unchanged lines hidden (view full) ---

113 reg = <0x20090000 0x1000>;
114 };
115
116 i2s0: i2s@20094000 {
117 compatible = "nxp,lpc3220-i2s";
118 reg = <0x20094000 0x1000>;
119 };
120
119 apb {
120 #address-cells = <1>;
121 #size-cells = <1>;
122 compatible = "simple-bus";
123 ranges = <0x20000000 0x20000000 0x30000000>;
124
125 ssp0: ssp@20084000 {
126 compatible = "arm,pl022", "arm,primecell";

--- 17 unchanged lines hidden (view full) ---

144 reg = <0x20090000 0x1000>;
145 };
146
147 i2s0: i2s@20094000 {
148 compatible = "nxp,lpc3220-i2s";
149 reg = <0x20094000 0x1000>;
150 };
151
121 sd@20098000 {
152 sd: sd@20098000 {
122 compatible = "arm,pl18x", "arm,primecell";
123 reg = <0x20098000 0x1000>;
124 interrupts = <0x0f 0>, <0x0d 0>;
125 status = "disabled";
126 };
127
128 i2s1: i2s@2009C000 {
129 compatible = "nxp,lpc3220-i2s";

--- 57 unchanged lines hidden (view full) ---

187 };
188
189 mpwm: mpwm@400E8000 {
190 compatible = "nxp,lpc3220-motor-pwm";
191 reg = <0x400E8000 0x78>;
192 status = "disabled";
193 #pwm-cells = <2>;
194 };
153 compatible = "arm,pl18x", "arm,primecell";
154 reg = <0x20098000 0x1000>;
155 interrupts = <0x0f 0>, <0x0d 0>;
156 status = "disabled";
157 };
158
159 i2s1: i2s@2009C000 {
160 compatible = "nxp,lpc3220-i2s";

--- 57 unchanged lines hidden (view full) ---

218 };
219
220 mpwm: mpwm@400E8000 {
221 compatible = "nxp,lpc3220-motor-pwm";
222 reg = <0x400E8000 0x78>;
223 status = "disabled";
224 #pwm-cells = <2>;
225 };
195
196 i2cusb: i2c@31020300 {
197 compatible = "nxp,pnx-i2c";
198 reg = <0x31020300 0x100>;
199 interrupts = <0x3f 0>;
200 #address-cells = <1>;
201 #size-cells = <0>;
202 pnx,timeout = <0x64>;
203 };
204 };
205
206 fab {
207 #address-cells = <1>;
208 #size-cells = <1>;
209 compatible = "simple-bus";
210 ranges = <0x20000000 0x20000000 0x30000000>;
211

--- 26 unchanged lines hidden (view full) ---

238
239 uart7: serial@4001c000 {
240 compatible = "nxp,lpc3220-hsuart";
241 reg = <0x4001c000 0x1000>;
242 interrupts = <24 0>;
243 status = "disabled";
244 };
245
226 };
227
228 fab {
229 #address-cells = <1>;
230 #size-cells = <1>;
231 compatible = "simple-bus";
232 ranges = <0x20000000 0x20000000 0x30000000>;
233

--- 26 unchanged lines hidden (view full) ---

260
261 uart7: serial@4001c000 {
262 compatible = "nxp,lpc3220-hsuart";
263 reg = <0x4001c000 0x1000>;
264 interrupts = <24 0>;
265 status = "disabled";
266 };
267
246 rtc@40024000 {
268 rtc: rtc@40024000 {
247 compatible = "nxp,lpc3220-rtc";
248 reg = <0x40024000 0x1000>;
249 interrupts = <0x34 0>;
250 };
251
252 gpio: gpio@40028000 {
253 compatible = "nxp,lpc3220-gpio";
254 reg = <0x40028000 0x1000>;
255 gpio-controller;
256 #gpio-cells = <3>; /* bank, pin, flags */
257 };
258
269 compatible = "nxp,lpc3220-rtc";
270 reg = <0x40024000 0x1000>;
271 interrupts = <0x34 0>;
272 };
273
274 gpio: gpio@40028000 {
275 compatible = "nxp,lpc3220-gpio";
276 reg = <0x40028000 0x1000>;
277 gpio-controller;
278 #gpio-cells = <3>; /* bank, pin, flags */
279 };
280
259 watchdog@4003C000 {
281 timer4: timer@4002C000 {
282 compatible = "nxp,lpc3220-timer";
283 reg = <0x4002C000 0x1000>;
284 interrupts = <0x3 0>;
285 status = "disabled";
286 };
287
288 timer5: timer@40030000 {
289 compatible = "nxp,lpc3220-timer";
290 reg = <0x40030000 0x1000>;
291 interrupts = <0x4 0>;
292 status = "disabled";
293 };
294
295 watchdog: watchdog@4003C000 {
260 compatible = "nxp,pnx4008-wdt";
261 reg = <0x4003C000 0x1000>;
262 };
263
296 compatible = "nxp,pnx4008-wdt";
297 reg = <0x4003C000 0x1000>;
298 };
299
300 timer0: timer@40044000 {
301 compatible = "nxp,lpc3220-timer";
302 reg = <0x40044000 0x1000>;
303 interrupts = <0x10 0>;
304 };
305
264 /*
265 * TSC vs. ADC: Since those two share the same
266 * hardware, you need to choose from one of the
267 * following two and do 'status = "okay";' for one of
268 * them
269 */
270
306 /*
307 * TSC vs. ADC: Since those two share the same
308 * hardware, you need to choose from one of the
309 * following two and do 'status = "okay";' for one of
310 * them
311 */
312
271 adc@40048000 {
313 adc: adc@40048000 {
272 compatible = "nxp,lpc3220-adc";
273 reg = <0x40048000 0x1000>;
274 interrupts = <0x27 0>;
275 status = "disabled";
276 };
277
314 compatible = "nxp,lpc3220-adc";
315 reg = <0x40048000 0x1000>;
316 interrupts = <0x27 0>;
317 status = "disabled";
318 };
319
278 tsc@40048000 {
320 tsc: tsc@40048000 {
279 compatible = "nxp,lpc3220-tsc";
280 reg = <0x40048000 0x1000>;
281 interrupts = <0x27 0>;
282 status = "disabled";
283 };
284
321 compatible = "nxp,lpc3220-tsc";
322 reg = <0x40048000 0x1000>;
323 interrupts = <0x27 0>;
324 status = "disabled";
325 };
326
285 key@40050000 {
327 timer1: timer@4004C000 {
328 compatible = "nxp,lpc3220-timer";
329 reg = <0x4004C000 0x1000>;
330 interrupts = <0x11 0>;
331 };
332
333 key: key@40050000 {
286 compatible = "nxp,lpc3220-key";
287 reg = <0x40050000 0x1000>;
288 interrupts = <54 0>;
289 status = "disabled";
290 };
291
334 compatible = "nxp,lpc3220-key";
335 reg = <0x40050000 0x1000>;
336 interrupts = <54 0>;
337 status = "disabled";
338 };
339
292 pwm: pwm@4005C000 {
340 timer2: timer@40058000 {
341 compatible = "nxp,lpc3220-timer";
342 reg = <0x40058000 0x1000>;
343 interrupts = <0x12 0>;
344 status = "disabled";
345 };
346
347 pwm1: pwm@4005C000 {
293 compatible = "nxp,lpc3220-pwm";
348 compatible = "nxp,lpc3220-pwm";
294 reg = <0x4005C000 0x8>;
349 reg = <0x4005C000 0x4>;
295 status = "disabled";
296 };
350 status = "disabled";
351 };
352
353 pwm2: pwm@4005C004 {
354 compatible = "nxp,lpc3220-pwm";
355 reg = <0x4005C004 0x4>;
356 status = "disabled";
357 };
358
359 timer3: timer@40060000 {
360 compatible = "nxp,lpc3220-timer";
361 reg = <0x40060000 0x1000>;
362 interrupts = <0x13 0>;
363 status = "disabled";
364 };
297 };
298 };
299};
365 };
366 };
367};