1/*
2 * Samsung's Exynos4210 SoC device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *

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16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20*/
21
22#include "exynos4.dtsi"
23#include "exynos4210-pinctrl.dtsi"
24
25/ {
26 compatible = "samsung,exynos4210", "samsung,exynos4";
27
28 aliases {
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2;
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu@900 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a9";
41 reg = <0x900>;
42 };
43
44 cpu@901 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a9";
47 reg = <0x901>;
48 };
49 };
50
51 pmu_system_controller: system-controller@10020000 {
52 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
53 "clkout4", "clkout8", "clkout9";
54 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
55 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
56 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
57 <&clock CLK_XUSBXTI>;
58 #clock-cells = <1>;
59 };
60
61 sysram@02020000 {
62 compatible = "mmio-sram";
63 reg = <0x02020000 0x20000>;
64 #address-cells = <1>;
65 #size-cells = <1>;
66 ranges = <0 0x02020000 0x20000>;
67
68 smp-sysram@0 {
69 compatible = "samsung,exynos4210-sysram";

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86 compatible = "arm,pl310-cache";
87 reg = <0x10502000 0x1000>;
88 cache-unified;
89 cache-level = <2>;
90 arm,tag-latency = <2 2 1>;
91 arm,data-latency = <2 2 1>;
92 };
93
94 gic: interrupt-controller@10490000 {
95 cpu-offset = <0x8000>;
96 };
97
98 combiner: interrupt-controller@10440000 {
99 samsung,combiner-nr = <16>;
100 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
101 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
102 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
103 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
104 };
105
106 mct@10050000 {
107 compatible = "samsung,exynos4210-mct";
108 reg = <0x10050000 0x800>;
109 interrupt-parent = <&mct_map>;
110 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
111 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
112 clock-names = "fin_pll", "mct";
113
114 mct_map: mct-map {

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148 };
149 };
150
151 pinctrl_2: pinctrl@03860000 {
152 compatible = "samsung,exynos4210-pinctrl";
153 reg = <0x03860000 0x1000>;
154 };
155
156 tmu@100C0000 {
157 compatible = "samsung,exynos4210-tmu";
158 interrupt-parent = <&combiner>;
159 reg = <0x100C0000 0x100>;
160 interrupts = <2 4>;
161 clocks = <&clock CLK_TMU_APBIF>;
162 clock-names = "tmu_apbif";
163 status = "disabled";
164 };
165
166 g2d@12800000 {
167 compatible = "samsung,s5pv210-g2d";
168 reg = <0x12800000 0x1000>;
169 interrupts = <0 89 0>;
170 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
171 clock-names = "sclk_fimg2d", "fimg2d";
172 status = "disabled";
173 };
174
175 camera {
176 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
177 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
178 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
179
180 fimc_0: fimc@11800000 {

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198 fimc_3: fimc@11830000 {
199 samsung,pix-limits = <1920 8192 1366 1920>;
200 samsung,rotators = <0>;
201 samsung,mainscaler-ext;
202 samsung,lcd-wb;
203 };
204 };
205
206 ppmu_lcd1: ppmu_lcd1@12240000 {
207 compatible = "samsung,exynos-ppmu";
208 reg = <0x12240000 0x2000>;
209 clocks = <&clock CLK_PPMULCD1>;
210 clock-names = "ppmu";
211 status = "disabled";
212 };
213};