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uart_dev_z8530.c (120378) uart_dev_z8530.c (120452)
1/*
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

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20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
1/*
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

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20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_z8530.c 120378 2003-09-23 09:25:38Z nyan $");
28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_z8530.c 120452 2003-09-26 05:14:56Z marcel $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/conf.h>
34#include <machine/bus.h>
35
36#include <dev/uart/uart.h>
37#include <dev/uart/uart_cpu.h>
38#include <dev/uart/uart_bus.h>
39#include <dev/uart/uart_dev_z8530.h>
40
41#include "uart_if.h"
42
43#define DEFAULT_RCLK 307200
44
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/conf.h>
34#include <machine/bus.h>
35
36#include <dev/uart/uart.h>
37#include <dev/uart/uart_cpu.h>
38#include <dev/uart/uart_bus.h>
39#include <dev/uart/uart_dev_z8530.h>
40
41#include "uart_if.h"
42
43#define DEFAULT_RCLK 307200
44
45#define IS_CHANNEL_A(bas) (((bas)->iobase & 7) != 0)
46#define IS_CHANNEL_B(bas) (((bas)->iobase & 7) == 0)
47
48/* Multiplexed I/O. */
49static __inline void
50uart_setmreg(struct uart_bas *bas, int reg, int val)
51{
52
53 uart_setreg(bas, REG_CTRL, reg);
54 uart_barrier(bas);
55 uart_setreg(bas, REG_CTRL, val);

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139 *tpcp = tpc;
140 return (0);
141}
142
143static int
144z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits,
145 int parity)
146{
45/* Multiplexed I/O. */
46static __inline void
47uart_setmreg(struct uart_bas *bas, int reg, int val)
48{
49
50 uart_setreg(bas, REG_CTRL, reg);
51 uart_barrier(bas);
52 uart_setreg(bas, REG_CTRL, val);

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136 *tpcp = tpc;
137 return (0);
138}
139
140static int
141z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits,
142 int parity)
143{
147 uint8_t tpc;
144 uint8_t mic, tpc;
148
149 if (bas->rclk == 0)
150 bas->rclk = DEFAULT_RCLK;
151
152 /* Assume we don't need to perform a full hardware reset. */
145
146 if (bas->rclk == 0)
147 bas->rclk = DEFAULT_RCLK;
148
149 /* Assume we don't need to perform a full hardware reset. */
153 uart_setmreg(bas, WR_MIC, ((IS_CHANNEL_A(bas)) ? MIC_CRA : MIC_CRB) |
154 MIC_MIE | MIC_NV);
150 mic = MIC_MIE | MIC_NV;
151 switch (bas->chan) {
152 case 1:
153 mic |= MIC_CRA;
154 break;
155 case 2:
156 mic |= MIC_CRB;
157 break;
158 }
159 uart_setmreg(bas, WR_MIC, mic);
155 uart_barrier(bas);
156 /* Set clock sources and enable BRG. */
157 uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG);
158 uart_setmreg(bas, WR_MCB2, MCB2_PCLK | MCB2_BRGE);
159 uart_barrier(bas);
160 /* Set data encoding. */
161 uart_setmreg(bas, WR_MCB1, MCB1_NRZ);
162 uart_barrier(bas);

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428 mtx_unlock_spin(&sc->sc_hwmtx);
429 return (error);
430}
431
432static int
433z8530_bus_probe(struct uart_softc *sc)
434{
435 char buf[80];
160 uart_barrier(bas);
161 /* Set clock sources and enable BRG. */
162 uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG);
163 uart_setmreg(bas, WR_MCB2, MCB2_PCLK | MCB2_BRGE);
164 uart_barrier(bas);
165 /* Set data encoding. */
166 uart_setmreg(bas, WR_MCB1, MCB1_NRZ);
167 uart_barrier(bas);

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433 mtx_unlock_spin(&sc->sc_hwmtx);
434 return (error);
435}
436
437static int
438z8530_bus_probe(struct uart_softc *sc)
439{
440 char buf[80];
436 const char *ch;
437 int error;
441 int error;
442 char ch;
438
439 error = z8530_probe(&sc->sc_bas);
440 if (error)
441 return (error);
442
443
444 error = z8530_probe(&sc->sc_bas);
445 if (error)
446 return (error);
447
443 /* Assume the address range is naturally aligned. */
444 ch = IS_CHANNEL_A(&sc->sc_bas) ? "A" : "B";
448 ch = sc->sc_bas.chan - 1 + 'A';
445
449
446 snprintf(buf, sizeof(buf), "z8530, channel %s", ch);
450 snprintf(buf, sizeof(buf), "z8530, channel %c", ch);
447 device_set_desc_copy(sc->sc_dev, buf);
448 return (0);
449}
450
451static int
452z8530_bus_receive(struct uart_softc *sc)
453{
454 struct uart_bas *bas;

--- 89 unchanged lines hidden --- 		451 device_set_desc_copy(sc->sc_dev, buf);
452 return (0);
453}
454
455static int
456z8530_bus_receive(struct uart_softc *sc)
457{
458 struct uart_bas *bas;

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