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1/*-
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_z8530.c 160717 2006-07-26 17:29:37Z marcel $");
28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_z8530.c 166100 2007-01-18 22:01:19Z marius $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/conf.h>
34#include <machine/bus.h>
35
36#include <dev/uart/uart.h>
37#include <dev/uart/uart_cpu.h>
38#include <dev/uart/uart_bus.h>
39
40#include <dev/ic/z8530.h>
41
42#include "uart_if.h"
43
44#define DEFAULT_RCLK 307200
45
46/* Hack! */
47#ifdef __powerpc__
48#define UART_PCLK 0
49#else
50#define UART_PCLK MCB2_PCLK
51#endif
52
53/* Multiplexed I/O. */
54static __inline void
55uart_setmreg(struct uart_bas *bas, int reg, int val)
56{
57
58 uart_setreg(bas, REG_CTRL, reg);
59 uart_barrier(bas);
60 uart_setreg(bas, REG_CTRL, val);
61}
62
63static __inline uint8_t
64uart_getmreg(struct uart_bas *bas, int reg)
65{
66
67 uart_setreg(bas, REG_CTRL, reg);
68 uart_barrier(bas);
69 return (uart_getreg(bas, REG_CTRL));
70}
71
72static int
73z8530_divisor(int rclk, int baudrate)
74{
75 int act_baud, divisor, error;
76
77 if (baudrate == 0)
78 return (-1);
79
80 divisor = (rclk + baudrate) / (baudrate << 1) - 2;
81 if (divisor < 0 || divisor >= 65536)
82 return (-1);
83 act_baud = rclk / 2 / (divisor + 2);
84
85 /* 10 times error in percent: */
86 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
87
88 /* 3.0% maximum error tolerance: */
89 if (error < -30 || error > 30)
90 return (-1);
91
92 return (divisor);
93}
94
95static int
96z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
97 int parity, uint8_t *tpcp)
98{
99 int divisor;
100 uint8_t mpm, rpc, tpc;
101
102 rpc = RPC_RXE;
103 mpm = MPM_CM16;
104 tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS));
105
106 if (databits >= 8) {
107 rpc |= RPC_RB8;
108 tpc |= TPC_TB8;
109 } else if (databits == 7) {
110 rpc |= RPC_RB7;
111 tpc |= TPC_TB7;
112 } else if (databits == 6) {
113 rpc |= RPC_RB6;
114 tpc |= TPC_TB6;
115 } else {
116 rpc |= RPC_RB5;
117 tpc |= TPC_TB5;
118 }
119 mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1;
120 switch (parity) {
121 case UART_PARITY_EVEN: mpm |= MPM_PE | MPM_EVEN; break;
122 case UART_PARITY_NONE: break;
123 case UART_PARITY_ODD: mpm |= MPM_PE; break;
124 default: return (EINVAL);
125 }
126
127 if (baudrate > 0) {
128 divisor = z8530_divisor(bas->rclk, baudrate);
129 if (divisor == -1)
130 return (EINVAL);
131 } else
132 divisor = -1;
133
134 uart_setmreg(bas, WR_MCB2, UART_PCLK);
135 uart_barrier(bas);
136
137 if (divisor >= 0) {
138 uart_setmreg(bas, WR_TCL, divisor & 0xff);
139 uart_barrier(bas);
140 uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff);
141 uart_barrier(bas);
142 }
143
144 uart_setmreg(bas, WR_RPC, rpc);
145 uart_barrier(bas);
146 uart_setmreg(bas, WR_MPM, mpm);
147 uart_barrier(bas);
148 uart_setmreg(bas, WR_TPC, tpc);
149 uart_barrier(bas);
150 uart_setmreg(bas, WR_MCB2, UART_PCLK | MCB2_BRGE);
151 uart_barrier(bas);
152 *tpcp = tpc;
153 return (0);
154}
155
156static int
157z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits,
158 int parity)
159{
160 uint8_t tpc;
161
162 if (bas->rclk == 0)
163 bas->rclk = DEFAULT_RCLK;
164
165 /* Assume we don't need to perform a full hardware reset. */
166 switch (bas->chan) {
167 case 1:
168 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRA);
169 break;
170 case 2:
171 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRB);
172 break;
173 }
174 uart_barrier(bas);
175 /* Set clock sources. */
176 uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG);
177 uart_setmreg(bas, WR_MCB2, UART_PCLK);
178 uart_barrier(bas);
179 /* Set data encoding. */
180 uart_setmreg(bas, WR_MCB1, MCB1_NRZ);
181 uart_barrier(bas);
182
183 tpc = TPC_DTR | TPC_RTS;
184 z8530_param(bas, baudrate, databits, stopbits, parity, &tpc);
185 return (int)tpc;
186}
187
188/*
189 * Low-level UART interface.
190 */
191static int z8530_probe(struct uart_bas *bas);
192static void z8530_init(struct uart_bas *bas, int, int, int, int);
193static void z8530_term(struct uart_bas *bas);
194static void z8530_putc(struct uart_bas *bas, int);
195static int z8530_poll(struct uart_bas *bas);
195static int z8530_rxready(struct uart_bas *bas);
196static int z8530_getc(struct uart_bas *bas, struct mtx *);
197
198struct uart_ops uart_z8530_ops = {
199 .probe = z8530_probe,
200 .init = z8530_init,
201 .term = z8530_term,
202 .putc = z8530_putc,
203 .poll = z8530_poll,
203 .rxready = z8530_rxready,
204 .getc = z8530_getc,
205};
206
207static int
208z8530_probe(struct uart_bas *bas)
209{
210
211 return (0);
212}
213
214static void
215z8530_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
216 int parity)
217{
218
219 z8530_setup(bas, baudrate, databits, stopbits, parity);
220}
221
222static void
223z8530_term(struct uart_bas *bas)
224{
225}
226
227static void
228z8530_putc(struct uart_bas *bas, int c)
229{
230
231 while (!(uart_getreg(bas, REG_CTRL) & BES_TXE))
232 ;
233 uart_setreg(bas, REG_DATA, c);
234 uart_barrier(bas);
235}
236
237static int
238z8530_poll(struct uart_bas *bas)
238z8530_rxready(struct uart_bas *bas)
239{
240
241 if (!(uart_getreg(bas, REG_CTRL) & BES_RXA))
242 return (-1);
243 return (uart_getreg(bas, REG_DATA));
241 return ((uart_getreg(bas, REG_CTRL) & BES_RXA) != 0 ? 1 : 0);
242}
243
244static int
245z8530_getc(struct uart_bas *bas, struct mtx *hwmtx)
246{
247 int c;
248
249 uart_lock(hwmtx);
250
251 while (!(uart_getreg(bas, REG_CTRL) & BES_RXA)) {
252 uart_unlock(hwmtx);
253 DELAY(10);
254 uart_lock(hwmtx);
255 }
256
257 c = uart_getreg(bas, REG_DATA);
258
259 uart_unlock(hwmtx);
260
261 return (c);
262}
263
264/*
265 * High-level UART interface.
266 */
267struct z8530_softc {
268 struct uart_softc base;
269 uint8_t tpc;
270 uint8_t txidle;
271};
272
273static int z8530_bus_attach(struct uart_softc *);
274static int z8530_bus_detach(struct uart_softc *);
275static int z8530_bus_flush(struct uart_softc *, int);
276static int z8530_bus_getsig(struct uart_softc *);
277static int z8530_bus_ioctl(struct uart_softc *, int, intptr_t);
278static int z8530_bus_ipend(struct uart_softc *);
279static int z8530_bus_param(struct uart_softc *, int, int, int, int);
280static int z8530_bus_probe(struct uart_softc *);
281static int z8530_bus_receive(struct uart_softc *);
282static int z8530_bus_setsig(struct uart_softc *, int);
283static int z8530_bus_transmit(struct uart_softc *);
284
285static kobj_method_t z8530_methods[] = {
286 KOBJMETHOD(uart_attach, z8530_bus_attach),
287 KOBJMETHOD(uart_detach, z8530_bus_detach),
288 KOBJMETHOD(uart_flush, z8530_bus_flush),
289 KOBJMETHOD(uart_getsig, z8530_bus_getsig),
290 KOBJMETHOD(uart_ioctl, z8530_bus_ioctl),
291 KOBJMETHOD(uart_ipend, z8530_bus_ipend),
292 KOBJMETHOD(uart_param, z8530_bus_param),
293 KOBJMETHOD(uart_probe, z8530_bus_probe),
294 KOBJMETHOD(uart_receive, z8530_bus_receive),
295 KOBJMETHOD(uart_setsig, z8530_bus_setsig),
296 KOBJMETHOD(uart_transmit, z8530_bus_transmit),
297 { 0, 0 }
298};
299
300struct uart_class uart_z8530_class = {
301 "z8530 class",
302 z8530_methods,
303 sizeof(struct z8530_softc),
304 .uc_range = 2,
305 .uc_rclk = DEFAULT_RCLK
306};
307
308#define SIGCHG(c, i, s, d) \
309 if (c) { \
310 i |= (i & s) ? s : s | d; \
311 } else { \
312 i = (i & s) ? (i & ~s) | d : i; \
313 }
314
315static int
316z8530_bus_attach(struct uart_softc *sc)
317{
318 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
319 struct uart_bas *bas;
320 struct uart_devinfo *di;
321
322 bas = &sc->sc_bas;
323 if (sc->sc_sysdev != NULL) {
324 di = sc->sc_sysdev;
325 z8530->tpc = TPC_DTR|TPC_RTS;
326 z8530_param(bas, di->baudrate, di->databits, di->stopbits,
327 di->parity, &z8530->tpc);
328 } else {
329 z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE);
330 z8530->tpc &= ~(TPC_DTR|TPC_RTS);
331 }
332 z8530->txidle = 1; /* Report SER_INT_TXIDLE. */
333
334 sc->sc_rxfifosz = 3;
335 sc->sc_txfifosz = 1;
336
337 (void)z8530_bus_getsig(sc);
338
339 uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD);
340 uart_barrier(bas);
341 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA);
342 uart_barrier(bas);
343 uart_setmreg(bas, WR_IV, 0);
344 uart_barrier(bas);
345 uart_setmreg(bas, WR_TPC, z8530->tpc);
346 uart_barrier(bas);
347 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_MIE);
348 uart_barrier(bas);
349 return (0);
350}
351
352static int
353z8530_bus_detach(struct uart_softc *sc)
354{
355
356 return (0);
357}
358
359static int
360z8530_bus_flush(struct uart_softc *sc, int what)
361{
362
363 return (0);
364}
365
366static int
367z8530_bus_getsig(struct uart_softc *sc)
368{
369 uint32_t new, old, sig;
370 uint8_t bes;
371
372 do {
373 old = sc->sc_hwsig;
374 sig = old;
375 uart_lock(sc->sc_hwmtx);
376 bes = uart_getmreg(&sc->sc_bas, RR_BES);
377 uart_unlock(sc->sc_hwmtx);
378 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS);
379 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD);
380 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR);
381 new = sig & ~SER_MASK_DELTA;
382 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
383 return (sig);
384}
385
386static int
387z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
388{
389 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
390 struct uart_bas *bas;
391 int baudrate, divisor, error;
392
393 bas = &sc->sc_bas;
394 error = 0;
395 uart_lock(sc->sc_hwmtx);
396 switch (request) {
397 case UART_IOCTL_BREAK:
398 if (data)
399 z8530->tpc |= TPC_BRK;
400 else
401 z8530->tpc &= ~TPC_BRK;
402 uart_setmreg(bas, WR_TPC, z8530->tpc);
403 uart_barrier(bas);
404 break;
405 case UART_IOCTL_BAUD:
406 divisor = uart_getmreg(bas, RR_TCH);
407 divisor = (divisor << 8) | uart_getmreg(bas, RR_TCL);
408 baudrate = bas->rclk / 2 / (divisor + 2);
409 *(int*)data = baudrate;
410 break;
411 default:
412 error = EINVAL;
413 break;
414 }
415 uart_unlock(sc->sc_hwmtx);
416 return (error);
417}
418
419static int
420z8530_bus_ipend(struct uart_softc *sc)
421{
422 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
423 struct uart_bas *bas;
424 int ipend;
425 uint32_t sig;
426 uint8_t bes, ip, iv, src;
427
428 bas = &sc->sc_bas;
429 ipend = 0;
430
431 uart_lock(sc->sc_hwmtx);
432 switch (bas->chan) {
433 case 1:
434 ip = uart_getmreg(bas, RR_IP);
435 break;
436 case 2: /* XXX hack!!! */
437 iv = uart_getmreg(bas, RR_IV) & 0x0E;
438 switch (iv) {
439 case IV_TEB: ip = IP_TIA; break;
440 case IV_XSB: ip = IP_SIA; break;
441 case IV_RAB: ip = IP_RIA; break;
442 default: ip = 0; break;
443 }
444 break;
445 default:
446 ip = 0;
447 break;
448 }
449
450 if (ip & IP_RIA)
451 ipend |= SER_INT_RXREADY;
452
453 if (ip & IP_TIA) {
454 uart_setreg(bas, REG_CTRL, CR_RSTTXI);
455 uart_barrier(bas);
456 if (z8530->txidle) {
457 ipend |= SER_INT_TXIDLE;
458 z8530->txidle = 0; /* Mask SER_INT_TXIDLE. */
459 }
460 }
461
462 if (ip & IP_SIA) {
463 uart_setreg(bas, REG_CTRL, CR_RSTXSI);
464 uart_barrier(bas);
465 bes = uart_getmreg(bas, RR_BES);
466 if (bes & BES_BRK)
467 ipend |= SER_INT_BREAK;
468 sig = sc->sc_hwsig;
469 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS);
470 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD);
471 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR);
472 if (sig & SER_MASK_DELTA)
473 ipend |= SER_INT_SIGCHG;
474 src = uart_getmreg(bas, RR_SRC);
475 if (src & SRC_OVR) {
476 uart_setreg(bas, REG_CTRL, CR_RSTERR);
477 uart_barrier(bas);
478 ipend |= SER_INT_OVERRUN;
479 }
480 }
481
482 if (ipend) {
483 uart_setreg(bas, REG_CTRL, CR_RSTIUS);
484 uart_barrier(bas);
485 }
486
487 uart_unlock(sc->sc_hwmtx);
488
489 return (ipend);
490}
491
492static int
493z8530_bus_param(struct uart_softc *sc, int baudrate, int databits,
494 int stopbits, int parity)
495{
496 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
497 int error;
498
499 uart_lock(sc->sc_hwmtx);
500 error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity,
501 &z8530->tpc);
502 uart_unlock(sc->sc_hwmtx);
503 return (error);
504}
505
506static int
507z8530_bus_probe(struct uart_softc *sc)
508{
509 char buf[80];
510 int error;
511 char ch;
512
513 error = z8530_probe(&sc->sc_bas);
514 if (error)
515 return (error);
516
517 ch = sc->sc_bas.chan - 1 + 'A';
518
519 snprintf(buf, sizeof(buf), "z8530, channel %c", ch);
520 device_set_desc_copy(sc->sc_dev, buf);
521 return (0);
522}
523
524static int
525z8530_bus_receive(struct uart_softc *sc)
526{
527 struct uart_bas *bas;
528 int xc;
529 uint8_t bes, src;
530
531 bas = &sc->sc_bas;
532 uart_lock(sc->sc_hwmtx);
533 bes = uart_getmreg(bas, RR_BES);
534 while (bes & BES_RXA) {
535 if (uart_rx_full(sc)) {
536 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
537 break;
538 }
539 xc = uart_getreg(bas, REG_DATA);
540 uart_barrier(bas);
541 src = uart_getmreg(bas, RR_SRC);
542 if (src & SRC_FE)
543 xc |= UART_STAT_FRAMERR;
544 if (src & SRC_PE)
545 xc |= UART_STAT_PARERR;
546 if (src & SRC_OVR)
547 xc |= UART_STAT_OVERRUN;
548 uart_rx_put(sc, xc);
549 if (src & (SRC_FE | SRC_PE | SRC_OVR)) {
550 uart_setreg(bas, REG_CTRL, CR_RSTERR);
551 uart_barrier(bas);
552 }
553 bes = uart_getmreg(bas, RR_BES);
554 }
555 /* Discard everything left in the Rx FIFO. */
556 while (bes & BES_RXA) {
557 (void)uart_getreg(bas, REG_DATA);
558 uart_barrier(bas);
559 src = uart_getmreg(bas, RR_SRC);
560 if (src & (SRC_FE | SRC_PE | SRC_OVR)) {
561 uart_setreg(bas, REG_CTRL, CR_RSTERR);
562 uart_barrier(bas);
563 }
564 bes = uart_getmreg(bas, RR_BES);
565 }
566 uart_unlock(sc->sc_hwmtx);
567 return (0);
568}
569
570static int
571z8530_bus_setsig(struct uart_softc *sc, int sig)
572{
573 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
574 struct uart_bas *bas;
575 uint32_t new, old;
576
577 bas = &sc->sc_bas;
578 do {
579 old = sc->sc_hwsig;
580 new = old;
581 if (sig & SER_DDTR) {
582 SIGCHG(sig & SER_DTR, new, SER_DTR,
583 SER_DDTR);
584 }
585 if (sig & SER_DRTS) {
586 SIGCHG(sig & SER_RTS, new, SER_RTS,
587 SER_DRTS);
588 }
589 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
590
591 uart_lock(sc->sc_hwmtx);
592 if (new & SER_DTR)
593 z8530->tpc |= TPC_DTR;
594 else
595 z8530->tpc &= ~TPC_DTR;
596 if (new & SER_RTS)
597 z8530->tpc |= TPC_RTS;
598 else
599 z8530->tpc &= ~TPC_RTS;
600 uart_setmreg(bas, WR_TPC, z8530->tpc);
601 uart_barrier(bas);
602 uart_unlock(sc->sc_hwmtx);
603 return (0);
604}
605
606static int
607z8530_bus_transmit(struct uart_softc *sc)
608{
609 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
610 struct uart_bas *bas;
611
612 bas = &sc->sc_bas;
613 uart_lock(sc->sc_hwmtx);
614 while (!(uart_getmreg(bas, RR_BES) & BES_TXE))
615 ;
616 uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]);
617 uart_barrier(bas);
618 sc->sc_txbusy = 1;
619 z8530->txidle = 1; /* Report SER_INT_TXIDLE again. */
620 uart_unlock(sc->sc_hwmtx);
621 return (0);
622}