29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/conf.h> 34#include <machine/bus.h> 35 36#include <dev/uart/uart.h> 37#include <dev/uart/uart_cpu.h> 38#include <dev/uart/uart_bus.h> 39 40#include <dev/ic/ns16550.h> 41 42#include "uart_if.h" 43 44#define DEFAULT_RCLK 1843200 45 46/* 47 * Clear pending interrupts. THRE is cleared by reading IIR. Data 48 * that may have been received gets lost here. 49 */ 50static void 51ns8250_clrint(struct uart_bas *bas) 52{ 53 uint8_t iir; 54 55 iir = uart_getreg(bas, REG_IIR); 56 while ((iir & IIR_NOPEND) == 0) { 57 iir &= IIR_IMASK; 58 if (iir == IIR_RLS) 59 (void)uart_getreg(bas, REG_LSR); 60 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 61 (void)uart_getreg(bas, REG_DATA); 62 else if (iir == IIR_MLSC) 63 (void)uart_getreg(bas, REG_MSR); 64 uart_barrier(bas); 65 iir = uart_getreg(bas, REG_IIR); 66 } 67} 68 69static int 70ns8250_delay(struct uart_bas *bas) 71{ 72 int divisor; 73 u_char lcr; 74 75 lcr = uart_getreg(bas, REG_LCR); 76 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 77 uart_barrier(bas); 78 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 79 uart_barrier(bas); 80 uart_setreg(bas, REG_LCR, lcr); 81 uart_barrier(bas); 82 83 /* 1/10th the time to transmit 1 character (estimate). */ 84 return (16000000 * divisor / bas->rclk); 85} 86 87static int 88ns8250_divisor(int rclk, int baudrate) 89{ 90 int actual_baud, divisor; 91 int error; 92 93 if (baudrate == 0) 94 return (0); 95 96 divisor = (rclk / (baudrate << 3) + 1) >> 1; 97 if (divisor == 0 || divisor >= 65536) 98 return (0); 99 actual_baud = rclk / (divisor << 4); 100 101 /* 10 times error in percent: */ 102 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 103 104 /* 3.0% maximum error tolerance: */ 105 if (error < -30 || error > 30) 106 return (0); 107 108 return (divisor); 109} 110 111static int 112ns8250_drain(struct uart_bas *bas, int what) 113{ 114 int delay, limit; 115 116 delay = ns8250_delay(bas); 117 118 if (what & UART_DRAIN_TRANSMITTER) { 119 /* 120 * Pick an arbitrary high limit to avoid getting stuck in 121 * an infinite loop when the hardware is broken. Make the 122 * limit high enough to handle large FIFOs. 123 */ 124 limit = 10*1024; 125 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 126 DELAY(delay); 127 if (limit == 0) { 128 /* printf("ns8250: transmitter appears stuck... "); */ 129 return (EIO); 130 } 131 } 132 133 if (what & UART_DRAIN_RECEIVER) { 134 /* 135 * Pick an arbitrary high limit to avoid getting stuck in 136 * an infinite loop when the hardware is broken. Make the 137 * limit high enough to handle large FIFOs and integrated 138 * UARTs. The HP rx2600 for example has 3 UARTs on the 139 * management board that tend to get a lot of data send 140 * to it when the UART is first activated. 141 */ 142 limit=10*4096; 143 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 144 (void)uart_getreg(bas, REG_DATA); 145 uart_barrier(bas); 146 DELAY(delay << 2); 147 } 148 if (limit == 0) { 149 /* printf("ns8250: receiver appears broken... "); */ 150 return (EIO); 151 } 152 } 153 154 return (0); 155} 156 157/* 158 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 159 * drained. WARNING: this function clobbers the FIFO setting! 160 */ 161static void 162ns8250_flush(struct uart_bas *bas, int what) 163{ 164 uint8_t fcr; 165 166 fcr = FCR_ENABLE; 167 if (what & UART_FLUSH_TRANSMITTER) 168 fcr |= FCR_XMT_RST; 169 if (what & UART_FLUSH_RECEIVER) 170 fcr |= FCR_RCV_RST; 171 uart_setreg(bas, REG_FCR, fcr); 172 uart_barrier(bas); 173} 174 175static int 176ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 177 int parity) 178{ 179 int divisor; 180 uint8_t lcr; 181 182 lcr = 0; 183 if (databits >= 8) 184 lcr |= LCR_8BITS; 185 else if (databits == 7) 186 lcr |= LCR_7BITS; 187 else if (databits == 6) 188 lcr |= LCR_6BITS; 189 else 190 lcr |= LCR_5BITS; 191 if (stopbits > 1) 192 lcr |= LCR_STOPB; 193 lcr |= parity << 3; 194 195 /* Set baudrate. */ 196 if (baudrate > 0) { 197 divisor = ns8250_divisor(bas->rclk, baudrate); 198 if (divisor == 0) 199 return (EINVAL); 200 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 201 uart_barrier(bas); 202 uart_setreg(bas, REG_DLL, divisor & 0xff); 203 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 204 uart_barrier(bas); 205 } 206 207 /* Set LCR and clear DLAB. */ 208 uart_setreg(bas, REG_LCR, lcr); 209 uart_barrier(bas); 210 return (0); 211} 212 213/* 214 * Low-level UART interface. 215 */ 216static int ns8250_probe(struct uart_bas *bas); 217static void ns8250_init(struct uart_bas *bas, int, int, int, int); 218static void ns8250_term(struct uart_bas *bas); 219static void ns8250_putc(struct uart_bas *bas, int);
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306} 307 308static int 309ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 310{ 311 int c, delay; 312 313 uart_lock(hwmtx); 314 315 /* 1/10th the time to transmit 1 character (estimate). */ 316 delay = ns8250_delay(bas); 317 318 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 319 uart_unlock(hwmtx); 320 DELAY(delay); 321 uart_lock(hwmtx); 322 } 323 324 c = uart_getreg(bas, REG_DATA); 325 326 uart_unlock(hwmtx); 327 328 return (c); 329} 330 331/* 332 * High-level UART interface. 333 */ 334struct ns8250_softc { 335 struct uart_softc base; 336 uint8_t fcr; 337 uint8_t ier; 338 uint8_t mcr; 339}; 340 341static int ns8250_bus_attach(struct uart_softc *); 342static int ns8250_bus_detach(struct uart_softc *); 343static int ns8250_bus_flush(struct uart_softc *, int); 344static int ns8250_bus_getsig(struct uart_softc *); 345static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); 346static int ns8250_bus_ipend(struct uart_softc *); 347static int ns8250_bus_param(struct uart_softc *, int, int, int, int); 348static int ns8250_bus_probe(struct uart_softc *); 349static int ns8250_bus_receive(struct uart_softc *); 350static int ns8250_bus_setsig(struct uart_softc *, int); 351static int ns8250_bus_transmit(struct uart_softc *); 352 353static kobj_method_t ns8250_methods[] = { 354 KOBJMETHOD(uart_attach, ns8250_bus_attach), 355 KOBJMETHOD(uart_detach, ns8250_bus_detach), 356 KOBJMETHOD(uart_flush, ns8250_bus_flush), 357 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 358 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 359 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 360 KOBJMETHOD(uart_param, ns8250_bus_param), 361 KOBJMETHOD(uart_probe, ns8250_bus_probe), 362 KOBJMETHOD(uart_receive, ns8250_bus_receive), 363 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 364 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 365 { 0, 0 } 366}; 367 368struct uart_class uart_ns8250_class = { 369 "ns8250 class", 370 ns8250_methods, 371 sizeof(struct ns8250_softc), 372 .uc_range = 8, 373 .uc_rclk = DEFAULT_RCLK 374}; 375 376#define SIGCHG(c, i, s, d) \ 377 if (c) { \ 378 i |= (i & s) ? s : s | d; \ 379 } else { \ 380 i = (i & s) ? (i & ~s) | d : i; \ 381 } 382 383static int 384ns8250_bus_attach(struct uart_softc *sc) 385{ 386 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 387 struct uart_bas *bas; 388 389 bas = &sc->sc_bas; 390 391 ns8250->mcr = uart_getreg(bas, REG_MCR); 392 ns8250->fcr = FCR_ENABLE | FCR_RX_MEDH; 393 uart_setreg(bas, REG_FCR, ns8250->fcr); 394 uart_barrier(bas); 395 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 396 397 if (ns8250->mcr & MCR_DTR) 398 sc->sc_hwsig |= SER_DTR; 399 if (ns8250->mcr & MCR_RTS) 400 sc->sc_hwsig |= SER_RTS; 401 ns8250_bus_getsig(sc); 402 403 ns8250_clrint(bas); 404 ns8250->ier = uart_getreg(bas, REG_IER) & 0xf0; 405 ns8250->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY; 406 uart_setreg(bas, REG_IER, ns8250->ier); 407 uart_barrier(bas); 408 return (0); 409} 410 411static int 412ns8250_bus_detach(struct uart_softc *sc) 413{ 414 struct uart_bas *bas; 415 u_char ier; 416 417 bas = &sc->sc_bas; 418 ier = uart_getreg(bas, REG_IER) & 0xf0; 419 uart_setreg(bas, REG_IER, ier); 420 uart_barrier(bas); 421 ns8250_clrint(bas); 422 return (0); 423} 424 425static int 426ns8250_bus_flush(struct uart_softc *sc, int what) 427{ 428 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 429 struct uart_bas *bas; 430 int error; 431 432 bas = &sc->sc_bas; 433 uart_lock(sc->sc_hwmtx); 434 if (sc->sc_rxfifosz > 1) { 435 ns8250_flush(bas, what); 436 uart_setreg(bas, REG_FCR, ns8250->fcr); 437 uart_barrier(bas); 438 error = 0; 439 } else 440 error = ns8250_drain(bas, what); 441 uart_unlock(sc->sc_hwmtx); 442 return (error); 443} 444 445static int 446ns8250_bus_getsig(struct uart_softc *sc) 447{ 448 uint32_t new, old, sig; 449 uint8_t msr; 450 451 do { 452 old = sc->sc_hwsig; 453 sig = old; 454 uart_lock(sc->sc_hwmtx); 455 msr = uart_getreg(&sc->sc_bas, REG_MSR); 456 uart_unlock(sc->sc_hwmtx); 457 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 458 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 459 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 460 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 461 new = sig & ~SER_MASK_DELTA; 462 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 463 return (sig); 464} 465 466static int 467ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 468{ 469 struct uart_bas *bas; 470 int baudrate, divisor, error; 471 uint8_t efr, lcr; 472 473 bas = &sc->sc_bas; 474 error = 0; 475 uart_lock(sc->sc_hwmtx); 476 switch (request) { 477 case UART_IOCTL_BREAK: 478 lcr = uart_getreg(bas, REG_LCR); 479 if (data) 480 lcr |= LCR_SBREAK; 481 else 482 lcr &= ~LCR_SBREAK; 483 uart_setreg(bas, REG_LCR, lcr); 484 uart_barrier(bas); 485 break; 486 case UART_IOCTL_IFLOW: 487 lcr = uart_getreg(bas, REG_LCR); 488 uart_barrier(bas); 489 uart_setreg(bas, REG_LCR, 0xbf); 490 uart_barrier(bas); 491 efr = uart_getreg(bas, REG_EFR); 492 if (data) 493 efr |= EFR_RTS; 494 else 495 efr &= ~EFR_RTS; 496 uart_setreg(bas, REG_EFR, efr); 497 uart_barrier(bas); 498 uart_setreg(bas, REG_LCR, lcr); 499 uart_barrier(bas); 500 break; 501 case UART_IOCTL_OFLOW: 502 lcr = uart_getreg(bas, REG_LCR); 503 uart_barrier(bas); 504 uart_setreg(bas, REG_LCR, 0xbf); 505 uart_barrier(bas); 506 efr = uart_getreg(bas, REG_EFR); 507 if (data) 508 efr |= EFR_CTS; 509 else 510 efr &= ~EFR_CTS; 511 uart_setreg(bas, REG_EFR, efr); 512 uart_barrier(bas); 513 uart_setreg(bas, REG_LCR, lcr); 514 uart_barrier(bas); 515 break; 516 case UART_IOCTL_BAUD: 517 lcr = uart_getreg(bas, REG_LCR); 518 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 519 uart_barrier(bas); 520 divisor = uart_getreg(bas, REG_DLL) | 521 (uart_getreg(bas, REG_DLH) << 8); 522 uart_barrier(bas); 523 uart_setreg(bas, REG_LCR, lcr); 524 uart_barrier(bas); 525 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 526 if (baudrate > 0) 527 *(int*)data = baudrate; 528 else 529 error = ENXIO; 530 break; 531 default: 532 error = EINVAL; 533 break; 534 } 535 uart_unlock(sc->sc_hwmtx); 536 return (error); 537} 538 539static int 540ns8250_bus_ipend(struct uart_softc *sc) 541{ 542 struct uart_bas *bas; 543 int ipend; 544 uint8_t iir, lsr; 545 546 bas = &sc->sc_bas; 547 uart_lock(sc->sc_hwmtx); 548 iir = uart_getreg(bas, REG_IIR); 549 if (iir & IIR_NOPEND) { 550 uart_unlock(sc->sc_hwmtx); 551 return (0); 552 } 553 ipend = 0; 554 if (iir & IIR_RXRDY) { 555 lsr = uart_getreg(bas, REG_LSR); 556 uart_unlock(sc->sc_hwmtx); 557 if (lsr & LSR_OE) 558 ipend |= SER_INT_OVERRUN; 559 if (lsr & LSR_BI) 560 ipend |= SER_INT_BREAK; 561 if (lsr & LSR_RXRDY) 562 ipend |= SER_INT_RXREADY; 563 } else { 564 uart_unlock(sc->sc_hwmtx); 565 if (iir & IIR_TXRDY) 566 ipend |= SER_INT_TXIDLE; 567 else 568 ipend |= SER_INT_SIGCHG; 569 } 570 return ((sc->sc_leaving) ? 0 : ipend); 571} 572 573static int 574ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 575 int stopbits, int parity) 576{ 577 struct uart_bas *bas; 578 int error; 579 580 bas = &sc->sc_bas; 581 uart_lock(sc->sc_hwmtx); 582 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 583 uart_unlock(sc->sc_hwmtx); 584 return (error); 585} 586 587static int 588ns8250_bus_probe(struct uart_softc *sc) 589{ 590 struct uart_bas *bas; 591 int count, delay, error, limit; 592 uint8_t lsr, mcr, ier; 593 594 bas = &sc->sc_bas; 595 596 error = ns8250_probe(bas); 597 if (error) 598 return (error); 599 600 mcr = MCR_IE; 601 if (sc->sc_sysdev == NULL) { 602 /* By using ns8250_init() we also set DTR and RTS. */ 603 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 604 } else 605 mcr |= MCR_DTR | MCR_RTS; 606 607 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 608 if (error) 609 return (error); 610 611 /* 612 * Set loopback mode. This avoids having garbage on the wire and 613 * also allows us send and receive data. We set DTR and RTS to 614 * avoid the possibility that automatic flow-control prevents 615 * any data from being sent. 616 */ 617 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 618 uart_barrier(bas); 619 620 /* 621 * Enable FIFOs. And check that the UART has them. If not, we're 622 * done. Since this is the first time we enable the FIFOs, we reset 623 * them. 624 */ 625 uart_setreg(bas, REG_FCR, FCR_ENABLE); 626 uart_barrier(bas); 627 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 628 /* 629 * NS16450 or INS8250. We don't bother to differentiate 630 * between them. They're too old to be interesting. 631 */ 632 uart_setreg(bas, REG_MCR, mcr); 633 uart_barrier(bas); 634 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 635 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 636 return (0); 637 } 638 639 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 640 uart_barrier(bas); 641 642 count = 0; 643 delay = ns8250_delay(bas); 644 645 /* We have FIFOs. Drain the transmitter and receiver. */ 646 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 647 if (error) { 648 uart_setreg(bas, REG_MCR, mcr); 649 uart_setreg(bas, REG_FCR, 0); 650 uart_barrier(bas); 651 goto describe; 652 } 653 654 /* 655 * We should have a sufficiently clean "pipe" to determine the 656 * size of the FIFOs. We send as much characters as is reasonable 657 * and wait for the the overflow bit in the LSR register to be 658 * asserted, counting the characters as we send them. Based on 659 * that count we know the FIFO size. 660 */ 661 do { 662 uart_setreg(bas, REG_DATA, 0); 663 uart_barrier(bas); 664 count++; 665 666 limit = 30; 667 lsr = 0; 668 /* 669 * LSR bits are cleared upon read, so we must accumulate 670 * them to be able to test LSR_OE below. 671 */ 672 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 673 --limit) 674 DELAY(delay); 675 if (limit == 0) { 676 ier = uart_getreg(bas, REG_IER) & 0xf0; 677 uart_setreg(bas, REG_IER, ier); 678 uart_setreg(bas, REG_MCR, mcr); 679 uart_setreg(bas, REG_FCR, 0); 680 uart_barrier(bas); 681 count = 0; 682 goto describe; 683 } 684 } while ((lsr & LSR_OE) == 0 && count < 130); 685 count--; 686 687 uart_setreg(bas, REG_MCR, mcr); 688 689 /* Reset FIFOs. */ 690 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 691 692 describe: 693 if (count >= 14 && count <= 16) { 694 sc->sc_rxfifosz = 16; 695 device_set_desc(sc->sc_dev, "16550 or compatible"); 696 } else if (count >= 28 && count <= 32) { 697 sc->sc_rxfifosz = 32; 698 device_set_desc(sc->sc_dev, "16650 or compatible"); 699 } else if (count >= 56 && count <= 64) { 700 sc->sc_rxfifosz = 64; 701 device_set_desc(sc->sc_dev, "16750 or compatible"); 702 } else if (count >= 112 && count <= 128) { 703 sc->sc_rxfifosz = 128; 704 device_set_desc(sc->sc_dev, "16950 or compatible"); 705 } else { 706 sc->sc_rxfifosz = 16; 707 device_set_desc(sc->sc_dev, 708 "Non-standard ns8250 class UART with FIFOs"); 709 } 710 711 /* 712 * Force the Tx FIFO size to 16 bytes for now. We don't program the 713 * Tx trigger. Also, we assume that all data has been sent when the 714 * interrupt happens. 715 */ 716 sc->sc_txfifosz = 16; 717 718#if 0 719 /* 720 * XXX there are some issues related to hardware flow control and 721 * it's likely that uart(4) is the cause. This basicly needs more 722 * investigation, but we avoid using for hardware flow control 723 * until then. 724 */ 725 /* 16650s or higher have automatic flow control. */ 726 if (sc->sc_rxfifosz > 16) { 727 sc->sc_hwiflow = 1; 728 sc->sc_hwoflow = 1; 729 } 730#endif 731 732 return (0); 733} 734 735static int 736ns8250_bus_receive(struct uart_softc *sc) 737{ 738 struct uart_bas *bas; 739 int xc; 740 uint8_t lsr; 741 742 bas = &sc->sc_bas; 743 uart_lock(sc->sc_hwmtx); 744 lsr = uart_getreg(bas, REG_LSR); 745 while (lsr & LSR_RXRDY) { 746 if (uart_rx_full(sc)) { 747 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 748 break; 749 } 750 xc = uart_getreg(bas, REG_DATA); 751 if (lsr & LSR_FE) 752 xc |= UART_STAT_FRAMERR; 753 if (lsr & LSR_PE) 754 xc |= UART_STAT_PARERR; 755 uart_rx_put(sc, xc); 756 lsr = uart_getreg(bas, REG_LSR); 757 } 758 /* Discard everything left in the Rx FIFO. */ 759 while (lsr & LSR_RXRDY) { 760 (void)uart_getreg(bas, REG_DATA); 761 uart_barrier(bas); 762 lsr = uart_getreg(bas, REG_LSR); 763 } 764 uart_unlock(sc->sc_hwmtx); 765 return (0); 766} 767 768static int 769ns8250_bus_setsig(struct uart_softc *sc, int sig) 770{ 771 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 772 struct uart_bas *bas; 773 uint32_t new, old; 774 775 bas = &sc->sc_bas; 776 do { 777 old = sc->sc_hwsig; 778 new = old; 779 if (sig & SER_DDTR) { 780 SIGCHG(sig & SER_DTR, new, SER_DTR, 781 SER_DDTR); 782 } 783 if (sig & SER_DRTS) { 784 SIGCHG(sig & SER_RTS, new, SER_RTS, 785 SER_DRTS); 786 } 787 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 788 uart_lock(sc->sc_hwmtx); 789 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 790 if (new & SER_DTR) 791 ns8250->mcr |= MCR_DTR; 792 if (new & SER_RTS) 793 ns8250->mcr |= MCR_RTS; 794 uart_setreg(bas, REG_MCR, ns8250->mcr); 795 uart_barrier(bas); 796 uart_unlock(sc->sc_hwmtx); 797 return (0); 798} 799 800static int 801ns8250_bus_transmit(struct uart_softc *sc) 802{ 803 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 804 struct uart_bas *bas; 805 int i; 806 807 bas = &sc->sc_bas; 808 uart_lock(sc->sc_hwmtx); 809 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 810 ; 811 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 812 uart_barrier(bas); 813 for (i = 0; i < sc->sc_txdatasz; i++) { 814 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 815 uart_barrier(bas); 816 } 817 sc->sc_txbusy = 1; 818 uart_unlock(sc->sc_hwmtx); 819 return (0); 820}
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