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e1000_phy.c (169589) e1000_phy.c (173788)
1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
33/*$FreeBSD: head/sys/dev/em/e1000_phy.c 169589 2007-05-16 00:14:23Z jfv $*/
33/* $FreeBSD: head/sys/dev/em/e1000_phy.c 173788 2007-11-20 21:41:22Z jfv $ */
34
35
36#include "e1000_api.h"
37#include "e1000_phy.h"
38
39static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
34
35
36#include "e1000_api.h"
37#include "e1000_phy.h"
38
39static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
40static void e1000_release_phy(struct e1000_hw *hw);
41static s32 e1000_acquire_phy(struct e1000_hw *hw);
40STATIC void e1000_release_phy(struct e1000_hw *hw);
41STATIC s32 e1000_acquire_phy(struct e1000_hw *hw);
42
43/* Cable length tables */
42
43/* Cable length tables */
44static const
45u16 e1000_m88_cable_length_table[] =
44static const u16 e1000_m88_cable_length_table[] =
46 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 (sizeof(e1000_m88_cable_length_table) / \
49 sizeof(e1000_m88_cable_length_table[0]))
50
45 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
46#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
47 (sizeof(e1000_m88_cable_length_table) / \
48 sizeof(e1000_m88_cable_length_table[0]))
49
51static const
52u16 e1000_igp_2_cable_length_table[] =
50static const u16 e1000_igp_2_cable_length_table[] =
53 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
54 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
55 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
56 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
57 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
58 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
59 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
60 104, 109, 114, 118, 121, 124};

--- 4 unchanged lines hidden (view full) ---

65/**
66 * e1000_check_reset_block_generic - Check if PHY reset is blocked
67 * @hw: pointer to the HW structure
68 *
69 * Read the PHY management control register and check whether a PHY reset
70 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
71 * return E1000_BLK_PHY_RESET (12).
72 **/
51 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
52 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
53 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
54 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
55 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
56 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
57 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
58 104, 109, 114, 118, 121, 124};

--- 4 unchanged lines hidden (view full) ---

63/**
64 * e1000_check_reset_block_generic - Check if PHY reset is blocked
65 * @hw: pointer to the HW structure
66 *
67 * Read the PHY management control register and check whether a PHY reset
68 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
69 * return E1000_BLK_PHY_RESET (12).
70 **/
73s32
74e1000_check_reset_block_generic(struct e1000_hw *hw)
71s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
75{
76 u32 manc;
77
78 DEBUGFUNC("e1000_check_reset_block");
79
80 manc = E1000_READ_REG(hw, E1000_MANC);
81
82 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
83 E1000_BLK_PHY_RESET : E1000_SUCCESS;
84}
85
86/**
87 * e1000_get_phy_id - Retrieve the PHY ID and revision
88 * @hw: pointer to the HW structure
89 *
90 * Reads the PHY registers and stores the PHY ID and possibly the PHY
91 * revision in the hardware structure.
92 **/
72{
73 u32 manc;
74
75 DEBUGFUNC("e1000_check_reset_block");
76
77 manc = E1000_READ_REG(hw, E1000_MANC);
78
79 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
80 E1000_BLK_PHY_RESET : E1000_SUCCESS;
81}
82
83/**
84 * e1000_get_phy_id - Retrieve the PHY ID and revision
85 * @hw: pointer to the HW structure
86 *
87 * Reads the PHY registers and stores the PHY ID and possibly the PHY
88 * revision in the hardware structure.
89 **/
93s32
94e1000_get_phy_id(struct e1000_hw *hw)
90s32 e1000_get_phy_id(struct e1000_hw *hw)
95{
96 struct e1000_phy_info *phy = &hw->phy;
97 s32 ret_val = E1000_SUCCESS;
98 u16 phy_id;
99
100 DEBUGFUNC("e1000_get_phy_id");
101
102 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id);

--- 14 unchanged lines hidden (view full) ---

117}
118
119/**
120 * e1000_phy_reset_dsp_generic - Reset PHY DSP
121 * @hw: pointer to the HW structure
122 *
123 * Reset the digital signal processor.
124 **/
91{
92 struct e1000_phy_info *phy = &hw->phy;
93 s32 ret_val = E1000_SUCCESS;
94 u16 phy_id;
95
96 DEBUGFUNC("e1000_get_phy_id");
97
98 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id);

--- 14 unchanged lines hidden (view full) ---

113}
114
115/**
116 * e1000_phy_reset_dsp_generic - Reset PHY DSP
117 * @hw: pointer to the HW structure
118 *
119 * Reset the digital signal processor.
120 **/
125s32
126e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
121s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
127{
128 s32 ret_val;
129
130 DEBUGFUNC("e1000_phy_reset_dsp_generic");
131
132 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
133 if (ret_val)
134 goto out;

--- 8 unchanged lines hidden (view full) ---

143 * e1000_read_phy_reg_mdic - Read MDI control register
144 * @hw: pointer to the HW structure
145 * @offset: register offset to be read
146 * @data: pointer to the read data
147 *
148 * Reads the MDI control regsiter in the PHY at offset and stores the
149 * information read to data.
150 **/
122{
123 s32 ret_val;
124
125 DEBUGFUNC("e1000_phy_reset_dsp_generic");
126
127 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
128 if (ret_val)
129 goto out;

--- 8 unchanged lines hidden (view full) ---

138 * e1000_read_phy_reg_mdic - Read MDI control register
139 * @hw: pointer to the HW structure
140 * @offset: register offset to be read
141 * @data: pointer to the read data
142 *
143 * Reads the MDI control regsiter in the PHY at offset and stores the
144 * information read to data.
145 **/
151static s32
152e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
146STATIC s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
153{
154 struct e1000_phy_info *phy = &hw->phy;
155 u32 i, mdic = 0;
156 s32 ret_val = E1000_SUCCESS;
157
158 DEBUGFUNC("e1000_read_phy_reg_mdic");
159
160 if (offset > MAX_PHY_REG_ADDRESS) {
161 DEBUGOUT1("PHY Address %d is out of range\n", offset);
162 ret_val = -E1000_ERR_PARAM;
163 goto out;
164 }
165
147{
148 struct e1000_phy_info *phy = &hw->phy;
149 u32 i, mdic = 0;
150 s32 ret_val = E1000_SUCCESS;
151
152 DEBUGFUNC("e1000_read_phy_reg_mdic");
153
154 if (offset > MAX_PHY_REG_ADDRESS) {
155 DEBUGOUT1("PHY Address %d is out of range\n", offset);
156 ret_val = -E1000_ERR_PARAM;
157 goto out;
158 }
159
166 /* Set up Op-code, Phy Address, and register offset in the MDI
160 /*
161 * Set up Op-code, Phy Address, and register offset in the MDI
167 * Control register. The MAC will take care of interfacing with the
168 * PHY to retrieve the desired data.
169 */
170 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
171 (phy->addr << E1000_MDIC_PHY_SHIFT) |
172 (E1000_MDIC_OP_READ));
173
174 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
175
162 * Control register. The MAC will take care of interfacing with the
163 * PHY to retrieve the desired data.
164 */
165 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
166 (phy->addr << E1000_MDIC_PHY_SHIFT) |
167 (E1000_MDIC_OP_READ));
168
169 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
170
176 /* Poll the ready bit to see if the MDI read completed */
177 for (i = 0; i < 64; i++) {
171 /*
172 * Poll the ready bit to see if the MDI read completed
173 * Increasing the time out as testing showed failures with
174 * the lower time out
175 */
176 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
178 usec_delay(50);
179 mdic = E1000_READ_REG(hw, E1000_MDIC);
180 if (mdic & E1000_MDIC_READY)
181 break;
182 }
183 if (!(mdic & E1000_MDIC_READY)) {
184 DEBUGOUT("MDI Read did not complete\n");
185 ret_val = -E1000_ERR_PHY;

--- 13 unchanged lines hidden (view full) ---

199/**
200 * e1000_write_phy_reg_mdic - Write MDI control register
201 * @hw: pointer to the HW structure
202 * @offset: register offset to write to
203 * @data: data to write to register at offset
204 *
205 * Writes data to MDI control register in the PHY at offset.
206 **/
177 usec_delay(50);
178 mdic = E1000_READ_REG(hw, E1000_MDIC);
179 if (mdic & E1000_MDIC_READY)
180 break;
181 }
182 if (!(mdic & E1000_MDIC_READY)) {
183 DEBUGOUT("MDI Read did not complete\n");
184 ret_val = -E1000_ERR_PHY;

--- 13 unchanged lines hidden (view full) ---

198/**
199 * e1000_write_phy_reg_mdic - Write MDI control register
200 * @hw: pointer to the HW structure
201 * @offset: register offset to write to
202 * @data: data to write to register at offset
203 *
204 * Writes data to MDI control register in the PHY at offset.
205 **/
207static s32
208e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
206STATIC s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
209{
210 struct e1000_phy_info *phy = &hw->phy;
211 u32 i, mdic = 0;
212 s32 ret_val = E1000_SUCCESS;
213
214 DEBUGFUNC("e1000_write_phy_reg_mdic");
215
216 if (offset > MAX_PHY_REG_ADDRESS) {
217 DEBUGOUT1("PHY Address %d is out of range\n", offset);
218 ret_val = -E1000_ERR_PARAM;
219 goto out;
220 }
221
207{
208 struct e1000_phy_info *phy = &hw->phy;
209 u32 i, mdic = 0;
210 s32 ret_val = E1000_SUCCESS;
211
212 DEBUGFUNC("e1000_write_phy_reg_mdic");
213
214 if (offset > MAX_PHY_REG_ADDRESS) {
215 DEBUGOUT1("PHY Address %d is out of range\n", offset);
216 ret_val = -E1000_ERR_PARAM;
217 goto out;
218 }
219
222 /* Set up Op-code, Phy Address, and register offset in the MDI
220 /*
221 * Set up Op-code, Phy Address, and register offset in the MDI
223 * Control register. The MAC will take care of interfacing with the
224 * PHY to retrieve the desired data.
225 */
226 mdic = (((u32)data) |
227 (offset << E1000_MDIC_REG_SHIFT) |
228 (phy->addr << E1000_MDIC_PHY_SHIFT) |
229 (E1000_MDIC_OP_WRITE));
230
231 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
232
222 * Control register. The MAC will take care of interfacing with the
223 * PHY to retrieve the desired data.
224 */
225 mdic = (((u32)data) |
226 (offset << E1000_MDIC_REG_SHIFT) |
227 (phy->addr << E1000_MDIC_PHY_SHIFT) |
228 (E1000_MDIC_OP_WRITE));
229
230 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
231
233 /* Poll the ready bit to see if the MDI read completed */
234 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
235 usec_delay(5);
232 /*
233 * Poll the ready bit to see if the MDI read completed
234 * Increasing the time out as testing showed failures with
235 * the lower time out
236 */
237 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
238 usec_delay(50);
236 mdic = E1000_READ_REG(hw, E1000_MDIC);
237 if (mdic & E1000_MDIC_READY)
238 break;
239 }
240 if (!(mdic & E1000_MDIC_READY)) {
241 DEBUGOUT("MDI Write did not complete\n");
242 ret_val = -E1000_ERR_PHY;
243 goto out;
244 }
239 mdic = E1000_READ_REG(hw, E1000_MDIC);
240 if (mdic & E1000_MDIC_READY)
241 break;
242 }
243 if (!(mdic & E1000_MDIC_READY)) {
244 DEBUGOUT("MDI Write did not complete\n");
245 ret_val = -E1000_ERR_PHY;
246 goto out;
247 }
248 if (mdic & E1000_MDIC_ERROR) {
249 DEBUGOUT("MDI Error\n");
250 ret_val = -E1000_ERR_PHY;
251 goto out;
252 }
245
246out:
247 return ret_val;
248}
249
250/**
251 * e1000_read_phy_reg_m88 - Read m88 PHY register
252 * @hw: pointer to the HW structure
253 * @offset: register offset to be read
254 * @data: pointer to the read data
255 *
256 * Acquires semaphore, if necessary, then reads the PHY register at offset
257 * and storing the retrieved information in data. Release any acquired
258 * semaphores before exiting.
259 **/
253
254out:
255 return ret_val;
256}
257
258/**
259 * e1000_read_phy_reg_m88 - Read m88 PHY register
260 * @hw: pointer to the HW structure
261 * @offset: register offset to be read
262 * @data: pointer to the read data
263 *
264 * Acquires semaphore, if necessary, then reads the PHY register at offset
265 * and storing the retrieved information in data. Release any acquired
266 * semaphores before exiting.
267 **/
260s32
261e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
268s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
262{
263 s32 ret_val;
264
265 DEBUGFUNC("e1000_read_phy_reg_m88");
266
267 ret_val = e1000_acquire_phy(hw);
268 if (ret_val)
269 goto out;

--- 12 unchanged lines hidden (view full) ---

282 * e1000_write_phy_reg_m88 - Write m88 PHY register
283 * @hw: pointer to the HW structure
284 * @offset: register offset to write to
285 * @data: data to write at register offset
286 *
287 * Acquires semaphore, if necessary, then writes the data to PHY register
288 * at the offset. Release any acquired semaphores before exiting.
289 **/
269{
270 s32 ret_val;
271
272 DEBUGFUNC("e1000_read_phy_reg_m88");
273
274 ret_val = e1000_acquire_phy(hw);
275 if (ret_val)
276 goto out;

--- 12 unchanged lines hidden (view full) ---

289 * e1000_write_phy_reg_m88 - Write m88 PHY register
290 * @hw: pointer to the HW structure
291 * @offset: register offset to write to
292 * @data: data to write at register offset
293 *
294 * Acquires semaphore, if necessary, then writes the data to PHY register
295 * at the offset. Release any acquired semaphores before exiting.
296 **/
290s32
291e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
297s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
292{
293 s32 ret_val;
294
295 DEBUGFUNC("e1000_write_phy_reg_m88");
296
297 ret_val = e1000_acquire_phy(hw);
298 if (ret_val)
299 goto out;

--- 13 unchanged lines hidden (view full) ---

313 * @hw: pointer to the HW structure
314 * @offset: register offset to be read
315 * @data: pointer to the read data
316 *
317 * Acquires semaphore, if necessary, then reads the PHY register at offset
318 * and storing the retrieved information in data. Release any acquired
319 * semaphores before exiting.
320 **/
298{
299 s32 ret_val;
300
301 DEBUGFUNC("e1000_write_phy_reg_m88");
302
303 ret_val = e1000_acquire_phy(hw);
304 if (ret_val)
305 goto out;

--- 13 unchanged lines hidden (view full) ---

319 * @hw: pointer to the HW structure
320 * @offset: register offset to be read
321 * @data: pointer to the read data
322 *
323 * Acquires semaphore, if necessary, then reads the PHY register at offset
324 * and storing the retrieved information in data. Release any acquired
325 * semaphores before exiting.
326 **/
321s32
322e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
327s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
323{
324 s32 ret_val;
325
326 DEBUGFUNC("e1000_read_phy_reg_igp");
327
328 ret_val = e1000_acquire_phy(hw);
329 if (ret_val)
330 goto out;

--- 22 unchanged lines hidden (view full) ---

353 * e1000_write_phy_reg_igp - Write igp PHY register
354 * @hw: pointer to the HW structure
355 * @offset: register offset to write to
356 * @data: data to write at register offset
357 *
358 * Acquires semaphore, if necessary, then writes the data to PHY register
359 * at the offset. Release any acquired semaphores before exiting.
360 **/
328{
329 s32 ret_val;
330
331 DEBUGFUNC("e1000_read_phy_reg_igp");
332
333 ret_val = e1000_acquire_phy(hw);
334 if (ret_val)
335 goto out;

--- 22 unchanged lines hidden (view full) ---

358 * e1000_write_phy_reg_igp - Write igp PHY register
359 * @hw: pointer to the HW structure
360 * @offset: register offset to write to
361 * @data: data to write at register offset
362 *
363 * Acquires semaphore, if necessary, then writes the data to PHY register
364 * at the offset. Release any acquired semaphores before exiting.
365 **/
361s32
362e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
366s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
363{
364 s32 ret_val;
365
366 DEBUGFUNC("e1000_write_phy_reg_igp");
367
368 ret_val = e1000_acquire_phy(hw);
369 if (ret_val)
370 goto out;

--- 23 unchanged lines hidden (view full) ---

394 * @hw: pointer to the HW structure
395 * @offset: register offset to be read
396 * @data: pointer to the read data
397 *
398 * Acquires semaphore, if necessary. Then reads the PHY register at offset
399 * using the kumeran interface. The information retrieved is stored in data.
400 * Release any acquired semaphores before exiting.
401 **/
367{
368 s32 ret_val;
369
370 DEBUGFUNC("e1000_write_phy_reg_igp");
371
372 ret_val = e1000_acquire_phy(hw);
373 if (ret_val)
374 goto out;

--- 23 unchanged lines hidden (view full) ---

398 * @hw: pointer to the HW structure
399 * @offset: register offset to be read
400 * @data: pointer to the read data
401 *
402 * Acquires semaphore, if necessary. Then reads the PHY register at offset
403 * using the kumeran interface. The information retrieved is stored in data.
404 * Release any acquired semaphores before exiting.
405 **/
402s32
403e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
406s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
404{
405 u32 kmrnctrlsta;
406 s32 ret_val;
407
408 DEBUGFUNC("e1000_read_kmrn_reg_generic");
409
410 ret_val = e1000_acquire_phy(hw);
411 if (ret_val)

--- 19 unchanged lines hidden (view full) ---

431 * @hw: pointer to the HW structure
432 * @offset: register offset to write to
433 * @data: data to write at register offset
434 *
435 * Acquires semaphore, if necessary. Then write the data to PHY register
436 * at the offset using the kumeran interface. Release any acquired semaphores
437 * before exiting.
438 **/
407{
408 u32 kmrnctrlsta;
409 s32 ret_val;
410
411 DEBUGFUNC("e1000_read_kmrn_reg_generic");
412
413 ret_val = e1000_acquire_phy(hw);
414 if (ret_val)

--- 19 unchanged lines hidden (view full) ---

434 * @hw: pointer to the HW structure
435 * @offset: register offset to write to
436 * @data: data to write at register offset
437 *
438 * Acquires semaphore, if necessary. Then write the data to PHY register
439 * at the offset using the kumeran interface. Release any acquired semaphores
440 * before exiting.
441 **/
439s32
440e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
442s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
441{
442 u32 kmrnctrlsta;
443 s32 ret_val;
444
445 DEBUGFUNC("e1000_write_kmrn_reg_generic");
446
447 ret_val = e1000_acquire_phy(hw);
448 if (ret_val)

--- 12 unchanged lines hidden (view full) ---

461
462/**
463 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
464 * @hw: pointer to the HW structure
465 *
466 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
467 * and downshift values are set also.
468 **/
443{
444 u32 kmrnctrlsta;
445 s32 ret_val;
446
447 DEBUGFUNC("e1000_write_kmrn_reg_generic");
448
449 ret_val = e1000_acquire_phy(hw);
450 if (ret_val)

--- 12 unchanged lines hidden (view full) ---

463
464/**
465 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
466 * @hw: pointer to the HW structure
467 *
468 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
469 * and downshift values are set also.
470 **/
469s32
470e1000_copper_link_setup_m88(struct e1000_hw *hw)
471s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
471{
472 struct e1000_phy_info *phy = &hw->phy;
473 s32 ret_val;
474 u16 phy_data;
475
476 DEBUGFUNC("e1000_copper_link_setup_m88");
477
478 if (phy->reset_disable) {
479 ret_val = E1000_SUCCESS;
480 goto out;
481 }
482
483 /* Enable CRS on TX. This must be set for half-duplex operation. */
484 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
485 if (ret_val)
486 goto out;
487
488 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
489
472{
473 struct e1000_phy_info *phy = &hw->phy;
474 s32 ret_val;
475 u16 phy_data;
476
477 DEBUGFUNC("e1000_copper_link_setup_m88");
478
479 if (phy->reset_disable) {
480 ret_val = E1000_SUCCESS;
481 goto out;
482 }
483
484 /* Enable CRS on TX. This must be set for half-duplex operation. */
485 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
486 if (ret_val)
487 goto out;
488
489 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
490
490 /* Options:
491 /*
492 * Options:
491 * MDI/MDI-X = 0 (default)
492 * 0 - Auto for all speeds
493 * 1 - MDI mode
494 * 2 - MDI-X mode
495 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
496 */
497 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
498

--- 8 unchanged lines hidden (view full) ---

507 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
508 break;
509 case 0:
510 default:
511 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
512 break;
513 }
514
493 * MDI/MDI-X = 0 (default)
494 * 0 - Auto for all speeds
495 * 1 - MDI mode
496 * 2 - MDI-X mode
497 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
498 */
499 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
500

--- 8 unchanged lines hidden (view full) ---

509 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
510 break;
511 case 0:
512 default:
513 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
514 break;
515 }
516
515 /* Options:
517 /*
518 * Options:
516 * disable_polarity_correction = 0 (default)
517 * Automatic Correction for Reversed Cable Polarity
518 * 0 - Disabled
519 * 1 - Enabled
520 */
521 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
522 if (phy->disable_polarity_correction == 1)
523 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
524
525 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
526 if (ret_val)
527 goto out;
528
529 if (phy->revision < E1000_REVISION_4) {
519 * disable_polarity_correction = 0 (default)
520 * Automatic Correction for Reversed Cable Polarity
521 * 0 - Disabled
522 * 1 - Enabled
523 */
524 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
525 if (phy->disable_polarity_correction == 1)
526 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
527
528 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
529 if (ret_val)
530 goto out;
531
532 if (phy->revision < E1000_REVISION_4) {
530 /* Force TX_CLK in the Extended PHY Specific Control Register
533 /*
534 * Force TX_CLK in the Extended PHY Specific Control Register
531 * to 25MHz clock.
532 */
533 ret_val = e1000_read_phy_reg(hw,
534 M88E1000_EXT_PHY_SPEC_CTRL,
535 &phy_data);
536 if (ret_val)
537 goto out;
538

--- 31 unchanged lines hidden (view full) ---

570
571/**
572 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
573 * @hw: pointer to the HW structure
574 *
575 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
576 * igp PHY's.
577 **/
535 * to 25MHz clock.
536 */
537 ret_val = e1000_read_phy_reg(hw,
538 M88E1000_EXT_PHY_SPEC_CTRL,
539 &phy_data);
540 if (ret_val)
541 goto out;
542

--- 31 unchanged lines hidden (view full) ---

574
575/**
576 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
577 * @hw: pointer to the HW structure
578 *
579 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
580 * igp PHY's.
581 **/
578s32
579e1000_copper_link_setup_igp(struct e1000_hw *hw)
582s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
580{
581 struct e1000_phy_info *phy = &hw->phy;
582 s32 ret_val;
583 u16 data;
584
585 DEBUGFUNC("e1000_copper_link_setup_igp");
586
587 if (phy->reset_disable) {

--- 5 unchanged lines hidden (view full) ---

593 if (ret_val) {
594 DEBUGOUT("Error resetting the PHY.\n");
595 goto out;
596 }
597
598 /* Wait 15ms for MAC to configure PHY from NVM settings. */
599 msec_delay(15);
600
583{
584 struct e1000_phy_info *phy = &hw->phy;
585 s32 ret_val;
586 u16 data;
587
588 DEBUGFUNC("e1000_copper_link_setup_igp");
589
590 if (phy->reset_disable) {

--- 5 unchanged lines hidden (view full) ---

596 if (ret_val) {
597 DEBUGOUT("Error resetting the PHY.\n");
598 goto out;
599 }
600
601 /* Wait 15ms for MAC to configure PHY from NVM settings. */
602 msec_delay(15);
603
601 /* The NVM settings will configure LPLU in D3 for
602 * non-IGP1 PHYs. */
604 /*
605 * The NVM settings will configure LPLU in D3 for
606 * non-IGP1 PHYs.
607 */
603 if (phy->type == e1000_phy_igp) {
604 /* disable lplu d3 during driver init */
605 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
606 if (ret_val) {
607 DEBUGOUT("Error Disabling LPLU D3\n");
608 goto out;
609 }
610 }

--- 24 unchanged lines hidden (view full) ---

635 break;
636 }
637 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
638 if (ret_val)
639 goto out;
640
641 /* set auto-master slave resolution settings */
642 if (hw->mac.autoneg) {
608 if (phy->type == e1000_phy_igp) {
609 /* disable lplu d3 during driver init */
610 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
611 if (ret_val) {
612 DEBUGOUT("Error Disabling LPLU D3\n");
613 goto out;
614 }
615 }

--- 24 unchanged lines hidden (view full) ---

640 break;
641 }
642 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
643 if (ret_val)
644 goto out;
645
646 /* set auto-master slave resolution settings */
647 if (hw->mac.autoneg) {
643 /* when autonegotiation advertisement is only 1000Mbps then we
648 /*
649 * when autonegotiation advertisement is only 1000Mbps then we
644 * should disable SmartSpeed and enable Auto MasterSlave
650 * should disable SmartSpeed and enable Auto MasterSlave
645 * resolution as hardware default. */
651 * resolution as hardware default.
652 */
646 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
647 /* Disable SmartSpeed */
648 ret_val = e1000_read_phy_reg(hw,
649 IGP01E1000_PHY_PORT_CONFIG,
650 &data);
651 if (ret_val)
652 goto out;
653

--- 50 unchanged lines hidden (view full) ---

704
705/**
706 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
707 * @hw: pointer to the HW structure
708 *
709 * Performs initial bounds checking on autoneg advertisement parameter, then
710 * configure to advertise the full capability. Setup the PHY to autoneg
711 * and restart the negotiation process between the link partner. If
653 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
654 /* Disable SmartSpeed */
655 ret_val = e1000_read_phy_reg(hw,
656 IGP01E1000_PHY_PORT_CONFIG,
657 &data);
658 if (ret_val)
659 goto out;
660

--- 50 unchanged lines hidden (view full) ---

711
712/**
713 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
714 * @hw: pointer to the HW structure
715 *
716 * Performs initial bounds checking on autoneg advertisement parameter, then
717 * configure to advertise the full capability. Setup the PHY to autoneg
718 * and restart the negotiation process between the link partner. If
712 * wait_for_link, then wait for autoneg to complete before exiting.
719 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
713 **/
720 **/
714s32
715e1000_copper_link_autoneg(struct e1000_hw *hw)
721s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
716{
717 struct e1000_phy_info *phy = &hw->phy;
718 s32 ret_val;
719 u16 phy_ctrl;
720
721 DEBUGFUNC("e1000_copper_link_autoneg");
722
722{
723 struct e1000_phy_info *phy = &hw->phy;
724 s32 ret_val;
725 u16 phy_ctrl;
726
727 DEBUGFUNC("e1000_copper_link_autoneg");
728
723 /* Perform some bounds checking on the autoneg advertisement
729 /*
730 * Perform some bounds checking on the autoneg advertisement
724 * parameter.
725 */
726 phy->autoneg_advertised &= phy->autoneg_mask;
727
731 * parameter.
732 */
733 phy->autoneg_advertised &= phy->autoneg_mask;
734
728 /* If autoneg_advertised is zero, we assume it was not defaulted
735 /*
736 * If autoneg_advertised is zero, we assume it was not defaulted
729 * by the calling code so we set to advertise full capability.
730 */
731 if (phy->autoneg_advertised == 0)
732 phy->autoneg_advertised = phy->autoneg_mask;
733
734 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
735 ret_val = e1000_phy_setup_autoneg(hw);
736 if (ret_val) {
737 DEBUGOUT("Error Setting up Auto-Negotiation\n");
738 goto out;
739 }
740 DEBUGOUT("Restarting Auto-Neg\n");
741
737 * by the calling code so we set to advertise full capability.
738 */
739 if (phy->autoneg_advertised == 0)
740 phy->autoneg_advertised = phy->autoneg_mask;
741
742 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
743 ret_val = e1000_phy_setup_autoneg(hw);
744 if (ret_val) {
745 DEBUGOUT("Error Setting up Auto-Negotiation\n");
746 goto out;
747 }
748 DEBUGOUT("Restarting Auto-Neg\n");
749
742 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
750 /*
751 * Restart auto-negotiation by setting the Auto Neg Enable bit and
743 * the Auto Neg Restart bit in the PHY control register.
744 */
745 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
746 if (ret_val)
747 goto out;
748
749 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
750 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
751 if (ret_val)
752 goto out;
753
752 * the Auto Neg Restart bit in the PHY control register.
753 */
754 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
755 if (ret_val)
756 goto out;
757
758 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
759 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
760 if (ret_val)
761 goto out;
762
754 /* Does the user want to wait for Auto-Neg to complete here, or
763 /*
764 * Does the user want to wait for Auto-Neg to complete here, or
755 * check at a later time (for example, callback routine).
756 */
765 * check at a later time (for example, callback routine).
766 */
757 if (phy->wait_for_link) {
767 if (phy->autoneg_wait_to_complete) {
758 ret_val = e1000_wait_autoneg(hw);
759 if (ret_val) {
760 DEBUGOUT("Error while waiting for "
761 "autoneg to complete\n");
762 goto out;
763 }
764 }
765

--- 7 unchanged lines hidden (view full) ---

773 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
774 * @hw: pointer to the HW structure
775 *
776 * Reads the MII auto-neg advertisement register and/or the 1000T control
777 * register and if the PHY is already setup for auto-negotiation, then
778 * return successful. Otherwise, setup advertisement and flow control to
779 * the appropriate values for the wanted auto-negotiation.
780 **/
768 ret_val = e1000_wait_autoneg(hw);
769 if (ret_val) {
770 DEBUGOUT("Error while waiting for "
771 "autoneg to complete\n");
772 goto out;
773 }
774 }
775

--- 7 unchanged lines hidden (view full) ---

783 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
784 * @hw: pointer to the HW structure
785 *
786 * Reads the MII auto-neg advertisement register and/or the 1000T control
787 * register and if the PHY is already setup for auto-negotiation, then
788 * return successful. Otherwise, setup advertisement and flow control to
789 * the appropriate values for the wanted auto-negotiation.
790 **/
781s32
782e1000_phy_setup_autoneg(struct e1000_hw *hw)
791s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
783{
784 struct e1000_phy_info *phy = &hw->phy;
785 s32 ret_val;
786 u16 mii_autoneg_adv_reg;
787 u16 mii_1000t_ctrl_reg = 0;
788
789 DEBUGFUNC("e1000_phy_setup_autoneg");
790

--- 8 unchanged lines hidden (view full) ---

799 /* Read the MII 1000Base-T Control Register (Address 9). */
800 ret_val = e1000_read_phy_reg(hw,
801 PHY_1000T_CTRL,
802 &mii_1000t_ctrl_reg);
803 if (ret_val)
804 goto out;
805 }
806
792{
793 struct e1000_phy_info *phy = &hw->phy;
794 s32 ret_val;
795 u16 mii_autoneg_adv_reg;
796 u16 mii_1000t_ctrl_reg = 0;
797
798 DEBUGFUNC("e1000_phy_setup_autoneg");
799

--- 8 unchanged lines hidden (view full) ---

808 /* Read the MII 1000Base-T Control Register (Address 9). */
809 ret_val = e1000_read_phy_reg(hw,
810 PHY_1000T_CTRL,
811 &mii_1000t_ctrl_reg);
812 if (ret_val)
813 goto out;
814 }
815
807 /* Need to parse both autoneg_advertised and fc and set up
816 /*
817 * Need to parse both autoneg_advertised and fc and set up
808 * the appropriate PHY registers. First we will parse for
809 * autoneg_advertised software override. Since we can advertise
810 * a plethora of combinations, we need to check each bit
811 * individually.
812 */
813
818 * the appropriate PHY registers. First we will parse for
819 * autoneg_advertised software override. Since we can advertise
820 * a plethora of combinations, we need to check each bit
821 * individually.
822 */
823
814 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
824 /*
825 * First we clear all the 10/100 mb speed bits in the Auto-Neg
815 * Advertisement Register (Address 4) and the 1000 mb speed bits in
816 * the 1000Base-T Control Register (Address 9).
817 */
818 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
819 NWAY_AR_100TX_HD_CAPS |
820 NWAY_AR_10T_FD_CAPS |
821 NWAY_AR_10T_HD_CAPS);
822 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);

--- 30 unchanged lines hidden (view full) ---

853 }
854
855 /* Do we want to advertise 1000 Mb Full Duplex? */
856 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
857 DEBUGOUT("Advertise 1000mb Full duplex\n");
858 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
859 }
860
826 * Advertisement Register (Address 4) and the 1000 mb speed bits in
827 * the 1000Base-T Control Register (Address 9).
828 */
829 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
830 NWAY_AR_100TX_HD_CAPS |
831 NWAY_AR_10T_FD_CAPS |
832 NWAY_AR_10T_HD_CAPS);
833 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);

--- 30 unchanged lines hidden (view full) ---

864 }
865
866 /* Do we want to advertise 1000 Mb Full Duplex? */
867 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
868 DEBUGOUT("Advertise 1000mb Full duplex\n");
869 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
870 }
871
861 /* Check for a software override of the flow control settings, and
872 /*
873 * Check for a software override of the flow control settings, and
862 * setup the PHY advertisement registers accordingly. If
863 * auto-negotiation is enabled, then software will have to set the
864 * "PAUSE" bits to the correct value in the Auto-Negotiation
865 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
866 * negotiation.
867 *
868 * The possible values of the "fc" parameter are:
869 * 0: Flow control is completely disabled
870 * 1: Rx flow control is enabled (we can receive pause frames
871 * but not send pause frames).
872 * 2: Tx flow control is enabled (we can send pause frames
873 * but we do not support receiving pause frames).
874 * setup the PHY advertisement registers accordingly. If
875 * auto-negotiation is enabled, then software will have to set the
876 * "PAUSE" bits to the correct value in the Auto-Negotiation
877 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
878 * negotiation.
879 *
880 * The possible values of the "fc" parameter are:
881 * 0: Flow control is completely disabled
882 * 1: Rx flow control is enabled (we can receive pause frames
883 * but not send pause frames).
884 * 2: Tx flow control is enabled (we can send pause frames
885 * but we do not support receiving pause frames).
874 * 3: Both Rx and TX flow control (symmetric) are enabled.
886 * 3: Both Rx and Tx flow control (symmetric) are enabled.
875 * other: No software override. The flow control configuration
876 * in the EEPROM is used.
877 */
887 * other: No software override. The flow control configuration
888 * in the EEPROM is used.
889 */
878 switch (hw->mac.fc) {
890 switch (hw->fc.type) {
879 case e1000_fc_none:
891 case e1000_fc_none:
880 /* Flow control (RX & TX) is completely disabled by a
892 /*
893 * Flow control (Rx & Tx) is completely disabled by a
881 * software over-ride.
882 */
883 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
884 break;
885 case e1000_fc_rx_pause:
894 * software over-ride.
895 */
896 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
897 break;
898 case e1000_fc_rx_pause:
886 /* RX Flow control is enabled, and TX Flow control is
899 /*
900 * Rx Flow control is enabled, and Tx Flow control is
887 * disabled, by a software over-ride.
901 * disabled, by a software over-ride.
888 */
889 /* Since there really isn't a way to advertise that we are
890 * capable of RX Pause ONLY, we will advertise that we
891 * support both symmetric and asymmetric RX PAUSE. Later
902 *
903 * Since there really isn't a way to advertise that we are
904 * capable of Rx Pause ONLY, we will advertise that we
905 * support both symmetric and asymmetric Rx PAUSE. Later
892 * (in e1000_config_fc_after_link_up) we will disable the
893 * hw's ability to send PAUSE frames.
894 */
895 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
896 break;
897 case e1000_fc_tx_pause:
906 * (in e1000_config_fc_after_link_up) we will disable the
907 * hw's ability to send PAUSE frames.
908 */
909 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
910 break;
911 case e1000_fc_tx_pause:
898 /* TX Flow control is enabled, and RX Flow control is
912 /*
913 * Tx Flow control is enabled, and Rx Flow control is
899 * disabled, by a software over-ride.
900 */
901 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
902 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
903 break;
904 case e1000_fc_full:
914 * disabled, by a software over-ride.
915 */
916 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
917 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
918 break;
919 case e1000_fc_full:
905 /* Flow control (both RX and TX) is enabled by a software
920 /*
921 * Flow control (both Rx and Tx) is enabled by a software
906 * over-ride.
907 */
908 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
909 break;
910 default:
911 DEBUGOUT("Flow control param set incorrectly\n");
912 ret_val = -E1000_ERR_CONFIG;
913 goto out;

--- 21 unchanged lines hidden (view full) ---

935 * e1000_setup_copper_link_generic - Configure copper link settings
936 * @hw: pointer to the HW structure
937 *
938 * Calls the appropriate function to configure the link for auto-neg or forced
939 * speed and duplex. Then we check for link, once link is established calls
940 * to configure collision distance and flow control are called. If link is
941 * not established, we return -E1000_ERR_PHY (-2).
942 **/
922 * over-ride.
923 */
924 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
925 break;
926 default:
927 DEBUGOUT("Flow control param set incorrectly\n");
928 ret_val = -E1000_ERR_CONFIG;
929 goto out;

--- 21 unchanged lines hidden (view full) ---

951 * e1000_setup_copper_link_generic - Configure copper link settings
952 * @hw: pointer to the HW structure
953 *
954 * Calls the appropriate function to configure the link for auto-neg or forced
955 * speed and duplex. Then we check for link, once link is established calls
956 * to configure collision distance and flow control are called. If link is
957 * not established, we return -E1000_ERR_PHY (-2).
958 **/
943s32
944e1000_setup_copper_link_generic(struct e1000_hw *hw)
959s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
945{
946 s32 ret_val;
960{
961 s32 ret_val;
947 boolean_t link;
962 bool link;
948
949 DEBUGFUNC("e1000_setup_copper_link_generic");
950
951 if (hw->mac.autoneg) {
963
964 DEBUGFUNC("e1000_setup_copper_link_generic");
965
966 if (hw->mac.autoneg) {
952 /* Setup autoneg and flow control advertisement and perform
953 * autonegotiation. */
967 /*
968 * Setup autoneg and flow control advertisement and perform
969 * autonegotiation.
970 */
954 ret_val = e1000_copper_link_autoneg(hw);
955 if (ret_val)
956 goto out;
957 } else {
971 ret_val = e1000_copper_link_autoneg(hw);
972 if (ret_val)
973 goto out;
974 } else {
958 /* PHY will be set to 10H, 10F, 100H or 100F
959 * depending on user settings. */
975 /*
976 * PHY will be set to 10H, 10F, 100H or 100F
977 * depending on user settings.
978 */
960 DEBUGOUT("Forcing Speed and Duplex\n");
961 ret_val = e1000_phy_force_speed_duplex(hw);
962 if (ret_val) {
963 DEBUGOUT("Error Forcing Speed and Duplex\n");
964 goto out;
965 }
966 }
967
979 DEBUGOUT("Forcing Speed and Duplex\n");
980 ret_val = e1000_phy_force_speed_duplex(hw);
981 if (ret_val) {
982 DEBUGOUT("Error Forcing Speed and Duplex\n");
983 goto out;
984 }
985 }
986
968 /* Check link status. Wait up to 100 microseconds for link to become
987 /*
988 * Check link status. Wait up to 100 microseconds for link to become
969 * valid.
970 */
971 ret_val = e1000_phy_has_link_generic(hw,
972 COPPER_LINK_UP_LIMIT,
973 10,
974 &link);
975 if (ret_val)
976 goto out;

--- 13 unchanged lines hidden (view full) ---

990/**
991 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
992 * @hw: pointer to the HW structure
993 *
994 * Calls the PHY setup function to force speed and duplex. Clears the
995 * auto-crossover to force MDI manually. Waits for link and returns
996 * successful if link up is successful, else -E1000_ERR_PHY (-2).
997 **/
989 * valid.
990 */
991 ret_val = e1000_phy_has_link_generic(hw,
992 COPPER_LINK_UP_LIMIT,
993 10,
994 &link);
995 if (ret_val)
996 goto out;

--- 13 unchanged lines hidden (view full) ---

1010/**
1011 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1012 * @hw: pointer to the HW structure
1013 *
1014 * Calls the PHY setup function to force speed and duplex. Clears the
1015 * auto-crossover to force MDI manually. Waits for link and returns
1016 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1017 **/
998s32
999e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1018s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1000{
1001 struct e1000_phy_info *phy = &hw->phy;
1002 s32 ret_val;
1003 u16 phy_data;
1019{
1020 struct e1000_phy_info *phy = &hw->phy;
1021 s32 ret_val;
1022 u16 phy_data;
1004 boolean_t link;
1023 bool link;
1005
1006 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1007
1008 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data);
1009 if (ret_val)
1010 goto out;
1011
1012 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1013
1014 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data);
1015 if (ret_val)
1016 goto out;
1017
1024
1025 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1026
1027 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data);
1028 if (ret_val)
1029 goto out;
1030
1031 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1032
1033 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data);
1034 if (ret_val)
1035 goto out;
1036
1018 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1037 /*
1038 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1019 * forced whenever speed and duplex are forced.
1020 */
1021 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1022 if (ret_val)
1023 goto out;
1024
1025 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1026 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1027
1028 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1029 if (ret_val)
1030 goto out;
1031
1032 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1033
1034 usec_delay(1);
1035
1039 * forced whenever speed and duplex are forced.
1040 */
1041 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1042 if (ret_val)
1043 goto out;
1044
1045 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1046 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1047
1048 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1049 if (ret_val)
1050 goto out;
1051
1052 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1053
1054 usec_delay(1);
1055
1036 if (phy->wait_for_link) {
1056 if (phy->autoneg_wait_to_complete) {
1037 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1038
1039 ret_val = e1000_phy_has_link_generic(hw,
1040 PHY_FORCE_LIMIT,
1041 100000,
1042 &link);
1043 if (ret_val)
1044 goto out;

--- 17 unchanged lines hidden (view full) ---

1062
1063/**
1064 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1065 * @hw: pointer to the HW structure
1066 *
1067 * Calls the PHY setup function to force speed and duplex. Clears the
1068 * auto-crossover to force MDI manually. Resets the PHY to commit the
1069 * changes. If time expires while waiting for link up, we reset the DSP.
1057 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1058
1059 ret_val = e1000_phy_has_link_generic(hw,
1060 PHY_FORCE_LIMIT,
1061 100000,
1062 &link);
1063 if (ret_val)
1064 goto out;

--- 17 unchanged lines hidden (view full) ---

1082
1083/**
1084 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1085 * @hw: pointer to the HW structure
1086 *
1087 * Calls the PHY setup function to force speed and duplex. Clears the
1088 * auto-crossover to force MDI manually. Resets the PHY to commit the
1089 * changes. If time expires while waiting for link up, we reset the DSP.
1070 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
1090 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1071 * successful completion, else return corresponding error code.
1072 **/
1091 * successful completion, else return corresponding error code.
1092 **/
1073s32
1074e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1093s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1075{
1076 struct e1000_phy_info *phy = &hw->phy;
1077 s32 ret_val;
1078 u16 phy_data;
1094{
1095 struct e1000_phy_info *phy = &hw->phy;
1096 s32 ret_val;
1097 u16 phy_data;
1079 boolean_t link;
1098 bool link;
1080
1081 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1082
1099
1100 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1101
1083 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1102 /*
1103 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1084 * forced whenever speed and duplex are forced.
1085 */
1086 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1087 if (ret_val)
1088 goto out;
1089
1090 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1091 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

--- 12 unchanged lines hidden (view full) ---

1104 phy_data |= MII_CR_RESET;
1105
1106 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data);
1107 if (ret_val)
1108 goto out;
1109
1110 usec_delay(1);
1111
1104 * forced whenever speed and duplex are forced.
1105 */
1106 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1107 if (ret_val)
1108 goto out;
1109
1110 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1111 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

--- 12 unchanged lines hidden (view full) ---

1124 phy_data |= MII_CR_RESET;
1125
1126 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data);
1127 if (ret_val)
1128 goto out;
1129
1130 usec_delay(1);
1131
1112 if (phy->wait_for_link) {
1132 if (phy->autoneg_wait_to_complete) {
1113 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1114
1115 ret_val = e1000_phy_has_link_generic(hw,
1116 PHY_FORCE_LIMIT,
1117 100000,
1118 &link);
1119 if (ret_val)
1120 goto out;
1121
1122 if (!link) {
1133 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1134
1135 ret_val = e1000_phy_has_link_generic(hw,
1136 PHY_FORCE_LIMIT,
1137 100000,
1138 &link);
1139 if (ret_val)
1140 goto out;
1141
1142 if (!link) {
1123 /* We didn't get link.
1143 /*
1144 * We didn't get link.
1124 * Reset the DSP and cross our fingers.
1125 */
1126 ret_val = e1000_write_phy_reg(hw,
1127 M88E1000_PHY_PAGE_SELECT,
1128 0x001d);
1129 if (ret_val)
1130 goto out;
1131 ret_val = e1000_phy_reset_dsp_generic(hw);

--- 9 unchanged lines hidden (view full) ---

1141 if (ret_val)
1142 goto out;
1143 }
1144
1145 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1146 if (ret_val)
1147 goto out;
1148
1145 * Reset the DSP and cross our fingers.
1146 */
1147 ret_val = e1000_write_phy_reg(hw,
1148 M88E1000_PHY_PAGE_SELECT,
1149 0x001d);
1150 if (ret_val)
1151 goto out;
1152 ret_val = e1000_phy_reset_dsp_generic(hw);

--- 9 unchanged lines hidden (view full) ---

1162 if (ret_val)
1163 goto out;
1164 }
1165
1166 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1167 if (ret_val)
1168 goto out;
1169
1149 /* Resetting the phy means we need to re-force TX_CLK in the
1170 /*
1171 * Resetting the phy means we need to re-force TX_CLK in the
1150 * Extended PHY Specific Control Register to 25MHz clock from
1151 * the reset value of 2.5MHz.
1152 */
1153 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1154 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1155 if (ret_val)
1156 goto out;
1157
1172 * Extended PHY Specific Control Register to 25MHz clock from
1173 * the reset value of 2.5MHz.
1174 */
1175 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1176 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1177 if (ret_val)
1178 goto out;
1179
1158 /* In addition, we must re-enable CRS on Tx for both half and full
1180 /*
1181 * In addition, we must re-enable CRS on Tx for both half and full
1159 * duplex.
1160 */
1161 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1162 if (ret_val)
1163 goto out;
1164
1165 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1166 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

--- 9 unchanged lines hidden (view full) ---

1176 *
1177 * Forces speed and duplex on the PHY by doing the following: disable flow
1178 * control, force speed/duplex on the MAC, disable auto speed detection,
1179 * disable auto-negotiation, configure duplex, configure speed, configure
1180 * the collision distance, write configuration to CTRL register. The
1181 * caller must write to the PHY_CONTROL register for these settings to
1182 * take affect.
1183 **/
1182 * duplex.
1183 */
1184 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1185 if (ret_val)
1186 goto out;
1187
1188 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1189 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

--- 9 unchanged lines hidden (view full) ---

1199 *
1200 * Forces speed and duplex on the PHY by doing the following: disable flow
1201 * control, force speed/duplex on the MAC, disable auto speed detection,
1202 * disable auto-negotiation, configure duplex, configure speed, configure
1203 * the collision distance, write configuration to CTRL register. The
1204 * caller must write to the PHY_CONTROL register for these settings to
1205 * take affect.
1206 **/
1184void
1185e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1207void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1186{
1187 struct e1000_mac_info *mac = &hw->mac;
1188 u32 ctrl;
1189
1190 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1191
1192 /* Turn off flow control when forcing speed/duplex */
1208{
1209 struct e1000_mac_info *mac = &hw->mac;
1210 u32 ctrl;
1211
1212 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1213
1214 /* Turn off flow control when forcing speed/duplex */
1193 mac->fc = e1000_fc_none;
1215 hw->fc.type = e1000_fc_none;
1194
1195 /* Force speed/duplex on the mac */
1196 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1197 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1198 ctrl &= ~E1000_CTRL_SPD_SEL;
1199
1200 /* Disable Auto Speed Detection */
1201 ctrl &= ~E1000_CTRL_ASDE;

--- 39 unchanged lines hidden (view full) ---

1241 *
1242 * The low power link up (lplu) state is set to the power management level D3
1243 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1244 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1245 * is used during Dx states where the power conservation is most important.
1246 * During driver activity, SmartSpeed should be enabled so performance is
1247 * maintained.
1248 **/
1216
1217 /* Force speed/duplex on the mac */
1218 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1219 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1220 ctrl &= ~E1000_CTRL_SPD_SEL;
1221
1222 /* Disable Auto Speed Detection */
1223 ctrl &= ~E1000_CTRL_ASDE;

--- 39 unchanged lines hidden (view full) ---

1263 *
1264 * The low power link up (lplu) state is set to the power management level D3
1265 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1266 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1267 * is used during Dx states where the power conservation is most important.
1268 * During driver activity, SmartSpeed should be enabled so performance is
1269 * maintained.
1270 **/
1249s32
1250e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, boolean_t active)
1271s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1251{
1252 struct e1000_phy_info *phy = &hw->phy;
1253 s32 ret_val;
1254 u16 data;
1255
1256 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1257
1258 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1259 if (ret_val)
1260 goto out;
1261
1262 if (!active) {
1263 data &= ~IGP02E1000_PM_D3_LPLU;
1264 ret_val = e1000_write_phy_reg(hw,
1265 IGP02E1000_PHY_POWER_MGMT,
1266 data);
1267 if (ret_val)
1268 goto out;
1272{
1273 struct e1000_phy_info *phy = &hw->phy;
1274 s32 ret_val;
1275 u16 data;
1276
1277 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1278
1279 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1280 if (ret_val)
1281 goto out;
1282
1283 if (!active) {
1284 data &= ~IGP02E1000_PM_D3_LPLU;
1285 ret_val = e1000_write_phy_reg(hw,
1286 IGP02E1000_PHY_POWER_MGMT,
1287 data);
1288 if (ret_val)
1289 goto out;
1269 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1290 /*
1291 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1270 * during Dx states where the power conservation is most
1271 * important. During driver activity we should enable
1292 * during Dx states where the power conservation is most
1293 * important. During driver activity we should enable
1272 * SmartSpeed, so performance is maintained. */
1294 * SmartSpeed, so performance is maintained.
1295 */
1273 if (phy->smart_speed == e1000_smart_speed_on) {
1274 ret_val = e1000_read_phy_reg(hw,
1275 IGP01E1000_PHY_PORT_CONFIG,
1276 &data);
1277 if (ret_val)
1278 goto out;
1279
1280 data |= IGP01E1000_PSCFR_SMART_SPEED;

--- 46 unchanged lines hidden (view full) ---

1327/**
1328 * e1000_check_downshift_generic - Checks whether a downshift in speed occured
1329 * @hw: pointer to the HW structure
1330 *
1331 * Success returns 0, Failure returns 1
1332 *
1333 * A downshift is detected by querying the PHY link health.
1334 **/
1296 if (phy->smart_speed == e1000_smart_speed_on) {
1297 ret_val = e1000_read_phy_reg(hw,
1298 IGP01E1000_PHY_PORT_CONFIG,
1299 &data);
1300 if (ret_val)
1301 goto out;
1302
1303 data |= IGP01E1000_PSCFR_SMART_SPEED;

--- 46 unchanged lines hidden (view full) ---

1350/**
1351 * e1000_check_downshift_generic - Checks whether a downshift in speed occured
1352 * @hw: pointer to the HW structure
1353 *
1354 * Success returns 0, Failure returns 1
1355 *
1356 * A downshift is detected by querying the PHY link health.
1357 **/
1335s32
1336e1000_check_downshift_generic(struct e1000_hw *hw)
1358s32 e1000_check_downshift_generic(struct e1000_hw *hw)
1337{
1338 struct e1000_phy_info *phy = &hw->phy;
1339 s32 ret_val;
1340 u16 phy_data, offset, mask;
1341
1342 DEBUGFUNC("e1000_check_downshift_generic");
1343
1344 switch (phy->type) {

--- 27 unchanged lines hidden (view full) ---

1372/**
1373 * e1000_check_polarity_m88 - Checks the polarity.
1374 * @hw: pointer to the HW structure
1375 *
1376 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1377 *
1378 * Polarity is determined based on the PHY specific status register.
1379 **/
1359{
1360 struct e1000_phy_info *phy = &hw->phy;
1361 s32 ret_val;
1362 u16 phy_data, offset, mask;
1363
1364 DEBUGFUNC("e1000_check_downshift_generic");
1365
1366 switch (phy->type) {

--- 27 unchanged lines hidden (view full) ---

1394/**
1395 * e1000_check_polarity_m88 - Checks the polarity.
1396 * @hw: pointer to the HW structure
1397 *
1398 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1399 *
1400 * Polarity is determined based on the PHY specific status register.
1401 **/
1380s32
1381e1000_check_polarity_m88(struct e1000_hw *hw)
1402s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1382{
1383 struct e1000_phy_info *phy = &hw->phy;
1384 s32 ret_val;
1385 u16 data;
1386
1387 DEBUGFUNC("e1000_check_polarity_m88");
1388
1389 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);

--- 10 unchanged lines hidden (view full) ---

1400 * e1000_check_polarity_igp - Checks the polarity.
1401 * @hw: pointer to the HW structure
1402 *
1403 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1404 *
1405 * Polarity is determined based on the PHY port status register, and the
1406 * current speed (since there is no polarity at 100Mbps).
1407 **/
1403{
1404 struct e1000_phy_info *phy = &hw->phy;
1405 s32 ret_val;
1406 u16 data;
1407
1408 DEBUGFUNC("e1000_check_polarity_m88");
1409
1410 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);

--- 10 unchanged lines hidden (view full) ---

1421 * e1000_check_polarity_igp - Checks the polarity.
1422 * @hw: pointer to the HW structure
1423 *
1424 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1425 *
1426 * Polarity is determined based on the PHY port status register, and the
1427 * current speed (since there is no polarity at 100Mbps).
1428 **/
1408s32
1409e1000_check_polarity_igp(struct e1000_hw *hw)
1429s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1410{
1411 struct e1000_phy_info *phy = &hw->phy;
1412 s32 ret_val;
1413 u16 data, offset, mask;
1414
1415 DEBUGFUNC("e1000_check_polarity_igp");
1416
1430{
1431 struct e1000_phy_info *phy = &hw->phy;
1432 s32 ret_val;
1433 u16 data, offset, mask;
1434
1435 DEBUGFUNC("e1000_check_polarity_igp");
1436
1417 /* Polarity is determined based on the speed of
1418 * our connection. */
1437 /*
1438 * Polarity is determined based on the speed of
1439 * our connection.
1440 */
1419 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1420 if (ret_val)
1421 goto out;
1422
1423 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1424 IGP01E1000_PSSR_SPEED_1000MBPS) {
1425 offset = IGP01E1000_PHY_PCS_INIT_REG;
1426 mask = IGP01E1000_PHY_POLARITY_MASK;
1427 } else {
1441 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1442 if (ret_val)
1443 goto out;
1444
1445 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1446 IGP01E1000_PSSR_SPEED_1000MBPS) {
1447 offset = IGP01E1000_PHY_PCS_INIT_REG;
1448 mask = IGP01E1000_PHY_POLARITY_MASK;
1449 } else {
1428 /* This really only applies to 10Mbps since
1450 /*
1451 * This really only applies to 10Mbps since
1429 * there is no polarity for 100Mbps (always 0).
1430 */
1431 offset = IGP01E1000_PHY_PORT_STATUS;
1432 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1433 }
1434
1435 ret_val = e1000_read_phy_reg(hw, offset, &data);
1436

--- 8 unchanged lines hidden (view full) ---

1445
1446/**
1447 * e1000_wait_autoneg_generic - Wait for auto-neg compeletion
1448 * @hw: pointer to the HW structure
1449 *
1450 * Waits for auto-negotiation to complete or for the auto-negotiation time
1451 * limit to expire, which ever happens first.
1452 **/
1452 * there is no polarity for 100Mbps (always 0).
1453 */
1454 offset = IGP01E1000_PHY_PORT_STATUS;
1455 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1456 }
1457
1458 ret_val = e1000_read_phy_reg(hw, offset, &data);
1459

--- 8 unchanged lines hidden (view full) ---

1468
1469/**
1470 * e1000_wait_autoneg_generic - Wait for auto-neg compeletion
1471 * @hw: pointer to the HW structure
1472 *
1473 * Waits for auto-negotiation to complete or for the auto-negotiation time
1474 * limit to expire, which ever happens first.
1475 **/
1453s32
1454e1000_wait_autoneg_generic(struct e1000_hw *hw)
1476s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
1455{
1456 s32 ret_val = E1000_SUCCESS;
1457 u16 i, phy_status;
1458
1459 DEBUGFUNC("e1000_wait_autoneg_generic");
1460
1461 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1462 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1463 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
1464 if (ret_val)
1465 break;
1466 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
1467 if (ret_val)
1468 break;
1469 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1470 break;
1471 msec_delay(100);
1472 }
1473
1477{
1478 s32 ret_val = E1000_SUCCESS;
1479 u16 i, phy_status;
1480
1481 DEBUGFUNC("e1000_wait_autoneg_generic");
1482
1483 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1484 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1485 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
1486 if (ret_val)
1487 break;
1488 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
1489 if (ret_val)
1490 break;
1491 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1492 break;
1493 msec_delay(100);
1494 }
1495
1474 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1496 /*
1497 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1475 * has completed.
1476 */
1477 return ret_val;
1478}
1479
1480/**
1481 * e1000_phy_has_link_generic - Polls PHY for link
1482 * @hw: pointer to the HW structure
1483 * @iterations: number of times to poll for link
1484 * @usec_interval: delay between polling attempts
1485 * @success: pointer to whether polling was successful or not
1486 *
1487 * Polls the PHY status register for link, 'iterations' number of times.
1488 **/
1498 * has completed.
1499 */
1500 return ret_val;
1501}
1502
1503/**
1504 * e1000_phy_has_link_generic - Polls PHY for link
1505 * @hw: pointer to the HW structure
1506 * @iterations: number of times to poll for link
1507 * @usec_interval: delay between polling attempts
1508 * @success: pointer to whether polling was successful or not
1509 *
1510 * Polls the PHY status register for link, 'iterations' number of times.
1511 **/
1489s32
1490e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1491 u32 usec_interval, boolean_t *success)
1512s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1513 u32 usec_interval, bool *success)
1492{
1493 s32 ret_val = E1000_SUCCESS;
1494 u16 i, phy_status;
1495
1496 DEBUGFUNC("e1000_phy_has_link_generic");
1497
1498 for (i = 0; i < iterations; i++) {
1514{
1515 s32 ret_val = E1000_SUCCESS;
1516 u16 i, phy_status;
1517
1518 DEBUGFUNC("e1000_phy_has_link_generic");
1519
1520 for (i = 0; i < iterations; i++) {
1499 /* Some PHYs require the PHY_STATUS register to be read
1521 /*
1522 * Some PHYs require the PHY_STATUS register to be read
1500 * twice due to the link bit being sticky. No harm doing
1501 * it across the board.
1502 */
1503 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
1504 if (ret_val)
1505 break;
1506 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
1507 if (ret_val)

--- 21 unchanged lines hidden (view full) ---

1529 * possible cable length values, which are:
1530 * Register Value Cable Length
1531 * 0 < 50 meters
1532 * 1 50 - 80 meters
1533 * 2 80 - 110 meters
1534 * 3 110 - 140 meters
1535 * 4 > 140 meters
1536 **/
1523 * twice due to the link bit being sticky. No harm doing
1524 * it across the board.
1525 */
1526 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
1527 if (ret_val)
1528 break;
1529 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
1530 if (ret_val)

--- 21 unchanged lines hidden (view full) ---

1552 * possible cable length values, which are:
1553 * Register Value Cable Length
1554 * 0 < 50 meters
1555 * 1 50 - 80 meters
1556 * 2 80 - 110 meters
1557 * 3 110 - 140 meters
1558 * 4 > 140 meters
1559 **/
1537s32
1538e1000_get_cable_length_m88(struct e1000_hw *hw)
1560s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
1539{
1540 struct e1000_phy_info *phy = &hw->phy;
1541 s32 ret_val;
1542 u16 phy_data, index;
1543
1544 DEBUGFUNC("e1000_get_cable_length_m88");
1545
1546 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);

--- 17 unchanged lines hidden (view full) ---

1564 *
1565 * The automatic gain control (agc) normalizes the amplitude of the
1566 * received signal, adjusting for the attenuation produced by the
1567 * cable. By reading the AGC registers, which reperesent the
1568 * cobination of course and fine gain value, the value can be put
1569 * into a lookup table to obtain the approximate cable length
1570 * for each channel.
1571 **/
1561{
1562 struct e1000_phy_info *phy = &hw->phy;
1563 s32 ret_val;
1564 u16 phy_data, index;
1565
1566 DEBUGFUNC("e1000_get_cable_length_m88");
1567
1568 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);

--- 17 unchanged lines hidden (view full) ---

1586 *
1587 * The automatic gain control (agc) normalizes the amplitude of the
1588 * received signal, adjusting for the attenuation produced by the
1589 * cable. By reading the AGC registers, which reperesent the
1590 * cobination of course and fine gain value, the value can be put
1591 * into a lookup table to obtain the approximate cable length
1592 * for each channel.
1593 **/
1572s32
1573e1000_get_cable_length_igp_2(struct e1000_hw *hw)
1594s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
1574{
1575 struct e1000_phy_info *phy = &hw->phy;
1595{
1596 struct e1000_phy_info *phy = &hw->phy;
1576 s32 ret_val;
1597 s32 ret_val = E1000_SUCCESS;
1577 u16 phy_data, i, agc_value = 0;
1578 u16 cur_agc_index, max_agc_index = 0;
1579 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1580 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1581 {IGP02E1000_PHY_AGC_A,
1582 IGP02E1000_PHY_AGC_B,
1583 IGP02E1000_PHY_AGC_C,
1584 IGP02E1000_PHY_AGC_D};
1585
1586 DEBUGFUNC("e1000_get_cable_length_igp_2");
1587
1588 /* Read the AGC registers for all channels */
1589 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1590 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
1591 if (ret_val)
1592 goto out;
1593
1598 u16 phy_data, i, agc_value = 0;
1599 u16 cur_agc_index, max_agc_index = 0;
1600 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1601 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1602 {IGP02E1000_PHY_AGC_A,
1603 IGP02E1000_PHY_AGC_B,
1604 IGP02E1000_PHY_AGC_C,
1605 IGP02E1000_PHY_AGC_D};
1606
1607 DEBUGFUNC("e1000_get_cable_length_igp_2");
1608
1609 /* Read the AGC registers for all channels */
1610 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1611 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
1612 if (ret_val)
1613 goto out;
1614
1594 /* Getting bits 15:9, which represent the combination of
1615 /*
1616 * Getting bits 15:9, which represent the combination of
1595 * course and fine gain values. The result is a number
1596 * that can be put into the lookup table to obtain the
1617 * course and fine gain values. The result is a number
1618 * that can be put into the lookup table to obtain the
1597 * approximate cable length. */
1619 * approximate cable length.
1620 */
1598 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1599 IGP02E1000_AGC_LENGTH_MASK;
1600
1601 /* Array index bound check. */
1602 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1603 (cur_agc_index == 0)) {
1604 ret_val = -E1000_ERR_PHY;
1605 goto out;

--- 30 unchanged lines hidden (view full) ---

1636 * @hw: pointer to the HW structure
1637 *
1638 * Valid for only copper links. Read the PHY status register (sticky read)
1639 * to verify that link is up. Read the PHY special control register to
1640 * determine the polarity and 10base-T extended distance. Read the PHY
1641 * special status register to determine MDI/MDIx and current speed. If
1642 * speed is 1000, then determine cable length, local and remote receiver.
1643 **/
1621 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1622 IGP02E1000_AGC_LENGTH_MASK;
1623
1624 /* Array index bound check. */
1625 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1626 (cur_agc_index == 0)) {
1627 ret_val = -E1000_ERR_PHY;
1628 goto out;

--- 30 unchanged lines hidden (view full) ---

1659 * @hw: pointer to the HW structure
1660 *
1661 * Valid for only copper links. Read the PHY status register (sticky read)
1662 * to verify that link is up. Read the PHY special control register to
1663 * determine the polarity and 10base-T extended distance. Read the PHY
1664 * special status register to determine MDI/MDIx and current speed. If
1665 * speed is 1000, then determine cable length, local and remote receiver.
1666 **/
1644s32
1645e1000_get_phy_info_m88(struct e1000_hw *hw)
1667s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
1646{
1647 struct e1000_phy_info *phy = &hw->phy;
1648 s32 ret_val;
1649 u16 phy_data;
1668{
1669 struct e1000_phy_info *phy = &hw->phy;
1670 s32 ret_val;
1671 u16 phy_data;
1650 boolean_t link;
1672 bool link;
1651
1652 DEBUGFUNC("e1000_get_phy_info_m88");
1653
1673
1674 DEBUGFUNC("e1000_get_phy_info_m88");
1675
1654 if (hw->media_type != e1000_media_type_copper) {
1676 if (hw->phy.media_type != e1000_media_type_copper) {
1655 DEBUGOUT("Phy info is only valid for copper media\n");
1656 ret_val = -E1000_ERR_CONFIG;
1657 goto out;
1658 }
1659
1660 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1661 if (ret_val)
1662 goto out;

--- 53 unchanged lines hidden (view full) ---

1716 * e1000_get_phy_info_igp - Retrieve igp PHY information
1717 * @hw: pointer to the HW structure
1718 *
1719 * Read PHY status to determine if link is up. If link is up, then
1720 * set/determine 10base-T extended distance and polarity correction. Read
1721 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1722 * determine on the cable length, local and remote receiver.
1723 **/
1677 DEBUGOUT("Phy info is only valid for copper media\n");
1678 ret_val = -E1000_ERR_CONFIG;
1679 goto out;
1680 }
1681
1682 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1683 if (ret_val)
1684 goto out;

--- 53 unchanged lines hidden (view full) ---

1738 * e1000_get_phy_info_igp - Retrieve igp PHY information
1739 * @hw: pointer to the HW structure
1740 *
1741 * Read PHY status to determine if link is up. If link is up, then
1742 * set/determine 10base-T extended distance and polarity correction. Read
1743 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1744 * determine on the cable length, local and remote receiver.
1745 **/
1724s32
1725e1000_get_phy_info_igp(struct e1000_hw *hw)
1746s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
1726{
1727 struct e1000_phy_info *phy = &hw->phy;
1728 s32 ret_val;
1729 u16 data;
1747{
1748 struct e1000_phy_info *phy = &hw->phy;
1749 s32 ret_val;
1750 u16 data;
1730 boolean_t link;
1751 bool link;
1731
1732 DEBUGFUNC("e1000_get_phy_info_igp");
1733
1734 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1735 if (ret_val)
1736 goto out;
1737
1738 if (!link) {

--- 43 unchanged lines hidden (view full) ---

1782
1783/**
1784 * e1000_phy_sw_reset_generic - PHY software reset
1785 * @hw: pointer to the HW structure
1786 *
1787 * Does a software reset of the PHY by reading the PHY control register and
1788 * setting/write the control register reset bit to the PHY.
1789 **/
1752
1753 DEBUGFUNC("e1000_get_phy_info_igp");
1754
1755 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1756 if (ret_val)
1757 goto out;
1758
1759 if (!link) {

--- 43 unchanged lines hidden (view full) ---

1803
1804/**
1805 * e1000_phy_sw_reset_generic - PHY software reset
1806 * @hw: pointer to the HW structure
1807 *
1808 * Does a software reset of the PHY by reading the PHY control register and
1809 * setting/write the control register reset bit to the PHY.
1810 **/
1790s32
1791e1000_phy_sw_reset_generic(struct e1000_hw *hw)
1811s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
1792{
1793 s32 ret_val;
1794 u16 phy_ctrl;
1795
1796 DEBUGFUNC("e1000_phy_sw_reset_generic");
1797
1798 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
1799 if (ret_val)

--- 14 unchanged lines hidden (view full) ---

1814 * e1000_phy_hw_reset_generic - PHY hardware reset
1815 * @hw: pointer to the HW structure
1816 *
1817 * Verify the reset block is not blocking us from resetting. Acquire
1818 * semaphore (if necessary) and read/set/write the device control reset
1819 * bit in the PHY. Wait the appropriate delay time for the device to
1820 * reset and relase the semaphore (if necessary).
1821 **/
1812{
1813 s32 ret_val;
1814 u16 phy_ctrl;
1815
1816 DEBUGFUNC("e1000_phy_sw_reset_generic");
1817
1818 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
1819 if (ret_val)

--- 14 unchanged lines hidden (view full) ---

1834 * e1000_phy_hw_reset_generic - PHY hardware reset
1835 * @hw: pointer to the HW structure
1836 *
1837 * Verify the reset block is not blocking us from resetting. Acquire
1838 * semaphore (if necessary) and read/set/write the device control reset
1839 * bit in the PHY. Wait the appropriate delay time for the device to
1840 * reset and relase the semaphore (if necessary).
1841 **/
1822s32
1823e1000_phy_hw_reset_generic(struct e1000_hw *hw)
1842s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
1824{
1825 struct e1000_phy_info *phy = &hw->phy;
1826 s32 ret_val;
1827 u32 ctrl;
1828
1829 DEBUGFUNC("e1000_phy_hw_reset_generic");
1830
1831 ret_val = e1000_check_reset_block(hw);

--- 27 unchanged lines hidden (view full) ---

1859
1860/**
1861 * e1000_get_cfg_done_generic - Generic configuration done
1862 * @hw: pointer to the HW structure
1863 *
1864 * Generic function to wait 10 milli-seconds for configuration to complete
1865 * and return success.
1866 **/
1843{
1844 struct e1000_phy_info *phy = &hw->phy;
1845 s32 ret_val;
1846 u32 ctrl;
1847
1848 DEBUGFUNC("e1000_phy_hw_reset_generic");
1849
1850 ret_val = e1000_check_reset_block(hw);

--- 27 unchanged lines hidden (view full) ---

1878
1879/**
1880 * e1000_get_cfg_done_generic - Generic configuration done
1881 * @hw: pointer to the HW structure
1882 *
1883 * Generic function to wait 10 milli-seconds for configuration to complete
1884 * and return success.
1885 **/
1867s32
1868e1000_get_cfg_done_generic(struct e1000_hw *hw)
1886s32 e1000_get_cfg_done_generic(struct e1000_hw *hw)
1869{
1870 DEBUGFUNC("e1000_get_cfg_done_generic");
1887{
1888 DEBUGFUNC("e1000_get_cfg_done_generic");
1889 UNREFERENCED_PARAMETER(hw);
1871
1872 msec_delay_irq(10);
1873
1874 return E1000_SUCCESS;
1875}
1876
1877/* Internal function pointers */
1878
1879/**
1880 * e1000_get_phy_cfg_done - Generic PHY configuration done
1881 * @hw: pointer to the HW structure
1882 *
1883 * Return success if silicon family did not implement a family specific
1884 * get_cfg_done function.
1885 **/
1890
1891 msec_delay_irq(10);
1892
1893 return E1000_SUCCESS;
1894}
1895
1896/* Internal function pointers */
1897
1898/**
1899 * e1000_get_phy_cfg_done - Generic PHY configuration done
1900 * @hw: pointer to the HW structure
1901 *
1902 * Return success if silicon family did not implement a family specific
1903 * get_cfg_done function.
1904 **/
1886s32
1887e1000_get_phy_cfg_done(struct e1000_hw *hw)
1905s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
1888{
1906{
1889 if (hw->func.get_cfg_done != NULL)
1907 if (hw->func.get_cfg_done)
1890 return hw->func.get_cfg_done(hw);
1908 return hw->func.get_cfg_done(hw);
1891 else
1892 return E1000_SUCCESS;
1909
1910 return E1000_SUCCESS;
1893}
1894
1895/**
1896 * e1000_release_phy - Generic release PHY
1897 * @hw: pointer to the HW structure
1898 *
1899 * Return if silicon family does not require a semaphore when accessing the
1900 * PHY.
1901 **/
1911}
1912
1913/**
1914 * e1000_release_phy - Generic release PHY
1915 * @hw: pointer to the HW structure
1916 *
1917 * Return if silicon family does not require a semaphore when accessing the
1918 * PHY.
1919 **/
1902void
1903e1000_release_phy(struct e1000_hw *hw)
1920void e1000_release_phy(struct e1000_hw *hw)
1904{
1921{
1905 if (hw->func.release_phy != NULL)
1922 if (hw->func.release_phy)
1906 hw->func.release_phy(hw);
1907}
1908
1909/**
1910 * e1000_acquire_phy - Generic acquire PHY
1911 * @hw: pointer to the HW structure
1912 *
1913 * Return success if silicon family does not require a semaphore when
1914 * accessing the PHY.
1915 **/
1923 hw->func.release_phy(hw);
1924}
1925
1926/**
1927 * e1000_acquire_phy - Generic acquire PHY
1928 * @hw: pointer to the HW structure
1929 *
1930 * Return success if silicon family does not require a semaphore when
1931 * accessing the PHY.
1932 **/
1916s32
1917e1000_acquire_phy(struct e1000_hw *hw)
1933s32 e1000_acquire_phy(struct e1000_hw *hw)
1918{
1934{
1919 if (hw->func.acquire_phy != NULL)
1935 if (hw->func.acquire_phy)
1920 return hw->func.acquire_phy(hw);
1936 return hw->func.acquire_phy(hw);
1921 else
1922 return E1000_SUCCESS;
1937
1938 return E1000_SUCCESS;
1923}
1924
1925/**
1926 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
1927 * @hw: pointer to the HW structure
1928 *
1929 * When the silicon family has not implemented a forced speed/duplex
1930 * function for the PHY, simply return E1000_SUCCESS.
1931 **/
1939}
1940
1941/**
1942 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
1943 * @hw: pointer to the HW structure
1944 *
1945 * When the silicon family has not implemented a forced speed/duplex
1946 * function for the PHY, simply return E1000_SUCCESS.
1947 **/
1932s32
1933e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1948s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1934{
1949{
1935 if (hw->func.force_speed_duplex != NULL)
1950 if (hw->func.force_speed_duplex)
1936 return hw->func.force_speed_duplex(hw);
1951 return hw->func.force_speed_duplex(hw);
1937 else
1938 return E1000_SUCCESS;
1952
1953 return E1000_SUCCESS;
1939}
1940
1941/**
1942 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
1943 * @hw: pointer to the HW structure
1944 *
1945 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
1946 **/
1954}
1955
1956/**
1957 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
1958 * @hw: pointer to the HW structure
1959 *
1960 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
1961 **/
1947s32
1948e1000_phy_init_script_igp3(struct e1000_hw *hw)
1962s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
1949{
1950 DEBUGOUT("Running IGP 3 PHY init script\n");
1951
1952 /* PHY init IGP 3 */
1953 /* Enable rise/fall, 10-mode work in class-A */
1954 e1000_write_phy_reg(hw, 0x2F5B, 0x9018);
1955 /* Remove all caps from Replica path filter */
1956 e1000_write_phy_reg(hw, 0x2F52, 0x0000);
1957 /* Bias trimming for ADC, AFE and Driver (Default) */
1958 e1000_write_phy_reg(hw, 0x2FB1, 0x8B24);
1959 /* Increase Hybrid poly bias */
1960 e1000_write_phy_reg(hw, 0x2FB2, 0xF8F0);
1963{
1964 DEBUGOUT("Running IGP 3 PHY init script\n");
1965
1966 /* PHY init IGP 3 */
1967 /* Enable rise/fall, 10-mode work in class-A */
1968 e1000_write_phy_reg(hw, 0x2F5B, 0x9018);
1969 /* Remove all caps from Replica path filter */
1970 e1000_write_phy_reg(hw, 0x2F52, 0x0000);
1971 /* Bias trimming for ADC, AFE and Driver (Default) */
1972 e1000_write_phy_reg(hw, 0x2FB1, 0x8B24);
1973 /* Increase Hybrid poly bias */
1974 e1000_write_phy_reg(hw, 0x2FB2, 0xF8F0);
1961 /* Add 4% to TX amplitude in Giga mode */
1975 /* Add 4% to Tx amplitude in Giga mode */
1962 e1000_write_phy_reg(hw, 0x2010, 0x10B0);
1963 /* Disable trimming (TTT) */
1964 e1000_write_phy_reg(hw, 0x2011, 0x0000);
1965 /* Poly DC correction to 94.6% + 2% for all channels */
1966 e1000_write_phy_reg(hw, 0x20DD, 0x249A);
1967 /* ABS DC correction to 95.9% */
1968 e1000_write_phy_reg(hw, 0x20DE, 0x00D3);
1969 /* BG temp curve trim */

--- 27 unchanged lines hidden (view full) ---

1997 /* Set AHT Preset bits */
1998 e1000_write_phy_reg(hw, 0x1F79, 0x0210);
1999 /* Change integ_factor of channel A to 3 */
2000 e1000_write_phy_reg(hw, 0x1895, 0x0003);
2001 /* Change prop_factor of channels BCD to 8 */
2002 e1000_write_phy_reg(hw, 0x1796, 0x0008);
2003 /* Change cg_icount + enable integbp for channels BCD */
2004 e1000_write_phy_reg(hw, 0x1798, 0xD008);
1976 e1000_write_phy_reg(hw, 0x2010, 0x10B0);
1977 /* Disable trimming (TTT) */
1978 e1000_write_phy_reg(hw, 0x2011, 0x0000);
1979 /* Poly DC correction to 94.6% + 2% for all channels */
1980 e1000_write_phy_reg(hw, 0x20DD, 0x249A);
1981 /* ABS DC correction to 95.9% */
1982 e1000_write_phy_reg(hw, 0x20DE, 0x00D3);
1983 /* BG temp curve trim */

--- 27 unchanged lines hidden (view full) ---

2011 /* Set AHT Preset bits */
2012 e1000_write_phy_reg(hw, 0x1F79, 0x0210);
2013 /* Change integ_factor of channel A to 3 */
2014 e1000_write_phy_reg(hw, 0x1895, 0x0003);
2015 /* Change prop_factor of channels BCD to 8 */
2016 e1000_write_phy_reg(hw, 0x1796, 0x0008);
2017 /* Change cg_icount + enable integbp for channels BCD */
2018 e1000_write_phy_reg(hw, 0x1798, 0xD008);
2005 /* Change cg_icount + enable integbp + change prop_factor_master
2019 /*
2020 * Change cg_icount + enable integbp + change prop_factor_master
2006 * to 8 for channel A
2007 */
2008 e1000_write_phy_reg(hw, 0x1898, 0xD918);
2009 /* Disable AHT in Slave mode on channel A */
2010 e1000_write_phy_reg(hw, 0x187A, 0x0800);
2021 * to 8 for channel A
2022 */
2023 e1000_write_phy_reg(hw, 0x1898, 0xD918);
2024 /* Disable AHT in Slave mode on channel A */
2025 e1000_write_phy_reg(hw, 0x187A, 0x0800);
2011 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2026 /*
2027 * Enable LPLU and disable AN to 1000 in non-D0a states,
2012 * Enable SPD+B2B
2013 */
2014 e1000_write_phy_reg(hw, 0x0019, 0x008D);
2015 /* Enable restart AN on an1000_dis change */
2016 e1000_write_phy_reg(hw, 0x001B, 0x2080);
2017 /* Enable wh_fifo read clock in 10/100 modes */
2018 e1000_write_phy_reg(hw, 0x0014, 0x0045);
2019 /* Restart AN, Speed selection is 1000 */
2020 e1000_write_phy_reg(hw, 0x0000, 0x1340);
2021
2022 return E1000_SUCCESS;
2023}
2024
2025/**
2026 * e1000_get_phy_type_from_id - Get PHY type from id
2027 * @phy_id: phy_id read from the phy
2028 *
2029 * Returns the phy type from the id.
2030 **/
2028 * Enable SPD+B2B
2029 */
2030 e1000_write_phy_reg(hw, 0x0019, 0x008D);
2031 /* Enable restart AN on an1000_dis change */
2032 e1000_write_phy_reg(hw, 0x001B, 0x2080);
2033 /* Enable wh_fifo read clock in 10/100 modes */
2034 e1000_write_phy_reg(hw, 0x0014, 0x0045);
2035 /* Restart AN, Speed selection is 1000 */
2036 e1000_write_phy_reg(hw, 0x0000, 0x1340);
2037
2038 return E1000_SUCCESS;
2039}
2040
2041/**
2042 * e1000_get_phy_type_from_id - Get PHY type from id
2043 * @phy_id: phy_id read from the phy
2044 *
2045 * Returns the phy type from the id.
2046 **/
2031e1000_phy_type
2032e1000_get_phy_type_from_id(u32 phy_id)
2047e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2033{
2034 e1000_phy_type phy_type = e1000_phy_unknown;
2035
2036 switch (phy_id) {
2037 case M88E1000_I_PHY_ID:
2038 case M88E1000_E_PHY_ID:
2039 case M88E1111_I_PHY_ID:
2040 case M88E1011_I_PHY_ID:

--- 15 unchanged lines hidden (view full) ---

2056 break;
2057 default:
2058 phy_type = e1000_phy_unknown;
2059 break;
2060 }
2061 return phy_type;
2062}
2063
2048{
2049 e1000_phy_type phy_type = e1000_phy_unknown;
2050
2051 switch (phy_id) {
2052 case M88E1000_I_PHY_ID:
2053 case M88E1000_E_PHY_ID:
2054 case M88E1111_I_PHY_ID:
2055 case M88E1011_I_PHY_ID:

--- 15 unchanged lines hidden (view full) ---

2071 break;
2072 default:
2073 phy_type = e1000_phy_unknown;
2074 break;
2075 }
2076 return phy_type;
2077}
2078
2079/**
2080 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2081 * @hw: pointer to the HW structure
2082 *
2083 * In the case of a PHY power down to save power, or to turn off link during a
2084 * driver unload, or wake on lan is not enabled, restore the link to previous
2085 * settings.
2086 **/
2087void e1000_power_up_phy_copper(struct e1000_hw *hw)
2088{
2089 u16 mii_reg = 0;
2064
2090
2091 /* The PHY will retain its settings across a power down/up cycle */
2092 e1000_read_phy_reg(hw, PHY_CONTROL, &mii_reg);
2093 mii_reg &= ~MII_CR_POWER_DOWN;
2094 e1000_write_phy_reg(hw, PHY_CONTROL, mii_reg);
2095}
2096
2097/**
2098 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2099 * @hw: pointer to the HW structure
2100 *
2101 * In the case of a PHY power down to save power, or to turn off link during a
2102 * driver unload, or wake on lan is not enabled, restore the link to previous
2103 * settings.
2104 **/
2105void e1000_power_down_phy_copper(struct e1000_hw *hw)
2106{
2107 u16 mii_reg = 0;
2108
2109 /* The PHY will retain its settings across a power down/up cycle */
2110 e1000_read_phy_reg(hw, PHY_CONTROL, &mii_reg);
2111 mii_reg |= MII_CR_POWER_DOWN;
2112 e1000_write_phy_reg(hw, PHY_CONTROL, mii_reg);
2113 msec_delay(1);
2114}