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e1000_phy.c (169248) e1000_phy.c (169589)
1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
33/*$FreeBSD: head/sys/dev/em/e1000_phy.c 169589 2007-05-16 00:14:23Z jfv $*/
33
34
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/em/e1000_phy.c 169248 2007-05-04 13:30:44Z rwatson $");
36
35
37
36#include "e1000_api.h"
38#include "e1000_phy.h"
39
40static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
41static void e1000_release_phy(struct e1000_hw *hw);
42static s32 e1000_acquire_phy(struct e1000_hw *hw);
43
44/* Cable length tables */
45static const

--- 14 unchanged lines hidden (view full) ---

60 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
61 104, 109, 114, 118, 121, 124};
62#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
63 (sizeof(e1000_igp_2_cable_length_table) / \
64 sizeof(e1000_igp_2_cable_length_table[0]))
65
66/**
67 * e1000_check_reset_block_generic - Check if PHY reset is blocked
37#include "e1000_phy.h"
38
39static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
40static void e1000_release_phy(struct e1000_hw *hw);
41static s32 e1000_acquire_phy(struct e1000_hw *hw);
42
43/* Cable length tables */
44static const

--- 14 unchanged lines hidden (view full) ---

59 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
60 104, 109, 114, 118, 121, 124};
61#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
62 (sizeof(e1000_igp_2_cable_length_table) / \
63 sizeof(e1000_igp_2_cable_length_table[0]))
64
65/**
66 * e1000_check_reset_block_generic - Check if PHY reset is blocked
68 * @hw - pointer to the HW structure
67 * @hw: pointer to the HW structure
69 *
70 * Read the PHY management control register and check whether a PHY reset
71 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
72 * return E1000_BLK_PHY_RESET (12).
73 **/
74s32
75e1000_check_reset_block_generic(struct e1000_hw *hw)
76{

--- 4 unchanged lines hidden (view full) ---

81 manc = E1000_READ_REG(hw, E1000_MANC);
82
83 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
84 E1000_BLK_PHY_RESET : E1000_SUCCESS;
85}
86
87/**
88 * e1000_get_phy_id - Retrieve the PHY ID and revision
68 *
69 * Read the PHY management control register and check whether a PHY reset
70 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
71 * return E1000_BLK_PHY_RESET (12).
72 **/
73s32
74e1000_check_reset_block_generic(struct e1000_hw *hw)
75{

--- 4 unchanged lines hidden (view full) ---

80 manc = E1000_READ_REG(hw, E1000_MANC);
81
82 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
83 E1000_BLK_PHY_RESET : E1000_SUCCESS;
84}
85
86/**
87 * e1000_get_phy_id - Retrieve the PHY ID and revision
89 * @hw - pointer to the HW structure
88 * @hw: pointer to the HW structure
90 *
91 * Reads the PHY registers and stores the PHY ID and possibly the PHY
92 * revision in the hardware structure.
93 **/
94s32
95e1000_get_phy_id(struct e1000_hw *hw)
96{
97 struct e1000_phy_info *phy = &hw->phy;

--- 16 unchanged lines hidden (view full) ---

114 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
115
116out:
117 return ret_val;
118}
119
120/**
121 * e1000_phy_reset_dsp_generic - Reset PHY DSP
89 *
90 * Reads the PHY registers and stores the PHY ID and possibly the PHY
91 * revision in the hardware structure.
92 **/
93s32
94e1000_get_phy_id(struct e1000_hw *hw)
95{
96 struct e1000_phy_info *phy = &hw->phy;

--- 16 unchanged lines hidden (view full) ---

113 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
114
115out:
116 return ret_val;
117}
118
119/**
120 * e1000_phy_reset_dsp_generic - Reset PHY DSP
122 * @hw - pointer to the HW structure
121 * @hw: pointer to the HW structure
123 *
124 * Reset the digital signal processor.
125 **/
126s32
127e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
128{
129 s32 ret_val;
130

--- 6 unchanged lines hidden (view full) ---

137 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
138
139out:
140 return ret_val;
141}
142
143/**
144 * e1000_read_phy_reg_mdic - Read MDI control register
122 *
123 * Reset the digital signal processor.
124 **/
125s32
126e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
127{
128 s32 ret_val;
129

--- 6 unchanged lines hidden (view full) ---

136 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
137
138out:
139 return ret_val;
140}
141
142/**
143 * e1000_read_phy_reg_mdic - Read MDI control register
145 * @hw - pointer to the HW structure
146 * @offset - register offset to be read
147 * @data - pointer to the read data
144 * @hw: pointer to the HW structure
145 * @offset: register offset to be read
146 * @data: pointer to the read data
148 *
149 * Reads the MDI control regsiter in the PHY at offset and stores the
150 * information read to data.
151 **/
152static s32
153e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
154{
155 struct e1000_phy_info *phy = &hw->phy;

--- 38 unchanged lines hidden (view full) ---

194 *data = (u16) mdic;
195
196out:
197 return ret_val;
198}
199
200/**
201 * e1000_write_phy_reg_mdic - Write MDI control register
147 *
148 * Reads the MDI control regsiter in the PHY at offset and stores the
149 * information read to data.
150 **/
151static s32
152e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
153{
154 struct e1000_phy_info *phy = &hw->phy;

--- 38 unchanged lines hidden (view full) ---

193 *data = (u16) mdic;
194
195out:
196 return ret_val;
197}
198
199/**
200 * e1000_write_phy_reg_mdic - Write MDI control register
202 * @hw - pointer to the HW structure
203 * @offset - register offset to write to
204 * @data - data to write to register at offset
201 * @hw: pointer to the HW structure
202 * @offset: register offset to write to
203 * @data: data to write to register at offset
205 *
206 * Writes data to MDI control register in the PHY at offset.
207 **/
208static s32
209e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
210{
211 struct e1000_phy_info *phy = &hw->phy;
212 u32 i, mdic = 0;

--- 32 unchanged lines hidden (view full) ---

245 }
246
247out:
248 return ret_val;
249}
250
251/**
252 * e1000_read_phy_reg_m88 - Read m88 PHY register
204 *
205 * Writes data to MDI control register in the PHY at offset.
206 **/
207static s32
208e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
209{
210 struct e1000_phy_info *phy = &hw->phy;
211 u32 i, mdic = 0;

--- 32 unchanged lines hidden (view full) ---

244 }
245
246out:
247 return ret_val;
248}
249
250/**
251 * e1000_read_phy_reg_m88 - Read m88 PHY register
253 * @hw - pointer to the HW structure
254 * @offset - register offset to be read
255 * @data - pointer to the read data
252 * @hw: pointer to the HW structure
253 * @offset: register offset to be read
254 * @data: pointer to the read data
256 *
257 * Acquires semaphore, if necessary, then reads the PHY register at offset
258 * and storing the retrieved information in data. Release any acquired
259 * semaphores before exiting.
260 **/
261s32
262e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
263{

--- 12 unchanged lines hidden (view full) ---

276 e1000_release_phy(hw);
277
278out:
279 return ret_val;
280}
281
282/**
283 * e1000_write_phy_reg_m88 - Write m88 PHY register
255 *
256 * Acquires semaphore, if necessary, then reads the PHY register at offset
257 * and storing the retrieved information in data. Release any acquired
258 * semaphores before exiting.
259 **/
260s32
261e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
262{

--- 12 unchanged lines hidden (view full) ---

275 e1000_release_phy(hw);
276
277out:
278 return ret_val;
279}
280
281/**
282 * e1000_write_phy_reg_m88 - Write m88 PHY register
284 * @hw - pointer to the HW structure
285 * @offset - register offset to write to
286 * @data - data to write at register offset
283 * @hw: pointer to the HW structure
284 * @offset: register offset to write to
285 * @data: data to write at register offset
287 *
288 * Acquires semaphore, if necessary, then writes the data to PHY register
289 * at the offset. Release any acquired semaphores before exiting.
290 **/
291s32
292e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
293{
294 s32 ret_val;

--- 11 unchanged lines hidden (view full) ---

306 e1000_release_phy(hw);
307
308out:
309 return ret_val;
310}
311
312/**
313 * e1000_read_phy_reg_igp - Read igp PHY register
286 *
287 * Acquires semaphore, if necessary, then writes the data to PHY register
288 * at the offset. Release any acquired semaphores before exiting.
289 **/
290s32
291e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
292{
293 s32 ret_val;

--- 11 unchanged lines hidden (view full) ---

305 e1000_release_phy(hw);
306
307out:
308 return ret_val;
309}
310
311/**
312 * e1000_read_phy_reg_igp - Read igp PHY register
314 * @hw - pointer to the HW structure
315 * @offset - register offset to be read
316 * @data - pointer to the read data
313 * @hw: pointer to the HW structure
314 * @offset: register offset to be read
315 * @data: pointer to the read data
317 *
318 * Acquires semaphore, if necessary, then reads the PHY register at offset
319 * and storing the retrieved information in data. Release any acquired
320 * semaphores before exiting.
321 **/
322s32
323e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
324{

--- 22 unchanged lines hidden (view full) ---

347 e1000_release_phy(hw);
348
349out:
350 return ret_val;
351}
352
353/**
354 * e1000_write_phy_reg_igp - Write igp PHY register
316 *
317 * Acquires semaphore, if necessary, then reads the PHY register at offset
318 * and storing the retrieved information in data. Release any acquired
319 * semaphores before exiting.
320 **/
321s32
322e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
323{

--- 22 unchanged lines hidden (view full) ---

346 e1000_release_phy(hw);
347
348out:
349 return ret_val;
350}
351
352/**
353 * e1000_write_phy_reg_igp - Write igp PHY register
355 * @hw - pointer to the HW structure
356 * @offset - register offset to write to
357 * @data - data to write at register offset
354 * @hw: pointer to the HW structure
355 * @offset: register offset to write to
356 * @data: data to write at register offset
358 *
359 * Acquires semaphore, if necessary, then writes the data to PHY register
360 * at the offset. Release any acquired semaphores before exiting.
361 **/
362s32
363e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
364{
365 s32 ret_val;

--- 21 unchanged lines hidden (view full) ---

387 e1000_release_phy(hw);
388
389out:
390 return ret_val;
391}
392
393/**
394 * e1000_read_kmrn_reg_generic - Read kumeran register
357 *
358 * Acquires semaphore, if necessary, then writes the data to PHY register
359 * at the offset. Release any acquired semaphores before exiting.
360 **/
361s32
362e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
363{
364 s32 ret_val;

--- 21 unchanged lines hidden (view full) ---

386 e1000_release_phy(hw);
387
388out:
389 return ret_val;
390}
391
392/**
393 * e1000_read_kmrn_reg_generic - Read kumeran register
395 * @hw - pointer to the HW structure
396 * @offset - register offset to be read
397 * @data - pointer to the read data
394 * @hw: pointer to the HW structure
395 * @offset: register offset to be read
396 * @data: pointer to the read data
398 *
399 * Acquires semaphore, if necessary. Then reads the PHY register at offset
400 * using the kumeran interface. The information retrieved is stored in data.
401 * Release any acquired semaphores before exiting.
402 **/
403s32
404e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
405{

--- 18 unchanged lines hidden (view full) ---

424 e1000_release_phy(hw);
425
426out:
427 return ret_val;
428}
429
430/**
431 * e1000_write_kmrn_reg_generic - Write kumeran register
397 *
398 * Acquires semaphore, if necessary. Then reads the PHY register at offset
399 * using the kumeran interface. The information retrieved is stored in data.
400 * Release any acquired semaphores before exiting.
401 **/
402s32
403e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
404{

--- 18 unchanged lines hidden (view full) ---

423 e1000_release_phy(hw);
424
425out:
426 return ret_val;
427}
428
429/**
430 * e1000_write_kmrn_reg_generic - Write kumeran register
432 * @hw - pointer to the HW structure
433 * @offset - register offset to write to
434 * @data - data to write at register offset
431 * @hw: pointer to the HW structure
432 * @offset: register offset to write to
433 * @data: data to write at register offset
435 *
436 * Acquires semaphore, if necessary. Then write the data to PHY register
437 * at the offset using the kumeran interface. Release any acquired semaphores
438 * before exiting.
439 **/
440s32
441e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
442{

--- 14 unchanged lines hidden (view full) ---

457 e1000_release_phy(hw);
458
459out:
460 return ret_val;
461}
462
463/**
464 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
434 *
435 * Acquires semaphore, if necessary. Then write the data to PHY register
436 * at the offset using the kumeran interface. Release any acquired semaphores
437 * before exiting.
438 **/
439s32
440e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
441{

--- 14 unchanged lines hidden (view full) ---

456 e1000_release_phy(hw);
457
458out:
459 return ret_val;
460}
461
462/**
463 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
465 * @hw - pointer to the HW structure
464 * @hw: pointer to the HW structure
466 *
467 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
468 * and downshift values are set also.
469 **/
470s32
471e1000_copper_link_setup_m88(struct e1000_hw *hw)
472{
473 struct e1000_phy_info *phy = &hw->phy;

--- 92 unchanged lines hidden (view full) ---

566 }
567
568out:
569 return ret_val;
570}
571
572/**
573 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
465 *
466 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
467 * and downshift values are set also.
468 **/
469s32
470e1000_copper_link_setup_m88(struct e1000_hw *hw)
471{
472 struct e1000_phy_info *phy = &hw->phy;

--- 92 unchanged lines hidden (view full) ---

565 }
566
567out:
568 return ret_val;
569}
570
571/**
572 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
574 * @hw - pointer to the HW structure
573 * @hw: pointer to the HW structure
575 *
576 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
577 * igp PHY's.
578 **/
579s32
580e1000_copper_link_setup_igp(struct e1000_hw *hw)
581{
582 struct e1000_phy_info *phy = &hw->phy;

--- 117 unchanged lines hidden (view full) ---

700 }
701
702out:
703 return ret_val;
704}
705
706/**
707 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
574 *
575 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
576 * igp PHY's.
577 **/
578s32
579e1000_copper_link_setup_igp(struct e1000_hw *hw)
580{
581 struct e1000_phy_info *phy = &hw->phy;

--- 117 unchanged lines hidden (view full) ---

699 }
700
701out:
702 return ret_val;
703}
704
705/**
706 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
708 * @hw - pointer to the HW structure
707 * @hw: pointer to the HW structure
709 *
710 * Performs initial bounds checking on autoneg advertisement parameter, then
711 * configure to advertise the full capability. Setup the PHY to autoneg
712 * and restart the negotiation process between the link partner. If
713 * wait_for_link, then wait for autoneg to complete before exiting.
714 **/
715s32
716e1000_copper_link_autoneg(struct e1000_hw *hw)

--- 50 unchanged lines hidden (view full) ---

767 hw->mac.get_link_status = TRUE;
768
769out:
770 return ret_val;
771}
772
773/**
774 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
708 *
709 * Performs initial bounds checking on autoneg advertisement parameter, then
710 * configure to advertise the full capability. Setup the PHY to autoneg
711 * and restart the negotiation process between the link partner. If
712 * wait_for_link, then wait for autoneg to complete before exiting.
713 **/
714s32
715e1000_copper_link_autoneg(struct e1000_hw *hw)

--- 50 unchanged lines hidden (view full) ---

766 hw->mac.get_link_status = TRUE;
767
768out:
769 return ret_val;
770}
771
772/**
773 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
775 * @hw - pointer to the HW structure
774 * @hw: pointer to the HW structure
776 *
777 * Reads the MII auto-neg advertisement register and/or the 1000T control
778 * register and if the PHY is already setup for auto-negotiation, then
779 * return successful. Otherwise, setup advertisement and flow control to
780 * the appropriate values for the wanted auto-negotiation.
781 **/
782s32
783e1000_phy_setup_autoneg(struct e1000_hw *hw)

--- 145 unchanged lines hidden (view full) ---

929 }
930
931out:
932 return ret_val;
933}
934
935/**
936 * e1000_setup_copper_link_generic - Configure copper link settings
775 *
776 * Reads the MII auto-neg advertisement register and/or the 1000T control
777 * register and if the PHY is already setup for auto-negotiation, then
778 * return successful. Otherwise, setup advertisement and flow control to
779 * the appropriate values for the wanted auto-negotiation.
780 **/
781s32
782e1000_phy_setup_autoneg(struct e1000_hw *hw)

--- 145 unchanged lines hidden (view full) ---

928 }
929
930out:
931 return ret_val;
932}
933
934/**
935 * e1000_setup_copper_link_generic - Configure copper link settings
937 * @hw - pointer to the HW structure
936 * @hw: pointer to the HW structure
938 *
939 * Calls the appropriate function to configure the link for auto-neg or forced
940 * speed and duplex. Then we check for link, once link is established calls
941 * to configure collision distance and flow control are called. If link is
942 * not established, we return -E1000_ERR_PHY (-2).
943 **/
944s32
945e1000_setup_copper_link_generic(struct e1000_hw *hw)

--- 39 unchanged lines hidden (view full) ---

985 }
986
987out:
988 return ret_val;
989}
990
991/**
992 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
937 *
938 * Calls the appropriate function to configure the link for auto-neg or forced
939 * speed and duplex. Then we check for link, once link is established calls
940 * to configure collision distance and flow control are called. If link is
941 * not established, we return -E1000_ERR_PHY (-2).
942 **/
943s32
944e1000_setup_copper_link_generic(struct e1000_hw *hw)

--- 39 unchanged lines hidden (view full) ---

984 }
985
986out:
987 return ret_val;
988}
989
990/**
991 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
993 * @hw - pointer to the HW structure
992 * @hw: pointer to the HW structure
994 *
995 * Calls the PHY setup function to force speed and duplex. Clears the
996 * auto-crossover to force MDI manually. Waits for link and returns
997 * successful if link up is successful, else -E1000_ERR_PHY (-2).
998 **/
999s32
1000e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1001{

--- 56 unchanged lines hidden (view full) ---

1058 }
1059
1060out:
1061 return ret_val;
1062}
1063
1064/**
1065 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
993 *
994 * Calls the PHY setup function to force speed and duplex. Clears the
995 * auto-crossover to force MDI manually. Waits for link and returns
996 * successful if link up is successful, else -E1000_ERR_PHY (-2).
997 **/
998s32
999e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1000{

--- 56 unchanged lines hidden (view full) ---

1057 }
1058
1059out:
1060 return ret_val;
1061}
1062
1063/**
1064 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1066 * @hw - pointer to the HW structure
1065 * @hw: pointer to the HW structure
1067 *
1068 * Calls the PHY setup function to force speed and duplex. Clears the
1069 * auto-crossover to force MDI manually. Resets the PHY to commit the
1070 * changes. If time expires while waiting for link up, we reset the DSP.
1071 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
1072 * successful completion, else return corresponding error code.
1073 **/
1074s32

--- 92 unchanged lines hidden (view full) ---

1167 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1168
1169out:
1170 return ret_val;
1171}
1172
1173/**
1174 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1066 *
1067 * Calls the PHY setup function to force speed and duplex. Clears the
1068 * auto-crossover to force MDI manually. Resets the PHY to commit the
1069 * changes. If time expires while waiting for link up, we reset the DSP.
1070 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
1071 * successful completion, else return corresponding error code.
1072 **/
1073s32

--- 92 unchanged lines hidden (view full) ---

1166 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1167
1168out:
1169 return ret_val;
1170}
1171
1172/**
1173 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1175 * @hw - pointer to the HW structure
1176 * @phy_ctrl - pointer to current value of PHY_CONTROL
1174 * @hw: pointer to the HW structure
1175 * @phy_ctrl: pointer to current value of PHY_CONTROL
1177 *
1178 * Forces speed and duplex on the PHY by doing the following: disable flow
1179 * control, force speed/duplex on the MAC, disable auto speed detection,
1180 * disable auto-negotiation, configure duplex, configure speed, configure
1181 * the collision distance, write configuration to CTRL register. The
1182 * caller must write to the PHY_CONTROL register for these settings to
1183 * take affect.
1184 **/

--- 45 unchanged lines hidden (view full) ---

1230
1231 e1000_config_collision_dist_generic(hw);
1232
1233 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1234}
1235
1236/**
1237 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1176 *
1177 * Forces speed and duplex on the PHY by doing the following: disable flow
1178 * control, force speed/duplex on the MAC, disable auto speed detection,
1179 * disable auto-negotiation, configure duplex, configure speed, configure
1180 * the collision distance, write configuration to CTRL register. The
1181 * caller must write to the PHY_CONTROL register for these settings to
1182 * take affect.
1183 **/

--- 45 unchanged lines hidden (view full) ---

1229
1230 e1000_config_collision_dist_generic(hw);
1231
1232 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1233}
1234
1235/**
1236 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1238 * @hw - pointer to the HW structure
1239 * @active boolean used to enable/disable lplu
1237 * @hw: pointer to the HW structure
1238 * @active: boolean used to enable/disable lplu
1240 *
1241 * Success returns 0, Failure returns 1
1242 *
1243 * The low power link up (lplu) state is set to the power management level D3
1244 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1245 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1246 * is used during Dx states where the power conservation is most important.
1247 * During driver activity, SmartSpeed should be enabled so performance is

--- 74 unchanged lines hidden (view full) ---

1322 }
1323
1324out:
1325 return ret_val;
1326}
1327
1328/**
1329 * e1000_check_downshift_generic - Checks whether a downshift in speed occured
1239 *
1240 * Success returns 0, Failure returns 1
1241 *
1242 * The low power link up (lplu) state is set to the power management level D3
1243 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1244 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1245 * is used during Dx states where the power conservation is most important.
1246 * During driver activity, SmartSpeed should be enabled so performance is

--- 74 unchanged lines hidden (view full) ---

1321 }
1322
1323out:
1324 return ret_val;
1325}
1326
1327/**
1328 * e1000_check_downshift_generic - Checks whether a downshift in speed occured
1330 * @hw - pointer to the HW structure
1329 * @hw: pointer to the HW structure
1331 *
1332 * Success returns 0, Failure returns 1
1333 *
1334 * A downshift is detected by querying the PHY link health.
1335 **/
1336s32
1337e1000_check_downshift_generic(struct e1000_hw *hw)
1338{

--- 28 unchanged lines hidden (view full) ---

1367 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE;
1368
1369out:
1370 return ret_val;
1371}
1372
1373/**
1374 * e1000_check_polarity_m88 - Checks the polarity.
1330 *
1331 * Success returns 0, Failure returns 1
1332 *
1333 * A downshift is detected by querying the PHY link health.
1334 **/
1335s32
1336e1000_check_downshift_generic(struct e1000_hw *hw)
1337{

--- 28 unchanged lines hidden (view full) ---

1366 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE;
1367
1368out:
1369 return ret_val;
1370}
1371
1372/**
1373 * e1000_check_polarity_m88 - Checks the polarity.
1375 * @hw - pointer to the HW structure
1374 * @hw: pointer to the HW structure
1376 *
1377 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1378 *
1379 * Polarity is determined based on the PHY specific status register.
1380 **/
1381s32
1382e1000_check_polarity_m88(struct e1000_hw *hw)
1383{

--- 10 unchanged lines hidden (view full) ---

1394 ? e1000_rev_polarity_reversed
1395 : e1000_rev_polarity_normal;
1396
1397 return ret_val;
1398}
1399
1400/**
1401 * e1000_check_polarity_igp - Checks the polarity.
1375 *
1376 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1377 *
1378 * Polarity is determined based on the PHY specific status register.
1379 **/
1380s32
1381e1000_check_polarity_m88(struct e1000_hw *hw)
1382{

--- 10 unchanged lines hidden (view full) ---

1393 ? e1000_rev_polarity_reversed
1394 : e1000_rev_polarity_normal;
1395
1396 return ret_val;
1397}
1398
1399/**
1400 * e1000_check_polarity_igp - Checks the polarity.
1402 * @hw - pointer to the HW structure
1401 * @hw: pointer to the HW structure
1403 *
1404 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1405 *
1406 * Polarity is determined based on the PHY port status register, and the
1407 * current speed (since there is no polarity at 100Mbps).
1408 **/
1409s32
1410e1000_check_polarity_igp(struct e1000_hw *hw)

--- 30 unchanged lines hidden (view full) ---

1441 : e1000_rev_polarity_normal;
1442
1443out:
1444 return ret_val;
1445}
1446
1447/**
1448 * e1000_wait_autoneg_generic - Wait for auto-neg compeletion
1402 *
1403 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1404 *
1405 * Polarity is determined based on the PHY port status register, and the
1406 * current speed (since there is no polarity at 100Mbps).
1407 **/
1408s32
1409e1000_check_polarity_igp(struct e1000_hw *hw)

--- 30 unchanged lines hidden (view full) ---

1440 : e1000_rev_polarity_normal;
1441
1442out:
1443 return ret_val;
1444}
1445
1446/**
1447 * e1000_wait_autoneg_generic - Wait for auto-neg compeletion
1449 * @hw - pointer to the HW structure
1448 * @hw: pointer to the HW structure
1450 *
1451 * Waits for auto-negotiation to complete or for the auto-negotiation time
1452 * limit to expire, which ever happens first.
1453 **/
1454s32
1455e1000_wait_autoneg_generic(struct e1000_hw *hw)
1456{
1457 s32 ret_val = E1000_SUCCESS;

--- 17 unchanged lines hidden (view full) ---

1475 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1476 * has completed.
1477 */
1478 return ret_val;
1479}
1480
1481/**
1482 * e1000_phy_has_link_generic - Polls PHY for link
1449 *
1450 * Waits for auto-negotiation to complete or for the auto-negotiation time
1451 * limit to expire, which ever happens first.
1452 **/
1453s32
1454e1000_wait_autoneg_generic(struct e1000_hw *hw)
1455{
1456 s32 ret_val = E1000_SUCCESS;

--- 17 unchanged lines hidden (view full) ---

1474 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1475 * has completed.
1476 */
1477 return ret_val;
1478}
1479
1480/**
1481 * e1000_phy_has_link_generic - Polls PHY for link
1483 * @hw - pointer to the HW structure
1484 * @iterations - number of times to poll for link
1485 * @usec_interval - delay between polling attempts
1486 * @success - pointer to whether polling was successful or not
1482 * @hw: pointer to the HW structure
1483 * @iterations: number of times to poll for link
1484 * @usec_interval: delay between polling attempts
1485 * @success: pointer to whether polling was successful or not
1487 *
1488 * Polls the PHY status register for link, 'iterations' number of times.
1489 **/
1490s32
1491e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1492 u32 usec_interval, boolean_t *success)
1493{
1494 s32 ret_val = E1000_SUCCESS;

--- 22 unchanged lines hidden (view full) ---

1517
1518 *success = (i < iterations) ? TRUE : FALSE;
1519
1520 return ret_val;
1521}
1522
1523/**
1524 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
1486 *
1487 * Polls the PHY status register for link, 'iterations' number of times.
1488 **/
1489s32
1490e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1491 u32 usec_interval, boolean_t *success)
1492{
1493 s32 ret_val = E1000_SUCCESS;

--- 22 unchanged lines hidden (view full) ---

1516
1517 *success = (i < iterations) ? TRUE : FALSE;
1518
1519 return ret_val;
1520}
1521
1522/**
1523 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
1525 * @hw - pointer to the HW structure
1524 * @hw: pointer to the HW structure
1526 *
1527 * Reads the PHY specific status register to retrieve the cable length
1528 * information. The cable length is determined by averaging the minimum and
1529 * maximum values to get the "average" cable length. The m88 PHY has four
1530 * possible cable length values, which are:
1531 * Register Value Cable Length
1532 * 0 < 50 meters
1533 * 1 50 - 80 meters

--- 22 unchanged lines hidden (view full) ---

1556 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1557
1558out:
1559 return ret_val;
1560}
1561
1562/**
1563 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1525 *
1526 * Reads the PHY specific status register to retrieve the cable length
1527 * information. The cable length is determined by averaging the minimum and
1528 * maximum values to get the "average" cable length. The m88 PHY has four
1529 * possible cable length values, which are:
1530 * Register Value Cable Length
1531 * 0 < 50 meters
1532 * 1 50 - 80 meters

--- 22 unchanged lines hidden (view full) ---

1555 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1556
1557out:
1558 return ret_val;
1559}
1560
1561/**
1562 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1564 * @hw - pointer to the HW structure
1563 * @hw: pointer to the HW structure
1565 *
1566 * The automatic gain control (agc) normalizes the amplitude of the
1567 * received signal, adjusting for the attenuation produced by the
1568 * cable. By reading the AGC registers, which reperesent the
1569 * cobination of course and fine gain value, the value can be put
1570 * into a lookup table to obtain the approximate cable length
1571 * for each channel.
1572 **/

--- 56 unchanged lines hidden (view full) ---

1629 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1630
1631out:
1632 return ret_val;
1633}
1634
1635/**
1636 * e1000_get_phy_info_m88 - Retrieve PHY information
1564 *
1565 * The automatic gain control (agc) normalizes the amplitude of the
1566 * received signal, adjusting for the attenuation produced by the
1567 * cable. By reading the AGC registers, which reperesent the
1568 * cobination of course and fine gain value, the value can be put
1569 * into a lookup table to obtain the approximate cable length
1570 * for each channel.
1571 **/

--- 56 unchanged lines hidden (view full) ---

1628 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1629
1630out:
1631 return ret_val;
1632}
1633
1634/**
1635 * e1000_get_phy_info_m88 - Retrieve PHY information
1637 * @hw - pointer to the HW structure
1636 * @hw: pointer to the HW structure
1638 *
1639 * Valid for only copper links. Read the PHY status register (sticky read)
1640 * to verify that link is up. Read the PHY special control register to
1641 * determine the polarity and 10base-T extended distance. Read the PHY
1642 * special status register to determine MDI/MDIx and current speed. If
1643 * speed is 1000, then determine cable length, local and remote receiver.
1644 **/
1645s32

--- 64 unchanged lines hidden (view full) ---

1710 }
1711
1712out:
1713 return ret_val;
1714}
1715
1716/**
1717 * e1000_get_phy_info_igp - Retrieve igp PHY information
1637 *
1638 * Valid for only copper links. Read the PHY status register (sticky read)
1639 * to verify that link is up. Read the PHY special control register to
1640 * determine the polarity and 10base-T extended distance. Read the PHY
1641 * special status register to determine MDI/MDIx and current speed. If
1642 * speed is 1000, then determine cable length, local and remote receiver.
1643 **/
1644s32

--- 64 unchanged lines hidden (view full) ---

1709 }
1710
1711out:
1712 return ret_val;
1713}
1714
1715/**
1716 * e1000_get_phy_info_igp - Retrieve igp PHY information
1718 * @hw - pointer to the HW structure
1717 * @hw: pointer to the HW structure
1719 *
1720 * Read PHY status to determine if link is up. If link is up, then
1721 * set/determine 10base-T extended distance and polarity correction. Read
1722 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1723 * determine on the cable length, local and remote receiver.
1724 **/
1725s32
1726e1000_get_phy_info_igp(struct e1000_hw *hw)

--- 51 unchanged lines hidden (view full) ---

1778 }
1779
1780out:
1781 return ret_val;
1782}
1783
1784/**
1785 * e1000_phy_sw_reset_generic - PHY software reset
1718 *
1719 * Read PHY status to determine if link is up. If link is up, then
1720 * set/determine 10base-T extended distance and polarity correction. Read
1721 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1722 * determine on the cable length, local and remote receiver.
1723 **/
1724s32
1725e1000_get_phy_info_igp(struct e1000_hw *hw)

--- 51 unchanged lines hidden (view full) ---

1777 }
1778
1779out:
1780 return ret_val;
1781}
1782
1783/**
1784 * e1000_phy_sw_reset_generic - PHY software reset
1786 * @hw - pointer to the HW structure
1785 * @hw: pointer to the HW structure
1787 *
1788 * Does a software reset of the PHY by reading the PHY control register and
1789 * setting/write the control register reset bit to the PHY.
1790 **/
1791s32
1792e1000_phy_sw_reset_generic(struct e1000_hw *hw)
1793{
1794 s32 ret_val;

--- 13 unchanged lines hidden (view full) ---

1808 usec_delay(1);
1809
1810out:
1811 return ret_val;
1812}
1813
1814/**
1815 * e1000_phy_hw_reset_generic - PHY hardware reset
1786 *
1787 * Does a software reset of the PHY by reading the PHY control register and
1788 * setting/write the control register reset bit to the PHY.
1789 **/
1790s32
1791e1000_phy_sw_reset_generic(struct e1000_hw *hw)
1792{
1793 s32 ret_val;

--- 13 unchanged lines hidden (view full) ---

1807 usec_delay(1);
1808
1809out:
1810 return ret_val;
1811}
1812
1813/**
1814 * e1000_phy_hw_reset_generic - PHY hardware reset
1816 * @hw - pointer to the HW structure
1815 * @hw: pointer to the HW structure
1817 *
1818 * Verify the reset block is not blocking us from resetting. Acquire
1819 * semaphore (if necessary) and read/set/write the device control reset
1820 * bit in the PHY. Wait the appropriate delay time for the device to
1821 * reset and relase the semaphore (if necessary).
1822 **/
1823s32
1824e1000_phy_hw_reset_generic(struct e1000_hw *hw)

--- 30 unchanged lines hidden (view full) ---

1855 ret_val = e1000_get_phy_cfg_done(hw);
1856
1857out:
1858 return ret_val;
1859}
1860
1861/**
1862 * e1000_get_cfg_done_generic - Generic configuration done
1816 *
1817 * Verify the reset block is not blocking us from resetting. Acquire
1818 * semaphore (if necessary) and read/set/write the device control reset
1819 * bit in the PHY. Wait the appropriate delay time for the device to
1820 * reset and relase the semaphore (if necessary).
1821 **/
1822s32
1823e1000_phy_hw_reset_generic(struct e1000_hw *hw)

--- 30 unchanged lines hidden (view full) ---

1854 ret_val = e1000_get_phy_cfg_done(hw);
1855
1856out:
1857 return ret_val;
1858}
1859
1860/**
1861 * e1000_get_cfg_done_generic - Generic configuration done
1863 * @hw - pointer to the HW structure
1862 * @hw: pointer to the HW structure
1864 *
1865 * Generic function to wait 10 milli-seconds for configuration to complete
1866 * and return success.
1867 **/
1868s32
1869e1000_get_cfg_done_generic(struct e1000_hw *hw)
1870{
1871 DEBUGFUNC("e1000_get_cfg_done_generic");
1872
1873 msec_delay_irq(10);
1874
1875 return E1000_SUCCESS;
1876}
1877
1878/* Internal function pointers */
1879
1880/**
1881 * e1000_get_phy_cfg_done - Generic PHY configuration done
1863 *
1864 * Generic function to wait 10 milli-seconds for configuration to complete
1865 * and return success.
1866 **/
1867s32
1868e1000_get_cfg_done_generic(struct e1000_hw *hw)
1869{
1870 DEBUGFUNC("e1000_get_cfg_done_generic");
1871
1872 msec_delay_irq(10);
1873
1874 return E1000_SUCCESS;
1875}
1876
1877/* Internal function pointers */
1878
1879/**
1880 * e1000_get_phy_cfg_done - Generic PHY configuration done
1882 * @hw - pointer to the HW structure
1881 * @hw: pointer to the HW structure
1883 *
1884 * Return success if silicon family did not implement a family specific
1885 * get_cfg_done function.
1886 **/
1887s32
1888e1000_get_phy_cfg_done(struct e1000_hw *hw)
1889{
1890 if (hw->func.get_cfg_done != NULL)
1891 return hw->func.get_cfg_done(hw);
1892 else
1893 return E1000_SUCCESS;
1894}
1895
1896/**
1897 * e1000_release_phy - Generic release PHY
1882 *
1883 * Return success if silicon family did not implement a family specific
1884 * get_cfg_done function.
1885 **/
1886s32
1887e1000_get_phy_cfg_done(struct e1000_hw *hw)
1888{
1889 if (hw->func.get_cfg_done != NULL)
1890 return hw->func.get_cfg_done(hw);
1891 else
1892 return E1000_SUCCESS;
1893}
1894
1895/**
1896 * e1000_release_phy - Generic release PHY
1898 * @hw - pointer to the HW structure
1897 * @hw: pointer to the HW structure
1899 *
1900 * Return if silicon family does not require a semaphore when accessing the
1901 * PHY.
1902 **/
1903void
1904e1000_release_phy(struct e1000_hw *hw)
1905{
1906 if (hw->func.release_phy != NULL)
1907 hw->func.release_phy(hw);
1908}
1909
1910/**
1911 * e1000_acquire_phy - Generic acquire PHY
1898 *
1899 * Return if silicon family does not require a semaphore when accessing the
1900 * PHY.
1901 **/
1902void
1903e1000_release_phy(struct e1000_hw *hw)
1904{
1905 if (hw->func.release_phy != NULL)
1906 hw->func.release_phy(hw);
1907}
1908
1909/**
1910 * e1000_acquire_phy - Generic acquire PHY
1912 * @hw - pointer to the HW structure
1911 * @hw: pointer to the HW structure
1913 *
1914 * Return success if silicon family does not require a semaphore when
1915 * accessing the PHY.
1916 **/
1917s32
1918e1000_acquire_phy(struct e1000_hw *hw)
1919{
1920 if (hw->func.acquire_phy != NULL)
1921 return hw->func.acquire_phy(hw);
1922 else
1923 return E1000_SUCCESS;
1924}
1925
1926/**
1927 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
1912 *
1913 * Return success if silicon family does not require a semaphore when
1914 * accessing the PHY.
1915 **/
1916s32
1917e1000_acquire_phy(struct e1000_hw *hw)
1918{
1919 if (hw->func.acquire_phy != NULL)
1920 return hw->func.acquire_phy(hw);
1921 else
1922 return E1000_SUCCESS;
1923}
1924
1925/**
1926 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
1928 * @hw - pointer to the HW structure
1927 * @hw: pointer to the HW structure
1929 *
1930 * When the silicon family has not implemented a forced speed/duplex
1931 * function for the PHY, simply return E1000_SUCCESS.
1932 **/
1933s32
1934e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1935{
1936 if (hw->func.force_speed_duplex != NULL)
1937 return hw->func.force_speed_duplex(hw);
1938 else
1939 return E1000_SUCCESS;
1940}
1941
1942/**
1943 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
1928 *
1929 * When the silicon family has not implemented a forced speed/duplex
1930 * function for the PHY, simply return E1000_SUCCESS.
1931 **/
1932s32
1933e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1934{
1935 if (hw->func.force_speed_duplex != NULL)
1936 return hw->func.force_speed_duplex(hw);
1937 else
1938 return E1000_SUCCESS;
1939}
1940
1941/**
1942 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
1944 * @hw - pointer to the HW structure
1943 * @hw: pointer to the HW structure
1945 *
1946 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
1947 **/
1948s32
1949e1000_phy_init_script_igp3(struct e1000_hw *hw)
1950{
1951 DEBUGOUT("Running IGP 3 PHY init script\n");
1952

--- 64 unchanged lines hidden (view full) ---

2017 e1000_write_phy_reg(hw, 0x001B, 0x2080);
2018 /* Enable wh_fifo read clock in 10/100 modes */
2019 e1000_write_phy_reg(hw, 0x0014, 0x0045);
2020 /* Restart AN, Speed selection is 1000 */
2021 e1000_write_phy_reg(hw, 0x0000, 0x1340);
2022
2023 return E1000_SUCCESS;
2024}
1944 *
1945 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
1946 **/
1947s32
1948e1000_phy_init_script_igp3(struct e1000_hw *hw)
1949{
1950 DEBUGOUT("Running IGP 3 PHY init script\n");
1951

--- 64 unchanged lines hidden (view full) ---

2016 e1000_write_phy_reg(hw, 0x001B, 0x2080);
2017 /* Enable wh_fifo read clock in 10/100 modes */
2018 e1000_write_phy_reg(hw, 0x0014, 0x0045);
2019 /* Restart AN, Speed selection is 1000 */
2020 e1000_write_phy_reg(hw, 0x0000, 0x1340);
2021
2022 return E1000_SUCCESS;
2023}
2024
2025/**
2026 * e1000_get_phy_type_from_id - Get PHY type from id
2027 * @phy_id: phy_id read from the phy
2028 *
2029 * Returns the phy type from the id.
2030 **/
2031e1000_phy_type
2032e1000_get_phy_type_from_id(u32 phy_id)
2033{
2034 e1000_phy_type phy_type = e1000_phy_unknown;
2035
2036 switch (phy_id) {
2037 case M88E1000_I_PHY_ID:
2038 case M88E1000_E_PHY_ID:
2039 case M88E1111_I_PHY_ID:
2040 case M88E1011_I_PHY_ID:
2041 phy_type = e1000_phy_m88;
2042 break;
2043 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2044 phy_type = e1000_phy_igp_2;
2045 break;
2046 case GG82563_E_PHY_ID:
2047 phy_type = e1000_phy_gg82563;
2048 break;
2049 case IGP03E1000_E_PHY_ID:
2050 phy_type = e1000_phy_igp_3;
2051 break;
2052 case IFE_E_PHY_ID:
2053 case IFE_PLUS_E_PHY_ID:
2054 case IFE_C_E_PHY_ID:
2055 phy_type = e1000_phy_ife;
2056 break;
2057 default:
2058 phy_type = e1000_phy_unknown;
2059 break;
2060 }
2061 return phy_type;
2062}
2063
2064