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e1000_ich8lan.c (287990) e1000_ich8lan.c (295323)
1/******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.c 287990 2015-09-19 18:22:59Z sbruno $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.c 295323 2016-02-05 17:14:37Z erj $*/
34
35/* 82562G 10/100 Network Connection
36 * 82562G-2 10/100 Network Connection
37 * 82562GT 10/100 Network Connection
38 * 82562GT-2 10/100 Network Connection
39 * 82562V 10/100 Network Connection
40 * 82562V-2 10/100 Network Connection
41 * 82566DC-2 Gigabit Network Connection

--- 45 unchanged lines hidden (view full) ---

87static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
88static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
89static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
90 bool active);
91static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
92 bool active);
93static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
94 u16 words, u16 *data);
34
35/* 82562G 10/100 Network Connection
36 * 82562G-2 10/100 Network Connection
37 * 82562GT 10/100 Network Connection
38 * 82562GT-2 10/100 Network Connection
39 * 82562V 10/100 Network Connection
40 * 82562V-2 10/100 Network Connection
41 * 82566DC-2 Gigabit Network Connection

--- 45 unchanged lines hidden (view full) ---

87static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
88static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
89static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
90 bool active);
91static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
92 bool active);
93static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
94 u16 words, u16 *data);
95static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
96 u16 *data);
95static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
96 u16 words, u16 *data);
97static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
98static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
97static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
98 u16 words, u16 *data);
99static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
100static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
101static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
99static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
100 u16 *data);
101static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
102static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
103static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
104static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
105static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
106static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);

--- 11 unchanged lines hidden (view full) ---

118static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
119static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
120static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
121static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
122static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
123 u32 offset, u8 *data);
124static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
125 u8 size, u16 *data);
102static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
103 u16 *data);
104static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
105static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
106static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
107static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
108static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
109static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);

--- 11 unchanged lines hidden (view full) ---

121static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
122static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
123static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
124static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
125static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
126 u32 offset, u8 *data);
127static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
128 u8 size, u16 *data);
129static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
130 u32 *data);
131static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
132 u32 offset, u32 *data);
133static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
134 u32 offset, u32 data);
135static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
136 u32 offset, u32 dword);
126static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
127 u32 offset, u16 *data);
128static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
129 u32 offset, u8 byte);
130static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
131static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
132static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
133static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);

--- 93 unchanged lines hidden (view full) ---

227 if (!ret_val)
228 ret_val = e1000_get_phy_id(hw);
229 hw->phy.ops.acquire(hw);
230 }
231
232 if (ret_val)
233 return FALSE;
234out:
137static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
138 u32 offset, u16 *data);
139static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
140 u32 offset, u8 byte);
141static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
142static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
143static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
144static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);

--- 93 unchanged lines hidden (view full) ---

238 if (!ret_val)
239 ret_val = e1000_get_phy_id(hw);
240 hw->phy.ops.acquire(hw);
241 }
242
243 if (ret_val)
244 return FALSE;
245out:
235 if (hw->mac.type == e1000_pch_lpt) {
236 /* Unforce SMBus mode in PHY */
237 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
238 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
239 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
246 if ((hw->mac.type == e1000_pch_lpt) ||
247 (hw->mac.type == e1000_pch_spt)) {
248 /* Only unforce SMBus if ME is not active */
249 if (!(E1000_READ_REG(hw, E1000_FWSM) &
250 E1000_ICH_FWSM_FW_VALID)) {
251 /* Unforce SMBus mode in PHY */
252 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
253 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
254 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
240
255
241 /* Unforce SMBus mode in MAC */
242 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
243 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
244 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
256 /* Unforce SMBus mode in MAC */
257 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
258 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
259 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
260 }
245 }
246
247 return TRUE;
248}
249
250/**
251 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
252 * @hw: pointer to the HW structure

--- 70 unchanged lines hidden (view full) ---

323 }
324
325 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
326 * inaccessible and resetting the PHY is not blocked, toggle the
327 * LANPHYPC Value bit to force the interconnect to PCIe mode.
328 */
329 switch (hw->mac.type) {
330 case e1000_pch_lpt:
261 }
262
263 return TRUE;
264}
265
266/**
267 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
268 * @hw: pointer to the HW structure

--- 70 unchanged lines hidden (view full) ---

339 }
340
341 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
342 * inaccessible and resetting the PHY is not blocked, toggle the
343 * LANPHYPC Value bit to force the interconnect to PCIe mode.
344 */
345 switch (hw->mac.type) {
346 case e1000_pch_lpt:
347 case e1000_pch_spt:
331 if (e1000_phy_is_accessible_pchlan(hw))
332 break;
333
334 /* Before toggling LANPHYPC, see if PHY is accessible by
335 * forcing MAC to SMBus mode first.
336 */
337 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
338 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;

--- 131 unchanged lines hidden (view full) ---

470 ret_val = e1000_get_phy_id(hw);
471 if (ret_val)
472 return ret_val;
473 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
474 break;
475 /* fall-through */
476 case e1000_pch2lan:
477 case e1000_pch_lpt:
348 if (e1000_phy_is_accessible_pchlan(hw))
349 break;
350
351 /* Before toggling LANPHYPC, see if PHY is accessible by
352 * forcing MAC to SMBus mode first.
353 */
354 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
355 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;

--- 131 unchanged lines hidden (view full) ---

487 ret_val = e1000_get_phy_id(hw);
488 if (ret_val)
489 return ret_val;
490 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
491 break;
492 /* fall-through */
493 case e1000_pch2lan:
494 case e1000_pch_lpt:
495 case e1000_pch_spt:
478 /* In case the PHY needs to be in mdio slow mode,
479 * set slow mode and try to get the PHY id again.
480 */
481 ret_val = e1000_set_mdio_slow_mode_hv(hw);
482 if (ret_val)
483 return ret_val;
484 ret_val = e1000_get_phy_id(hw);
485 if (ret_val)

--- 126 unchanged lines hidden (view full) ---

612 * pointers.
613 **/
614static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
615{
616 struct e1000_nvm_info *nvm = &hw->nvm;
617 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
618 u32 gfpreg, sector_base_addr, sector_end_addr;
619 u16 i;
496 /* In case the PHY needs to be in mdio slow mode,
497 * set slow mode and try to get the PHY id again.
498 */
499 ret_val = e1000_set_mdio_slow_mode_hv(hw);
500 if (ret_val)
501 return ret_val;
502 ret_val = e1000_get_phy_id(hw);
503 if (ret_val)

--- 126 unchanged lines hidden (view full) ---

630 * pointers.
631 **/
632static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
633{
634 struct e1000_nvm_info *nvm = &hw->nvm;
635 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
636 u32 gfpreg, sector_base_addr, sector_end_addr;
637 u16 i;
638 u32 nvm_size;
620
621 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
622
639
640 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
641
623 /* Can't read flash registers if the register set isn't mapped. */
624 nvm->type = e1000_nvm_flash_sw;
642 nvm->type = e1000_nvm_flash_sw;
625 if (!hw->flash_address) {
626 DEBUGOUT("ERROR: Flash registers not mapped\n");
627 return -E1000_ERR_CONFIG;
628 }
629
643
630 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
644 if (hw->mac.type == e1000_pch_spt) {
645 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
646 * STRAP register. This is because in SPT the GbE Flash region
647 * is no longer accessed through the flash registers. Instead,
648 * the mechanism has changed, and the Flash region access
649 * registers are now implemented in GbE memory space.
650 */
651 nvm->flash_base_addr = 0;
652 nvm_size =
653 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
654 * NVM_SIZE_MULTIPLIER;
655 nvm->flash_bank_size = nvm_size / 2;
656 /* Adjust to word count */
657 nvm->flash_bank_size /= sizeof(u16);
658 /* Set the base address for flash register access */
659 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
660 } else {
661 /* Can't read flash registers if register set isn't mapped. */
662 if (!hw->flash_address) {
663 DEBUGOUT("ERROR: Flash registers not mapped\n");
664 return -E1000_ERR_CONFIG;
665 }
631
666
632 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
633 * Add 1 to sector_end_addr since this sector is included in
634 * the overall size.
635 */
636 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
637 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
667 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
638
668
639 /* flash_base_addr is byte-aligned */
640 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
669 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
670 * Add 1 to sector_end_addr since this sector is included in
671 * the overall size.
672 */
673 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
674 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
641
675
642 /* find total size of the NVM, then cut in half since the total
643 * size represents two separate NVM banks.
644 */
645 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
646 << FLASH_SECTOR_ADDR_SHIFT);
647 nvm->flash_bank_size /= 2;
648 /* Adjust to word count */
649 nvm->flash_bank_size /= sizeof(u16);
676 /* flash_base_addr is byte-aligned */
677 nvm->flash_base_addr = sector_base_addr
678 << FLASH_SECTOR_ADDR_SHIFT;
650
679
680 /* find total size of the NVM, then cut in half since the total
681 * size represents two separate NVM banks.
682 */
683 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
684 << FLASH_SECTOR_ADDR_SHIFT);
685 nvm->flash_bank_size /= 2;
686 /* Adjust to word count */
687 nvm->flash_bank_size /= sizeof(u16);
688 }
689
651 nvm->word_size = E1000_SHADOW_RAM_WORDS;
652
653 /* Clear shadow ram */
654 for (i = 0; i < nvm->word_size; i++) {
655 dev_spec->shadow_ram[i].modified = FALSE;
656 dev_spec->shadow_ram[i].value = 0xFFFF;
657 }
658
659 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
660 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
661
662 /* Function Pointers */
663 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
664 nvm->ops.release = e1000_release_nvm_ich8lan;
690 nvm->word_size = E1000_SHADOW_RAM_WORDS;
691
692 /* Clear shadow ram */
693 for (i = 0; i < nvm->word_size; i++) {
694 dev_spec->shadow_ram[i].modified = FALSE;
695 dev_spec->shadow_ram[i].value = 0xFFFF;
696 }
697
698 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
699 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
700
701 /* Function Pointers */
702 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
703 nvm->ops.release = e1000_release_nvm_ich8lan;
665 nvm->ops.read = e1000_read_nvm_ich8lan;
666 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
704 if (hw->mac.type == e1000_pch_spt) {
705 nvm->ops.read = e1000_read_nvm_spt;
706 nvm->ops.update = e1000_update_nvm_checksum_spt;
707 } else {
708 nvm->ops.read = e1000_read_nvm_ich8lan;
709 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
710 }
667 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
668 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
669 nvm->ops.write = e1000_write_nvm_ich8lan;
670
671 return E1000_SUCCESS;
672}
673
674/**
675 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
676 * @hw: pointer to the HW structure
677 *
678 * Initialize family-specific MAC parameters and function
679 * pointers.
680 **/
681static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
682{
683 struct e1000_mac_info *mac = &hw->mac;
711 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
712 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
713 nvm->ops.write = e1000_write_nvm_ich8lan;
714
715 return E1000_SUCCESS;
716}
717
718/**
719 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
720 * @hw: pointer to the HW structure
721 *
722 * Initialize family-specific MAC parameters and function
723 * pointers.
724 **/
725static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
726{
727 struct e1000_mac_info *mac = &hw->mac;
684#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
685 u16 pci_cfg;
686#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
687
688 DEBUGFUNC("e1000_init_mac_params_ich8lan");
689
690 /* Set media type function pointer */
691 hw->phy.media_type = e1000_media_type_copper;
692
693 /* Set mta register count */
694 mac->mta_reg_count = 32;

--- 52 unchanged lines hidden (view full) ---

747 mac->ops.led_on = e1000_led_on_ich8lan;
748 mac->ops.led_off = e1000_led_off_ich8lan;
749 break;
750 case e1000_pch2lan:
751 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
752 mac->ops.rar_set = e1000_rar_set_pch2lan;
753 /* fall-through */
754 case e1000_pch_lpt:
728
729 DEBUGFUNC("e1000_init_mac_params_ich8lan");
730
731 /* Set media type function pointer */
732 hw->phy.media_type = e1000_media_type_copper;
733
734 /* Set mta register count */
735 mac->mta_reg_count = 32;

--- 52 unchanged lines hidden (view full) ---

788 mac->ops.led_on = e1000_led_on_ich8lan;
789 mac->ops.led_off = e1000_led_off_ich8lan;
790 break;
791 case e1000_pch2lan:
792 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
793 mac->ops.rar_set = e1000_rar_set_pch2lan;
794 /* fall-through */
795 case e1000_pch_lpt:
796 case e1000_pch_spt:
755 /* multicast address update for pch2 */
756 mac->ops.update_mc_addr_list =
757 e1000_update_mc_addr_list_pch2lan;
797 /* multicast address update for pch2 */
798 mac->ops.update_mc_addr_list =
799 e1000_update_mc_addr_list_pch2lan;
800 /* fall-through */
758 case e1000_pchlan:
801 case e1000_pchlan:
759#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
760 /* save PCH revision_id */
761 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
762 hw->revision_id = (u8)(pci_cfg &= 0x000F);
763#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
764 /* check management mode */
765 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
766 /* ID LED init */
767 mac->ops.id_led_init = e1000_id_led_init_pchlan;
768 /* setup LED */
769 mac->ops.setup_led = e1000_setup_led_pchlan;
770 /* cleanup LED */
771 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
772 /* turn on/off LED */
773 mac->ops.led_on = e1000_led_on_pchlan;
774 mac->ops.led_off = e1000_led_off_pchlan;
775 break;
776 default:
777 break;
778 }
779
802 /* check management mode */
803 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
804 /* ID LED init */
805 mac->ops.id_led_init = e1000_id_led_init_pchlan;
806 /* setup LED */
807 mac->ops.setup_led = e1000_setup_led_pchlan;
808 /* cleanup LED */
809 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
810 /* turn on/off LED */
811 mac->ops.led_on = e1000_led_on_pchlan;
812 mac->ops.led_off = e1000_led_off_pchlan;
813 break;
814 default:
815 break;
816 }
817
780 if (mac->type == e1000_pch_lpt) {
818 if ((mac->type == e1000_pch_lpt) ||
819 (mac->type == e1000_pch_spt)) {
781 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
782 mac->ops.rar_set = e1000_rar_set_pch_lpt;
783 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
784 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
785 }
786
787 /* Enable PCS Lock-loss workaround for ICH8 */
788 if (mac->type == e1000_ich8lan)

--- 213 unchanged lines hidden (view full) ---

1002 E1000_KMRNCTRLSTA_K1_CONFIG,
1003 reg);
1004release:
1005 hw->phy.ops.release(hw);
1006 } else {
1007 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1008 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1009
820 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
821 mac->ops.rar_set = e1000_rar_set_pch_lpt;
822 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
823 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
824 }
825
826 /* Enable PCS Lock-loss workaround for ICH8 */
827 if (mac->type == e1000_ich8lan)

--- 213 unchanged lines hidden (view full) ---

1041 E1000_KMRNCTRLSTA_K1_CONFIG,
1042 reg);
1043release:
1044 hw->phy.ops.release(hw);
1045 } else {
1046 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1047 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1048
1010 if (!link || ((status & E1000_STATUS_SPEED_100) &&
1011 (status & E1000_STATUS_FD)))
1049 if ((hw->phy.revision > 5) || !link ||
1050 ((status & E1000_STATUS_SPEED_100) &&
1051 (status & E1000_STATUS_FD)))
1012 goto update_fextnvm6;
1013
1014 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1015 if (ret_val)
1016 return ret_val;
1017
1018 /* Clear link status transmit timeout */
1019 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;

--- 196 unchanged lines hidden (view full) ---

1216 * ME firmware to start the ULP configuration. If not on an ME enabled
1217 * system, configure the ULP mode by software.
1218 */
1219s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1220{
1221 u32 mac_reg;
1222 s32 ret_val = E1000_SUCCESS;
1223 u16 phy_reg;
1052 goto update_fextnvm6;
1053
1054 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1055 if (ret_val)
1056 return ret_val;
1057
1058 /* Clear link status transmit timeout */
1059 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;

--- 196 unchanged lines hidden (view full) ---

1256 * ME firmware to start the ULP configuration. If not on an ME enabled
1257 * system, configure the ULP mode by software.
1258 */
1259s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1260{
1261 u32 mac_reg;
1262 s32 ret_val = E1000_SUCCESS;
1263 u16 phy_reg;
1264 u16 oem_reg = 0;
1224
1225 if ((hw->mac.type < e1000_pch_lpt) ||
1226 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1227 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1228 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1229 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1230 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1231 return 0;

--- 39 unchanged lines hidden (view full) ---

1271 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1272 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1273
1274 /* Force SMBus mode in MAC */
1275 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1276 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1277 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1278
1265
1266 if ((hw->mac.type < e1000_pch_lpt) ||
1267 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1268 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1269 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1270 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1271 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1272 return 0;

--- 39 unchanged lines hidden (view full) ---

1312 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1313 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1314
1315 /* Force SMBus mode in MAC */
1316 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1317 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1318 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1319
1320 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1321 * LPLU and disable Gig speed when entering ULP
1322 */
1323 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1324 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1325 &oem_reg);
1326 if (ret_val)
1327 goto release;
1328
1329 phy_reg = oem_reg;
1330 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1331
1332 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1333 phy_reg);
1334
1335 if (ret_val)
1336 goto release;
1337 }
1338
1279 /* Set Inband ULP Exit, Reset to SMBus mode and
1280 * Disable SMBus Release on PERST# in PHY
1281 */
1282 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1283 if (ret_val)
1284 goto release;
1285 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1286 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1287 if (to_sx) {
1288 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1289 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1339 /* Set Inband ULP Exit, Reset to SMBus mode and
1340 * Disable SMBus Release on PERST# in PHY
1341 */
1342 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1343 if (ret_val)
1344 goto release;
1345 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1346 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1347 if (to_sx) {
1348 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1349 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1350 else
1351 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1290
1291 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1352
1353 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1354 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1292 } else {
1293 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1355 } else {
1356 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1357 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1358 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1294 }
1295 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1296
1297 /* Set Disable SMBus Release on PERST# in MAC */
1298 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1299 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1300 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1301
1302 /* Commit ULP changes in PHY by starting auto ULP configuration */
1303 phy_reg |= I218_ULP_CONFIG1_START;
1304 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1359 }
1360 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1361
1362 /* Set Disable SMBus Release on PERST# in MAC */
1363 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1364 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1365 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1366
1367 /* Commit ULP changes in PHY by starting auto ULP configuration */
1368 phy_reg |= I218_ULP_CONFIG1_START;
1369 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1370
1371 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1372 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1373 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1374 oem_reg);
1375 if (ret_val)
1376 goto release;
1377 }
1378
1305release:
1306 hw->phy.ops.release(hw);
1307out:
1308 if (ret_val)
1309 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1310 else
1311 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1312

--- 34 unchanged lines hidden (view full) ---

1347 if (force) {
1348 /* Request ME un-configure ULP mode in the PHY */
1349 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1350 mac_reg &= ~E1000_H2ME_ULP;
1351 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1352 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1353 }
1354
1379release:
1380 hw->phy.ops.release(hw);
1381out:
1382 if (ret_val)
1383 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1384 else
1385 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1386

--- 34 unchanged lines hidden (view full) ---

1421 if (force) {
1422 /* Request ME un-configure ULP mode in the PHY */
1423 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1424 mac_reg &= ~E1000_H2ME_ULP;
1425 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1426 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1427 }
1428
1355 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1429 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1356 while (E1000_READ_REG(hw, E1000_FWSM) &
1357 E1000_FWSM_ULP_CFG_DONE) {
1430 while (E1000_READ_REG(hw, E1000_FWSM) &
1431 E1000_FWSM_ULP_CFG_DONE) {
1358 if (i++ == 10) {
1432 if (i++ == 30) {
1359 ret_val = -E1000_ERR_PHY;
1360 goto out;
1361 }
1362
1363 msec_delay(10);
1364 }
1365 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1366

--- 57 unchanged lines hidden (view full) ---

1424 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1425 if (ret_val)
1426 goto release;
1427 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1428 I218_ULP_CONFIG1_STICKY_ULP |
1429 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1430 I218_ULP_CONFIG1_WOL_HOST |
1431 I218_ULP_CONFIG1_INBAND_EXIT |
1433 ret_val = -E1000_ERR_PHY;
1434 goto out;
1435 }
1436
1437 msec_delay(10);
1438 }
1439 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1440

--- 57 unchanged lines hidden (view full) ---

1498 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1499 if (ret_val)
1500 goto release;
1501 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1502 I218_ULP_CONFIG1_STICKY_ULP |
1503 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1504 I218_ULP_CONFIG1_WOL_HOST |
1505 I218_ULP_CONFIG1_INBAND_EXIT |
1506 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1507 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1432 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1433 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1434
1435 /* Commit ULP changes by starting auto ULP configuration */
1436 phy_reg |= I218_ULP_CONFIG1_START;
1437 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1438
1439 /* Clear Disable SMBus Release on PERST# in MAC */

--- 22 unchanged lines hidden (view full) ---

1462 *
1463 * Checks to see of the link status of the hardware has changed. If a
1464 * change in link status has been detected, then we read the PHY registers
1465 * to get the current speed/duplex if link exists.
1466 **/
1467static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1468{
1469 struct e1000_mac_info *mac = &hw->mac;
1508 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1509 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1510
1511 /* Commit ULP changes by starting auto ULP configuration */
1512 phy_reg |= I218_ULP_CONFIG1_START;
1513 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1514
1515 /* Clear Disable SMBus Release on PERST# in MAC */

--- 22 unchanged lines hidden (view full) ---

1538 *
1539 * Checks to see of the link status of the hardware has changed. If a
1540 * change in link status has been detected, then we read the PHY registers
1541 * to get the current speed/duplex if link exists.
1542 **/
1543static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1544{
1545 struct e1000_mac_info *mac = &hw->mac;
1470 s32 ret_val;
1546 s32 ret_val, tipg_reg = 0;
1547 u16 emi_addr, emi_val = 0;
1471 bool link;
1472 u16 phy_reg;
1473
1474 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1475
1476 /* We only want to go out to the PHY registers to see if Auto-Neg
1477 * has completed and/or if our link status has changed. The
1478 * get_link_status flag is set upon receiving a Link Status

--- 16 unchanged lines hidden (view full) ---

1495 return ret_val;
1496 }
1497
1498 /* When connected at 10Mbps half-duplex, some parts are excessively
1499 * aggressive resulting in many collisions. To avoid this, increase
1500 * the IPG and reduce Rx latency in the PHY.
1501 */
1502 if (((hw->mac.type == e1000_pch2lan) ||
1548 bool link;
1549 u16 phy_reg;
1550
1551 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1552
1553 /* We only want to go out to the PHY registers to see if Auto-Neg
1554 * has completed and/or if our link status has changed. The
1555 * get_link_status flag is set upon receiving a Link Status

--- 16 unchanged lines hidden (view full) ---

1572 return ret_val;
1573 }
1574
1575 /* When connected at 10Mbps half-duplex, some parts are excessively
1576 * aggressive resulting in many collisions. To avoid this, increase
1577 * the IPG and reduce Rx latency in the PHY.
1578 */
1579 if (((hw->mac.type == e1000_pch2lan) ||
1503 (hw->mac.type == e1000_pch_lpt)) && link) {
1504 u32 reg;
1505 reg = E1000_READ_REG(hw, E1000_STATUS);
1506 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1507 u16 emi_addr;
1580 (hw->mac.type == e1000_pch_lpt) ||
1581 (hw->mac.type == e1000_pch_spt)) && link) {
1582 u16 speed, duplex;
1508
1583
1509 reg = E1000_READ_REG(hw, E1000_TIPG);
1510 reg &= ~E1000_TIPG_IPGT_MASK;
1511 reg |= 0xFF;
1512 E1000_WRITE_REG(hw, E1000_TIPG, reg);
1584 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1585 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1586 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1513
1587
1588 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1589 tipg_reg |= 0xFF;
1514 /* Reduce Rx latency in analog PHY */
1590 /* Reduce Rx latency in analog PHY */
1515 ret_val = hw->phy.ops.acquire(hw);
1516 if (ret_val)
1517 return ret_val;
1591 emi_val = 0;
1592 } else if (hw->mac.type == e1000_pch_spt &&
1593 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1594 tipg_reg |= 0xC;
1595 emi_val = 1;
1596 } else {
1597 /* Roll back the default values */
1598 tipg_reg |= 0x08;
1599 emi_val = 1;
1600 }
1518
1601
1519 if (hw->mac.type == e1000_pch2lan)
1520 emi_addr = I82579_RX_CONFIG;
1602 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1603
1604 ret_val = hw->phy.ops.acquire(hw);
1605 if (ret_val)
1606 return ret_val;
1607
1608 if (hw->mac.type == e1000_pch2lan)
1609 emi_addr = I82579_RX_CONFIG;
1610 else
1611 emi_addr = I217_RX_CONFIG;
1612 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1613
1614 if (hw->mac.type == e1000_pch_lpt ||
1615 hw->mac.type == e1000_pch_spt) {
1616 u16 phy_reg;
1617
1618 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1619 &phy_reg);
1620 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1621 if (speed == SPEED_100 || speed == SPEED_10)
1622 phy_reg |= 0x3E8;
1521 else
1623 else
1522 emi_addr = I217_RX_CONFIG;
1523 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0);
1624 phy_reg |= 0xFA;
1625 hw->phy.ops.write_reg_locked(hw,
1626 I217_PLL_CLOCK_GATE_REG,
1627 phy_reg);
1628 }
1629 hw->phy.ops.release(hw);
1524
1630
1525 hw->phy.ops.release(hw);
1631 if (ret_val)
1632 return ret_val;
1526
1633
1527 if (ret_val)
1528 return ret_val;
1634 if (hw->mac.type == e1000_pch_spt) {
1635 u16 data;
1636 u16 ptr_gap;
1637
1638 if (speed == SPEED_1000) {
1639 ret_val = hw->phy.ops.acquire(hw);
1640 if (ret_val)
1641 return ret_val;
1642
1643 ret_val = hw->phy.ops.read_reg_locked(hw,
1644 PHY_REG(776, 20),
1645 &data);
1646 if (ret_val) {
1647 hw->phy.ops.release(hw);
1648 return ret_val;
1649 }
1650
1651 ptr_gap = (data & (0x3FF << 2)) >> 2;
1652 if (ptr_gap < 0x18) {
1653 data &= ~(0x3FF << 2);
1654 data |= (0x18 << 2);
1655 ret_val =
1656 hw->phy.ops.write_reg_locked(hw,
1657 PHY_REG(776, 20), data);
1658 }
1659 hw->phy.ops.release(hw);
1660 if (ret_val)
1661 return ret_val;
1662 } else {
1663 ret_val = hw->phy.ops.acquire(hw);
1664 if (ret_val)
1665 return ret_val;
1666
1667 ret_val = hw->phy.ops.write_reg_locked(hw,
1668 PHY_REG(776, 20),
1669 0xC023);
1670 hw->phy.ops.release(hw);
1671 if (ret_val)
1672 return ret_val;
1673
1674 }
1529 }
1530 }
1531
1675 }
1676 }
1677
1678 /* I217 Packet Loss issue:
1679 * ensure that FEXTNVM4 Beacon Duration is set correctly
1680 * on power up.
1681 * Set the Beacon Duration for I217 to 8 usec
1682 */
1683 if ((hw->mac.type == e1000_pch_lpt) ||
1684 (hw->mac.type == e1000_pch_spt)) {
1685 u32 mac_reg;
1686
1687 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1688 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1689 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1690 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1691 }
1692
1532 /* Work-around I218 hang issue */
1533 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1534 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1535 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1536 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1537 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1538 if (ret_val)
1539 return ret_val;
1540 }
1693 /* Work-around I218 hang issue */
1694 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1695 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1696 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1697 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1698 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1699 if (ret_val)
1700 return ret_val;
1701 }
1541 if (hw->mac.type == e1000_pch_lpt) {
1702 if ((hw->mac.type == e1000_pch_lpt) ||
1703 (hw->mac.type == e1000_pch_spt)) {
1542 /* Set platform power management values for
1543 * Latency Tolerance Reporting (LTR)
1544 * Optimized Buffer Flush/Fill (OBFF)
1545 */
1546 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1547 if (ret_val)
1548 return ret_val;
1549 }
1550
1551 /* Clear link partner's EEE ability */
1552 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1553
1704 /* Set platform power management values for
1705 * Latency Tolerance Reporting (LTR)
1706 * Optimized Buffer Flush/Fill (OBFF)
1707 */
1708 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1709 if (ret_val)
1710 return ret_val;
1711 }
1712
1713 /* Clear link partner's EEE ability */
1714 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1715
1716 /* FEXTNVM6 K1-off workaround */
1717 if (hw->mac.type == e1000_pch_spt) {
1718 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1719 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1720
1721 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1722 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1723 else
1724 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1725
1726 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1727 }
1728
1554 if (!link)
1555 return E1000_SUCCESS; /* No link detected */
1556
1557 mac->get_link_status = FALSE;
1558
1559 switch (hw->mac.type) {
1560 case e1000_pch2lan:
1561 ret_val = e1000_k1_workaround_lv(hw);

--- 77 unchanged lines hidden (view full) ---

1639 case e1000_ich8lan:
1640 case e1000_ich9lan:
1641 case e1000_ich10lan:
1642 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1643 break;
1644 case e1000_pchlan:
1645 case e1000_pch2lan:
1646 case e1000_pch_lpt:
1729 if (!link)
1730 return E1000_SUCCESS; /* No link detected */
1731
1732 mac->get_link_status = FALSE;
1733
1734 switch (hw->mac.type) {
1735 case e1000_pch2lan:
1736 ret_val = e1000_k1_workaround_lv(hw);

--- 77 unchanged lines hidden (view full) ---

1814 case e1000_ich8lan:
1815 case e1000_ich9lan:
1816 case e1000_ich10lan:
1817 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1818 break;
1819 case e1000_pchlan:
1820 case e1000_pch2lan:
1821 case e1000_pch_lpt:
1822 case e1000_pch_spt:
1647 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1648 break;
1649 default:
1650 break;
1651 }
1652}
1653
1654/**

--- 366 unchanged lines hidden (view full) ---

2021 do {
2022 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2023 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2024 blocked = TRUE;
2025 msec_delay(10);
2026 continue;
2027 }
2028 blocked = FALSE;
1823 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1824 break;
1825 default:
1826 break;
1827 }
1828}
1829
1830/**

--- 366 unchanged lines hidden (view full) ---

2197 do {
2198 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2199 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2200 blocked = TRUE;
2201 msec_delay(10);
2202 continue;
2203 }
2204 blocked = FALSE;
2029 } while (blocked && (i++ < 10));
2205 } while (blocked && (i++ < 30));
2030 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2031}
2032
2033/**
2034 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2035 * @hw: pointer to the HW structure
2036 *
2037 * Assumes semaphore already acquired.

--- 64 unchanged lines hidden (view full) ---

2102 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2103 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2104 break;
2105 }
2106 /* Fall-thru */
2107 case e1000_pchlan:
2108 case e1000_pch2lan:
2109 case e1000_pch_lpt:
2206 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2207}
2208
2209/**
2210 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2211 * @hw: pointer to the HW structure
2212 *
2213 * Assumes semaphore already acquired.

--- 64 unchanged lines hidden (view full) ---

2278 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2279 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2280 break;
2281 }
2282 /* Fall-thru */
2283 case e1000_pchlan:
2284 case e1000_pch2lan:
2285 case e1000_pch_lpt:
2286 case e1000_pch_spt:
2110 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2111 break;
2112 default:
2113 return ret_val;
2114 }
2115
2116 ret_val = hw->phy.ops.acquire(hw);
2117 if (ret_val)

--- 1093 unchanged lines hidden (view full) ---

3211 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3212 **/
3213static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3214{
3215 u32 eecd;
3216 struct e1000_nvm_info *nvm = &hw->nvm;
3217 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3218 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2287 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2288 break;
2289 default:
2290 return ret_val;
2291 }
2292
2293 ret_val = hw->phy.ops.acquire(hw);
2294 if (ret_val)

--- 1093 unchanged lines hidden (view full) ---

3388 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3389 **/
3390static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3391{
3392 u32 eecd;
3393 struct e1000_nvm_info *nvm = &hw->nvm;
3394 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3395 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3396 u32 nvm_dword = 0;
3219 u8 sig_byte = 0;
3220 s32 ret_val;
3221
3222 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3223
3224 switch (hw->mac.type) {
3397 u8 sig_byte = 0;
3398 s32 ret_val;
3399
3400 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3401
3402 switch (hw->mac.type) {
3403 case e1000_pch_spt:
3404 bank1_offset = nvm->flash_bank_size;
3405 act_offset = E1000_ICH_NVM_SIG_WORD;
3406
3407 /* set bank to 0 in case flash read fails */
3408 *bank = 0;
3409
3410 /* Check bank 0 */
3411 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3412 &nvm_dword);
3413 if (ret_val)
3414 return ret_val;
3415 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3416 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3417 E1000_ICH_NVM_SIG_VALUE) {
3418 *bank = 0;
3419 return E1000_SUCCESS;
3420 }
3421
3422 /* Check bank 1 */
3423 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3424 bank1_offset,
3425 &nvm_dword);
3426 if (ret_val)
3427 return ret_val;
3428 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3429 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3430 E1000_ICH_NVM_SIG_VALUE) {
3431 *bank = 1;
3432 return E1000_SUCCESS;
3433 }
3434
3435 DEBUGOUT("ERROR: No valid NVM bank present\n");
3436 return -E1000_ERR_NVM;
3225 case e1000_ich8lan:
3226 case e1000_ich9lan:
3227 eecd = E1000_READ_REG(hw, E1000_EECD);
3228 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3229 E1000_EECD_SEC1VAL_VALID_MASK) {
3230 if (eecd & E1000_EECD_SEC1VAL)
3231 *bank = 1;
3232 else

--- 31 unchanged lines hidden (view full) ---

3264 }
3265
3266 DEBUGOUT("ERROR: No valid NVM bank present\n");
3267 return -E1000_ERR_NVM;
3268 }
3269}
3270
3271/**
3437 case e1000_ich8lan:
3438 case e1000_ich9lan:
3439 eecd = E1000_READ_REG(hw, E1000_EECD);
3440 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3441 E1000_EECD_SEC1VAL_VALID_MASK) {
3442 if (eecd & E1000_EECD_SEC1VAL)
3443 *bank = 1;
3444 else

--- 31 unchanged lines hidden (view full) ---

3476 }
3477
3478 DEBUGOUT("ERROR: No valid NVM bank present\n");
3479 return -E1000_ERR_NVM;
3480 }
3481}
3482
3483/**
3484 * e1000_read_nvm_spt - NVM access for SPT
3485 * @hw: pointer to the HW structure
3486 * @offset: The offset (in bytes) of the word(s) to read.
3487 * @words: Size of data to read in words.
3488 * @data: pointer to the word(s) to read at offset.
3489 *
3490 * Reads a word(s) from the NVM
3491 **/
3492static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3493 u16 *data)
3494{
3495 struct e1000_nvm_info *nvm = &hw->nvm;
3496 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3497 u32 act_offset;
3498 s32 ret_val = E1000_SUCCESS;
3499 u32 bank = 0;
3500 u32 dword = 0;
3501 u16 offset_to_read;
3502 u16 i;
3503
3504 DEBUGFUNC("e1000_read_nvm_spt");
3505
3506 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3507 (words == 0)) {
3508 DEBUGOUT("nvm parameter(s) out of bounds\n");
3509 ret_val = -E1000_ERR_NVM;
3510 goto out;
3511 }
3512
3513 nvm->ops.acquire(hw);
3514
3515 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3516 if (ret_val != E1000_SUCCESS) {
3517 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3518 bank = 0;
3519 }
3520
3521 act_offset = (bank) ? nvm->flash_bank_size : 0;
3522 act_offset += offset;
3523
3524 ret_val = E1000_SUCCESS;
3525
3526 for (i = 0; i < words; i += 2) {
3527 if (words - i == 1) {
3528 if (dev_spec->shadow_ram[offset+i].modified) {
3529 data[i] = dev_spec->shadow_ram[offset+i].value;
3530 } else {
3531 offset_to_read = act_offset + i -
3532 ((act_offset + i) % 2);
3533 ret_val =
3534 e1000_read_flash_dword_ich8lan(hw,
3535 offset_to_read,
3536 &dword);
3537 if (ret_val)
3538 break;
3539 if ((act_offset + i) % 2 == 0)
3540 data[i] = (u16)(dword & 0xFFFF);
3541 else
3542 data[i] = (u16)((dword >> 16) & 0xFFFF);
3543 }
3544 } else {
3545 offset_to_read = act_offset + i;
3546 if (!(dev_spec->shadow_ram[offset+i].modified) ||
3547 !(dev_spec->shadow_ram[offset+i+1].modified)) {
3548 ret_val =
3549 e1000_read_flash_dword_ich8lan(hw,
3550 offset_to_read,
3551 &dword);
3552 if (ret_val)
3553 break;
3554 }
3555 if (dev_spec->shadow_ram[offset+i].modified)
3556 data[i] = dev_spec->shadow_ram[offset+i].value;
3557 else
3558 data[i] = (u16) (dword & 0xFFFF);
3559 if (dev_spec->shadow_ram[offset+i].modified)
3560 data[i+1] =
3561 dev_spec->shadow_ram[offset+i+1].value;
3562 else
3563 data[i+1] = (u16) (dword >> 16 & 0xFFFF);
3564 }
3565 }
3566
3567 nvm->ops.release(hw);
3568
3569out:
3570 if (ret_val)
3571 DEBUGOUT1("NVM read error: %d\n", ret_val);
3572
3573 return ret_val;
3574}
3575
3576/**
3272 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3273 * @hw: pointer to the HW structure
3274 * @offset: The offset (in bytes) of the word(s) to read.
3275 * @words: Size of data to read in words
3276 * @data: Pointer to the word(s) to read at offset.
3277 *
3278 * Reads a word(s) from the NVM using the flash access registers.
3279 **/

--- 70 unchanged lines hidden (view full) ---

3350 if (!hsfsts.hsf_status.fldesvalid) {
3351 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3352 return -E1000_ERR_NVM;
3353 }
3354
3355 /* Clear FCERR and DAEL in hw status by writing 1 */
3356 hsfsts.hsf_status.flcerr = 1;
3357 hsfsts.hsf_status.dael = 1;
3577 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3578 * @hw: pointer to the HW structure
3579 * @offset: The offset (in bytes) of the word(s) to read.
3580 * @words: Size of data to read in words
3581 * @data: Pointer to the word(s) to read at offset.
3582 *
3583 * Reads a word(s) from the NVM using the flash access registers.
3584 **/

--- 70 unchanged lines hidden (view full) ---

3655 if (!hsfsts.hsf_status.fldesvalid) {
3656 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3657 return -E1000_ERR_NVM;
3658 }
3659
3660 /* Clear FCERR and DAEL in hw status by writing 1 */
3661 hsfsts.hsf_status.flcerr = 1;
3662 hsfsts.hsf_status.dael = 1;
3358 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3663 if (hw->mac.type == e1000_pch_spt)
3664 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3665 hsfsts.regval & 0xFFFF);
3666 else
3667 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3359
3360 /* Either we should have a hardware SPI cycle in progress
3361 * bit to check against, in order to start a new cycle or
3362 * FDONE bit should be changed in the hardware so that it
3363 * is 1 after hardware reset, which can then be used as an
3364 * indication whether a cycle is in progress or has been
3365 * completed.
3366 */
3367
3368 if (!hsfsts.hsf_status.flcinprog) {
3369 /* There is no cycle running at present,
3370 * so we can start a cycle.
3371 * Begin by setting Flash Cycle Done.
3372 */
3373 hsfsts.hsf_status.flcdone = 1;
3668
3669 /* Either we should have a hardware SPI cycle in progress
3670 * bit to check against, in order to start a new cycle or
3671 * FDONE bit should be changed in the hardware so that it
3672 * is 1 after hardware reset, which can then be used as an
3673 * indication whether a cycle is in progress or has been
3674 * completed.
3675 */
3676
3677 if (!hsfsts.hsf_status.flcinprog) {
3678 /* There is no cycle running at present,
3679 * so we can start a cycle.
3680 * Begin by setting Flash Cycle Done.
3681 */
3682 hsfsts.hsf_status.flcdone = 1;
3374 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3683 if (hw->mac.type == e1000_pch_spt)
3684 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3685 hsfsts.regval & 0xFFFF);
3686 else
3687 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3688 hsfsts.regval);
3375 ret_val = E1000_SUCCESS;
3376 } else {
3377 s32 i;
3378
3379 /* Otherwise poll for sometime so the current
3380 * cycle has a chance to end before giving up.
3381 */
3382 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {

--- 5 unchanged lines hidden (view full) ---

3388 }
3389 usec_delay(1);
3390 }
3391 if (ret_val == E1000_SUCCESS) {
3392 /* Successful in waiting for previous cycle to timeout,
3393 * now set the Flash Cycle Done.
3394 */
3395 hsfsts.hsf_status.flcdone = 1;
3689 ret_val = E1000_SUCCESS;
3690 } else {
3691 s32 i;
3692
3693 /* Otherwise poll for sometime so the current
3694 * cycle has a chance to end before giving up.
3695 */
3696 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {

--- 5 unchanged lines hidden (view full) ---

3702 }
3703 usec_delay(1);
3704 }
3705 if (ret_val == E1000_SUCCESS) {
3706 /* Successful in waiting for previous cycle to timeout,
3707 * now set the Flash Cycle Done.
3708 */
3709 hsfsts.hsf_status.flcdone = 1;
3396 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3397 hsfsts.regval);
3710 if (hw->mac.type == e1000_pch_spt)
3711 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3712 hsfsts.regval & 0xFFFF);
3713 else
3714 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3715 hsfsts.regval);
3398 } else {
3399 DEBUGOUT("Flash controller busy, cannot get access\n");
3400 }
3401 }
3402
3403 return ret_val;
3404}
3405

--- 8 unchanged lines hidden (view full) ---

3414{
3415 union ich8_hws_flash_ctrl hsflctl;
3416 union ich8_hws_flash_status hsfsts;
3417 u32 i = 0;
3418
3419 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3420
3421 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3716 } else {
3717 DEBUGOUT("Flash controller busy, cannot get access\n");
3718 }
3719 }
3720
3721 return ret_val;
3722}
3723

--- 8 unchanged lines hidden (view full) ---

3732{
3733 union ich8_hws_flash_ctrl hsflctl;
3734 union ich8_hws_flash_status hsfsts;
3735 u32 i = 0;
3736
3737 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3738
3739 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3422 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3740 if (hw->mac.type == e1000_pch_spt)
3741 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3742 else
3743 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3423 hsflctl.hsf_ctrl.flcgo = 1;
3424
3744 hsflctl.hsf_ctrl.flcgo = 1;
3745
3425 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3746 if (hw->mac.type == e1000_pch_spt)
3747 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3748 hsflctl.regval << 16);
3749 else
3750 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3426
3427 /* wait till FDONE bit is set to 1 */
3428 do {
3429 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3430 if (hsfsts.hsf_status.flcdone)
3431 break;
3432 usec_delay(1);
3433 } while (i++ < timeout);
3434
3435 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3436 return E1000_SUCCESS;
3437
3438 return -E1000_ERR_NVM;
3439}
3440
3441/**
3751
3752 /* wait till FDONE bit is set to 1 */
3753 do {
3754 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3755 if (hsfsts.hsf_status.flcdone)
3756 break;
3757 usec_delay(1);
3758 } while (i++ < timeout);
3759
3760 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3761 return E1000_SUCCESS;
3762
3763 return -E1000_ERR_NVM;
3764}
3765
3766/**
3767 * e1000_read_flash_dword_ich8lan - Read dword from flash
3768 * @hw: pointer to the HW structure
3769 * @offset: offset to data location
3770 * @data: pointer to the location for storing the data
3771 *
3772 * Reads the flash dword at offset into data. Offset is converted
3773 * to bytes before read.
3774 **/
3775static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3776 u32 *data)
3777{
3778 DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3779
3780 if (!data)
3781 return -E1000_ERR_NVM;
3782
3783 /* Must convert word offset into bytes. */
3784 offset <<= 1;
3785
3786 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3787}
3788
3789/**
3442 * e1000_read_flash_word_ich8lan - Read word from flash
3443 * @hw: pointer to the HW structure
3444 * @offset: offset to data location
3445 * @data: pointer to the location for storing the data
3446 *
3447 * Reads the flash word at offset into data. Offset is converted
3448 * to bytes before read.
3449 **/

--- 20 unchanged lines hidden (view full) ---

3470 * Reads a single byte from the NVM using the flash access registers.
3471 **/
3472static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3473 u8 *data)
3474{
3475 s32 ret_val;
3476 u16 word = 0;
3477
3790 * e1000_read_flash_word_ich8lan - Read word from flash
3791 * @hw: pointer to the HW structure
3792 * @offset: offset to data location
3793 * @data: pointer to the location for storing the data
3794 *
3795 * Reads the flash word at offset into data. Offset is converted
3796 * to bytes before read.
3797 **/

--- 20 unchanged lines hidden (view full) ---

3818 * Reads a single byte from the NVM using the flash access registers.
3819 **/
3820static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3821 u8 *data)
3822{
3823 s32 ret_val;
3824 u16 word = 0;
3825
3478 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3826 /* In SPT, only 32 bits access is supported,
3827 * so this function should not be called.
3828 */
3829 if (hw->mac.type == e1000_pch_spt)
3830 return -E1000_ERR_NVM;
3831 else
3832 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3479
3480 if (ret_val)
3481 return ret_val;
3482
3483 *data = (u8)word;
3484
3485 return E1000_SUCCESS;
3486}

--- 69 unchanged lines hidden (view full) ---

3556 break;
3557 }
3558 }
3559 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3560
3561 return ret_val;
3562}
3563
3833
3834 if (ret_val)
3835 return ret_val;
3836
3837 *data = (u8)word;
3838
3839 return E1000_SUCCESS;
3840}

--- 69 unchanged lines hidden (view full) ---

3910 break;
3911 }
3912 }
3913 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3914
3915 return ret_val;
3916}
3917
3918/**
3919 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3920 * @hw: pointer to the HW structure
3921 * @offset: The offset (in bytes) of the dword to read.
3922 * @data: Pointer to the dword to store the value read.
3923 *
3924 * Reads a byte or word from the NVM using the flash access registers.
3925 **/
3926static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3927 u32 *data)
3928{
3929 union ich8_hws_flash_status hsfsts;
3930 union ich8_hws_flash_ctrl hsflctl;
3931 u32 flash_linear_addr;
3932 s32 ret_val = -E1000_ERR_NVM;
3933 u8 count = 0;
3564
3934
3935 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3936
3937 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3938 hw->mac.type != e1000_pch_spt)
3939 return -E1000_ERR_NVM;
3940 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3941 hw->nvm.flash_base_addr);
3942
3943 do {
3944 usec_delay(1);
3945 /* Steps */
3946 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3947 if (ret_val != E1000_SUCCESS)
3948 break;
3949 /* In SPT, This register is in Lan memory space, not flash.
3950 * Therefore, only 32 bit access is supported
3951 */
3952 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3953
3954 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3955 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3956 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3957 /* In SPT, This register is in Lan memory space, not flash.
3958 * Therefore, only 32 bit access is supported
3959 */
3960 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3961 (u32)hsflctl.regval << 16);
3962 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3963
3964 ret_val = e1000_flash_cycle_ich8lan(hw,
3965 ICH_FLASH_READ_COMMAND_TIMEOUT);
3966
3967 /* Check if FCERR is set to 1, if set to 1, clear it
3968 * and try the whole sequence a few more times, else
3969 * read in (shift in) the Flash Data0, the order is
3970 * least significant byte first msb to lsb
3971 */
3972 if (ret_val == E1000_SUCCESS) {
3973 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3974 break;
3975 } else {
3976 /* If we've gotten here, then things are probably
3977 * completely hosed, but if the error condition is
3978 * detected, it won't hurt to give it another try...
3979 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3980 */
3981 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3982 ICH_FLASH_HSFSTS);
3983 if (hsfsts.hsf_status.flcerr) {
3984 /* Repeat for some time before giving up. */
3985 continue;
3986 } else if (!hsfsts.hsf_status.flcdone) {
3987 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3988 break;
3989 }
3990 }
3991 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3992
3993 return ret_val;
3994}
3995
3565/**
3566 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3567 * @hw: pointer to the HW structure
3568 * @offset: The offset (in bytes) of the word(s) to write.
3569 * @words: Size of data to write in words
3570 * @data: Pointer to the word(s) to write at offset.
3571 *
3572 * Writes a byte or word to the NVM using the flash access registers.

--- 21 unchanged lines hidden (view full) ---

3594 }
3595
3596 nvm->ops.release(hw);
3597
3598 return E1000_SUCCESS;
3599}
3600
3601/**
3996/**
3997 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3998 * @hw: pointer to the HW structure
3999 * @offset: The offset (in bytes) of the word(s) to write.
4000 * @words: Size of data to write in words
4001 * @data: Pointer to the word(s) to write at offset.
4002 *
4003 * Writes a byte or word to the NVM using the flash access registers.

--- 21 unchanged lines hidden (view full) ---

4025 }
4026
4027 nvm->ops.release(hw);
4028
4029 return E1000_SUCCESS;
4030}
4031
4032/**
4033 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
4034 * @hw: pointer to the HW structure
4035 *
4036 * The NVM checksum is updated by calling the generic update_nvm_checksum,
4037 * which writes the checksum to the shadow ram. The changes in the shadow
4038 * ram are then committed to the EEPROM by processing each bank at a time
4039 * checking for the modified bit and writing only the pending changes.
4040 * After a successful commit, the shadow ram is cleared and is ready for
4041 * future writes.
4042 **/
4043static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
4044{
4045 struct e1000_nvm_info *nvm = &hw->nvm;
4046 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4047 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4048 s32 ret_val;
4049 u32 dword = 0;
4050
4051 DEBUGFUNC("e1000_update_nvm_checksum_spt");
4052
4053 ret_val = e1000_update_nvm_checksum_generic(hw);
4054 if (ret_val)
4055 goto out;
4056
4057 if (nvm->type != e1000_nvm_flash_sw)
4058 goto out;
4059
4060 nvm->ops.acquire(hw);
4061
4062 /* We're writing to the opposite bank so if we're on bank 1,
4063 * write to bank 0 etc. We also need to erase the segment that
4064 * is going to be written
4065 */
4066 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4067 if (ret_val != E1000_SUCCESS) {
4068 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4069 bank = 0;
4070 }
4071
4072 if (bank == 0) {
4073 new_bank_offset = nvm->flash_bank_size;
4074 old_bank_offset = 0;
4075 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4076 if (ret_val)
4077 goto release;
4078 } else {
4079 old_bank_offset = nvm->flash_bank_size;
4080 new_bank_offset = 0;
4081 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4082 if (ret_val)
4083 goto release;
4084 }
4085 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4086 /* Determine whether to write the value stored
4087 * in the other NVM bank or a modified value stored
4088 * in the shadow RAM
4089 */
4090 ret_val = e1000_read_flash_dword_ich8lan(hw,
4091 i + old_bank_offset,
4092 &dword);
4093
4094 if (dev_spec->shadow_ram[i].modified) {
4095 dword &= 0xffff0000;
4096 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4097 }
4098 if (dev_spec->shadow_ram[i + 1].modified) {
4099 dword &= 0x0000ffff;
4100 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4101 << 16);
4102 }
4103 if (ret_val)
4104 break;
4105
4106 /* If the word is 0x13, then make sure the signature bits
4107 * (15:14) are 11b until the commit has completed.
4108 * This will allow us to write 10b which indicates the
4109 * signature is valid. We want to do this after the write
4110 * has completed so that we don't mark the segment valid
4111 * while the write is still in progress
4112 */
4113 if (i == E1000_ICH_NVM_SIG_WORD - 1)
4114 dword |= E1000_ICH_NVM_SIG_MASK << 16;
4115
4116 /* Convert offset to bytes. */
4117 act_offset = (i + new_bank_offset) << 1;
4118
4119 usec_delay(100);
4120
4121 /* Write the data to the new bank. Offset in words*/
4122 act_offset = i + new_bank_offset;
4123 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4124 dword);
4125 if (ret_val)
4126 break;
4127 }
4128
4129 /* Don't bother writing the segment valid bits if sector
4130 * programming failed.
4131 */
4132 if (ret_val) {
4133 DEBUGOUT("Flash commit failed.\n");
4134 goto release;
4135 }
4136
4137 /* Finally validate the new segment by setting bit 15:14
4138 * to 10b in word 0x13 , this can be done without an
4139 * erase as well since these bits are 11 to start with
4140 * and we need to change bit 14 to 0b
4141 */
4142 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4143
4144 /*offset in words but we read dword*/
4145 --act_offset;
4146 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4147
4148 if (ret_val)
4149 goto release;
4150
4151 dword &= 0xBFFFFFFF;
4152 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4153
4154 if (ret_val)
4155 goto release;
4156
4157 /* And invalidate the previously valid segment by setting
4158 * its signature word (0x13) high_byte to 0b. This can be
4159 * done without an erase because flash erase sets all bits
4160 * to 1's. We can write 1's to 0's without an erase
4161 */
4162 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4163
4164 /* offset in words but we read dword*/
4165 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4166 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4167
4168 if (ret_val)
4169 goto release;
4170
4171 dword &= 0x00FFFFFF;
4172 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4173
4174 if (ret_val)
4175 goto release;
4176
4177 /* Great! Everything worked, we can now clear the cached entries. */
4178 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4179 dev_spec->shadow_ram[i].modified = FALSE;
4180 dev_spec->shadow_ram[i].value = 0xFFFF;
4181 }
4182
4183release:
4184 nvm->ops.release(hw);
4185
4186 /* Reload the EEPROM, or else modifications will not appear
4187 * until after the next adapter reset.
4188 */
4189 if (!ret_val) {
4190 nvm->ops.reload(hw);
4191 msec_delay(10);
4192 }
4193
4194out:
4195 if (ret_val)
4196 DEBUGOUT1("NVM update error: %d\n", ret_val);
4197
4198 return ret_val;
4199}
4200
4201/**
3602 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3603 * @hw: pointer to the HW structure
3604 *
3605 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3606 * which writes the checksum to the shadow ram. The changes in the shadow
3607 * ram are then committed to the EEPROM by processing each bank at a time
3608 * checking for the modified bit and writing only the pending changes.
3609 * After a successful commit, the shadow ram is cleared and is ready for

--- 160 unchanged lines hidden (view full) ---

3770
3771 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
3772 * the checksum needs to be fixed. This bit is an indication that
3773 * the NVM was prepared by OEM software and did not calculate
3774 * the checksum...a likely scenario.
3775 */
3776 switch (hw->mac.type) {
3777 case e1000_pch_lpt:
4202 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4203 * @hw: pointer to the HW structure
4204 *
4205 * The NVM checksum is updated by calling the generic update_nvm_checksum,
4206 * which writes the checksum to the shadow ram. The changes in the shadow
4207 * ram are then committed to the EEPROM by processing each bank at a time
4208 * checking for the modified bit and writing only the pending changes.
4209 * After a successful commit, the shadow ram is cleared and is ready for

--- 160 unchanged lines hidden (view full) ---

4370
4371 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4372 * the checksum needs to be fixed. This bit is an indication that
4373 * the NVM was prepared by OEM software and did not calculate
4374 * the checksum...a likely scenario.
4375 */
4376 switch (hw->mac.type) {
4377 case e1000_pch_lpt:
4378 case e1000_pch_spt:
3778 word = NVM_COMPAT;
3779 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3780 break;
3781 default:
3782 word = NVM_FUTURE_INIT_WORD1;
3783 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3784 break;
3785 }

--- 31 unchanged lines hidden (view full) ---

3817 union ich8_hws_flash_ctrl hsflctl;
3818 u32 flash_linear_addr;
3819 u32 flash_data = 0;
3820 s32 ret_val;
3821 u8 count = 0;
3822
3823 DEBUGFUNC("e1000_write_ich8_data");
3824
4379 word = NVM_COMPAT;
4380 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4381 break;
4382 default:
4383 word = NVM_FUTURE_INIT_WORD1;
4384 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4385 break;
4386 }

--- 31 unchanged lines hidden (view full) ---

4418 union ich8_hws_flash_ctrl hsflctl;
4419 u32 flash_linear_addr;
4420 u32 flash_data = 0;
4421 s32 ret_val;
4422 u8 count = 0;
4423
4424 DEBUGFUNC("e1000_write_ich8_data");
4425
3825 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3826 return -E1000_ERR_NVM;
4426 if (hw->mac.type == e1000_pch_spt) {
4427 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4428 return -E1000_ERR_NVM;
4429 } else {
4430 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4431 return -E1000_ERR_NVM;
4432 }
3827
3828 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3829 hw->nvm.flash_base_addr);
3830
3831 do {
3832 usec_delay(1);
3833 /* Steps */
3834 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3835 if (ret_val != E1000_SUCCESS)
3836 break;
4433
4434 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4435 hw->nvm.flash_base_addr);
4436
4437 do {
4438 usec_delay(1);
4439 /* Steps */
4440 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4441 if (ret_val != E1000_SUCCESS)
4442 break;
3837 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4443 /* In SPT, This register is in Lan memory space, not
4444 * flash. Therefore, only 32 bit access is supported
4445 */
4446 if (hw->mac.type == e1000_pch_spt)
4447 hsflctl.regval =
4448 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4449 else
4450 hsflctl.regval =
4451 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3838
3839 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3840 hsflctl.hsf_ctrl.fldbcount = size - 1;
3841 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4452
4453 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4454 hsflctl.hsf_ctrl.fldbcount = size - 1;
4455 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3842 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
4456 /* In SPT, This register is in Lan memory space,
4457 * not flash. Therefore, only 32 bit access is
4458 * supported
4459 */
4460 if (hw->mac.type == e1000_pch_spt)
4461 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4462 hsflctl.regval << 16);
4463 else
4464 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4465 hsflctl.regval);
3843
3844 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3845
3846 if (size == 1)
3847 flash_data = (u32)data & 0x00FF;
3848 else
3849 flash_data = (u32)data;
3850

--- 21 unchanged lines hidden (view full) ---

3872 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3873 break;
3874 }
3875 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3876
3877 return ret_val;
3878}
3879
4466
4467 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4468
4469 if (size == 1)
4470 flash_data = (u32)data & 0x00FF;
4471 else
4472 flash_data = (u32)data;
4473

--- 21 unchanged lines hidden (view full) ---

4495 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4496 break;
4497 }
4498 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4499
4500 return ret_val;
4501}
4502
4503/**
4504* e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4505* @hw: pointer to the HW structure
4506* @offset: The offset (in bytes) of the dwords to read.
4507* @data: The 4 bytes to write to the NVM.
4508*
4509* Writes one/two/four bytes to the NVM using the flash access registers.
4510**/
4511static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4512 u32 data)
4513{
4514 union ich8_hws_flash_status hsfsts;
4515 union ich8_hws_flash_ctrl hsflctl;
4516 u32 flash_linear_addr;
4517 s32 ret_val;
4518 u8 count = 0;
3880
4519
4520 DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4521
4522 if (hw->mac.type == e1000_pch_spt) {
4523 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4524 return -E1000_ERR_NVM;
4525 }
4526 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4527 hw->nvm.flash_base_addr);
4528 do {
4529 usec_delay(1);
4530 /* Steps */
4531 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4532 if (ret_val != E1000_SUCCESS)
4533 break;
4534
4535 /* In SPT, This register is in Lan memory space, not
4536 * flash. Therefore, only 32 bit access is supported
4537 */
4538 if (hw->mac.type == e1000_pch_spt)
4539 hsflctl.regval = E1000_READ_FLASH_REG(hw,
4540 ICH_FLASH_HSFSTS)
4541 >> 16;
4542 else
4543 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4544 ICH_FLASH_HSFCTL);
4545
4546 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4547 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4548
4549 /* In SPT, This register is in Lan memory space,
4550 * not flash. Therefore, only 32 bit access is
4551 * supported
4552 */
4553 if (hw->mac.type == e1000_pch_spt)
4554 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4555 hsflctl.regval << 16);
4556 else
4557 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4558 hsflctl.regval);
4559
4560 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4561
4562 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4563
4564 /* check if FCERR is set to 1 , if set to 1, clear it
4565 * and try the whole sequence a few more times else done
4566 */
4567 ret_val = e1000_flash_cycle_ich8lan(hw,
4568 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4569
4570 if (ret_val == E1000_SUCCESS)
4571 break;
4572
4573 /* If we're here, then things are most likely
4574 * completely hosed, but if the error condition
4575 * is detected, it won't hurt to give it another
4576 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4577 */
4578 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4579
4580 if (hsfsts.hsf_status.flcerr)
4581 /* Repeat for some time before giving up. */
4582 continue;
4583 if (!hsfsts.hsf_status.flcdone) {
4584 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4585 break;
4586 }
4587 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4588
4589 return ret_val;
4590}
4591
3881/**
3882 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3883 * @hw: pointer to the HW structure
3884 * @offset: The index of the byte to read.
3885 * @data: The byte to write to the NVM.
3886 *
3887 * Writes a single byte to the NVM using the flash access registers.
3888 **/
3889static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3890 u8 data)
3891{
3892 u16 word = (u16)data;
3893
3894 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3895
3896 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3897}
3898
4592/**
4593 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4594 * @hw: pointer to the HW structure
4595 * @offset: The index of the byte to read.
4596 * @data: The byte to write to the NVM.
4597 *
4598 * Writes a single byte to the NVM using the flash access registers.
4599 **/
4600static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4601 u8 data)
4602{
4603 u16 word = (u16)data;
4604
4605 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
4606
4607 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4608}
4609
4610/**
4611* e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4612* @hw: pointer to the HW structure
4613* @offset: The offset of the word to write.
4614* @dword: The dword to write to the NVM.
4615*
4616* Writes a single dword to the NVM using the flash access registers.
4617* Goes through a retry algorithm before giving up.
4618**/
4619static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4620 u32 offset, u32 dword)
4621{
4622 s32 ret_val;
4623 u16 program_retries;
3899
4624
4625 DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
3900
4626
4627 /* Must convert word offset into bytes. */
4628 offset <<= 1;
4629
4630 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4631
4632 if (!ret_val)
4633 return ret_val;
4634 for (program_retries = 0; program_retries < 100; program_retries++) {
4635 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4636 usec_delay(100);
4637 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4638 if (ret_val == E1000_SUCCESS)
4639 break;
4640 }
4641 if (program_retries == 100)
4642 return -E1000_ERR_NVM;
4643
4644 return E1000_SUCCESS;
4645}
4646
3901/**
3902 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3903 * @hw: pointer to the HW structure
3904 * @offset: The offset of the byte to write.
3905 * @byte: The byte to write to the NVM.
3906 *
3907 * Writes a single byte to the NVM using the flash access registers.
3908 * Goes through a retry algorithm before giving up.

--- 92 unchanged lines hidden (view full) ---

4001 /* Steps */
4002 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4003 if (ret_val)
4004 return ret_val;
4005
4006 /* Write a value 11 (block Erase) in Flash
4007 * Cycle field in hw flash control
4008 */
4647/**
4648 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4649 * @hw: pointer to the HW structure
4650 * @offset: The offset of the byte to write.
4651 * @byte: The byte to write to the NVM.
4652 *
4653 * Writes a single byte to the NVM using the flash access registers.
4654 * Goes through a retry algorithm before giving up.

--- 92 unchanged lines hidden (view full) ---

4747 /* Steps */
4748 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4749 if (ret_val)
4750 return ret_val;
4751
4752 /* Write a value 11 (block Erase) in Flash
4753 * Cycle field in hw flash control
4754 */
4009 hsflctl.regval =
4010 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4755 if (hw->mac.type == e1000_pch_spt)
4756 hsflctl.regval =
4757 E1000_READ_FLASH_REG(hw,
4758 ICH_FLASH_HSFSTS)>>16;
4759 else
4760 hsflctl.regval =
4761 E1000_READ_FLASH_REG16(hw,
4762 ICH_FLASH_HSFCTL);
4011
4012 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4763
4764 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4013 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4014 hsflctl.regval);
4765 if (hw->mac.type == e1000_pch_spt)
4766 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4767 hsflctl.regval << 16);
4768 else
4769 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4770 hsflctl.regval);
4015
4016 /* Write the last 24 bits of an index within the
4017 * block into Flash Linear address field in Flash
4018 * Address.
4019 */
4020 flash_linear_addr += (j * sector_size);
4021 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4022 flash_linear_addr);

--- 416 unchanged lines hidden (view full) ---

4439 /* Disable IPv6 extension header parsing because some malformed
4440 * IPv6 headers can hang the Rx.
4441 */
4442 if (hw->mac.type == e1000_ich8lan)
4443 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4444 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
4445
4446 /* Enable ECC on Lynxpoint */
4771
4772 /* Write the last 24 bits of an index within the
4773 * block into Flash Linear address field in Flash
4774 * Address.
4775 */
4776 flash_linear_addr += (j * sector_size);
4777 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4778 flash_linear_addr);

--- 416 unchanged lines hidden (view full) ---

5195 /* Disable IPv6 extension header parsing because some malformed
5196 * IPv6 headers can hang the Rx.
5197 */
5198 if (hw->mac.type == e1000_ich8lan)
5199 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5200 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5201
5202 /* Enable ECC on Lynxpoint */
4447 if (hw->mac.type == e1000_pch_lpt) {
5203 if ((hw->mac.type == e1000_pch_lpt) ||
5204 (hw->mac.type == e1000_pch_spt)) {
4448 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
4449 reg |= E1000_PBECCSTS_ECC_ENABLE;
4450 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
4451
4452 reg = E1000_READ_REG(hw, E1000_CTRL);
4453 reg |= E1000_CTRL_MEHE;
4454 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4455 }

--- 415 unchanged lines hidden (view full) ---

4871 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4872
4873 if (hw->phy.type == e1000_phy_i217) {
4874 u16 phy_reg, device_id = hw->device_id;
4875
4876 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4877 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4878 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5205 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5206 reg |= E1000_PBECCSTS_ECC_ENABLE;
5207 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5208
5209 reg = E1000_READ_REG(hw, E1000_CTRL);
5210 reg |= E1000_CTRL_MEHE;
5211 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5212 }

--- 415 unchanged lines hidden (view full) ---

5628 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5629
5630 if (hw->phy.type == e1000_phy_i217) {
5631 u16 phy_reg, device_id = hw->device_id;
5632
5633 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5634 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5635 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4879 (device_id == E1000_DEV_ID_PCH_I218_V3)) {
5636 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5637 (hw->mac.type == e1000_pch_spt)) {
4880 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4881
4882 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
4883 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4884 }
4885
4886 ret_val = hw->phy.ops.acquire(hw);
4887 if (ret_val)

--- 99 unchanged lines hidden (view full) ---

4987 * @hw: pointer to the HW structure
4988 *
4989 * During Sx to S0 transitions on non-managed devices or managed devices
4990 * on which PHY resets are not blocked, if the PHY registers cannot be
4991 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4992 * the PHY.
4993 * On i217, setup Intel Rapid Start Technology.
4994 **/
5638 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5639
5640 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5641 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5642 }
5643
5644 ret_val = hw->phy.ops.acquire(hw);
5645 if (ret_val)

--- 99 unchanged lines hidden (view full) ---

5745 * @hw: pointer to the HW structure
5746 *
5747 * During Sx to S0 transitions on non-managed devices or managed devices
5748 * on which PHY resets are not blocked, if the PHY registers cannot be
5749 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5750 * the PHY.
5751 * On i217, setup Intel Rapid Start Technology.
5752 **/
4995void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5753u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4996{
4997 s32 ret_val;
4998
4999 DEBUGFUNC("e1000_resume_workarounds_pchlan");
5000 if (hw->mac.type < e1000_pch2lan)
5754{
5755 s32 ret_val;
5756
5757 DEBUGFUNC("e1000_resume_workarounds_pchlan");
5758 if (hw->mac.type < e1000_pch2lan)
5001 return;
5759 return E1000_SUCCESS;
5002
5003 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5004 if (ret_val) {
5005 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5760
5761 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5762 if (ret_val) {
5763 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5006 return;
5764 return ret_val;
5007 }
5008
5009 /* For i217 Intel Rapid Start Technology support when the system
5010 * is transitioning from Sx and no manageability engine is present
5011 * configure SMBus to restore on reset, disable proxy, and enable
5012 * the reset on MTA (Multicast table array).
5013 */
5014 if (hw->phy.type == e1000_phy_i217) {
5015 u16 phy_reg;
5016
5017 ret_val = hw->phy.ops.acquire(hw);
5018 if (ret_val) {
5019 DEBUGOUT("Failed to setup iRST\n");
5765 }
5766
5767 /* For i217 Intel Rapid Start Technology support when the system
5768 * is transitioning from Sx and no manageability engine is present
5769 * configure SMBus to restore on reset, disable proxy, and enable
5770 * the reset on MTA (Multicast table array).
5771 */
5772 if (hw->phy.type == e1000_phy_i217) {
5773 u16 phy_reg;
5774
5775 ret_val = hw->phy.ops.acquire(hw);
5776 if (ret_val) {
5777 DEBUGOUT("Failed to setup iRST\n");
5020 return;
5778 return ret_val;
5021 }
5022
5023 /* Clear Auto Enable LPI after link up */
5024 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5025 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5026 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5027
5028 if (!(E1000_READ_REG(hw, E1000_FWSM) &

--- 17 unchanged lines hidden (view full) ---

5046 if (ret_val)
5047 goto release;
5048 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5049 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5050release:
5051 if (ret_val)
5052 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5053 hw->phy.ops.release(hw);
5779 }
5780
5781 /* Clear Auto Enable LPI after link up */
5782 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5783 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5784 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5785
5786 if (!(E1000_READ_REG(hw, E1000_FWSM) &

--- 17 unchanged lines hidden (view full) ---

5804 if (ret_val)
5805 goto release;
5806 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5807 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5808release:
5809 if (ret_val)
5810 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5811 hw->phy.ops.release(hw);
5812 return ret_val;
5054 }
5813 }
5814 return E1000_SUCCESS;
5055}
5056
5057/**
5058 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5059 * @hw: pointer to the HW structure
5060 *
5061 * Return the LED back to the default configuration.
5062 **/

--- 279 unchanged lines hidden --- 		5815}
5816
5817/**
5818 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5819 * @hw: pointer to the HW structure
5820 *
5821 * Return the LED back to the default configuration.
5822 **/

--- 279 unchanged lines hidden ---