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e1000_ich8lan.c (169589) e1000_ich8lan.c (173788)
1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
33/*$FreeBSD: head/sys/dev/em/e1000_ich8lan.c 169589 2007-05-16 00:14:23Z jfv $*/
33/* $FreeBSD: head/sys/dev/em/e1000_ich8lan.c 173788 2007-11-20 21:41:22Z jfv $ */
34
35
36/* e1000_ich8lan
37 * e1000_ich9lan
38 */
39
40#include "e1000_api.h"
41#include "e1000_ich8lan.h"
42
43void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw);
44
34
35
36/* e1000_ich8lan
37 * e1000_ich9lan
38 */
39
40#include "e1000_api.h"
41#include "e1000_ich8lan.h"
42
43void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw);
44
45STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
46STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
47STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
48STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
49STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
50STATIC boolean_t e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
51STATIC s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
52STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
53STATIC s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw);
54STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
55STATIC s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw);
56STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
57 boolean_t active);
58STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
59 boolean_t active);
60STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
61 u16 words, u16 *data);
62STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
63 u16 words, u16 *data);
64STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
65STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
66STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
67 u16 *data);
68STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
69STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
70STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
71STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
72STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
73STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
74 u16 *speed, u16 *duplex);
75STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
76STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
77STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
78STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
79STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
80static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
81static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
82static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw);
83static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
84static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
85static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
86 u8 size, u16* data);
87STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
88 u32 offset, u16 *data);
89static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
90 u32 offset, u8 byte);
91STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
92 u32 offset, u8 data);
93static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
94 u8 size, u16 data);
95STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
45STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
46STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
47STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
48STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
49STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
50STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
51STATIC s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
52STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
53STATIC s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw);
54STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
55STATIC s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw);
56STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
57 bool active);
58STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
59 bool active);
60STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
61 u16 words, u16 *data);
62STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
63 u16 words, u16 *data);
64STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
65STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
66STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
67 u16 *data);
68STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
69STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
70STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
71STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
72STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
73STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
74 u16 *speed, u16 *duplex);
75STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
76STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
77STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
78STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
79STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
80static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
81static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
82static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw);
83static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
84static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
85static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
86 u8 size, u16* data);
87STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
88 u32 offset, u16 *data);
89static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
90 u32 offset, u8 byte);
91STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
92 u32 offset, u8 data);
93static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
94 u8 size, u16 data);
95STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
96STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
96
97/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
98/* Offset 04h HSFSTS */
99union ich8_hws_flash_status {
100 struct ich8_hsfsts {
101 u16 flcdone :1; /* bit 0 Flash Cycle Done */
102 u16 flcerr :1; /* bit 1 Flash Cycle Error */
103 u16 dael :1; /* bit 2 Direct Access error Log */

--- 28 unchanged lines hidden (view full) ---

132 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
133 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
134 } hsf_flregacc;
135 u16 regval;
136};
137
138struct e1000_shadow_ram {
139 u16 value;
97
98/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
99/* Offset 04h HSFSTS */
100union ich8_hws_flash_status {
101 struct ich8_hsfsts {
102 u16 flcdone :1; /* bit 0 Flash Cycle Done */
103 u16 flcerr :1; /* bit 1 Flash Cycle Error */
104 u16 dael :1; /* bit 2 Direct Access error Log */

--- 28 unchanged lines hidden (view full) ---

133 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
134 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
135 } hsf_flregacc;
136 u16 regval;
137};
138
139struct e1000_shadow_ram {
140 u16 value;
140 boolean_t modified;
141 bool modified;
141};
142
143struct e1000_dev_spec_ich8lan {
142};
143
144struct e1000_dev_spec_ich8lan {
144 boolean_t kmrn_lock_loss_workaround_enabled;
145 bool kmrn_lock_loss_workaround_enabled;
145 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
146};
147
148/**
149 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
150 * @hw: pointer to the HW structure
151 *
152 * Initialize family-specific PHY parameters and function pointers.
153 **/
146 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
147};
148
149/**
150 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
151 * @hw: pointer to the HW structure
152 *
153 * Initialize family-specific PHY parameters and function pointers.
154 **/
154STATIC s32
155e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
155STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
156{
157 struct e1000_phy_info *phy = &hw->phy;
158 struct e1000_functions *func = &hw->func;
159 s32 ret_val = E1000_SUCCESS;
160 u16 i = 0;
161
162 DEBUGFUNC("e1000_init_phy_params_ich8lan");
163

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172 func->get_cfg_done = e1000_get_cfg_done_ich8lan;
173 func->get_phy_info = e1000_get_phy_info_ich8lan;
174 func->read_phy_reg = e1000_read_phy_reg_igp;
175 func->release_phy = e1000_release_swflag_ich8lan;
176 func->reset_phy = e1000_phy_hw_reset_ich8lan;
177 func->set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
178 func->set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
179 func->write_phy_reg = e1000_write_phy_reg_igp;
156{
157 struct e1000_phy_info *phy = &hw->phy;
158 struct e1000_functions *func = &hw->func;
159 s32 ret_val = E1000_SUCCESS;
160 u16 i = 0;
161
162 DEBUGFUNC("e1000_init_phy_params_ich8lan");
163

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172 func->get_cfg_done = e1000_get_cfg_done_ich8lan;
173 func->get_phy_info = e1000_get_phy_info_ich8lan;
174 func->read_phy_reg = e1000_read_phy_reg_igp;
175 func->release_phy = e1000_release_swflag_ich8lan;
176 func->reset_phy = e1000_phy_hw_reset_ich8lan;
177 func->set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
178 func->set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
179 func->write_phy_reg = e1000_write_phy_reg_igp;
180 func->power_up_phy = e1000_power_up_phy_copper;
181 func->power_down_phy = e1000_power_down_phy_copper_ich8lan;
180
181
182 phy->id = 0;
183 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
184 (i++ < 100)) {
185 msec_delay(1);
186 ret_val = e1000_get_phy_id(hw);
187 if (ret_val)

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211
212/**
213 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
214 * @hw: pointer to the HW structure
215 *
216 * Initialize family-specific NVM parameters and function
217 * pointers.
218 **/
182
183
184 phy->id = 0;
185 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
186 (i++ < 100)) {
187 msec_delay(1);
188 ret_val = e1000_get_phy_id(hw);
189 if (ret_val)

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213
214/**
215 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
216 * @hw: pointer to the HW structure
217 *
218 * Initialize family-specific NVM parameters and function
219 * pointers.
220 **/
219STATIC s32
220e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
221STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
221{
222 struct e1000_nvm_info *nvm = &hw->nvm;
223 struct e1000_functions *func = &hw->func;
224 struct e1000_dev_spec_ich8lan *dev_spec;
225 u32 gfpreg, sector_base_addr, sector_end_addr;
222{
223 struct e1000_nvm_info *nvm = &hw->nvm;
224 struct e1000_functions *func = &hw->func;
225 struct e1000_dev_spec_ich8lan *dev_spec;
226 u32 gfpreg, sector_base_addr, sector_end_addr;
226 s32 ret_val = E1000_SUCCESS;
227 s32 ret_val = E1000_SUCCESS;
227 u16 i;
228
229 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
230
228 u16 i;
229
230 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
231
231 /* Can't read flash registers if the register set isn't mapped.
232 */
232 /* Can't read flash registers if the register set isn't mapped. */
233 if (!hw->flash_address) {
234 DEBUGOUT("ERROR: Flash registers not mapped\n");
235 ret_val = -E1000_ERR_CONFIG;
236 goto out;
237 }
238
239 nvm->type = e1000_nvm_flash_sw;
240
241 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
242
233 if (!hw->flash_address) {
234 DEBUGOUT("ERROR: Flash registers not mapped\n");
235 ret_val = -E1000_ERR_CONFIG;
236 goto out;
237 }
238
239 nvm->type = e1000_nvm_flash_sw;
240
241 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
242
243 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
243 /*
244 * sector_X_addr is a "sector"-aligned address (4096 bytes)
244 * Add 1 to sector_end_addr since this sector is included in
245 * Add 1 to sector_end_addr since this sector is included in
245 * the overall size. */
246 * the overall size.
247 */
246 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
247 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
248
249 /* flash_base_addr is byte-aligned */
250 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
251
248 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
249 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
250
251 /* flash_base_addr is byte-aligned */
252 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
253
252 /* find total size of the NVM, then cut in half since the total
253 * size represents two separate NVM banks. */
254 /*
255 * find total size of the NVM, then cut in half since the total
256 * size represents two separate NVM banks.
257 */
254 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
255 << FLASH_SECTOR_ADDR_SHIFT;
256 nvm->flash_bank_size /= 2;
257 /* Adjust to word count */
258 nvm->flash_bank_size /= sizeof(u16);
259
260 nvm->word_size = E1000_SHADOW_RAM_WORDS;
261
262 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
263
258 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
259 << FLASH_SECTOR_ADDR_SHIFT;
260 nvm->flash_bank_size /= 2;
261 /* Adjust to word count */
262 nvm->flash_bank_size /= sizeof(u16);
263
264 nvm->word_size = E1000_SHADOW_RAM_WORDS;
265
266 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
267
264 if (dev_spec == NULL) {
268 if (!dev_spec) {
265 DEBUGOUT("dev_spec pointer is set to NULL.\n");
266 ret_val = -E1000_ERR_CONFIG;
267 goto out;
268 }
269
270 /* Clear shadow ram */
271 for (i = 0; i < nvm->word_size; i++) {
272 dev_spec->shadow_ram[i].modified = FALSE;

--- 15 unchanged lines hidden (view full) ---

288
289/**
290 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
291 * @hw: pointer to the HW structure
292 *
293 * Initialize family-specific MAC parameters and function
294 * pointers.
295 **/
269 DEBUGOUT("dev_spec pointer is set to NULL.\n");
270 ret_val = -E1000_ERR_CONFIG;
271 goto out;
272 }
273
274 /* Clear shadow ram */
275 for (i = 0; i < nvm->word_size; i++) {
276 dev_spec->shadow_ram[i].modified = FALSE;

--- 15 unchanged lines hidden (view full) ---

292
293/**
294 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
295 * @hw: pointer to the HW structure
296 *
297 * Initialize family-specific MAC parameters and function
298 * pointers.
299 **/
296STATIC s32
297e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
300STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
298{
299 struct e1000_mac_info *mac = &hw->mac;
300 struct e1000_functions *func = &hw->func;
301 s32 ret_val = E1000_SUCCESS;
302
303 DEBUGFUNC("e1000_init_mac_params_ich8lan");
304
305 /* Set media type function pointer */
301{
302 struct e1000_mac_info *mac = &hw->mac;
303 struct e1000_functions *func = &hw->func;
304 s32 ret_val = E1000_SUCCESS;
305
306 DEBUGFUNC("e1000_init_mac_params_ich8lan");
307
308 /* Set media type function pointer */
306 hw->media_type = e1000_media_type_copper;
309 hw->phy.media_type = e1000_media_type_copper;
307
308 /* Set mta register count */
309 mac->mta_reg_count = 32;
310 /* Set rar entry count */
311 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
312 if (mac->type == e1000_ich8lan)
313 mac->rar_entry_count--;
314 /* Set if part includes ASF firmware */

--- 15 unchanged lines hidden (view full) ---

330 func->setup_physical_interface = e1000_setup_copper_link_ich8lan;
331 /* check for link */
332 func->check_for_link = e1000_check_for_copper_link_generic;
333 /* check management mode */
334 func->check_mng_mode = e1000_check_mng_mode_ich8lan;
335 /* link info */
336 func->get_link_up_info = e1000_get_link_up_info_ich8lan;
337 /* multicast address update */
310
311 /* Set mta register count */
312 mac->mta_reg_count = 32;
313 /* Set rar entry count */
314 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
315 if (mac->type == e1000_ich8lan)
316 mac->rar_entry_count--;
317 /* Set if part includes ASF firmware */

--- 15 unchanged lines hidden (view full) ---

333 func->setup_physical_interface = e1000_setup_copper_link_ich8lan;
334 /* check for link */
335 func->check_for_link = e1000_check_for_copper_link_generic;
336 /* check management mode */
337 func->check_mng_mode = e1000_check_mng_mode_ich8lan;
338 /* link info */
339 func->get_link_up_info = e1000_get_link_up_info_ich8lan;
340 /* multicast address update */
338 func->mc_addr_list_update = e1000_mc_addr_list_update_generic;
341 func->update_mc_addr_list = e1000_update_mc_addr_list_generic;
339 /* setting MTA */
340 func->mta_set = e1000_mta_set_generic;
341 /* blink LED */
342 func->blink_led = e1000_blink_led_generic;
343 /* setup LED */
344 func->setup_led = e1000_setup_led_generic;
345 /* cleanup LED */
346 func->cleanup_led = e1000_cleanup_led_ich8lan;

--- 22 unchanged lines hidden (view full) ---

369}
370
371/**
372 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
373 * @hw: pointer to the HW structure
374 *
375 * Initialize family-specific function pointers for PHY, MAC, and NVM.
376 **/
342 /* setting MTA */
343 func->mta_set = e1000_mta_set_generic;
344 /* blink LED */
345 func->blink_led = e1000_blink_led_generic;
346 /* setup LED */
347 func->setup_led = e1000_setup_led_generic;
348 /* cleanup LED */
349 func->cleanup_led = e1000_cleanup_led_ich8lan;

--- 22 unchanged lines hidden (view full) ---

372}
373
374/**
375 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
376 * @hw: pointer to the HW structure
377 *
378 * Initialize family-specific function pointers for PHY, MAC, and NVM.
379 **/
377void
378e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
380void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
379{
380 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
381
382 hw->func.init_mac_params = e1000_init_mac_params_ich8lan;
383 hw->func.init_nvm_params = e1000_init_nvm_params_ich8lan;
384 hw->func.init_phy_params = e1000_init_phy_params_ich8lan;
385}
386
387/**
388 * e1000_acquire_swflag_ich8lan - Acquire software control flag
389 * @hw: pointer to the HW structure
390 *
391 * Acquires the software control flag for performing NVM and PHY
392 * operations. This is a function pointer entry point only called by
393 * read/write routines for the PHY and NVM parts.
394 **/
381{
382 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
383
384 hw->func.init_mac_params = e1000_init_mac_params_ich8lan;
385 hw->func.init_nvm_params = e1000_init_nvm_params_ich8lan;
386 hw->func.init_phy_params = e1000_init_phy_params_ich8lan;
387}
388
389/**
390 * e1000_acquire_swflag_ich8lan - Acquire software control flag
391 * @hw: pointer to the HW structure
392 *
393 * Acquires the software control flag for performing NVM and PHY
394 * operations. This is a function pointer entry point only called by
395 * read/write routines for the PHY and NVM parts.
396 **/
395STATIC s32
396e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
397STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
397{
398 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
399 s32 ret_val = E1000_SUCCESS;
400
401 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
402
403 while (timeout) {
404 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);

--- 4 unchanged lines hidden (view full) ---

409 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
410 break;
411 msec_delay_irq(1);
412 timeout--;
413 }
414
415 if (!timeout) {
416 DEBUGOUT("FW or HW has locked the resource for too long.\n");
398{
399 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
400 s32 ret_val = E1000_SUCCESS;
401
402 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
403
404 while (timeout) {
405 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);

--- 4 unchanged lines hidden (view full) ---

410 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
411 break;
412 msec_delay_irq(1);
413 timeout--;
414 }
415
416 if (!timeout) {
417 DEBUGOUT("FW or HW has locked the resource for too long.\n");
418 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
419 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
417 ret_val = -E1000_ERR_CONFIG;
418 goto out;
419 }
420
421out:
422 return ret_val;
423}
424
425/**
426 * e1000_release_swflag_ich8lan - Release software control flag
427 * @hw: pointer to the HW structure
428 *
429 * Releases the software control flag for performing NVM and PHY operations.
430 * This is a function pointer entry point only called by read/write
431 * routines for the PHY and NVM parts.
432 **/
420 ret_val = -E1000_ERR_CONFIG;
421 goto out;
422 }
423
424out:
425 return ret_val;
426}
427
428/**
429 * e1000_release_swflag_ich8lan - Release software control flag
430 * @hw: pointer to the HW structure
431 *
432 * Releases the software control flag for performing NVM and PHY operations.
433 * This is a function pointer entry point only called by read/write
434 * routines for the PHY and NVM parts.
435 **/
433STATIC void
434e1000_release_swflag_ich8lan(struct e1000_hw *hw)
436STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
435{
436 u32 extcnf_ctrl;
437
438 DEBUGFUNC("e1000_release_swflag_ich8lan");
439
440 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
441 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
442 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);

--- 4 unchanged lines hidden (view full) ---

447/**
448 * e1000_check_mng_mode_ich8lan - Checks management mode
449 * @hw: pointer to the HW structure
450 *
451 * This checks if the adapter has manageability enabled.
452 * This is a function pointer entry point only called by read/write
453 * routines for the PHY and NVM parts.
454 **/
437{
438 u32 extcnf_ctrl;
439
440 DEBUGFUNC("e1000_release_swflag_ich8lan");
441
442 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
443 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
444 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);

--- 4 unchanged lines hidden (view full) ---

449/**
450 * e1000_check_mng_mode_ich8lan - Checks management mode
451 * @hw: pointer to the HW structure
452 *
453 * This checks if the adapter has manageability enabled.
454 * This is a function pointer entry point only called by read/write
455 * routines for the PHY and NVM parts.
456 **/
455STATIC boolean_t
456e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
457STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
457{
458 u32 fwsm;
459
460 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
461
462 fwsm = E1000_READ_REG(hw, E1000_FWSM);
463
464 return ((fwsm & E1000_FWSM_MODE_MASK) ==
465 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
466}
467
468/**
469 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
470 * @hw: pointer to the HW structure
471 *
472 * Checks if firmware is blocking the reset of the PHY.
473 * This is a function pointer entry point only called by
474 * reset routines.
475 **/
458{
459 u32 fwsm;
460
461 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
462
463 fwsm = E1000_READ_REG(hw, E1000_FWSM);
464
465 return ((fwsm & E1000_FWSM_MODE_MASK) ==
466 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
467}
468
469/**
470 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
471 * @hw: pointer to the HW structure
472 *
473 * Checks if firmware is blocking the reset of the PHY.
474 * This is a function pointer entry point only called by
475 * reset routines.
476 **/
476STATIC s32
477e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
477STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
478{
479 u32 fwsm;
480
481 DEBUGFUNC("e1000_check_reset_block_ich8lan");
482
483 fwsm = E1000_READ_REG(hw, E1000_FWSM);
484
485 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
486 : E1000_BLK_PHY_RESET;
487}
488
489/**
490 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
491 * @hw: pointer to the HW structure
492 *
493 * Forces the speed and duplex settings of the PHY.
494 * This is a function pointer entry point only called by
495 * PHY setup routines.
496 **/
478{
479 u32 fwsm;
480
481 DEBUGFUNC("e1000_check_reset_block_ich8lan");
482
483 fwsm = E1000_READ_REG(hw, E1000_FWSM);
484
485 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
486 : E1000_BLK_PHY_RESET;
487}
488
489/**
490 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
491 * @hw: pointer to the HW structure
492 *
493 * Forces the speed and duplex settings of the PHY.
494 * This is a function pointer entry point only called by
495 * PHY setup routines.
496 **/
497STATIC s32
498e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
497STATIC s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
499{
500 struct e1000_phy_info *phy = &hw->phy;
501 s32 ret_val;
502 u16 data;
498{
499 struct e1000_phy_info *phy = &hw->phy;
500 s32 ret_val;
501 u16 data;
503 boolean_t link;
502 bool link;
504
505 DEBUGFUNC("e1000_phy_force_speed_duplex_ich8lan");
506
507 if (phy->type != e1000_phy_ife) {
508 ret_val = e1000_phy_force_speed_duplex_igp(hw);
509 goto out;
510 }
511

--- 18 unchanged lines hidden (view full) ---

530 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, data);
531 if (ret_val)
532 goto out;
533
534 DEBUGOUT1("IFE PMC: %X\n", data);
535
536 usec_delay(1);
537
503
504 DEBUGFUNC("e1000_phy_force_speed_duplex_ich8lan");
505
506 if (phy->type != e1000_phy_ife) {
507 ret_val = e1000_phy_force_speed_duplex_igp(hw);
508 goto out;
509 }
510

--- 18 unchanged lines hidden (view full) ---

529 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, data);
530 if (ret_val)
531 goto out;
532
533 DEBUGOUT1("IFE PMC: %X\n", data);
534
535 usec_delay(1);
536
538 if (phy->wait_for_link) {
537 if (phy->autoneg_wait_to_complete) {
539 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
540
541 ret_val = e1000_phy_has_link_generic(hw,
542 PHY_FORCE_LIMIT,
543 100000,
544 &link);
545 if (ret_val)
546 goto out;

--- 18 unchanged lines hidden (view full) ---

565/**
566 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
567 * @hw: pointer to the HW structure
568 *
569 * Resets the PHY
570 * This is a function pointer entry point called by drivers
571 * or other shared routines.
572 **/
538 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
539
540 ret_val = e1000_phy_has_link_generic(hw,
541 PHY_FORCE_LIMIT,
542 100000,
543 &link);
544 if (ret_val)
545 goto out;

--- 18 unchanged lines hidden (view full) ---

564/**
565 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
566 * @hw: pointer to the HW structure
567 *
568 * Resets the PHY
569 * This is a function pointer entry point called by drivers
570 * or other shared routines.
571 **/
573STATIC s32
574e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
572STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
575{
576 struct e1000_phy_info *phy = &hw->phy;
577 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
578 s32 ret_val;
579 u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
580 u16 word_addr, reg_data, reg_addr, phy_page = 0;
581
582 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
583
584 ret_val = e1000_phy_hw_reset_generic(hw);
585 if (ret_val)
586 goto out;
587
573{
574 struct e1000_phy_info *phy = &hw->phy;
575 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
576 s32 ret_val;
577 u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
578 u16 word_addr, reg_data, reg_addr, phy_page = 0;
579
580 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
581
582 ret_val = e1000_phy_hw_reset_generic(hw);
583 if (ret_val)
584 goto out;
585
588 /* Initialize the PHY from the NVM on ICH platforms. This
586 /*
587 * Initialize the PHY from the NVM on ICH platforms. This
589 * is needed due to an issue where the NVM configuration is
590 * not properly autoloaded after power transitions.
591 * Therefore, after each PHY reset, we will load the
592 * configuration data out of the NVM manually.
593 */
594 if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
595 /* Check if SW needs configure the PHY */
596 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) ||

--- 8 unchanged lines hidden (view full) ---

605
606 /* Wait for basic configuration completes before proceeding*/
607 do {
608 data = E1000_READ_REG(hw, E1000_STATUS);
609 data &= E1000_STATUS_LAN_INIT_DONE;
610 usec_delay(100);
611 } while ((!data) && --loop);
612
588 * is needed due to an issue where the NVM configuration is
589 * not properly autoloaded after power transitions.
590 * Therefore, after each PHY reset, we will load the
591 * configuration data out of the NVM manually.
592 */
593 if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
594 /* Check if SW needs configure the PHY */
595 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) ||

--- 8 unchanged lines hidden (view full) ---

604
605 /* Wait for basic configuration completes before proceeding*/
606 do {
607 data = E1000_READ_REG(hw, E1000_STATUS);
608 data &= E1000_STATUS_LAN_INIT_DONE;
609 usec_delay(100);
610 } while ((!data) && --loop);
611
613 /* If basic configuration is incomplete before the above loop
612 /*
613 * If basic configuration is incomplete before the above loop
614 * count reaches 0, loading the configuration from NVM will
615 * leave the PHY in a bad state possibly resulting in no link.
616 */
617 if (loop == 0) {
618 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
619 }
620
621 /* Clear the Init Done bit for the next init event */
622 data = E1000_READ_REG(hw, E1000_STATUS);
623 data &= ~E1000_STATUS_LAN_INIT_DONE;
624 E1000_WRITE_REG(hw, E1000_STATUS, data);
625
614 * count reaches 0, loading the configuration from NVM will
615 * leave the PHY in a bad state possibly resulting in no link.
616 */
617 if (loop == 0) {
618 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
619 }
620
621 /* Clear the Init Done bit for the next init event */
622 data = E1000_READ_REG(hw, E1000_STATUS);
623 data &= ~E1000_STATUS_LAN_INIT_DONE;
624 E1000_WRITE_REG(hw, E1000_STATUS, data);
625
626 /* Make sure HW does not configure LCD from PHY
627 * extended configuration before SW configuration */
626 /*
627 * Make sure HW does not configure LCD from PHY
628 * extended configuration before SW configuration
629 */
628 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
629 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
630 goto out;
631
632 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
633 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
634 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
635 if (!cnf_size)
636 goto out;
637
638 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
639 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
640
630 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
631 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
632 goto out;
633
634 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
635 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
636 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
637 if (!cnf_size)
638 goto out;
639
640 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
641 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
642
641 /* Configure LCD from extended configuration
642 * region. */
643 /*
644 * Configure LCD from extended configuration
645 * region.
646 */
643
644 /* cnf_base_addr is in DWORD */
645 word_addr = (u16)(cnf_base_addr << 1);
646
647 for (i = 0; i < cnf_size; i++) {
648 ret_val = e1000_read_nvm(hw,
649 (word_addr + i * 2),
650 1,

--- 31 unchanged lines hidden (view full) ---

682/**
683 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
684 * @hw: pointer to the HW structure
685 *
686 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
687 * This is a function pointer entry point called by drivers
688 * or other shared routines.
689 **/
647
648 /* cnf_base_addr is in DWORD */
649 word_addr = (u16)(cnf_base_addr << 1);
650
651 for (i = 0; i < cnf_size; i++) {
652 ret_val = e1000_read_nvm(hw,
653 (word_addr + i * 2),
654 1,

--- 31 unchanged lines hidden (view full) ---

686/**
687 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
688 * @hw: pointer to the HW structure
689 *
690 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
691 * This is a function pointer entry point called by drivers
692 * or other shared routines.
693 **/
690STATIC s32
691e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
694STATIC s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
692{
693 s32 ret_val = -E1000_ERR_PHY_TYPE;
694
695 DEBUGFUNC("e1000_get_phy_info_ich8lan");
696
697 switch (hw->phy.type) {
698 case e1000_phy_ife:
699 ret_val = e1000_get_phy_info_ife_ich8lan(hw);

--- 11 unchanged lines hidden (view full) ---

711/**
712 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
713 * @hw: pointer to the HW structure
714 *
715 * Populates "phy" structure with various feature states.
716 * This function is only called by other family-specific
717 * routines.
718 **/
695{
696 s32 ret_val = -E1000_ERR_PHY_TYPE;
697
698 DEBUGFUNC("e1000_get_phy_info_ich8lan");
699
700 switch (hw->phy.type) {
701 case e1000_phy_ife:
702 ret_val = e1000_get_phy_info_ife_ich8lan(hw);

--- 11 unchanged lines hidden (view full) ---

714/**
715 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
716 * @hw: pointer to the HW structure
717 *
718 * Populates "phy" structure with various feature states.
719 * This function is only called by other family-specific
720 * routines.
721 **/
719static s32
720e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
722static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
721{
722 struct e1000_phy_info *phy = &hw->phy;
723 s32 ret_val;
724 u16 data;
723{
724 struct e1000_phy_info *phy = &hw->phy;
725 s32 ret_val;
726 u16 data;
725 boolean_t link;
727 bool link;
726
727 DEBUGFUNC("e1000_get_phy_info_ife_ich8lan");
728
729 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
730 if (ret_val)
731 goto out;
732
733 if (!link) {

--- 37 unchanged lines hidden (view full) ---

771/**
772 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
773 * @hw: pointer to the HW structure
774 *
775 * Polarity is determined on the polarity reveral feature being enabled.
776 * This function is only called by other family-specific
777 * routines.
778 **/
728
729 DEBUGFUNC("e1000_get_phy_info_ife_ich8lan");
730
731 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
732 if (ret_val)
733 goto out;
734
735 if (!link) {

--- 37 unchanged lines hidden (view full) ---

773/**
774 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
775 * @hw: pointer to the HW structure
776 *
777 * Polarity is determined on the polarity reveral feature being enabled.
778 * This function is only called by other family-specific
779 * routines.
780 **/
779STATIC s32
780e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
781STATIC s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
781{
782 struct e1000_phy_info *phy = &hw->phy;
783 s32 ret_val;
784 u16 phy_data, offset, mask;
785
786 DEBUGFUNC("e1000_check_polarity_ife_ich8lan");
787
782{
783 struct e1000_phy_info *phy = &hw->phy;
784 s32 ret_val;
785 u16 phy_data, offset, mask;
786
787 DEBUGFUNC("e1000_check_polarity_ife_ich8lan");
788
788 /* Polarity is determined based on the reversal feature
789 /*
790 * Polarity is determined based on the reversal feature
789 * being enabled.
790 */
791 if (phy->polarity_correction) {
792 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
793 mask = IFE_PESC_POLARITY_REVERSED;
794 } else {
795 offset = IFE_PHY_SPECIAL_CONTROL;
796 mask = IFE_PSC_FORCE_POLARITY;

--- 17 unchanged lines hidden (view full) ---

814 * Sets the LPLU D0 state according to the active flag. When
815 * activating LPLU this function also disables smart speed
816 * and vice versa. LPLU will not be activated unless the
817 * device autonegotiation advertisement meets standards of
818 * either 10 or 10/100 or 10/100/1000 at all duplexes.
819 * This is a function pointer entry point only called by
820 * PHY setup routines.
821 **/
791 * being enabled.
792 */
793 if (phy->polarity_correction) {
794 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
795 mask = IFE_PESC_POLARITY_REVERSED;
796 } else {
797 offset = IFE_PHY_SPECIAL_CONTROL;
798 mask = IFE_PSC_FORCE_POLARITY;

--- 17 unchanged lines hidden (view full) ---

816 * Sets the LPLU D0 state according to the active flag. When
817 * activating LPLU this function also disables smart speed
818 * and vice versa. LPLU will not be activated unless the
819 * device autonegotiation advertisement meets standards of
820 * either 10 or 10/100 or 10/100/1000 at all duplexes.
821 * This is a function pointer entry point only called by
822 * PHY setup routines.
823 **/
822STATIC s32
823e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, boolean_t active)
824STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
825 bool active)
824{
825 struct e1000_phy_info *phy = &hw->phy;
826 u32 phy_ctrl;
827 s32 ret_val = E1000_SUCCESS;
828 u16 data;
829
830 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
831
826{
827 struct e1000_phy_info *phy = &hw->phy;
828 u32 phy_ctrl;
829 s32 ret_val = E1000_SUCCESS;
830 u16 data;
831
832 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
833
832 if (phy->type != e1000_phy_igp_3)
834 if (phy->type == e1000_phy_ife)
833 goto out;
834
835 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
836
837 if (active) {
838 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
839 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
840
835 goto out;
836
837 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
838
839 if (active) {
840 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
841 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
842
841 /* Call gig speed drop workaround on LPLU before accessing
842 * any PHY registers */
843 /*
844 * Call gig speed drop workaround on LPLU before accessing
845 * any PHY registers
846 */
843 if ((hw->mac.type == e1000_ich8lan) &&
844 (hw->phy.type == e1000_phy_igp_3))
845 e1000_gig_downshift_workaround_ich8lan(hw);
846
847 /* When LPLU is enabled, we should disable SmartSpeed */
848 ret_val = e1000_read_phy_reg(hw,
849 IGP01E1000_PHY_PORT_CONFIG,
850 &data);
851 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
852 ret_val = e1000_write_phy_reg(hw,
853 IGP01E1000_PHY_PORT_CONFIG,
854 data);
855 if (ret_val)
856 goto out;
857 } else {
858 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
859 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
860
847 if ((hw->mac.type == e1000_ich8lan) &&
848 (hw->phy.type == e1000_phy_igp_3))
849 e1000_gig_downshift_workaround_ich8lan(hw);
850
851 /* When LPLU is enabled, we should disable SmartSpeed */
852 ret_val = e1000_read_phy_reg(hw,
853 IGP01E1000_PHY_PORT_CONFIG,
854 &data);
855 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
856 ret_val = e1000_write_phy_reg(hw,
857 IGP01E1000_PHY_PORT_CONFIG,
858 data);
859 if (ret_val)
860 goto out;
861 } else {
862 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
863 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
864
861 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
865 /*
866 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
862 * during Dx states where the power conservation is most
863 * important. During driver activity we should enable
867 * during Dx states where the power conservation is most
868 * important. During driver activity we should enable
864 * SmartSpeed, so performance is maintained. */
869 * SmartSpeed, so performance is maintained.
870 */
865 if (phy->smart_speed == e1000_smart_speed_on) {
866 ret_val = e1000_read_phy_reg(hw,
867 IGP01E1000_PHY_PORT_CONFIG,
868 &data);
869 if (ret_val)
870 goto out;
871
872 data |= IGP01E1000_PSCFR_SMART_SPEED;

--- 30 unchanged lines hidden (view full) ---

903 * Sets the LPLU D3 state according to the active flag. When
904 * activating LPLU this function also disables smart speed
905 * and vice versa. LPLU will not be activated unless the
906 * device autonegotiation advertisement meets standards of
907 * either 10 or 10/100 or 10/100/1000 at all duplexes.
908 * This is a function pointer entry point only called by
909 * PHY setup routines.
910 **/
871 if (phy->smart_speed == e1000_smart_speed_on) {
872 ret_val = e1000_read_phy_reg(hw,
873 IGP01E1000_PHY_PORT_CONFIG,
874 &data);
875 if (ret_val)
876 goto out;
877
878 data |= IGP01E1000_PSCFR_SMART_SPEED;

--- 30 unchanged lines hidden (view full) ---

909 * Sets the LPLU D3 state according to the active flag. When
910 * activating LPLU this function also disables smart speed
911 * and vice versa. LPLU will not be activated unless the
912 * device autonegotiation advertisement meets standards of
913 * either 10 or 10/100 or 10/100/1000 at all duplexes.
914 * This is a function pointer entry point only called by
915 * PHY setup routines.
916 **/
911STATIC s32
912e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, boolean_t active)
917STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
918 bool active)
913{
914 struct e1000_phy_info *phy = &hw->phy;
915 u32 phy_ctrl;
916 s32 ret_val = E1000_SUCCESS;
917 u16 data;
918
919 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
920
921 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
922
923 if (!active) {
924 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
925 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
919{
920 struct e1000_phy_info *phy = &hw->phy;
921 u32 phy_ctrl;
922 s32 ret_val = E1000_SUCCESS;
923 u16 data;
924
925 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
926
927 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
928
929 if (!active) {
930 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
931 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
926 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
932 /*
933 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
927 * during Dx states where the power conservation is most
928 * important. During driver activity we should enable
934 * during Dx states where the power conservation is most
935 * important. During driver activity we should enable
929 * SmartSpeed, so performance is maintained. */
936 * SmartSpeed, so performance is maintained.
937 */
930 if (phy->smart_speed == e1000_smart_speed_on) {
931 ret_val = e1000_read_phy_reg(hw,
932 IGP01E1000_PHY_PORT_CONFIG,
933 &data);
934 if (ret_val)
935 goto out;
936
937 data |= IGP01E1000_PSCFR_SMART_SPEED;

--- 17 unchanged lines hidden (view full) ---

955 goto out;
956 }
957 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
958 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
959 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
960 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
961 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
962
938 if (phy->smart_speed == e1000_smart_speed_on) {
939 ret_val = e1000_read_phy_reg(hw,
940 IGP01E1000_PHY_PORT_CONFIG,
941 &data);
942 if (ret_val)
943 goto out;
944
945 data |= IGP01E1000_PSCFR_SMART_SPEED;

--- 17 unchanged lines hidden (view full) ---

963 goto out;
964 }
965 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
966 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
967 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
968 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
969 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
970
963 /* Call gig speed drop workaround on LPLU before accessing
964 * any PHY registers */
971 /*
972 * Call gig speed drop workaround on LPLU before accessing
973 * any PHY registers
974 */
965 if ((hw->mac.type == e1000_ich8lan) &&
966 (hw->phy.type == e1000_phy_igp_3))
967 e1000_gig_downshift_workaround_ich8lan(hw);
968
969 /* When LPLU is enabled, we should disable SmartSpeed */
970 ret_val = e1000_read_phy_reg(hw,
971 IGP01E1000_PHY_PORT_CONFIG,
972 &data);

--- 6 unchanged lines hidden (view full) ---

979 data);
980 }
981
982out:
983 return ret_val;
984}
985
986/**
975 if ((hw->mac.type == e1000_ich8lan) &&
976 (hw->phy.type == e1000_phy_igp_3))
977 e1000_gig_downshift_workaround_ich8lan(hw);
978
979 /* When LPLU is enabled, we should disable SmartSpeed */
980 ret_val = e1000_read_phy_reg(hw,
981 IGP01E1000_PHY_PORT_CONFIG,
982 &data);

--- 6 unchanged lines hidden (view full) ---

989 data);
990 }
991
992out:
993 return ret_val;
994}
995
996/**
997 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
998 * @hw: pointer to the HW structure
999 * @bank: pointer to the variable that returns the active bank
1000 *
1001 * Reads signature byte from the NVM using the flash access registers.
1002 **/
1003STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1004{
1005 s32 ret_val = E1000_SUCCESS;
1006 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL)
1007 *bank = 1;
1008 else
1009 *bank = 0;
1010
1011 return ret_val;
1012}
1013
1014/**
987 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
988 * @hw: pointer to the HW structure
989 * @offset: The offset (in bytes) of the word(s) to read.
990 * @words: Size of data to read in words
991 * @data: Pointer to the word(s) to read at offset.
992 *
993 * Reads a word(s) from the NVM using the flash access registers.
994 **/
1015 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1016 * @hw: pointer to the HW structure
1017 * @offset: The offset (in bytes) of the word(s) to read.
1018 * @words: Size of data to read in words
1019 * @data: Pointer to the word(s) to read at offset.
1020 *
1021 * Reads a word(s) from the NVM using the flash access registers.
1022 **/
995STATIC s32
996e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
1023STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1024 u16 *data)
997{
998 struct e1000_nvm_info *nvm = &hw->nvm;
999 struct e1000_dev_spec_ich8lan *dev_spec;
1000 u32 act_offset;
1001 s32 ret_val = E1000_SUCCESS;
1025{
1026 struct e1000_nvm_info *nvm = &hw->nvm;
1027 struct e1000_dev_spec_ich8lan *dev_spec;
1028 u32 act_offset;
1029 s32 ret_val = E1000_SUCCESS;
1030 u32 bank = 0;
1002 u16 i, word;
1003
1004 DEBUGFUNC("e1000_read_nvm_ich8lan");
1005
1006 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
1007
1031 u16 i, word;
1032
1033 DEBUGFUNC("e1000_read_nvm_ich8lan");
1034
1035 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
1036
1008 if (dev_spec == NULL) {
1037 if (!dev_spec) {
1009 DEBUGOUT("dev_spec pointer is set to NULL.\n");
1010 ret_val = -E1000_ERR_CONFIG;
1011 goto out;
1012 }
1013
1014 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1015 (words == 0)) {
1016 DEBUGOUT("nvm parameter(s) out of bounds\n");
1017 ret_val = -E1000_ERR_NVM;
1018 goto out;
1019 }
1020
1021 ret_val = e1000_acquire_nvm(hw);
1022 if (ret_val)
1023 goto out;
1024
1038 DEBUGOUT("dev_spec pointer is set to NULL.\n");
1039 ret_val = -E1000_ERR_CONFIG;
1040 goto out;
1041 }
1042
1043 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1044 (words == 0)) {
1045 DEBUGOUT("nvm parameter(s) out of bounds\n");
1046 ret_val = -E1000_ERR_NVM;
1047 goto out;
1048 }
1049
1050 ret_val = e1000_acquire_nvm(hw);
1051 if (ret_val)
1052 goto out;
1053
1025 /* Start with the bank offset, then add the relative offset. */
1026 act_offset = (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL)
1027 ? nvm->flash_bank_size
1028 : 0;
1054 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1055 if (ret_val != E1000_SUCCESS)
1056 goto out;
1057
1058 act_offset = (bank) ? nvm->flash_bank_size : 0;
1029 act_offset += offset;
1030
1031 for (i = 0; i < words; i++) {
1059 act_offset += offset;
1060
1061 for (i = 0; i < words; i++) {
1032 if ((dev_spec->shadow_ram != NULL) &&
1033 (dev_spec->shadow_ram[offset+i].modified == TRUE)) {
1062 if ((dev_spec->shadow_ram) &&
1063 (dev_spec->shadow_ram[offset+i].modified)) {
1034 data[i] = dev_spec->shadow_ram[offset+i].value;
1035 } else {
1036 ret_val = e1000_read_flash_word_ich8lan(hw,
1037 act_offset + i,
1038 &word);
1039 if (ret_val)
1040 break;
1041 data[i] = word;

--- 8 unchanged lines hidden (view full) ---

1050
1051/**
1052 * e1000_flash_cycle_init_ich8lan - Initialize flash
1053 * @hw: pointer to the HW structure
1054 *
1055 * This function does initial flash setup so that a new read/write/erase cycle
1056 * can be started.
1057 **/
1064 data[i] = dev_spec->shadow_ram[offset+i].value;
1065 } else {
1066 ret_val = e1000_read_flash_word_ich8lan(hw,
1067 act_offset + i,
1068 &word);
1069 if (ret_val)
1070 break;
1071 data[i] = word;

--- 8 unchanged lines hidden (view full) ---

1080
1081/**
1082 * e1000_flash_cycle_init_ich8lan - Initialize flash
1083 * @hw: pointer to the HW structure
1084 *
1085 * This function does initial flash setup so that a new read/write/erase cycle
1086 * can be started.
1087 **/
1058static s32
1059e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1088static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1060{
1061 union ich8_hws_flash_status hsfsts;
1062 s32 ret_val = -E1000_ERR_NVM;
1063 s32 i = 0;
1064
1065 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
1066
1067 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);

--- 6 unchanged lines hidden (view full) ---

1074 }
1075
1076 /* Clear FCERR and DAEL in hw status by writing 1 */
1077 hsfsts.hsf_status.flcerr = 1;
1078 hsfsts.hsf_status.dael = 1;
1079
1080 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
1081
1089{
1090 union ich8_hws_flash_status hsfsts;
1091 s32 ret_val = -E1000_ERR_NVM;
1092 s32 i = 0;
1093
1094 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
1095
1096 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);

--- 6 unchanged lines hidden (view full) ---

1103 }
1104
1105 /* Clear FCERR and DAEL in hw status by writing 1 */
1106 hsfsts.hsf_status.flcerr = 1;
1107 hsfsts.hsf_status.dael = 1;
1108
1109 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
1110
1082 /* Either we should have a hardware SPI cycle in progress
1111 /*
1112 * Either we should have a hardware SPI cycle in progress
1083 * bit to check against, in order to start a new cycle or
1084 * FDONE bit should be changed in the hardware so that it
1085 * is 1 after harware reset, which can then be used as an
1086 * indication whether a cycle is in progress or has been
1087 * completed.
1088 */
1089
1090 if (hsfsts.hsf_status.flcinprog == 0) {
1113 * bit to check against, in order to start a new cycle or
1114 * FDONE bit should be changed in the hardware so that it
1115 * is 1 after harware reset, which can then be used as an
1116 * indication whether a cycle is in progress or has been
1117 * completed.
1118 */
1119
1120 if (hsfsts.hsf_status.flcinprog == 0) {
1091 /* There is no cycle running at present,
1092 * so we can start a cycle */
1093 /* Begin by setting Flash Cycle Done. */
1121 /*
1122 * There is no cycle running at present,
1123 * so we can start a cycle.
1124 * Begin by setting Flash Cycle Done.
1125 */
1094 hsfsts.hsf_status.flcdone = 1;
1095 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
1096 ret_val = E1000_SUCCESS;
1097 } else {
1126 hsfsts.hsf_status.flcdone = 1;
1127 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
1128 ret_val = E1000_SUCCESS;
1129 } else {
1098 /* otherwise poll for sometime so the current
1099 * cycle has a chance to end before giving up. */
1130 /*
1131 * Otherwise poll for sometime so the current
1132 * cycle has a chance to end before giving up.
1133 */
1100 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1101 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1102 ICH_FLASH_HSFSTS);
1103 if (hsfsts.hsf_status.flcinprog == 0) {
1104 ret_val = E1000_SUCCESS;
1105 break;
1106 }
1107 usec_delay(1);
1108 }
1109 if (ret_val == E1000_SUCCESS) {
1134 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1135 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1136 ICH_FLASH_HSFSTS);
1137 if (hsfsts.hsf_status.flcinprog == 0) {
1138 ret_val = E1000_SUCCESS;
1139 break;
1140 }
1141 usec_delay(1);
1142 }
1143 if (ret_val == E1000_SUCCESS) {
1110 /* Successful in waiting for previous cycle to timeout,
1111 * now set the Flash Cycle Done. */
1144 /*
1145 * Successful in waiting for previous cycle to timeout,
1146 * now set the Flash Cycle Done.
1147 */
1112 hsfsts.hsf_status.flcdone = 1;
1113 E1000_WRITE_FLASH_REG16(hw,
1114 ICH_FLASH_HSFSTS,
1115 hsfsts.regval);
1116 } else {
1117 DEBUGOUT("Flash controller busy, cannot get access");
1118 }
1119 }

--- 4 unchanged lines hidden (view full) ---

1124
1125/**
1126 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1127 * @hw: pointer to the HW structure
1128 * @timeout: maximum time to wait for completion
1129 *
1130 * This function starts a flash cycle and waits for its completion.
1131 **/
1148 hsfsts.hsf_status.flcdone = 1;
1149 E1000_WRITE_FLASH_REG16(hw,
1150 ICH_FLASH_HSFSTS,
1151 hsfsts.regval);
1152 } else {
1153 DEBUGOUT("Flash controller busy, cannot get access");
1154 }
1155 }

--- 4 unchanged lines hidden (view full) ---

1160
1161/**
1162 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1163 * @hw: pointer to the HW structure
1164 * @timeout: maximum time to wait for completion
1165 *
1166 * This function starts a flash cycle and waits for its completion.
1167 **/
1132static s32
1133e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1168static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1134{
1135 union ich8_hws_flash_ctrl hsflctl;
1136 union ich8_hws_flash_status hsfsts;
1137 s32 ret_val = -E1000_ERR_NVM;
1138 u32 i = 0;
1139
1140 DEBUGFUNC("e1000_flash_cycle_ich8lan");
1141

--- 20 unchanged lines hidden (view full) ---

1162 * e1000_read_flash_word_ich8lan - Read word from flash
1163 * @hw: pointer to the HW structure
1164 * @offset: offset to data location
1165 * @data: pointer to the location for storing the data
1166 *
1167 * Reads the flash word at offset into data. Offset is converted
1168 * to bytes before read.
1169 **/
1169{
1170 union ich8_hws_flash_ctrl hsflctl;
1171 union ich8_hws_flash_status hsfsts;
1172 s32 ret_val = -E1000_ERR_NVM;
1173 u32 i = 0;
1174
1175 DEBUGFUNC("e1000_flash_cycle_ich8lan");
1176

--- 20 unchanged lines hidden (view full) ---

1197 * e1000_read_flash_word_ich8lan - Read word from flash
1198 * @hw: pointer to the HW structure
1199 * @offset: offset to data location
1200 * @data: pointer to the location for storing the data
1201 *
1202 * Reads the flash word at offset into data. Offset is converted
1203 * to bytes before read.
1204 **/
1170STATIC s32
1171e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, u16 *data)
1205STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1206 u16 *data)
1172{
1173 s32 ret_val;
1174
1175 DEBUGFUNC("e1000_read_flash_word_ich8lan");
1176
1207{
1208 s32 ret_val;
1209
1210 DEBUGFUNC("e1000_read_flash_word_ich8lan");
1211
1177 if (data == NULL) {
1212 if (!data) {
1178 ret_val = -E1000_ERR_NVM;
1179 goto out;
1180 }
1181
1182 /* Must convert offset into bytes. */
1183 offset <<= 1;
1184
1185 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data);

--- 6 unchanged lines hidden (view full) ---

1192 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1193 * @hw: pointer to the HW structure
1194 * @offset: The offset (in bytes) of the byte or word to read.
1195 * @size: Size of data to read, 1=byte 2=word
1196 * @data: Pointer to the word to store the value read.
1197 *
1198 * Reads a byte or word from the NVM using the flash access registers.
1199 **/
1213 ret_val = -E1000_ERR_NVM;
1214 goto out;
1215 }
1216
1217 /* Must convert offset into bytes. */
1218 offset <<= 1;
1219
1220 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data);

--- 6 unchanged lines hidden (view full) ---

1227 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1228 * @hw: pointer to the HW structure
1229 * @offset: The offset (in bytes) of the byte or word to read.
1230 * @size: Size of data to read, 1=byte 2=word
1231 * @data: Pointer to the word to store the value read.
1232 *
1233 * Reads a byte or word from the NVM using the flash access registers.
1234 **/
1200static s32
1201e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1202 u8 size, u16* data)
1235static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1236 u8 size, u16* data)
1203{
1204 union ich8_hws_flash_status hsfsts;
1205 union ich8_hws_flash_ctrl hsflctl;
1206 u32 flash_linear_addr;
1207 u32 flash_data = 0;
1208 s32 ret_val = -E1000_ERR_NVM;
1209 u8 count = 0;
1210
1211 DEBUGFUNC("e1000_read_flash_data_ich8lan");
1212
1237{
1238 union ich8_hws_flash_status hsfsts;
1239 union ich8_hws_flash_ctrl hsflctl;
1240 u32 flash_linear_addr;
1241 u32 flash_data = 0;
1242 s32 ret_val = -E1000_ERR_NVM;
1243 u8 count = 0;
1244
1245 DEBUGFUNC("e1000_read_flash_data_ich8lan");
1246
1213 if (size < 1 || size > 2 || data == 0x0 ||
1214 offset > ICH_FLASH_LINEAR_ADDR_MASK)
1247 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1215 goto out;
1216
1217 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1218 hw->nvm.flash_base_addr;
1219
1220 do {
1221 usec_delay(1);
1222 /* Steps */

--- 7 unchanged lines hidden (view full) ---

1230 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1231 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
1232
1233 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
1234
1235 ret_val = e1000_flash_cycle_ich8lan(hw,
1236 ICH_FLASH_READ_COMMAND_TIMEOUT);
1237
1248 goto out;
1249
1250 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1251 hw->nvm.flash_base_addr;
1252
1253 do {
1254 usec_delay(1);
1255 /* Steps */

--- 7 unchanged lines hidden (view full) ---

1263 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1264 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
1265
1266 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
1267
1268 ret_val = e1000_flash_cycle_ich8lan(hw,
1269 ICH_FLASH_READ_COMMAND_TIMEOUT);
1270
1238 /* Check if FCERR is set to 1, if set to 1, clear it
1271 /*
1272 * Check if FCERR is set to 1, if set to 1, clear it
1239 * and try the whole sequence a few more times, else
1240 * read in (shift in) the Flash Data0, the order is
1273 * and try the whole sequence a few more times, else
1274 * read in (shift in) the Flash Data0, the order is
1241 * least significant byte first msb to lsb */
1275 * least significant byte first msb to lsb
1276 */
1242 if (ret_val == E1000_SUCCESS) {
1243 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
1244 if (size == 1) {
1245 *data = (u8)(flash_data & 0x000000FF);
1246 } else if (size == 2) {
1247 *data = (u16)(flash_data & 0x0000FFFF);
1248 }
1249 break;
1250 } else {
1277 if (ret_val == E1000_SUCCESS) {
1278 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
1279 if (size == 1) {
1280 *data = (u8)(flash_data & 0x000000FF);
1281 } else if (size == 2) {
1282 *data = (u16)(flash_data & 0x0000FFFF);
1283 }
1284 break;
1285 } else {
1251 /* If we've gotten here, then things are probably
1286 /*
1287 * If we've gotten here, then things are probably
1252 * completely hosed, but if the error condition is
1253 * detected, it won't hurt to give it another try...
1254 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1255 */
1256 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1257 ICH_FLASH_HSFSTS);
1258 if (hsfsts.hsf_status.flcerr == 1) {
1259 /* Repeat for some time before giving up. */

--- 14 unchanged lines hidden (view full) ---

1274 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1275 * @hw: pointer to the HW structure
1276 * @offset: The offset (in bytes) of the word(s) to write.
1277 * @words: Size of data to write in words
1278 * @data: Pointer to the word(s) to write at offset.
1279 *
1280 * Writes a byte or word to the NVM using the flash access registers.
1281 **/
1288 * completely hosed, but if the error condition is
1289 * detected, it won't hurt to give it another try...
1290 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1291 */
1292 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1293 ICH_FLASH_HSFSTS);
1294 if (hsfsts.hsf_status.flcerr == 1) {
1295 /* Repeat for some time before giving up. */

--- 14 unchanged lines hidden (view full) ---

1310 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1311 * @hw: pointer to the HW structure
1312 * @offset: The offset (in bytes) of the word(s) to write.
1313 * @words: Size of data to write in words
1314 * @data: Pointer to the word(s) to write at offset.
1315 *
1316 * Writes a byte or word to the NVM using the flash access registers.
1317 **/
1282STATIC s32
1283e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
1318STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1319 u16 *data)
1284{
1285 struct e1000_nvm_info *nvm = &hw->nvm;
1286 struct e1000_dev_spec_ich8lan *dev_spec;
1287 s32 ret_val = E1000_SUCCESS;
1288 u16 i;
1289
1290 DEBUGFUNC("e1000_write_nvm_ich8lan");
1291
1292 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
1293
1320{
1321 struct e1000_nvm_info *nvm = &hw->nvm;
1322 struct e1000_dev_spec_ich8lan *dev_spec;
1323 s32 ret_val = E1000_SUCCESS;
1324 u16 i;
1325
1326 DEBUGFUNC("e1000_write_nvm_ich8lan");
1327
1328 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
1329
1294 if (dev_spec == NULL) {
1330 if (!dev_spec) {
1295 DEBUGOUT("dev_spec pointer is set to NULL.\n");
1296 ret_val = -E1000_ERR_CONFIG;
1297 goto out;
1298 }
1299
1300 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1301 (words == 0)) {
1302 DEBUGOUT("nvm parameter(s) out of bounds\n");

--- 22 unchanged lines hidden (view full) ---

1325 *
1326 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1327 * which writes the checksum to the shadow ram. The changes in the shadow
1328 * ram are then committed to the EEPROM by processing each bank at a time
1329 * checking for the modified bit and writing only the pending changes.
1330 * After a succesful commit, the shadow ram is cleared and is ready for
1331 * future writes.
1332 **/
1331 DEBUGOUT("dev_spec pointer is set to NULL.\n");
1332 ret_val = -E1000_ERR_CONFIG;
1333 goto out;
1334 }
1335
1336 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1337 (words == 0)) {
1338 DEBUGOUT("nvm parameter(s) out of bounds\n");

--- 22 unchanged lines hidden (view full) ---

1361 *
1362 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1363 * which writes the checksum to the shadow ram. The changes in the shadow
1364 * ram are then committed to the EEPROM by processing each bank at a time
1365 * checking for the modified bit and writing only the pending changes.
1366 * After a succesful commit, the shadow ram is cleared and is ready for
1367 * future writes.
1368 **/
1333STATIC s32
1334e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1369STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1335{
1336 struct e1000_nvm_info *nvm = &hw->nvm;
1337 struct e1000_dev_spec_ich8lan *dev_spec;
1370{
1371 struct e1000_nvm_info *nvm = &hw->nvm;
1372 struct e1000_dev_spec_ich8lan *dev_spec;
1338 u32 i, act_offset, new_bank_offset, old_bank_offset;
1373 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1339 s32 ret_val;
1340 u16 data;
1341
1342 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
1343
1344 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
1345
1346 ret_val = e1000_update_nvm_checksum_generic(hw);
1347 if (ret_val)
1348 goto out;
1349
1350 if (nvm->type != e1000_nvm_flash_sw)
1351 goto out;
1352
1353 ret_val = e1000_acquire_nvm(hw);
1354 if (ret_val)
1355 goto out;
1356
1374 s32 ret_val;
1375 u16 data;
1376
1377 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
1378
1379 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
1380
1381 ret_val = e1000_update_nvm_checksum_generic(hw);
1382 if (ret_val)
1383 goto out;
1384
1385 if (nvm->type != e1000_nvm_flash_sw)
1386 goto out;
1387
1388 ret_val = e1000_acquire_nvm(hw);
1389 if (ret_val)
1390 goto out;
1391
1357 /* We're writing to the opposite bank so if we're on bank 1,
1392 /*
1393 * We're writing to the opposite bank so if we're on bank 1,
1358 * write to bank 0 etc. We also need to erase the segment that
1394 * write to bank 0 etc. We also need to erase the segment that
1359 * is going to be written */
1360 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL)) {
1395 * is going to be written
1396 */
1397 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1398 if (ret_val != E1000_SUCCESS)
1399 goto out;
1400
1401 if (bank == 0) {
1361 new_bank_offset = nvm->flash_bank_size;
1362 old_bank_offset = 0;
1363 e1000_erase_flash_bank_ich8lan(hw, 1);
1364 } else {
1365 old_bank_offset = nvm->flash_bank_size;
1366 new_bank_offset = 0;
1367 e1000_erase_flash_bank_ich8lan(hw, 0);
1368 }
1369
1370 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
1402 new_bank_offset = nvm->flash_bank_size;
1403 old_bank_offset = 0;
1404 e1000_erase_flash_bank_ich8lan(hw, 1);
1405 } else {
1406 old_bank_offset = nvm->flash_bank_size;
1407 new_bank_offset = 0;
1408 e1000_erase_flash_bank_ich8lan(hw, 0);
1409 }
1410
1411 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
1371 /* Determine whether to write the value stored
1412 /*
1413 * Determine whether to write the value stored
1372 * in the other NVM bank or a modified value stored
1414 * in the other NVM bank or a modified value stored
1373 * in the shadow RAM */
1374 if (dev_spec->shadow_ram[i].modified == TRUE) {
1415 * in the shadow RAM
1416 */
1417 if (dev_spec->shadow_ram[i].modified) {
1375 data = dev_spec->shadow_ram[i].value;
1376 } else {
1377 e1000_read_flash_word_ich8lan(hw,
1378 i + old_bank_offset,
1379 &data);
1380 }
1381
1418 data = dev_spec->shadow_ram[i].value;
1419 } else {
1420 e1000_read_flash_word_ich8lan(hw,
1421 i + old_bank_offset,
1422 &data);
1423 }
1424
1382 /* If the word is 0x13, then make sure the signature bits
1425 /*
1426 * If the word is 0x13, then make sure the signature bits
1383 * (15:14) are 11b until the commit has completed.
1384 * This will allow us to write 10b which indicates the
1385 * signature is valid. We want to do this after the write
1386 * has completed so that we don't mark the segment valid
1427 * (15:14) are 11b until the commit has completed.
1428 * This will allow us to write 10b which indicates the
1429 * signature is valid. We want to do this after the write
1430 * has completed so that we don't mark the segment valid
1387 * while the write is still in progress */
1431 * while the write is still in progress
1432 */
1388 if (i == E1000_ICH_NVM_SIG_WORD)
1389 data |= E1000_ICH_NVM_SIG_MASK;
1390
1391 /* Convert offset to bytes. */
1392 act_offset = (i + new_bank_offset) << 1;
1393
1394 usec_delay(100);
1395 /* Write the bytes to the new bank. */

--- 6 unchanged lines hidden (view full) ---

1402 usec_delay(100);
1403 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1404 act_offset + 1,
1405 (u8)(data >> 8));
1406 if (ret_val)
1407 break;
1408 }
1409
1433 if (i == E1000_ICH_NVM_SIG_WORD)
1434 data |= E1000_ICH_NVM_SIG_MASK;
1435
1436 /* Convert offset to bytes. */
1437 act_offset = (i + new_bank_offset) << 1;
1438
1439 usec_delay(100);
1440 /* Write the bytes to the new bank. */

--- 6 unchanged lines hidden (view full) ---

1447 usec_delay(100);
1448 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1449 act_offset + 1,
1450 (u8)(data >> 8));
1451 if (ret_val)
1452 break;
1453 }
1454
1410 /* Don't bother writing the segment valid bits if sector
1411 * programming failed. */
1455 /*
1456 * Don't bother writing the segment valid bits if sector
1457 * programming failed.
1458 */
1412 if (ret_val) {
1413 DEBUGOUT("Flash commit failed.\n");
1414 e1000_release_nvm(hw);
1415 goto out;
1416 }
1417
1459 if (ret_val) {
1460 DEBUGOUT("Flash commit failed.\n");
1461 e1000_release_nvm(hw);
1462 goto out;
1463 }
1464
1418 /* Finally validate the new segment by setting bit 15:14
1465 /*
1466 * Finally validate the new segment by setting bit 15:14
1419 * to 10b in word 0x13 , this can be done without an
1420 * erase as well since these bits are 11 to start with
1467 * to 10b in word 0x13 , this can be done without an
1468 * erase as well since these bits are 11 to start with
1421 * and we need to change bit 14 to 0b */
1469 * and we need to change bit 14 to 0b
1470 */
1422 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1423 e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1424 data &= 0xBFFF;
1425 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1426 act_offset * 2 + 1,
1427 (u8)(data >> 8));
1428 if (ret_val) {
1429 e1000_release_nvm(hw);
1430 goto out;
1431 }
1432
1471 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1472 e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1473 data &= 0xBFFF;
1474 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1475 act_offset * 2 + 1,
1476 (u8)(data >> 8));
1477 if (ret_val) {
1478 e1000_release_nvm(hw);
1479 goto out;
1480 }
1481
1433 /* And invalidate the previously valid segment by setting
1482 /*
1483 * And invalidate the previously valid segment by setting
1434 * its signature word (0x13) high_byte to 0b. This can be
1435 * done without an erase because flash erase sets all bits
1484 * its signature word (0x13) high_byte to 0b. This can be
1485 * done without an erase because flash erase sets all bits
1436 * to 1's. We can write 1's to 0's without an erase */
1486 * to 1's. We can write 1's to 0's without an erase
1487 */
1437 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1438 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1439 if (ret_val) {
1440 e1000_release_nvm(hw);
1441 goto out;
1442 }
1443
1444 /* Great! Everything worked, we can now clear the cached entries. */
1445 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
1446 dev_spec->shadow_ram[i].modified = FALSE;
1447 dev_spec->shadow_ram[i].value = 0xFFFF;
1448 }
1449
1450 e1000_release_nvm(hw);
1451
1488 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1489 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1490 if (ret_val) {
1491 e1000_release_nvm(hw);
1492 goto out;
1493 }
1494
1495 /* Great! Everything worked, we can now clear the cached entries. */
1496 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
1497 dev_spec->shadow_ram[i].modified = FALSE;
1498 dev_spec->shadow_ram[i].value = 0xFFFF;
1499 }
1500
1501 e1000_release_nvm(hw);
1502
1452 /* Reload the EEPROM, or else modifications will not appear
1503 /*
1504 * Reload the EEPROM, or else modifications will not appear
1453 * until after the next adapter reset.
1454 */
1455 e1000_reload_nvm(hw);
1456 msec_delay(10);
1457
1458out:
1459 return ret_val;
1460}
1461
1462/**
1463 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1464 * @hw: pointer to the HW structure
1465 *
1466 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1467 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1468 * calculated, in which case we need to calculate the checksum and set bit 6.
1469 **/
1505 * until after the next adapter reset.
1506 */
1507 e1000_reload_nvm(hw);
1508 msec_delay(10);
1509
1510out:
1511 return ret_val;
1512}
1513
1514/**
1515 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1516 * @hw: pointer to the HW structure
1517 *
1518 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1519 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1520 * calculated, in which case we need to calculate the checksum and set bit 6.
1521 **/
1470STATIC s32
1471e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1522STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1472{
1473 s32 ret_val = E1000_SUCCESS;
1474 u16 data;
1475
1476 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
1477
1523{
1524 s32 ret_val = E1000_SUCCESS;
1525 u16 data;
1526
1527 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
1528
1478 /* Read 0x19 and check bit 6. If this bit is 0, the checksum
1529 /*
1530 * Read 0x19 and check bit 6. If this bit is 0, the checksum
1479 * needs to be fixed. This bit is an indication that the NVM
1480 * was prepared by OEM software and did not calculate the
1481 * checksum...a likely scenario.
1482 */
1483 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1484 if (ret_val)
1485 goto out;
1486

--- 17 unchanged lines hidden (view full) ---

1504 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1505 * @hw: pointer to the HW structure
1506 * @offset: The offset (in bytes) of the byte/word to read.
1507 * @size: Size of data to read, 1=byte 2=word
1508 * @data: The byte(s) to write to the NVM.
1509 *
1510 * Writes one/two bytes to the NVM using the flash access registers.
1511 **/
1531 * needs to be fixed. This bit is an indication that the NVM
1532 * was prepared by OEM software and did not calculate the
1533 * checksum...a likely scenario.
1534 */
1535 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1536 if (ret_val)
1537 goto out;
1538

--- 17 unchanged lines hidden (view full) ---

1556 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1557 * @hw: pointer to the HW structure
1558 * @offset: The offset (in bytes) of the byte/word to read.
1559 * @size: Size of data to read, 1=byte 2=word
1560 * @data: The byte(s) to write to the NVM.
1561 *
1562 * Writes one/two bytes to the NVM using the flash access registers.
1563 **/
1512static s32
1513e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1514 u8 size, u16 data)
1564static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1565 u8 size, u16 data)
1515{
1516 union ich8_hws_flash_status hsfsts;
1517 union ich8_hws_flash_ctrl hsflctl;
1518 u32 flash_linear_addr;
1519 u32 flash_data = 0;
1520 s32 ret_val = -E1000_ERR_NVM;
1521 u8 count = 0;
1522

--- 23 unchanged lines hidden (view full) ---

1546
1547 if (size == 1)
1548 flash_data = (u32)data & 0x00FF;
1549 else
1550 flash_data = (u32)data;
1551
1552 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
1553
1566{
1567 union ich8_hws_flash_status hsfsts;
1568 union ich8_hws_flash_ctrl hsflctl;
1569 u32 flash_linear_addr;
1570 u32 flash_data = 0;
1571 s32 ret_val = -E1000_ERR_NVM;
1572 u8 count = 0;
1573

--- 23 unchanged lines hidden (view full) ---

1597
1598 if (size == 1)
1599 flash_data = (u32)data & 0x00FF;
1600 else
1601 flash_data = (u32)data;
1602
1603 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
1604
1554 /* check if FCERR is set to 1 , if set to 1, clear it
1555 * and try the whole sequence a few more times else done */
1605 /*
1606 * check if FCERR is set to 1 , if set to 1, clear it
1607 * and try the whole sequence a few more times else done
1608 */
1556 ret_val = e1000_flash_cycle_ich8lan(hw,
1557 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1558 if (ret_val == E1000_SUCCESS) {
1559 break;
1560 } else {
1609 ret_val = e1000_flash_cycle_ich8lan(hw,
1610 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1611 if (ret_val == E1000_SUCCESS) {
1612 break;
1613 } else {
1561 /* If we're here, then things are most likely
1614 /*
1615 * If we're here, then things are most likely
1562 * completely hosed, but if the error condition
1563 * is detected, it won't hurt to give it another
1564 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1565 */
1566 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1567 ICH_FLASH_HSFSTS);
1568 if (hsfsts.hsf_status.flcerr == 1) {
1569 /* Repeat for some time before giving up. */

--- 13 unchanged lines hidden (view full) ---

1583/**
1584 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1585 * @hw: pointer to the HW structure
1586 * @offset: The index of the byte to read.
1587 * @data: The byte to write to the NVM.
1588 *
1589 * Writes a single byte to the NVM using the flash access registers.
1590 **/
1616 * completely hosed, but if the error condition
1617 * is detected, it won't hurt to give it another
1618 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1619 */
1620 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1621 ICH_FLASH_HSFSTS);
1622 if (hsfsts.hsf_status.flcerr == 1) {
1623 /* Repeat for some time before giving up. */

--- 13 unchanged lines hidden (view full) ---

1637/**
1638 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1639 * @hw: pointer to the HW structure
1640 * @offset: The index of the byte to read.
1641 * @data: The byte to write to the NVM.
1642 *
1643 * Writes a single byte to the NVM using the flash access registers.
1644 **/
1591STATIC s32
1592e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 data)
1645STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1646 u8 data)
1593{
1594 u16 word = (u16)data;
1595
1596 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
1597
1598 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1599}
1600
1601/**
1602 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1603 * @hw: pointer to the HW structure
1604 * @offset: The offset of the byte to write.
1605 * @byte: The byte to write to the NVM.
1606 *
1607 * Writes a single byte to the NVM using the flash access registers.
1608 * Goes through a retry algorithm before giving up.
1609 **/
1647{
1648 u16 word = (u16)data;
1649
1650 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
1651
1652 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1653}
1654
1655/**
1656 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1657 * @hw: pointer to the HW structure
1658 * @offset: The offset of the byte to write.
1659 * @byte: The byte to write to the NVM.
1660 *
1661 * Writes a single byte to the NVM using the flash access registers.
1662 * Goes through a retry algorithm before giving up.
1663 **/
1610static s32
1611e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 byte)
1664static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1665 u8 byte)
1612{
1613 s32 ret_val;
1614 u16 program_retries;
1615
1616 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
1617
1618 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1666{
1667 s32 ret_val;
1668 u16 program_retries;
1669
1670 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
1671
1672 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1619 if (ret_val)
1673 if (ret_val == E1000_SUCCESS)
1620 goto out;
1621
1674 goto out;
1675
1622 usec_delay(100);
1623
1624 for (program_retries = 0; program_retries < 100; program_retries++) {
1625 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
1626 usec_delay(100);
1627 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1628 if (ret_val == E1000_SUCCESS)
1629 break;
1630 }
1631 if (program_retries == 100) {

--- 8 unchanged lines hidden (view full) ---

1640/**
1641 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1642 * @hw: pointer to the HW structure
1643 * @bank: 0 for first bank, 1 for second bank, etc.
1644 *
1645 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1646 * bank N is 4096 * N + flash_reg_addr.
1647 **/
1676 for (program_retries = 0; program_retries < 100; program_retries++) {
1677 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
1678 usec_delay(100);
1679 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1680 if (ret_val == E1000_SUCCESS)
1681 break;
1682 }
1683 if (program_retries == 100) {

--- 8 unchanged lines hidden (view full) ---

1692/**
1693 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1694 * @hw: pointer to the HW structure
1695 * @bank: 0 for first bank, 1 for second bank, etc.
1696 *
1697 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1698 * bank N is 4096 * N + flash_reg_addr.
1699 **/
1648STATIC s32
1649e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1700STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1650{
1651 struct e1000_nvm_info *nvm = &hw->nvm;
1652 union ich8_hws_flash_status hsfsts;
1653 union ich8_hws_flash_ctrl hsflctl;
1654 u32 flash_linear_addr;
1701{
1702 struct e1000_nvm_info *nvm = &hw->nvm;
1703 union ich8_hws_flash_status hsfsts;
1704 union ich8_hws_flash_ctrl hsflctl;
1705 u32 flash_linear_addr;
1655 u32 flash_bank_size = nvm->flash_bank_size * 2; /* bank size is in 16bit words - adjust to bytes */
1706 /* bank size is in 16bit words - adjust to bytes */
1707 u32 flash_bank_size = nvm->flash_bank_size * 2;
1656 s32 ret_val = E1000_SUCCESS;
1657 s32 count = 0;
1658 s32 j, iteration, sector_size;
1659
1660 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
1661
1662 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1663
1708 s32 ret_val = E1000_SUCCESS;
1709 s32 count = 0;
1710 s32 j, iteration, sector_size;
1711
1712 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
1713
1714 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1715
1664 /* Determine HW Sector size: Read BERASE bits of hw flash status
1665 * register */
1666 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
1716 /*
1717 * Determine HW Sector size: Read BERASE bits of hw flash status
1718 * register
1719 * 00: The Hw sector is 256 bytes, hence we need to erase 16
1667 * consecutive sectors. The start index for the nth Hw sector
1668 * can be calculated as = bank * 4096 + n * 256
1669 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1670 * The start index for the nth Hw sector can be calculated
1671 * as = bank * 4096
1672 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1673 * (ich9 only, otherwise error condition)
1674 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536

--- 32 unchanged lines hidden (view full) ---

1707
1708 for (j = 0; j < iteration ; j++) {
1709 do {
1710 /* Steps */
1711 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1712 if (ret_val)
1713 goto out;
1714
1720 * consecutive sectors. The start index for the nth Hw sector
1721 * can be calculated as = bank * 4096 + n * 256
1722 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1723 * The start index for the nth Hw sector can be calculated
1724 * as = bank * 4096
1725 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1726 * (ich9 only, otherwise error condition)
1727 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536

--- 32 unchanged lines hidden (view full) ---

1760
1761 for (j = 0; j < iteration ; j++) {
1762 do {
1763 /* Steps */
1764 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1765 if (ret_val)
1766 goto out;
1767
1715 /* Write a value 11 (block Erase) in Flash
1716 * Cycle field in hw flash control */
1768 /*
1769 * Write a value 11 (block Erase) in Flash
1770 * Cycle field in hw flash control
1771 */
1717 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
1718 ICH_FLASH_HSFCTL);
1719 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1720 E1000_WRITE_FLASH_REG16(hw,
1721 ICH_FLASH_HSFCTL,
1722 hsflctl.regval);
1723
1772 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
1773 ICH_FLASH_HSFCTL);
1774 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1775 E1000_WRITE_FLASH_REG16(hw,
1776 ICH_FLASH_HSFCTL,
1777 hsflctl.regval);
1778
1724 /* Write the last 24 bits of an index within the
1779 /*
1780 * Write the last 24 bits of an index within the
1725 * block into Flash Linear address field in Flash
1726 * Address.
1727 */
1728 flash_linear_addr += (j * sector_size);
1729 E1000_WRITE_FLASH_REG(hw,
1730 ICH_FLASH_FADDR,
1731 flash_linear_addr);
1732
1733 ret_val = e1000_flash_cycle_ich8lan(hw,
1734 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1735 if (ret_val == E1000_SUCCESS) {
1736 break;
1737 } else {
1781 * block into Flash Linear address field in Flash
1782 * Address.
1783 */
1784 flash_linear_addr += (j * sector_size);
1785 E1000_WRITE_FLASH_REG(hw,
1786 ICH_FLASH_FADDR,
1787 flash_linear_addr);
1788
1789 ret_val = e1000_flash_cycle_ich8lan(hw,
1790 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1791 if (ret_val == E1000_SUCCESS) {
1792 break;
1793 } else {
1738 /* Check if FCERR is set to 1. If 1,
1794 /*
1795 * Check if FCERR is set to 1. If 1,
1739 * clear it and try the whole sequence
1796 * clear it and try the whole sequence
1740 * a few more times else Done */
1797 * a few more times else Done
1798 */
1741 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1742 ICH_FLASH_HSFSTS);
1743 if (hsfsts.hsf_status.flcerr == 1) {
1799 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1800 ICH_FLASH_HSFSTS);
1801 if (hsfsts.hsf_status.flcerr == 1) {
1744 /* repeat for some time before
1745 * giving up */
1802 /*
1803 * repeat for some time before
1804 * giving up
1805 */
1746 continue;
1747 } else if (hsfsts.hsf_status.flcdone == 0)
1748 goto out;
1749 }
1750 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
1751 }
1752
1753out:

--- 4 unchanged lines hidden (view full) ---

1758 * e1000_valid_led_default_ich8lan - Set the default LED settings
1759 * @hw: pointer to the HW structure
1760 * @data: Pointer to the LED settings
1761 *
1762 * Reads the LED default settings from the NVM to data. If the NVM LED
1763 * settings is all 0's or F's, set the LED default to a valid LED default
1764 * setting.
1765 **/
1806 continue;
1807 } else if (hsfsts.hsf_status.flcdone == 0)
1808 goto out;
1809 }
1810 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
1811 }
1812
1813out:

--- 4 unchanged lines hidden (view full) ---

1818 * e1000_valid_led_default_ich8lan - Set the default LED settings
1819 * @hw: pointer to the HW structure
1820 * @data: Pointer to the LED settings
1821 *
1822 * Reads the LED default settings from the NVM to data. If the NVM LED
1823 * settings is all 0's or F's, set the LED default to a valid LED default
1824 * setting.
1825 **/
1766STATIC s32
1767e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1826STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1768{
1769 s32 ret_val;
1770
1771 DEBUGFUNC("e1000_valid_led_default_ich8lan");
1772
1773 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1774 if (ret_val) {
1775 DEBUGOUT("NVM Read Error\n");

--- 10 unchanged lines hidden (view full) ---

1786
1787/**
1788 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1789 * @hw: pointer to the HW structure
1790 *
1791 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1792 * register, so the the bus width is hard coded.
1793 **/
1827{
1828 s32 ret_val;
1829
1830 DEBUGFUNC("e1000_valid_led_default_ich8lan");
1831
1832 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1833 if (ret_val) {
1834 DEBUGOUT("NVM Read Error\n");

--- 10 unchanged lines hidden (view full) ---

1845
1846/**
1847 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1848 * @hw: pointer to the HW structure
1849 *
1850 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1851 * register, so the the bus width is hard coded.
1852 **/
1794STATIC s32
1795e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1853STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1796{
1797 struct e1000_bus_info *bus = &hw->bus;
1798 s32 ret_val;
1799
1800 DEBUGFUNC("e1000_get_bus_info_ich8lan");
1801
1802 ret_val = e1000_get_bus_info_pcie_generic(hw);
1803
1854{
1855 struct e1000_bus_info *bus = &hw->bus;
1856 s32 ret_val;
1857
1858 DEBUGFUNC("e1000_get_bus_info_ich8lan");
1859
1860 ret_val = e1000_get_bus_info_pcie_generic(hw);
1861
1804 /* ICH devices are "PCI Express"-ish. They have
1862 /*
1863 * ICH devices are "PCI Express"-ish. They have
1805 * a configuration space, but do not contain
1806 * PCI Express Capability registers, so bus width
1807 * must be hardcoded.
1808 */
1809 if (bus->width == e1000_bus_width_unknown)
1810 bus->width = e1000_bus_width_pcie_x1;
1811
1812 return ret_val;
1813}
1814
1815/**
1816 * e1000_reset_hw_ich8lan - Reset the hardware
1817 * @hw: pointer to the HW structure
1818 *
1819 * Does a full reset of the hardware which includes a reset of the PHY and
1820 * MAC.
1821 **/
1864 * a configuration space, but do not contain
1865 * PCI Express Capability registers, so bus width
1866 * must be hardcoded.
1867 */
1868 if (bus->width == e1000_bus_width_unknown)
1869 bus->width = e1000_bus_width_pcie_x1;
1870
1871 return ret_val;
1872}
1873
1874/**
1875 * e1000_reset_hw_ich8lan - Reset the hardware
1876 * @hw: pointer to the HW structure
1877 *
1878 * Does a full reset of the hardware which includes a reset of the PHY and
1879 * MAC.
1880 **/
1822STATIC s32
1823e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1881STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1824{
1825 u32 ctrl, icr, kab;
1826 s32 ret_val;
1827
1828 DEBUGFUNC("e1000_reset_hw_ich8lan");
1829
1882{
1883 u32 ctrl, icr, kab;
1884 s32 ret_val;
1885
1886 DEBUGFUNC("e1000_reset_hw_ich8lan");
1887
1830 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1888 /*
1889 * Prevent the PCI-E bus from sticking if there is no TLP connection
1831 * on the last TLP read/write transaction when MAC is reset.
1832 */
1833 ret_val = e1000_disable_pcie_master_generic(hw);
1834 if (ret_val) {
1835 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1836 }
1837
1838 DEBUGOUT("Masking off all interrupts\n");
1839 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1840
1890 * on the last TLP read/write transaction when MAC is reset.
1891 */
1892 ret_val = e1000_disable_pcie_master_generic(hw);
1893 if (ret_val) {
1894 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1895 }
1896
1897 DEBUGOUT("Masking off all interrupts\n");
1898 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1899
1841 /* Disable the Transmit and Receive units. Then delay to allow
1900 /*
1901 * Disable the Transmit and Receive units. Then delay to allow
1842 * any pending transactions to complete before we hit the MAC
1843 * with the global reset.
1844 */
1845 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1846 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1847 E1000_WRITE_FLUSH(hw);
1848
1849 msec_delay(10);

--- 4 unchanged lines hidden (view full) ---

1854 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
1855 /* Set Packet Buffer Size to 16k. */
1856 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
1857 }
1858
1859 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1860
1861 if (!e1000_check_reset_block(hw) && !hw->phy.reset_disable) {
1902 * any pending transactions to complete before we hit the MAC
1903 * with the global reset.
1904 */
1905 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1906 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1907 E1000_WRITE_FLUSH(hw);
1908
1909 msec_delay(10);

--- 4 unchanged lines hidden (view full) ---

1914 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
1915 /* Set Packet Buffer Size to 16k. */
1916 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
1917 }
1918
1919 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1920
1921 if (!e1000_check_reset_block(hw) && !hw->phy.reset_disable) {
1862 /* PHY HW reset requires MAC CORE reset at the same
1922 /*
1923 * PHY HW reset requires MAC CORE reset at the same
1863 * time to make sure the interface between MAC and the
1864 * external PHY is reset.
1865 */
1866 ctrl |= E1000_CTRL_PHY_RST;
1867 }
1868 ret_val = e1000_acquire_swflag_ich8lan(hw);
1869 DEBUGOUT("Issuing a global reset to ich8lan");
1870 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));

--- 26 unchanged lines hidden (view full) ---

1897 * Prepares the hardware for transmit and receive by doing the following:
1898 * - initialize hardware bits
1899 * - initialize LED identification
1900 * - setup receive address registers
1901 * - setup flow control
1902 * - setup transmit discriptors
1903 * - clear statistics
1904 **/
1924 * time to make sure the interface between MAC and the
1925 * external PHY is reset.
1926 */
1927 ctrl |= E1000_CTRL_PHY_RST;
1928 }
1929 ret_val = e1000_acquire_swflag_ich8lan(hw);
1930 DEBUGOUT("Issuing a global reset to ich8lan");
1931 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));

--- 26 unchanged lines hidden (view full) ---

1958 * Prepares the hardware for transmit and receive by doing the following:
1959 * - initialize hardware bits
1960 * - initialize LED identification
1961 * - setup receive address registers
1962 * - setup flow control
1963 * - setup transmit discriptors
1964 * - clear statistics
1965 **/
1905STATIC s32
1906e1000_init_hw_ich8lan(struct e1000_hw *hw)
1966STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
1907{
1908 struct e1000_mac_info *mac = &hw->mac;
1909 u32 ctrl_ext, txdctl, snoop;
1910 s32 ret_val;
1911 u16 i;
1912
1913 DEBUGFUNC("e1000_init_hw_ich8lan");
1914
1915 e1000_initialize_hw_bits_ich8lan(hw);
1916
1917 /* Initialize identification LED */
1918 ret_val = e1000_id_led_init_generic(hw);
1919 if (ret_val) {
1920 DEBUGOUT("Error initializing identification LED\n");
1967{
1968 struct e1000_mac_info *mac = &hw->mac;
1969 u32 ctrl_ext, txdctl, snoop;
1970 s32 ret_val;
1971 u16 i;
1972
1973 DEBUGFUNC("e1000_init_hw_ich8lan");
1974
1975 e1000_initialize_hw_bits_ich8lan(hw);
1976
1977 /* Initialize identification LED */
1978 ret_val = e1000_id_led_init_generic(hw);
1979 if (ret_val) {
1980 DEBUGOUT("Error initializing identification LED\n");
1921 goto out;
1981 /* This is not fatal and we should not stop init due to this */
1922 }
1923
1924 /* Setup the receive address. */
1925 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
1926
1927 /* Zero out the Multicast HASH table */
1928 DEBUGOUT("Zeroing the MTA\n");
1929 for (i = 0; i < mac->mta_reg_count; i++)
1930 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1931
1932 /* Setup link and flow control */
1933 ret_val = e1000_setup_link(hw);
1934
1935 /* Set the transmit descriptor write-back policy for both queues */
1982 }
1983
1984 /* Setup the receive address. */
1985 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
1986
1987 /* Zero out the Multicast HASH table */
1988 DEBUGOUT("Zeroing the MTA\n");
1989 for (i = 0; i < mac->mta_reg_count; i++)
1990 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1991
1992 /* Setup link and flow control */
1993 ret_val = e1000_setup_link(hw);
1994
1995 /* Set the transmit descriptor write-back policy for both queues */
1936 txdctl = E1000_READ_REG(hw, E1000_TXDCTL);
1996 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
1937 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1938 E1000_TXDCTL_FULL_TX_DESC_WB;
1939 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1940 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1997 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1998 E1000_TXDCTL_FULL_TX_DESC_WB;
1999 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2000 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1941 E1000_WRITE_REG(hw, E1000_TXDCTL, txdctl);
1942 txdctl = E1000_READ_REG(hw, E1000_TXDCTL1);
2001 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
2002 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
1943 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1944 E1000_TXDCTL_FULL_TX_DESC_WB;
1945 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1946 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2003 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2004 E1000_TXDCTL_FULL_TX_DESC_WB;
2005 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2006 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1947 E1000_WRITE_REG(hw, E1000_TXDCTL1, txdctl);
2007 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
1948
2008
1949 /* ICH8 has opposite polarity of no_snoop bits.
1950 * By default, we should use snoop behavior. */
2009 /*
2010 * ICH8 has opposite polarity of no_snoop bits.
2011 * By default, we should use snoop behavior.
2012 */
1951 if (mac->type == e1000_ich8lan)
1952 snoop = PCIE_ICH8_SNOOP_ALL;
1953 else
1954 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
1955 e1000_set_pcie_no_snoop_generic(hw, snoop);
1956
1957 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1958 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1959 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1960
2013 if (mac->type == e1000_ich8lan)
2014 snoop = PCIE_ICH8_SNOOP_ALL;
2015 else
2016 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
2017 e1000_set_pcie_no_snoop_generic(hw, snoop);
2018
2019 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2020 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2021 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2022
1961 /* Clear all of the statistics registers (clear on read). It is
2023 /*
2024 * Clear all of the statistics registers (clear on read). It is
1962 * important that we do this after we have tried to establish link
1963 * because the symbol error count will increment wildly if there
1964 * is no link.
1965 */
1966 e1000_clear_hw_cntrs_ich8lan(hw);
1967
2025 * important that we do this after we have tried to establish link
2026 * because the symbol error count will increment wildly if there
2027 * is no link.
2028 */
2029 e1000_clear_hw_cntrs_ich8lan(hw);
2030
1968out:
1969 return ret_val;
1970}
1971/**
1972 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
1973 * @hw: pointer to the HW structure
1974 *
1975 * Sets/Clears required hardware bits necessary for correctly setting up the
1976 * hardware for transmit and receive.
1977 **/
2031 return ret_val;
2032}
2033/**
2034 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2035 * @hw: pointer to the HW structure
2036 *
2037 * Sets/Clears required hardware bits necessary for correctly setting up the
2038 * hardware for transmit and receive.
2039 **/
1978static void
1979e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2040static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
1980{
1981 u32 reg;
1982
1983 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
1984
1985 if (hw->mac.disable_hw_init_bits)
1986 goto out;
1987
1988 /* Extended Device Control */
1989 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1990 reg |= (1 << 22);
1991 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1992
1993 /* Transmit Descriptor Control 0 */
2041{
2042 u32 reg;
2043
2044 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
2045
2046 if (hw->mac.disable_hw_init_bits)
2047 goto out;
2048
2049 /* Extended Device Control */
2050 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2051 reg |= (1 << 22);
2052 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2053
2054 /* Transmit Descriptor Control 0 */
1994 reg = E1000_READ_REG(hw, E1000_TXDCTL);
2055 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1995 reg |= (1 << 22);
2056 reg |= (1 << 22);
1996 E1000_WRITE_REG(hw, E1000_TXDCTL, reg);
2057 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1997
1998 /* Transmit Descriptor Control 1 */
2058
2059 /* Transmit Descriptor Control 1 */
1999 reg = E1000_READ_REG(hw, E1000_TXDCTL1);
2060 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
2000 reg |= (1 << 22);
2061 reg |= (1 << 22);
2001 E1000_WRITE_REG(hw, E1000_TXDCTL1, reg);
2062 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
2002
2003 /* Transmit Arbitration Control 0 */
2063
2064 /* Transmit Arbitration Control 0 */
2004 reg = E1000_READ_REG(hw, E1000_TARC0);
2065 reg = E1000_READ_REG(hw, E1000_TARC(0));
2005 if (hw->mac.type == e1000_ich8lan)
2006 reg |= (1 << 28) | (1 << 29);
2007 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2066 if (hw->mac.type == e1000_ich8lan)
2067 reg |= (1 << 28) | (1 << 29);
2068 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2008 E1000_WRITE_REG(hw, E1000_TARC0, reg);
2069 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
2009
2010 /* Transmit Arbitration Control 1 */
2070
2071 /* Transmit Arbitration Control 1 */
2011 reg = E1000_READ_REG(hw, E1000_TARC1);
2072 reg = E1000_READ_REG(hw, E1000_TARC(1));
2012 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
2013 reg &= ~(1 << 28);
2014 else
2015 reg |= (1 << 28);
2016 reg |= (1 << 24) | (1 << 26) | (1 << 30);
2073 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
2074 reg &= ~(1 << 28);
2075 else
2076 reg |= (1 << 28);
2077 reg |= (1 << 24) | (1 << 26) | (1 << 30);
2017 E1000_WRITE_REG(hw, E1000_TARC1, reg);
2078 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
2018
2019 /* Device Status */
2020 if (hw->mac.type == e1000_ich8lan) {
2021 reg = E1000_READ_REG(hw, E1000_STATUS);
2022 reg &= ~(1 << 31);
2023 E1000_WRITE_REG(hw, E1000_STATUS, reg);
2024 }
2025

--- 6 unchanged lines hidden (view full) ---

2032 * @hw: pointer to the HW structure
2033 *
2034 * Determines which flow control settings to use, then configures flow
2035 * control. Calls the appropriate media-specific link configuration
2036 * function. Assuming the adapter has a valid link partner, a valid link
2037 * should be established. Assumes the hardware has previously been reset
2038 * and the transmitter and receiver are not enabled.
2039 **/
2079
2080 /* Device Status */
2081 if (hw->mac.type == e1000_ich8lan) {
2082 reg = E1000_READ_REG(hw, E1000_STATUS);
2083 reg &= ~(1 << 31);
2084 E1000_WRITE_REG(hw, E1000_STATUS, reg);
2085 }
2086

--- 6 unchanged lines hidden (view full) ---

2093 * @hw: pointer to the HW structure
2094 *
2095 * Determines which flow control settings to use, then configures flow
2096 * control. Calls the appropriate media-specific link configuration
2097 * function. Assuming the adapter has a valid link partner, a valid link
2098 * should be established. Assumes the hardware has previously been reset
2099 * and the transmitter and receiver are not enabled.
2100 **/
2040STATIC s32
2041e1000_setup_link_ich8lan(struct e1000_hw *hw)
2101STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2042{
2102{
2043 struct e1000_mac_info *mac = &hw->mac;
2044 struct e1000_functions *func = &hw->func;
2045 s32 ret_val = E1000_SUCCESS;
2046
2047 DEBUGFUNC("e1000_setup_link_ich8lan");
2048
2049 if (e1000_check_reset_block(hw))
2050 goto out;
2051
2103 struct e1000_functions *func = &hw->func;
2104 s32 ret_val = E1000_SUCCESS;
2105
2106 DEBUGFUNC("e1000_setup_link_ich8lan");
2107
2108 if (e1000_check_reset_block(hw))
2109 goto out;
2110
2052 /* ICH parts do not have a word in the NVM to determine
2111 /*
2112 * ICH parts do not have a word in the NVM to determine
2053 * the default flow control setting, so we explicitly
2054 * set it to full.
2055 */
2113 * the default flow control setting, so we explicitly
2114 * set it to full.
2115 */
2056 if (mac->fc == e1000_fc_default)
2057 mac->fc = e1000_fc_full;
2116 if (hw->fc.type == e1000_fc_default)
2117 hw->fc.type = e1000_fc_full;
2058
2118
2059 mac->original_fc = mac->fc;
2119 hw->fc.original_type = hw->fc.type;
2060
2120
2061 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", mac->fc);
2121 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type);
2062
2063 /* Continue to configure the copper link. */
2064 ret_val = func->setup_physical_interface(hw);
2065 if (ret_val)
2066 goto out;
2067
2122
2123 /* Continue to configure the copper link. */
2124 ret_val = func->setup_physical_interface(hw);
2125 if (ret_val)
2126 goto out;
2127
2068 E1000_WRITE_REG(hw, E1000_FCTTV, mac->fc_pause_time);
2128 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
2069
2070 ret_val = e1000_set_fc_watermarks_generic(hw);
2071
2072out:
2073 return ret_val;
2074}
2075
2076/**
2077 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2078 * @hw: pointer to the HW structure
2079 *
2080 * Configures the kumeran interface to the PHY to wait the appropriate time
2081 * when polling the PHY, then call the generic setup_copper_link to finish
2082 * configuring the copper link.
2083 **/
2129
2130 ret_val = e1000_set_fc_watermarks_generic(hw);
2131
2132out:
2133 return ret_val;
2134}
2135
2136/**
2137 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2138 * @hw: pointer to the HW structure
2139 *
2140 * Configures the kumeran interface to the PHY to wait the appropriate time
2141 * when polling the PHY, then call the generic setup_copper_link to finish
2142 * configuring the copper link.
2143 **/
2084STATIC s32
2085e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2144STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2086{
2087 u32 ctrl;
2088 s32 ret_val;
2089 u16 reg_data;
2090
2091 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
2092
2093 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2094 ctrl |= E1000_CTRL_SLU;
2095 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2096 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2097
2145{
2146 u32 ctrl;
2147 s32 ret_val;
2148 u16 reg_data;
2149
2150 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
2151
2152 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2153 ctrl |= E1000_CTRL_SLU;
2154 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2155 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2156
2098 /* Set the mac to wait the maximum time between each iteration
2157 /*
2158 * Set the mac to wait the maximum time between each iteration
2099 * and increase the max iterations when polling the phy;
2159 * and increase the max iterations when polling the phy;
2100 * this fixes erroneous timeouts at 10Mbps. */
2160 * this fixes erroneous timeouts at 10Mbps.
2161 */
2101 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2102 if (ret_val)
2103 goto out;
2104 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2105 if (ret_val)
2106 goto out;
2107 reg_data |= 0x3F;
2108 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2109 if (ret_val)
2110 goto out;
2111
2112 if (hw->phy.type == e1000_phy_igp_3) {
2113 ret_val = e1000_copper_link_setup_igp(hw);
2114 if (ret_val)
2115 goto out;
2116 }
2117
2162 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2163 if (ret_val)
2164 goto out;
2165 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2166 if (ret_val)
2167 goto out;
2168 reg_data |= 0x3F;
2169 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2170 if (ret_val)
2171 goto out;
2172
2173 if (hw->phy.type == e1000_phy_igp_3) {
2174 ret_val = e1000_copper_link_setup_igp(hw);
2175 if (ret_val)
2176 goto out;
2177 }
2178
2179 if (hw->phy.type == e1000_phy_ife) {
2180 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
2181 if (ret_val)
2182 goto out;
2183
2184 reg_data &= ~IFE_PMC_AUTO_MDIX;
2185
2186 switch (hw->phy.mdix) {
2187 case 1:
2188 reg_data &= ~IFE_PMC_FORCE_MDIX;
2189 break;
2190 case 2:
2191 reg_data |= IFE_PMC_FORCE_MDIX;
2192 break;
2193 case 0:
2194 default:
2195 reg_data |= IFE_PMC_AUTO_MDIX;
2196 break;
2197 }
2198 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, reg_data);
2199 if (ret_val)
2200 goto out;
2201 }
2118 ret_val = e1000_setup_copper_link_generic(hw);
2119
2120out:
2121 return ret_val;
2122}
2123
2124/**
2125 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2126 * @hw: pointer to the HW structure
2127 * @speed: pointer to store current link speed
2128 * @duplex: pointer to store the current link duplex
2129 *
2130 * Calls the generic get_speed_and_duplex to retreive the current link
2131 * information and then calls the Kumeran lock loss workaround for links at
2132 * gigabit speeds.
2133 **/
2202 ret_val = e1000_setup_copper_link_generic(hw);
2203
2204out:
2205 return ret_val;
2206}
2207
2208/**
2209 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2210 * @hw: pointer to the HW structure
2211 * @speed: pointer to store current link speed
2212 * @duplex: pointer to store the current link duplex
2213 *
2214 * Calls the generic get_speed_and_duplex to retreive the current link
2215 * information and then calls the Kumeran lock loss workaround for links at
2216 * gigabit speeds.
2217 **/
2134STATIC s32
2135e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, u16 *duplex)
2218STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2219 u16 *duplex)
2136{
2137 s32 ret_val;
2138
2139 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
2140
2141 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
2142 if (ret_val)
2143 goto out;

--- 18 unchanged lines hidden (view full) ---

2162 * 0) if workaround is optionally disabled do nothing
2163 * 1) wait 1ms for Kumeran link to come up
2164 * 2) check Kumeran Diagnostic register PCS lock loss bit
2165 * 3) if not set the link is locked (all is good), otherwise...
2166 * 4) reset the PHY
2167 * 5) repeat up to 10 times
2168 * Note: this is only called for IGP3 copper when speed is 1gb.
2169 **/
2220{
2221 s32 ret_val;
2222
2223 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
2224
2225 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
2226 if (ret_val)
2227 goto out;

--- 18 unchanged lines hidden (view full) ---

2246 * 0) if workaround is optionally disabled do nothing
2247 * 1) wait 1ms for Kumeran link to come up
2248 * 2) check Kumeran Diagnostic register PCS lock loss bit
2249 * 3) if not set the link is locked (all is good), otherwise...
2250 * 4) reset the PHY
2251 * 5) repeat up to 10 times
2252 * Note: this is only called for IGP3 copper when speed is 1gb.
2253 **/
2170static s32
2171e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2254static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2172{
2173 struct e1000_dev_spec_ich8lan *dev_spec;
2174 u32 phy_ctrl;
2175 s32 ret_val = E1000_SUCCESS;
2176 u16 i, data;
2255{
2256 struct e1000_dev_spec_ich8lan *dev_spec;
2257 u32 phy_ctrl;
2258 s32 ret_val = E1000_SUCCESS;
2259 u16 i, data;
2177 boolean_t link;
2260 bool link;
2178
2179 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
2180
2181 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
2182
2261
2262 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
2263
2264 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
2265
2183 if (dev_spec == NULL) {
2266 if (!dev_spec) {
2184 DEBUGOUT("dev_spec pointer is set to NULL.\n");
2185 ret_val = -E1000_ERR_CONFIG;
2186 goto out;
2187 }
2188
2267 DEBUGOUT("dev_spec pointer is set to NULL.\n");
2268 ret_val = -E1000_ERR_CONFIG;
2269 goto out;
2270 }
2271
2189 if (dev_spec->kmrn_lock_loss_workaround_enabled == FALSE)
2272 if (!(dev_spec->kmrn_lock_loss_workaround_enabled))
2190 goto out;
2191
2273 goto out;
2274
2192 /* Make sure link is up before proceeding. If not just return.
2275 /*
2276 * Make sure link is up before proceeding. If not just return.
2193 * Attempting this while link is negotiating fouled up link
2277 * Attempting this while link is negotiating fouled up link
2194 * stability */
2278 * stability
2279 */
2195 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2196 if (!link) {
2197 ret_val = E1000_SUCCESS;
2198 goto out;
2199 }
2200
2201 for (i = 0; i < 10; i++) {
2202 /* read once to clear */

--- 16 unchanged lines hidden (view full) ---

2219 msec_delay_irq(5);
2220 }
2221 /* Disable GigE link negotiation */
2222 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2223 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2224 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2225 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2226
2280 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2281 if (!link) {
2282 ret_val = E1000_SUCCESS;
2283 goto out;
2284 }
2285
2286 for (i = 0; i < 10; i++) {
2287 /* read once to clear */

--- 16 unchanged lines hidden (view full) ---

2304 msec_delay_irq(5);
2305 }
2306 /* Disable GigE link negotiation */
2307 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2308 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2309 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2310 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2311
2227 /* Call gig speed drop workaround on Giga disable before accessing
2228 * any PHY registers */
2312 /*
2313 * Call gig speed drop workaround on Giga disable before accessing
2314 * any PHY registers
2315 */
2229 e1000_gig_downshift_workaround_ich8lan(hw);
2230
2231 /* unable to acquire PCS lock */
2232 ret_val = -E1000_ERR_PHY;
2233
2234out:
2235 return ret_val;
2236}
2237
2238/**
2239 * e1000_set_kmrn_lock_loss_workaound_ich8lan - Set Kumeran workaround state
2240 * @hw: pointer to the HW structure
2241 * @state: boolean value used to set the current Kumaran workaround state
2242 *
2243 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
2244 * /disabled - FALSE).
2245 **/
2316 e1000_gig_downshift_workaround_ich8lan(hw);
2317
2318 /* unable to acquire PCS lock */
2319 ret_val = -E1000_ERR_PHY;
2320
2321out:
2322 return ret_val;
2323}
2324
2325/**
2326 * e1000_set_kmrn_lock_loss_workaound_ich8lan - Set Kumeran workaround state
2327 * @hw: pointer to the HW structure
2328 * @state: boolean value used to set the current Kumaran workaround state
2329 *
2330 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
2331 * /disabled - FALSE).
2332 **/
2246void
2247e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2248 boolean_t state)
2333void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2334 bool state)
2249{
2250 struct e1000_dev_spec_ich8lan *dev_spec;
2251
2252 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
2253
2254 if (hw->mac.type != e1000_ich8lan) {
2255 DEBUGOUT("Workaround applies to ICH8 only.\n");
2256 goto out;
2257 }
2258
2259 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
2260
2335{
2336 struct e1000_dev_spec_ich8lan *dev_spec;
2337
2338 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
2339
2340 if (hw->mac.type != e1000_ich8lan) {
2341 DEBUGOUT("Workaround applies to ICH8 only.\n");
2342 goto out;
2343 }
2344
2345 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
2346
2261 if (dev_spec == NULL) {
2347 if (!dev_spec) {
2262 DEBUGOUT("dev_spec pointer is set to NULL.\n");
2263 goto out;
2264 }
2265
2266 dev_spec->kmrn_lock_loss_workaround_enabled = state;
2267
2268out:
2269 return;

--- 4 unchanged lines hidden (view full) ---

2274 * @hw: pointer to the HW structure
2275 *
2276 * Workaround for 82566 power-down on D3 entry:
2277 * 1) disable gigabit link
2278 * 2) write VR power-down enable
2279 * 3) read it back
2280 * Continue if successful, else issue LCD reset and repeat
2281 **/
2348 DEBUGOUT("dev_spec pointer is set to NULL.\n");
2349 goto out;
2350 }
2351
2352 dev_spec->kmrn_lock_loss_workaround_enabled = state;
2353
2354out:
2355 return;

--- 4 unchanged lines hidden (view full) ---

2360 * @hw: pointer to the HW structure
2361 *
2362 * Workaround for 82566 power-down on D3 entry:
2363 * 1) disable gigabit link
2364 * 2) write VR power-down enable
2365 * 3) read it back
2366 * Continue if successful, else issue LCD reset and repeat
2367 **/
2282void
2283e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2368void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2284{
2285 u32 reg;
2286 u16 data;
2287 u8 retry = 0;
2288
2289 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
2290
2291 if (hw->phy.type != e1000_phy_igp_3)
2292 goto out;
2293
2294 /* Try the workaround twice (if needed) */
2295 do {
2296 /* Disable link */
2297 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2298 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2299 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2300 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
2301
2369{
2370 u32 reg;
2371 u16 data;
2372 u8 retry = 0;
2373
2374 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
2375
2376 if (hw->phy.type != e1000_phy_igp_3)
2377 goto out;
2378
2379 /* Try the workaround twice (if needed) */
2380 do {
2381 /* Disable link */
2382 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2383 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2384 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2385 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
2386
2302 /* Call gig speed drop workaround on Giga disable before
2303 * accessing any PHY registers */
2387 /*
2388 * Call gig speed drop workaround on Giga disable before
2389 * accessing any PHY registers
2390 */
2304 if (hw->mac.type == e1000_ich8lan)
2305 e1000_gig_downshift_workaround_ich8lan(hw);
2306
2307 /* Write VR power-down enable */
2308 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &data);
2309 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2310 e1000_write_phy_reg(hw,
2311 IGP3_VR_CTRL,

--- 20 unchanged lines hidden (view full) ---

2332 * @hw: pointer to the HW structure
2333 *
2334 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2335 * LPLU, Giga disable, MDIC PHY reset):
2336 * 1) Set Kumeran Near-end loopback
2337 * 2) Clear Kumeran Near-end loopback
2338 * Should only be called for ICH8[m] devices with IGP_3 Phy.
2339 **/
2391 if (hw->mac.type == e1000_ich8lan)
2392 e1000_gig_downshift_workaround_ich8lan(hw);
2393
2394 /* Write VR power-down enable */
2395 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &data);
2396 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2397 e1000_write_phy_reg(hw,
2398 IGP3_VR_CTRL,

--- 20 unchanged lines hidden (view full) ---

2419 * @hw: pointer to the HW structure
2420 *
2421 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2422 * LPLU, Giga disable, MDIC PHY reset):
2423 * 1) Set Kumeran Near-end loopback
2424 * 2) Clear Kumeran Near-end loopback
2425 * Should only be called for ICH8[m] devices with IGP_3 Phy.
2426 **/
2340void
2341e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2427void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2342{
2343 s32 ret_val = E1000_SUCCESS;
2344 u16 reg_data;
2345
2346 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
2347
2348 if ((hw->mac.type != e1000_ich8lan) ||
2349 (hw->phy.type != e1000_phy_igp_3))

--- 16 unchanged lines hidden (view full) ---

2366}
2367
2368/**
2369 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2370 * @hw: pointer to the HW structure
2371 *
2372 * Return the LED back to the default configuration.
2373 **/
2428{
2429 s32 ret_val = E1000_SUCCESS;
2430 u16 reg_data;
2431
2432 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
2433
2434 if ((hw->mac.type != e1000_ich8lan) ||
2435 (hw->phy.type != e1000_phy_igp_3))

--- 16 unchanged lines hidden (view full) ---

2452}
2453
2454/**
2455 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2456 * @hw: pointer to the HW structure
2457 *
2458 * Return the LED back to the default configuration.
2459 **/
2374STATIC s32
2375e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2460STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2376{
2377 s32 ret_val = E1000_SUCCESS;
2378
2379 DEBUGFUNC("e1000_cleanup_led_ich8lan");
2380
2381 if (hw->phy.type == e1000_phy_ife)
2382 ret_val = e1000_write_phy_reg(hw,
2383 IFE_PHY_SPECIAL_CONTROL_LED,

--- 5 unchanged lines hidden (view full) ---

2389}
2390
2391/**
2392 * e1000_led_on_ich8lan - Turn LED's on
2393 * @hw: pointer to the HW structure
2394 *
2395 * Turn on the LED's.
2396 **/
2461{
2462 s32 ret_val = E1000_SUCCESS;
2463
2464 DEBUGFUNC("e1000_cleanup_led_ich8lan");
2465
2466 if (hw->phy.type == e1000_phy_ife)
2467 ret_val = e1000_write_phy_reg(hw,
2468 IFE_PHY_SPECIAL_CONTROL_LED,

--- 5 unchanged lines hidden (view full) ---

2474}
2475
2476/**
2477 * e1000_led_on_ich8lan - Turn LED's on
2478 * @hw: pointer to the HW structure
2479 *
2480 * Turn on the LED's.
2481 **/
2397STATIC s32
2398e1000_led_on_ich8lan(struct e1000_hw *hw)
2482STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2399{
2400 s32 ret_val = E1000_SUCCESS;
2401
2402 DEBUGFUNC("e1000_led_on_ich8lan");
2403
2404 if (hw->phy.type == e1000_phy_ife)
2405 ret_val = e1000_write_phy_reg(hw,
2406 IFE_PHY_SPECIAL_CONTROL_LED,

--- 5 unchanged lines hidden (view full) ---

2412}
2413
2414/**
2415 * e1000_led_off_ich8lan - Turn LED's off
2416 * @hw: pointer to the HW structure
2417 *
2418 * Turn off the LED's.
2419 **/
2483{
2484 s32 ret_val = E1000_SUCCESS;
2485
2486 DEBUGFUNC("e1000_led_on_ich8lan");
2487
2488 if (hw->phy.type == e1000_phy_ife)
2489 ret_val = e1000_write_phy_reg(hw,
2490 IFE_PHY_SPECIAL_CONTROL_LED,

--- 5 unchanged lines hidden (view full) ---

2496}
2497
2498/**
2499 * e1000_led_off_ich8lan - Turn LED's off
2500 * @hw: pointer to the HW structure
2501 *
2502 * Turn off the LED's.
2503 **/
2420STATIC s32
2421e1000_led_off_ich8lan(struct e1000_hw *hw)
2504STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2422{
2423 s32 ret_val = E1000_SUCCESS;
2424
2425 DEBUGFUNC("e1000_led_off_ich8lan");
2426
2427 if (hw->phy.type == e1000_phy_ife)
2428 ret_val = e1000_write_phy_reg(hw,
2429 IFE_PHY_SPECIAL_CONTROL_LED,

--- 9 unchanged lines hidden (view full) ---

2439 * @hw: pointer to the HW structure
2440 *
2441 * Read the management control register for the config done bit for
2442 * completion status. NOTE: silicon which is EEPROM-less will fail trying
2443 * to read the config done bit, so an error is *ONLY* logged and returns
2444 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
2445 * would not be able to be reset or change link.
2446 **/
2505{
2506 s32 ret_val = E1000_SUCCESS;
2507
2508 DEBUGFUNC("e1000_led_off_ich8lan");
2509
2510 if (hw->phy.type == e1000_phy_ife)
2511 ret_val = e1000_write_phy_reg(hw,
2512 IFE_PHY_SPECIAL_CONTROL_LED,

--- 9 unchanged lines hidden (view full) ---

2522 * @hw: pointer to the HW structure
2523 *
2524 * Read the management control register for the config done bit for
2525 * completion status. NOTE: silicon which is EEPROM-less will fail trying
2526 * to read the config done bit, so an error is *ONLY* logged and returns
2527 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
2528 * would not be able to be reset or change link.
2529 **/
2447STATIC s32
2448e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2530STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2449{
2531{
2532 s32 ret_val = E1000_SUCCESS;
2533
2450 e1000_get_cfg_done_generic(hw);
2451
2452 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2453 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
2454 (hw->phy.type == e1000_phy_igp_3)) {
2455 e1000_phy_init_script_igp3(hw);
2456 }
2457
2534 e1000_get_cfg_done_generic(hw);
2535
2536 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2537 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
2538 (hw->phy.type == e1000_phy_igp_3)) {
2539 e1000_phy_init_script_igp3(hw);
2540 }
2541
2458 return E1000_SUCCESS;
2542 return ret_val;
2459}
2460
2461/**
2543}
2544
2545/**
2546 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
2547 * @hw: pointer to the HW structure
2548 *
2549 * In the case of a PHY power down to save power, or to turn off link during a
2550 * driver unload, or wake on lan is not enabled, remove the link.
2551 **/
2552STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
2553{
2554 /* If the management interface is not enabled, then power down */
2555 if (!(e1000_check_mng_mode(hw) || e1000_check_reset_block(hw)))
2556 e1000_power_down_phy_copper(hw);
2557
2558 return;
2559}
2560
2561/**
2462 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2463 * @hw: pointer to the HW structure
2464 *
2465 * Clears hardware counters specific to the silicon family and calls
2466 * clear_hw_cntrs_generic to clear all general purpose counters.
2467 **/
2562 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2563 * @hw: pointer to the HW structure
2564 *
2565 * Clears hardware counters specific to the silicon family and calls
2566 * clear_hw_cntrs_generic to clear all general purpose counters.
2567 **/
2468STATIC void
2469e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2568STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2470{
2471 volatile u32 temp;
2472
2473 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
2474
2475 e1000_clear_hw_cntrs_base_generic(hw);
2476
2477 temp = E1000_READ_REG(hw, E1000_ALGNERRC);

--- 14 unchanged lines hidden --- 		2569{
2570 volatile u32 temp;
2571
2572 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
2573
2574 e1000_clear_hw_cntrs_base_generic(hw);
2575
2576 temp = E1000_READ_REG(hw, E1000_ALGNERRC);

--- 14 unchanged lines hidden ---