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e1000_ich8lan.c (169248) e1000_ich8lan.c (169589)
1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
33/*$FreeBSD: head/sys/dev/em/e1000_ich8lan.c 169589 2007-05-16 00:14:23Z jfv $*/
33
34
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/em/e1000_ich8lan.c 169248 2007-05-04 13:30:44Z rwatson $");
36
35
37
38/* e1000_ich8lan
39 * e1000_ich9lan
40 */
41
36/* e1000_ich8lan
37 * e1000_ich9lan
38 */
39
40#include "e1000_api.h"
42#include "e1000_ich8lan.h"
43
44void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw);
45
46STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
47STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
48STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
49STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);

--- 93 unchanged lines hidden (view full) ---

143
144struct e1000_dev_spec_ich8lan {
145 boolean_t kmrn_lock_loss_workaround_enabled;
146 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
147};
148
149/**
150 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
41#include "e1000_ich8lan.h"
42
43void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw);
44
45STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
46STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
47STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
48STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);

--- 93 unchanged lines hidden (view full) ---

142
143struct e1000_dev_spec_ich8lan {
144 boolean_t kmrn_lock_loss_workaround_enabled;
145 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
146};
147
148/**
149 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
151 * @hw - pointer to the HW structure
150 * @hw: pointer to the HW structure
152 *
153 * Initialize family-specific PHY parameters and function pointers.
154 **/
155STATIC s32
156e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
157{
158 struct e1000_phy_info *phy = &hw->phy;
159 struct e1000_functions *func = &hw->func;
160 s32 ret_val = E1000_SUCCESS;
151 *
152 * Initialize family-specific PHY parameters and function pointers.
153 **/
154STATIC s32
155e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
156{
157 struct e1000_phy_info *phy = &hw->phy;
158 struct e1000_functions *func = &hw->func;
159 s32 ret_val = E1000_SUCCESS;
160 u16 i = 0;
161
162 DEBUGFUNC("e1000_init_phy_params_ich8lan");
163
164 phy->addr = 1;
165 phy->reset_delay_us = 100;
166
167 func->acquire_phy = e1000_acquire_swflag_ich8lan;
168 func->check_polarity = e1000_check_polarity_ife_ich8lan;

--- 4 unchanged lines hidden (view full) ---

173 func->get_phy_info = e1000_get_phy_info_ich8lan;
174 func->read_phy_reg = e1000_read_phy_reg_igp;
175 func->release_phy = e1000_release_swflag_ich8lan;
176 func->reset_phy = e1000_phy_hw_reset_ich8lan;
177 func->set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
178 func->set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
179 func->write_phy_reg = e1000_write_phy_reg_igp;
180
161
162 DEBUGFUNC("e1000_init_phy_params_ich8lan");
163
164 phy->addr = 1;
165 phy->reset_delay_us = 100;
166
167 func->acquire_phy = e1000_acquire_swflag_ich8lan;
168 func->check_polarity = e1000_check_polarity_ife_ich8lan;

--- 4 unchanged lines hidden (view full) ---

173 func->get_phy_info = e1000_get_phy_info_ich8lan;
174 func->read_phy_reg = e1000_read_phy_reg_igp;
175 func->release_phy = e1000_release_swflag_ich8lan;
176 func->reset_phy = e1000_phy_hw_reset_ich8lan;
177 func->set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
178 func->set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
179 func->write_phy_reg = e1000_write_phy_reg_igp;
180
181 ret_val = e1000_get_phy_id(hw);
182 if (ret_val)
183 goto out;
184
181
182 phy->id = 0;
183 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
184 (i++ < 100)) {
185 msec_delay(1);
186 ret_val = e1000_get_phy_id(hw);
187 if (ret_val)
188 goto out;
189 }
190
185 /* Verify phy id */
186 switch (phy->id) {
187 case IGP03E1000_E_PHY_ID:
188 phy->type = e1000_phy_igp_3;
189 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
190 break;
191 case IFE_E_PHY_ID:
192 case IFE_PLUS_E_PHY_ID:

--- 7 unchanged lines hidden (view full) ---

200 }
201
202out:
203 return ret_val;
204}
205
206/**
207 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
191 /* Verify phy id */
192 switch (phy->id) {
193 case IGP03E1000_E_PHY_ID:
194 phy->type = e1000_phy_igp_3;
195 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
196 break;
197 case IFE_E_PHY_ID:
198 case IFE_PLUS_E_PHY_ID:

--- 7 unchanged lines hidden (view full) ---

206 }
207
208out:
209 return ret_val;
210}
211
212/**
213 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
208 * @hw - pointer to the HW structure
214 * @hw: pointer to the HW structure
209 *
210 * Initialize family-specific NVM parameters and function
211 * pointers.
212 **/
213STATIC s32
214e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
215{
216 struct e1000_nvm_info *nvm = &hw->nvm;

--- 60 unchanged lines hidden (view full) ---

277 func->write_nvm = e1000_write_nvm_ich8lan;
278
279out:
280 return ret_val;
281}
282
283/**
284 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
215 *
216 * Initialize family-specific NVM parameters and function
217 * pointers.
218 **/
219STATIC s32
220e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
221{
222 struct e1000_nvm_info *nvm = &hw->nvm;

--- 60 unchanged lines hidden (view full) ---

283 func->write_nvm = e1000_write_nvm_ich8lan;
284
285out:
286 return ret_val;
287}
288
289/**
290 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
285 * @hw - pointer to the HW structure
291 * @hw: pointer to the HW structure
286 *
287 * Initialize family-specific MAC parameters and function
288 * pointers.
289 **/
290STATIC s32
291e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
292{
293 struct e1000_mac_info *mac = &hw->mac;

--- 65 unchanged lines hidden (view full) ---

359
360
361out:
362 return ret_val;
363}
364
365/**
366 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
292 *
293 * Initialize family-specific MAC parameters and function
294 * pointers.
295 **/
296STATIC s32
297e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
298{
299 struct e1000_mac_info *mac = &hw->mac;

--- 65 unchanged lines hidden (view full) ---

365
366
367out:
368 return ret_val;
369}
370
371/**
372 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
367 * @hw - pointer to the HW structure
373 * @hw: pointer to the HW structure
368 *
369 * Initialize family-specific function pointers for PHY, MAC, and NVM.
370 **/
371void
372e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
373{
374 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
375
376 hw->func.init_mac_params = e1000_init_mac_params_ich8lan;
377 hw->func.init_nvm_params = e1000_init_nvm_params_ich8lan;
378 hw->func.init_phy_params = e1000_init_phy_params_ich8lan;
379}
380
381/**
382 * e1000_acquire_swflag_ich8lan - Acquire software control flag
374 *
375 * Initialize family-specific function pointers for PHY, MAC, and NVM.
376 **/
377void
378e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
379{
380 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
381
382 hw->func.init_mac_params = e1000_init_mac_params_ich8lan;
383 hw->func.init_nvm_params = e1000_init_nvm_params_ich8lan;
384 hw->func.init_phy_params = e1000_init_phy_params_ich8lan;
385}
386
387/**
388 * e1000_acquire_swflag_ich8lan - Acquire software control flag
383 * @hw - pointer to the HW structure
389 * @hw: pointer to the HW structure
384 *
385 * Acquires the software control flag for performing NVM and PHY
386 * operations. This is a function pointer entry point only called by
387 * read/write routines for the PHY and NVM parts.
388 **/
389STATIC s32
390e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
391{

--- 21 unchanged lines hidden (view full) ---

413 }
414
415out:
416 return ret_val;
417}
418
419/**
420 * e1000_release_swflag_ich8lan - Release software control flag
390 *
391 * Acquires the software control flag for performing NVM and PHY
392 * operations. This is a function pointer entry point only called by
393 * read/write routines for the PHY and NVM parts.
394 **/
395STATIC s32
396e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
397{

--- 21 unchanged lines hidden (view full) ---

419 }
420
421out:
422 return ret_val;
423}
424
425/**
426 * e1000_release_swflag_ich8lan - Release software control flag
421 * @hw - pointer to the HW structure
427 * @hw: pointer to the HW structure
422 *
423 * Releases the software control flag for performing NVM and PHY operations.
424 * This is a function pointer entry point only called by read/write
425 * routines for the PHY and NVM parts.
426 **/
427STATIC void
428e1000_release_swflag_ich8lan(struct e1000_hw *hw)
429{

--- 5 unchanged lines hidden (view full) ---

435 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
436 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
437
438 return;
439}
440
441/**
442 * e1000_check_mng_mode_ich8lan - Checks management mode
428 *
429 * Releases the software control flag for performing NVM and PHY operations.
430 * This is a function pointer entry point only called by read/write
431 * routines for the PHY and NVM parts.
432 **/
433STATIC void
434e1000_release_swflag_ich8lan(struct e1000_hw *hw)
435{

--- 5 unchanged lines hidden (view full) ---

441 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
442 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
443
444 return;
445}
446
447/**
448 * e1000_check_mng_mode_ich8lan - Checks management mode
443 * @hw - pointer to the HW structure
449 * @hw: pointer to the HW structure
444 *
445 * This checks if the adapter has manageability enabled.
446 * This is a function pointer entry point only called by read/write
447 * routines for the PHY and NVM parts.
448 **/
449STATIC boolean_t
450e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
451{

--- 4 unchanged lines hidden (view full) ---

456 fwsm = E1000_READ_REG(hw, E1000_FWSM);
457
458 return ((fwsm & E1000_FWSM_MODE_MASK) ==
459 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
460}
461
462/**
463 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
450 *
451 * This checks if the adapter has manageability enabled.
452 * This is a function pointer entry point only called by read/write
453 * routines for the PHY and NVM parts.
454 **/
455STATIC boolean_t
456e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
457{

--- 4 unchanged lines hidden (view full) ---

462 fwsm = E1000_READ_REG(hw, E1000_FWSM);
463
464 return ((fwsm & E1000_FWSM_MODE_MASK) ==
465 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
466}
467
468/**
469 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
464 * @hw - pointer to the HW structure
470 * @hw: pointer to the HW structure
465 *
466 * Checks if firmware is blocking the reset of the PHY.
467 * This is a function pointer entry point only called by
468 * reset routines.
469 **/
470STATIC s32
471e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
472{

--- 4 unchanged lines hidden (view full) ---

477 fwsm = E1000_READ_REG(hw, E1000_FWSM);
478
479 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
480 : E1000_BLK_PHY_RESET;
481}
482
483/**
484 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
471 *
472 * Checks if firmware is blocking the reset of the PHY.
473 * This is a function pointer entry point only called by
474 * reset routines.
475 **/
476STATIC s32
477e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
478{

--- 4 unchanged lines hidden (view full) ---

483 fwsm = E1000_READ_REG(hw, E1000_FWSM);
484
485 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
486 : E1000_BLK_PHY_RESET;
487}
488
489/**
490 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
485 * @hw - pointer to the HW structure
491 * @hw: pointer to the HW structure
486 *
487 * Forces the speed and duplex settings of the PHY.
488 * This is a function pointer entry point only called by
489 * PHY setup routines.
490 **/
491STATIC s32
492e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
493{

--- 59 unchanged lines hidden (view full) ---

553 }
554
555out:
556 return ret_val;
557}
558
559/**
560 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
492 *
493 * Forces the speed and duplex settings of the PHY.
494 * This is a function pointer entry point only called by
495 * PHY setup routines.
496 **/
497STATIC s32
498e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
499{

--- 59 unchanged lines hidden (view full) ---

559 }
560
561out:
562 return ret_val;
563}
564
565/**
566 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
561 * @hw - pointer to the HW structure
567 * @hw: pointer to the HW structure
562 *
563 * Resets the PHY
564 * This is a function pointer entry point called by drivers
565 * or other shared routines.
566 **/
567STATIC s32
568e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
569{

--- 100 unchanged lines hidden (view full) ---

670 }
671
672out:
673 return ret_val;
674}
675
676/**
677 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
568 *
569 * Resets the PHY
570 * This is a function pointer entry point called by drivers
571 * or other shared routines.
572 **/
573STATIC s32
574e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
575{

--- 100 unchanged lines hidden (view full) ---

676 }
677
678out:
679 return ret_val;
680}
681
682/**
683 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
678 * @hw - pointer to the HW structure
684 * @hw: pointer to the HW structure
679 *
680 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
681 * This is a function pointer entry point called by drivers
682 * or other shared routines.
683 **/
684STATIC s32
685e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
686{

--- 12 unchanged lines hidden (view full) ---

699 break;
700 }
701
702 return ret_val;
703}
704
705/**
706 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
685 *
686 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
687 * This is a function pointer entry point called by drivers
688 * or other shared routines.
689 **/
690STATIC s32
691e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
692{

--- 12 unchanged lines hidden (view full) ---

705 break;
706 }
707
708 return ret_val;
709}
710
711/**
712 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
707 * @hw - pointer to the HW structure
713 * @hw: pointer to the HW structure
708 *
709 * Populates "phy" structure with various feature states.
710 * This function is only called by other family-specific
711 * routines.
712 **/
713static s32
714e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
715{

--- 43 unchanged lines hidden (view full) ---

759 phy->remote_rx = e1000_1000t_rx_status_undefined;
760
761out:
762 return ret_val;
763}
764
765/**
766 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
714 *
715 * Populates "phy" structure with various feature states.
716 * This function is only called by other family-specific
717 * routines.
718 **/
719static s32
720e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
721{

--- 43 unchanged lines hidden (view full) ---

765 phy->remote_rx = e1000_1000t_rx_status_undefined;
766
767out:
768 return ret_val;
769}
770
771/**
772 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
767 * @hw - pointer to the HW structure
773 * @hw: pointer to the HW structure
768 *
769 * Polarity is determined on the polarity reveral feature being enabled.
770 * This function is only called by other family-specific
771 * routines.
772 **/
773STATIC s32
774e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
775{

--- 21 unchanged lines hidden (view full) ---

797 ? e1000_rev_polarity_reversed
798 : e1000_rev_polarity_normal;
799
800 return ret_val;
801}
802
803/**
804 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
774 *
775 * Polarity is determined on the polarity reveral feature being enabled.
776 * This function is only called by other family-specific
777 * routines.
778 **/
779STATIC s32
780e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
781{

--- 21 unchanged lines hidden (view full) ---

803 ? e1000_rev_polarity_reversed
804 : e1000_rev_polarity_normal;
805
806 return ret_val;
807}
808
809/**
810 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
805 * @hw - pointer to the HW structure
806 * @active - TRUE to enable LPLU, FALSE to disable
811 * @hw: pointer to the HW structure
812 * @active: TRUE to enable LPLU, FALSE to disable
807 *
808 * Sets the LPLU D0 state according to the active flag. When
809 * activating LPLU this function also disables smart speed
810 * and vice versa. LPLU will not be activated unless the
811 * device autonegotiation advertisement meets standards of
812 * either 10 or 10/100 or 10/100/1000 at all duplexes.
813 * This is a function pointer entry point only called by
814 * PHY setup routines.

--- 71 unchanged lines hidden (view full) ---

886 }
887
888out:
889 return ret_val;
890}
891
892/**
893 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
813 *
814 * Sets the LPLU D0 state according to the active flag. When
815 * activating LPLU this function also disables smart speed
816 * and vice versa. LPLU will not be activated unless the
817 * device autonegotiation advertisement meets standards of
818 * either 10 or 10/100 or 10/100/1000 at all duplexes.
819 * This is a function pointer entry point only called by
820 * PHY setup routines.

--- 71 unchanged lines hidden (view full) ---

892 }
893
894out:
895 return ret_val;
896}
897
898/**
899 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
894 * @hw - pointer to the HW structure
895 * @active - TRUE to enable LPLU, FALSE to disable
900 * @hw: pointer to the HW structure
901 * @active: TRUE to enable LPLU, FALSE to disable
896 *
897 * Sets the LPLU D3 state according to the active flag. When
898 * activating LPLU this function also disables smart speed
899 * and vice versa. LPLU will not be activated unless the
900 * device autonegotiation advertisement meets standards of
901 * either 10 or 10/100 or 10/100/1000 at all duplexes.
902 * This is a function pointer entry point only called by
903 * PHY setup routines.

--- 70 unchanged lines hidden (view full) ---

974 }
975
976out:
977 return ret_val;
978}
979
980/**
981 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
902 *
903 * Sets the LPLU D3 state according to the active flag. When
904 * activating LPLU this function also disables smart speed
905 * and vice versa. LPLU will not be activated unless the
906 * device autonegotiation advertisement meets standards of
907 * either 10 or 10/100 or 10/100/1000 at all duplexes.
908 * This is a function pointer entry point only called by
909 * PHY setup routines.

--- 70 unchanged lines hidden (view full) ---

980 }
981
982out:
983 return ret_val;
984}
985
986/**
987 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
982 * @hw - pointer to the HW structure
983 * @offset - The offset (in bytes) of the word(s) to read.
984 * @words - Size of data to read in words
985 * @data - Pointer to the word(s) to read at offset.
988 * @hw: pointer to the HW structure
989 * @offset: The offset (in bytes) of the word(s) to read.
990 * @words: Size of data to read in words
991 * @data: Pointer to the word(s) to read at offset.
986 *
987 * Reads a word(s) from the NVM using the flash access registers.
988 **/
989STATIC s32
990e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
991{
992 struct e1000_nvm_info *nvm = &hw->nvm;
993 struct e1000_dev_spec_ich8lan *dev_spec;

--- 45 unchanged lines hidden (view full) ---

1039 e1000_release_nvm(hw);
1040
1041out:
1042 return ret_val;
1043}
1044
1045/**
1046 * e1000_flash_cycle_init_ich8lan - Initialize flash
992 *
993 * Reads a word(s) from the NVM using the flash access registers.
994 **/
995STATIC s32
996e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
997{
998 struct e1000_nvm_info *nvm = &hw->nvm;
999 struct e1000_dev_spec_ich8lan *dev_spec;

--- 45 unchanged lines hidden (view full) ---

1045 e1000_release_nvm(hw);
1046
1047out:
1048 return ret_val;
1049}
1050
1051/**
1052 * e1000_flash_cycle_init_ich8lan - Initialize flash
1047 * @hw - pointer to the HW structure
1053 * @hw: pointer to the HW structure
1048 *
1049 * This function does initial flash setup so that a new read/write/erase cycle
1050 * can be started.
1051 **/
1052static s32
1053e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1054{
1055 union ich8_hws_flash_status hsfsts;

--- 57 unchanged lines hidden (view full) ---

1113 }
1114
1115out:
1116 return ret_val;
1117}
1118
1119/**
1120 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1054 *
1055 * This function does initial flash setup so that a new read/write/erase cycle
1056 * can be started.
1057 **/
1058static s32
1059e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1060{
1061 union ich8_hws_flash_status hsfsts;

--- 57 unchanged lines hidden (view full) ---

1119 }
1120
1121out:
1122 return ret_val;
1123}
1124
1125/**
1126 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1121 * @hw - pointer to the HW structure
1122 * @timeout - maximum time to wait for completion
1127 * @hw: pointer to the HW structure
1128 * @timeout: maximum time to wait for completion
1123 *
1124 * This function starts a flash cycle and waits for its completion.
1125 **/
1126static s32
1127e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1128{
1129 union ich8_hws_flash_ctrl hsflctl;
1130 union ich8_hws_flash_status hsfsts;

--- 18 unchanged lines hidden (view full) ---

1149 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1150 ret_val = E1000_SUCCESS;
1151
1152 return ret_val;
1153}
1154
1155/**
1156 * e1000_read_flash_word_ich8lan - Read word from flash
1129 *
1130 * This function starts a flash cycle and waits for its completion.
1131 **/
1132static s32
1133e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1134{
1135 union ich8_hws_flash_ctrl hsflctl;
1136 union ich8_hws_flash_status hsfsts;

--- 18 unchanged lines hidden (view full) ---

1155 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1156 ret_val = E1000_SUCCESS;
1157
1158 return ret_val;
1159}
1160
1161/**
1162 * e1000_read_flash_word_ich8lan - Read word from flash
1157 * @hw - pointer to the HW structure
1158 * @offset - offset to data location
1159 * @data - pointer to the location for storing the data
1163 * @hw: pointer to the HW structure
1164 * @offset: offset to data location
1165 * @data: pointer to the location for storing the data
1160 *
1161 * Reads the flash word at offset into data. Offset is converted
1162 * to bytes before read.
1163 **/
1164STATIC s32
1165e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, u16 *data)
1166{
1167 s32 ret_val;

--- 11 unchanged lines hidden (view full) ---

1179 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1180
1181out:
1182 return ret_val;
1183}
1184
1185/**
1186 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1166 *
1167 * Reads the flash word at offset into data. Offset is converted
1168 * to bytes before read.
1169 **/
1170STATIC s32
1171e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, u16 *data)
1172{
1173 s32 ret_val;

--- 11 unchanged lines hidden (view full) ---

1185 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1186
1187out:
1188 return ret_val;
1189}
1190
1191/**
1192 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1187 * @hw - pointer to the HW structure
1188 * @offset - The offset (in bytes) of the byte or word to read.
1189 * @size - Size of data to read, 1=byte 2=word
1190 * @data - Pointer to the word to store the value read.
1193 * @hw: pointer to the HW structure
1194 * @offset: The offset (in bytes) of the byte or word to read.
1195 * @size: Size of data to read, 1=byte 2=word
1196 * @data: Pointer to the word to store the value read.
1191 *
1192 * Reads a byte or word from the NVM using the flash access registers.
1193 **/
1194static s32
1195e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1196 u8 size, u16* data)
1197{
1198 union ich8_hws_flash_status hsfsts;

--- 62 unchanged lines hidden (view full) ---

1261 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1262
1263out:
1264 return ret_val;
1265}
1266
1267/**
1268 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1197 *
1198 * Reads a byte or word from the NVM using the flash access registers.
1199 **/
1200static s32
1201e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1202 u8 size, u16* data)
1203{
1204 union ich8_hws_flash_status hsfsts;

--- 62 unchanged lines hidden (view full) ---

1267 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1268
1269out:
1270 return ret_val;
1271}
1272
1273/**
1274 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1269 * @hw - pointer to the HW structure
1270 * @offset - The offset (in bytes) of the word(s) to write.
1271 * @words - Size of data to write in words
1272 * @data - Pointer to the word(s) to write at offset.
1275 * @hw: pointer to the HW structure
1276 * @offset: The offset (in bytes) of the word(s) to write.
1277 * @words: Size of data to write in words
1278 * @data: Pointer to the word(s) to write at offset.
1273 *
1274 * Writes a byte or word to the NVM using the flash access registers.
1275 **/
1276STATIC s32
1277e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
1278{
1279 struct e1000_nvm_info *nvm = &hw->nvm;
1280 struct e1000_dev_spec_ich8lan *dev_spec;

--- 29 unchanged lines hidden (view full) ---

1310 e1000_release_nvm(hw);
1311
1312out:
1313 return ret_val;
1314}
1315
1316/**
1317 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1279 *
1280 * Writes a byte or word to the NVM using the flash access registers.
1281 **/
1282STATIC s32
1283e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
1284{
1285 struct e1000_nvm_info *nvm = &hw->nvm;
1286 struct e1000_dev_spec_ich8lan *dev_spec;

--- 29 unchanged lines hidden (view full) ---

1316 e1000_release_nvm(hw);
1317
1318out:
1319 return ret_val;
1320}
1321
1322/**
1323 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1318 * @hw - pointer to the HW structure
1324 * @hw: pointer to the HW structure
1319 *
1320 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1321 * which writes the checksum to the shadow ram. The changes in the shadow
1322 * ram are then committed to the EEPROM by processing each bank at a time
1323 * checking for the modified bit and writing only the pending changes.
1324 * After a succesful commit, the shadow ram is cleared and is ready for
1325 * future writes.
1326 **/

--- 123 unchanged lines hidden (view full) ---

1450 msec_delay(10);
1451
1452out:
1453 return ret_val;
1454}
1455
1456/**
1457 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1325 *
1326 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1327 * which writes the checksum to the shadow ram. The changes in the shadow
1328 * ram are then committed to the EEPROM by processing each bank at a time
1329 * checking for the modified bit and writing only the pending changes.
1330 * After a succesful commit, the shadow ram is cleared and is ready for
1331 * future writes.
1332 **/

--- 123 unchanged lines hidden (view full) ---

1456 msec_delay(10);
1457
1458out:
1459 return ret_val;
1460}
1461
1462/**
1463 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1458 * @hw - pointer to the HW structure
1464 * @hw: pointer to the HW structure
1459 *
1460 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1461 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1462 * calculated, in which case we need to calculate the checksum and set bit 6.
1463 **/
1464STATIC s32
1465e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1466{

--- 24 unchanged lines hidden (view full) ---

1491 ret_val = e1000_validate_nvm_checksum_generic(hw);
1492
1493out:
1494 return ret_val;
1495}
1496
1497/**
1498 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1465 *
1466 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1467 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1468 * calculated, in which case we need to calculate the checksum and set bit 6.
1469 **/
1470STATIC s32
1471e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1472{

--- 24 unchanged lines hidden (view full) ---

1497 ret_val = e1000_validate_nvm_checksum_generic(hw);
1498
1499out:
1500 return ret_val;
1501}
1502
1503/**
1504 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1499 * @hw - pointer to the HW structure
1500 * @offset - The offset (in bytes) of the byte/word to read.
1501 * @size - Size of data to read, 1=byte 2=word
1502 * @data - The byte(s) to write to the NVM.
1505 * @hw: pointer to the HW structure
1506 * @offset: The offset (in bytes) of the byte/word to read.
1507 * @size: Size of data to read, 1=byte 2=word
1508 * @data: The byte(s) to write to the NVM.
1503 *
1504 * Writes one/two bytes to the NVM using the flash access registers.
1505 **/
1506static s32
1507e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1508 u8 size, u16 data)
1509{
1510 union ich8_hws_flash_status hsfsts;

--- 60 unchanged lines hidden (view full) ---

1571 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1572
1573out:
1574 return ret_val;
1575}
1576
1577/**
1578 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1509 *
1510 * Writes one/two bytes to the NVM using the flash access registers.
1511 **/
1512static s32
1513e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1514 u8 size, u16 data)
1515{
1516 union ich8_hws_flash_status hsfsts;

--- 60 unchanged lines hidden (view full) ---

1577 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1578
1579out:
1580 return ret_val;
1581}
1582
1583/**
1584 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1579 * @hw - pointer to the HW structure
1580 * @offset - The index of the byte to read.
1581 * @data - The byte to write to the NVM.
1585 * @hw: pointer to the HW structure
1586 * @offset: The index of the byte to read.
1587 * @data: The byte to write to the NVM.
1582 *
1583 * Writes a single byte to the NVM using the flash access registers.
1584 **/
1585STATIC s32
1586e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 data)
1587{
1588 u16 word = (u16)data;
1589
1590 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
1591
1592 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1593}
1594
1595/**
1596 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1588 *
1589 * Writes a single byte to the NVM using the flash access registers.
1590 **/
1591STATIC s32
1592e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 data)
1593{
1594 u16 word = (u16)data;
1595
1596 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
1597
1598 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1599}
1600
1601/**
1602 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1597 * @hw - pointer to the HW structure
1598 * @offset - The offset of the byte to write.
1599 * @byte - The byte to write to the NVM.
1603 * @hw: pointer to the HW structure
1604 * @offset: The offset of the byte to write.
1605 * @byte: The byte to write to the NVM.
1600 *
1601 * Writes a single byte to the NVM using the flash access registers.
1602 * Goes through a retry algorithm before giving up.
1603 **/
1604static s32
1605e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 byte)
1606{
1607 s32 ret_val;

--- 20 unchanged lines hidden (view full) ---

1628 }
1629
1630out:
1631 return ret_val;
1632}
1633
1634/**
1635 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1606 *
1607 * Writes a single byte to the NVM using the flash access registers.
1608 * Goes through a retry algorithm before giving up.
1609 **/
1610static s32
1611e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 byte)
1612{
1613 s32 ret_val;

--- 20 unchanged lines hidden (view full) ---

1634 }
1635
1636out:
1637 return ret_val;
1638}
1639
1640/**
1641 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1636 * @hw - pointer to the HW structure
1637 * @bank - 0 for first bank, 1 for second bank, etc.
1642 * @hw: pointer to the HW structure
1643 * @bank: 0 for first bank, 1 for second bank, etc.
1638 *
1639 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1640 * bank N is 4096 * N + flash_reg_addr.
1641 **/
1642STATIC s32
1643e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1644{
1645 struct e1000_nvm_info *nvm = &hw->nvm;

--- 99 unchanged lines hidden (view full) ---

1745 }
1746
1747out:
1748 return ret_val;
1749}
1750
1751/**
1752 * e1000_valid_led_default_ich8lan - Set the default LED settings
1644 *
1645 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1646 * bank N is 4096 * N + flash_reg_addr.
1647 **/
1648STATIC s32
1649e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1650{
1651 struct e1000_nvm_info *nvm = &hw->nvm;

--- 99 unchanged lines hidden (view full) ---

1751 }
1752
1753out:
1754 return ret_val;
1755}
1756
1757/**
1758 * e1000_valid_led_default_ich8lan - Set the default LED settings
1753 * @hw - pointer to the HW structure
1754 * @data - Pointer to the LED settings
1759 * @hw: pointer to the HW structure
1760 * @data: Pointer to the LED settings
1755 *
1756 * Reads the LED default settings from the NVM to data. If the NVM LED
1757 * settings is all 0's or F's, set the LED default to a valid LED default
1758 * setting.
1759 **/
1760STATIC s32
1761e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1762{

--- 12 unchanged lines hidden (view full) ---

1775 *data = ID_LED_DEFAULT_ICH8LAN;
1776
1777out:
1778 return ret_val;
1779}
1780
1781/**
1782 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1761 *
1762 * Reads the LED default settings from the NVM to data. If the NVM LED
1763 * settings is all 0's or F's, set the LED default to a valid LED default
1764 * setting.
1765 **/
1766STATIC s32
1767e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1768{

--- 12 unchanged lines hidden (view full) ---

1781 *data = ID_LED_DEFAULT_ICH8LAN;
1782
1783out:
1784 return ret_val;
1785}
1786
1787/**
1788 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1783 * @hw - pointer to the HW structure
1789 * @hw: pointer to the HW structure
1784 *
1785 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1786 * register, so the the bus width is hard coded.
1787 **/
1788STATIC s32
1789e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1790{
1791 struct e1000_bus_info *bus = &hw->bus;

--- 11 unchanged lines hidden (view full) ---

1803 if (bus->width == e1000_bus_width_unknown)
1804 bus->width = e1000_bus_width_pcie_x1;
1805
1806 return ret_val;
1807}
1808
1809/**
1810 * e1000_reset_hw_ich8lan - Reset the hardware
1790 *
1791 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1792 * register, so the the bus width is hard coded.
1793 **/
1794STATIC s32
1795e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1796{
1797 struct e1000_bus_info *bus = &hw->bus;

--- 11 unchanged lines hidden (view full) ---

1809 if (bus->width == e1000_bus_width_unknown)
1810 bus->width = e1000_bus_width_pcie_x1;
1811
1812 return ret_val;
1813}
1814
1815/**
1816 * e1000_reset_hw_ich8lan - Reset the hardware
1811 * @hw - pointer to the HW structure
1817 * @hw: pointer to the HW structure
1812 *
1813 * Does a full reset of the hardware which includes a reset of the PHY and
1814 * MAC.
1815 **/
1816STATIC s32
1817e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1818{
1819 u32 ctrl, icr, kab;

--- 41 unchanged lines hidden (view full) ---

1861 }
1862 ret_val = e1000_acquire_swflag_ich8lan(hw);
1863 DEBUGOUT("Issuing a global reset to ich8lan");
1864 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
1865 msec_delay(20);
1866
1867 ret_val = e1000_get_auto_rd_done_generic(hw);
1868 if (ret_val) {
1818 *
1819 * Does a full reset of the hardware which includes a reset of the PHY and
1820 * MAC.
1821 **/
1822STATIC s32
1823e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1824{
1825 u32 ctrl, icr, kab;

--- 41 unchanged lines hidden (view full) ---

1867 }
1868 ret_val = e1000_acquire_swflag_ich8lan(hw);
1869 DEBUGOUT("Issuing a global reset to ich8lan");
1870 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
1871 msec_delay(20);
1872
1873 ret_val = e1000_get_auto_rd_done_generic(hw);
1874 if (ret_val) {
1869 /*
1875 /*
1870 * When auto config read does not complete, do not
1871 * return with an error. This can happen in situations
1872 * where there is no eeprom and prevents getting link.
1873 */
1874 DEBUGOUT("Auto Read Done did not complete\n");
1875 }
1876
1877 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1878 icr = E1000_READ_REG(hw, E1000_ICR);
1879
1880 kab = E1000_READ_REG(hw, E1000_KABGTXD);
1881 kab |= E1000_KABGTXD_BGSQLBIAS;
1882 E1000_WRITE_REG(hw, E1000_KABGTXD, kab);
1883
1884 return ret_val;
1885}
1886
1887/**
1888 * e1000_init_hw_ich8lan - Initialize the hardware
1876 * When auto config read does not complete, do not
1877 * return with an error. This can happen in situations
1878 * where there is no eeprom and prevents getting link.
1879 */
1880 DEBUGOUT("Auto Read Done did not complete\n");
1881 }
1882
1883 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1884 icr = E1000_READ_REG(hw, E1000_ICR);
1885
1886 kab = E1000_READ_REG(hw, E1000_KABGTXD);
1887 kab |= E1000_KABGTXD_BGSQLBIAS;
1888 E1000_WRITE_REG(hw, E1000_KABGTXD, kab);
1889
1890 return ret_val;
1891}
1892
1893/**
1894 * e1000_init_hw_ich8lan - Initialize the hardware
1889 * @hw - pointer to the HW structure
1895 * @hw: pointer to the HW structure
1890 *
1891 * Prepares the hardware for transmit and receive by doing the following:
1892 * - initialize hardware bits
1893 * - initialize LED identification
1894 * - setup receive address registers
1895 * - setup flow control
1896 * - setup transmit discriptors
1897 * - clear statistics

--- 61 unchanged lines hidden (view full) ---

1959 */
1960 e1000_clear_hw_cntrs_ich8lan(hw);
1961
1962out:
1963 return ret_val;
1964}
1965/**
1966 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
1896 *
1897 * Prepares the hardware for transmit and receive by doing the following:
1898 * - initialize hardware bits
1899 * - initialize LED identification
1900 * - setup receive address registers
1901 * - setup flow control
1902 * - setup transmit discriptors
1903 * - clear statistics

--- 61 unchanged lines hidden (view full) ---

1965 */
1966 e1000_clear_hw_cntrs_ich8lan(hw);
1967
1968out:
1969 return ret_val;
1970}
1971/**
1972 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
1967 * @hw - pointer to the HW structure
1973 * @hw: pointer to the HW structure
1968 *
1969 * Sets/Clears required hardware bits necessary for correctly setting up the
1970 * hardware for transmit and receive.
1971 **/
1972static void
1973e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
1974{
1975 u32 reg;

--- 42 unchanged lines hidden (view full) ---

2018 }
2019
2020out:
2021 return;
2022}
2023
2024/**
2025 * e1000_setup_link_ich8lan - Setup flow control and link settings
1974 *
1975 * Sets/Clears required hardware bits necessary for correctly setting up the
1976 * hardware for transmit and receive.
1977 **/
1978static void
1979e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
1980{
1981 u32 reg;

--- 42 unchanged lines hidden (view full) ---

2024 }
2025
2026out:
2027 return;
2028}
2029
2030/**
2031 * e1000_setup_link_ich8lan - Setup flow control and link settings
2026 * @hw - pointer to the HW structure
2032 * @hw: pointer to the HW structure
2027 *
2028 * Determines which flow control settings to use, then configures flow
2029 * control. Calls the appropriate media-specific link configuration
2030 * function. Assuming the adapter has a valid link partner, a valid link
2031 * should be established. Assumes the hardware has previously been reset
2032 * and the transmitter and receiver are not enabled.
2033 **/
2034STATIC s32

--- 29 unchanged lines hidden (view full) ---

2064 ret_val = e1000_set_fc_watermarks_generic(hw);
2065
2066out:
2067 return ret_val;
2068}
2069
2070/**
2071 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2033 *
2034 * Determines which flow control settings to use, then configures flow
2035 * control. Calls the appropriate media-specific link configuration
2036 * function. Assuming the adapter has a valid link partner, a valid link
2037 * should be established. Assumes the hardware has previously been reset
2038 * and the transmitter and receiver are not enabled.
2039 **/
2040STATIC s32

--- 29 unchanged lines hidden (view full) ---

2070 ret_val = e1000_set_fc_watermarks_generic(hw);
2071
2072out:
2073 return ret_val;
2074}
2075
2076/**
2077 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2072 * @hw - pointer to the HW structure
2078 * @hw: pointer to the HW structure
2073 *
2074 * Configures the kumeran interface to the PHY to wait the appropriate time
2075 * when polling the PHY, then call the generic setup_copper_link to finish
2076 * configuring the copper link.
2077 **/
2078STATIC s32
2079e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2080{

--- 31 unchanged lines hidden (view full) ---

2112 ret_val = e1000_setup_copper_link_generic(hw);
2113
2114out:
2115 return ret_val;
2116}
2117
2118/**
2119 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2079 *
2080 * Configures the kumeran interface to the PHY to wait the appropriate time
2081 * when polling the PHY, then call the generic setup_copper_link to finish
2082 * configuring the copper link.
2083 **/
2084STATIC s32
2085e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2086{

--- 31 unchanged lines hidden (view full) ---

2118 ret_val = e1000_setup_copper_link_generic(hw);
2119
2120out:
2121 return ret_val;
2122}
2123
2124/**
2125 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2120 * @hw - pointer to the HW structure
2121 * @speed - pointer to store current link speed
2122 * @duplex - pointer to store the current link duplex
2126 * @hw: pointer to the HW structure
2127 * @speed: pointer to store current link speed
2128 * @duplex: pointer to store the current link duplex
2123 *
2124 * Calls the generic get_speed_and_duplex to retreive the current link
2125 * information and then calls the Kumeran lock loss workaround for links at
2126 * gigabit speeds.
2127 **/
2128STATIC s32
2129e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, u16 *duplex)
2130{

--- 12 unchanged lines hidden (view full) ---

2143 }
2144
2145out:
2146 return ret_val;
2147}
2148
2149/**
2150 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2129 *
2130 * Calls the generic get_speed_and_duplex to retreive the current link
2131 * information and then calls the Kumeran lock loss workaround for links at
2132 * gigabit speeds.
2133 **/
2134STATIC s32
2135e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, u16 *duplex)
2136{

--- 12 unchanged lines hidden (view full) ---

2149 }
2150
2151out:
2152 return ret_val;
2153}
2154
2155/**
2156 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2151 * @hw - pointer to the HW structure
2157 * @hw: pointer to the HW structure
2152 *
2153 * Work-around for 82566 Kumeran PCS lock loss:
2154 * On link status change (i.e. PCI reset, speed change) and link is up and
2155 * speed is gigabit-
2156 * 0) if workaround is optionally disabled do nothing
2157 * 1) wait 1ms for Kumeran link to come up
2158 * 2) check Kumeran Diagnostic register PCS lock loss bit
2159 * 3) if not set the link is locked (all is good), otherwise...

--- 66 unchanged lines hidden (view full) ---

2226 ret_val = -E1000_ERR_PHY;
2227
2228out:
2229 return ret_val;
2230}
2231
2232/**
2233 * e1000_set_kmrn_lock_loss_workaound_ich8lan - Set Kumeran workaround state
2158 *
2159 * Work-around for 82566 Kumeran PCS lock loss:
2160 * On link status change (i.e. PCI reset, speed change) and link is up and
2161 * speed is gigabit-
2162 * 0) if workaround is optionally disabled do nothing
2163 * 1) wait 1ms for Kumeran link to come up
2164 * 2) check Kumeran Diagnostic register PCS lock loss bit
2165 * 3) if not set the link is locked (all is good), otherwise...

--- 66 unchanged lines hidden (view full) ---

2232 ret_val = -E1000_ERR_PHY;
2233
2234out:
2235 return ret_val;
2236}
2237
2238/**
2239 * e1000_set_kmrn_lock_loss_workaound_ich8lan - Set Kumeran workaround state
2234 * @hw - pointer to the HW structure
2235 * @state - boolean value used to set the current Kumaran workaround state
2240 * @hw: pointer to the HW structure
2241 * @state: boolean value used to set the current Kumaran workaround state
2236 *
2237 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
2238 * /disabled - FALSE).
2239 **/
2240void
2241e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2242 boolean_t state)
2243{

--- 16 unchanged lines hidden (view full) ---

2260 dev_spec->kmrn_lock_loss_workaround_enabled = state;
2261
2262out:
2263 return;
2264}
2265
2266/**
2267 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2242 *
2243 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
2244 * /disabled - FALSE).
2245 **/
2246void
2247e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2248 boolean_t state)
2249{

--- 16 unchanged lines hidden (view full) ---

2266 dev_spec->kmrn_lock_loss_workaround_enabled = state;
2267
2268out:
2269 return;
2270}
2271
2272/**
2273 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2268 * @hw - pointer to the HW structure
2274 * @hw: pointer to the HW structure
2269 *
2270 * Workaround for 82566 power-down on D3 entry:
2271 * 1) disable gigabit link
2272 * 2) write VR power-down enable
2273 * 3) read it back
2274 * Continue if successful, else issue LCD reset and repeat
2275 **/
2276void

--- 25 unchanged lines hidden (view full) ---

2302 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &data);
2303 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2304 e1000_write_phy_reg(hw,
2305 IGP3_VR_CTRL,
2306 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2307
2308 /* Read it back and test */
2309 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &data);
2275 *
2276 * Workaround for 82566 power-down on D3 entry:
2277 * 1) disable gigabit link
2278 * 2) write VR power-down enable
2279 * 3) read it back
2280 * Continue if successful, else issue LCD reset and repeat
2281 **/
2282void

--- 25 unchanged lines hidden (view full) ---

2308 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &data);
2309 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2310 e1000_write_phy_reg(hw,
2311 IGP3_VR_CTRL,
2312 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2313
2314 /* Read it back and test */
2315 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &data);
2310 if ((data & IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2316 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2317 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2311 break;
2312
2313 /* Issue PHY reset and repeat at most one more time */
2314 reg = E1000_READ_REG(hw, E1000_CTRL);
2315 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
2316 retry++;
2317 } while (retry);
2318
2319out:
2320 return;
2321}
2322
2323/**
2324 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2318 break;
2319
2320 /* Issue PHY reset and repeat at most one more time */
2321 reg = E1000_READ_REG(hw, E1000_CTRL);
2322 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
2323 retry++;
2324 } while (retry);
2325
2326out:
2327 return;
2328}
2329
2330/**
2331 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2325 * @hw - pointer to the HW structure
2332 * @hw: pointer to the HW structure
2326 *
2327 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2328 * LPLU, Giga disable, MDIC PHY reset):
2329 * 1) Set Kumeran Near-end loopback
2330 * 2) Clear Kumeran Near-end loopback
2331 * Should only be called for ICH8[m] devices with IGP_3 Phy.
2332 **/
2333void

--- 21 unchanged lines hidden (view full) ---

2355 ret_val = e1000_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2356 reg_data);
2357out:
2358 return;
2359}
2360
2361/**
2362 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2333 *
2334 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2335 * LPLU, Giga disable, MDIC PHY reset):
2336 * 1) Set Kumeran Near-end loopback
2337 * 2) Clear Kumeran Near-end loopback
2338 * Should only be called for ICH8[m] devices with IGP_3 Phy.
2339 **/
2340void

--- 21 unchanged lines hidden (view full) ---

2362 ret_val = e1000_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2363 reg_data);
2364out:
2365 return;
2366}
2367
2368/**
2369 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2363 * @hw - pointer to the HW structure
2370 * @hw: pointer to the HW structure
2364 *
2365 * Return the LED back to the default configuration.
2366 **/
2367STATIC s32
2368e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2369{
2370 s32 ret_val = E1000_SUCCESS;
2371

--- 6 unchanged lines hidden (view full) ---

2378 else
2379 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
2380
2381 return ret_val;
2382}
2383
2384/**
2385 * e1000_led_on_ich8lan - Turn LED's on
2371 *
2372 * Return the LED back to the default configuration.
2373 **/
2374STATIC s32
2375e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2376{
2377 s32 ret_val = E1000_SUCCESS;
2378

--- 6 unchanged lines hidden (view full) ---

2385 else
2386 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
2387
2388 return ret_val;
2389}
2390
2391/**
2392 * e1000_led_on_ich8lan - Turn LED's on
2386 * @hw - pointer to the HW structure
2393 * @hw: pointer to the HW structure
2387 *
2388 * Turn on the LED's.
2389 **/
2390STATIC s32
2391e1000_led_on_ich8lan(struct e1000_hw *hw)
2392{
2393 s32 ret_val = E1000_SUCCESS;
2394

--- 6 unchanged lines hidden (view full) ---

2401 else
2402 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
2403
2404 return ret_val;
2405}
2406
2407/**
2408 * e1000_led_off_ich8lan - Turn LED's off
2394 *
2395 * Turn on the LED's.
2396 **/
2397STATIC s32
2398e1000_led_on_ich8lan(struct e1000_hw *hw)
2399{
2400 s32 ret_val = E1000_SUCCESS;
2401

--- 6 unchanged lines hidden (view full) ---

2408 else
2409 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
2410
2411 return ret_val;
2412}
2413
2414/**
2415 * e1000_led_off_ich8lan - Turn LED's off
2409 * @hw - pointer to the HW structure
2416 * @hw: pointer to the HW structure
2410 *
2411 * Turn off the LED's.
2412 **/
2413STATIC s32
2414e1000_led_off_ich8lan(struct e1000_hw *hw)
2415{
2416 s32 ret_val = E1000_SUCCESS;
2417

--- 6 unchanged lines hidden (view full) ---

2424 else
2425 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2426
2427 return ret_val;
2428}
2429
2430/**
2431 * e1000_get_cfg_done_ich8lan - Read config done bit
2417 *
2418 * Turn off the LED's.
2419 **/
2420STATIC s32
2421e1000_led_off_ich8lan(struct e1000_hw *hw)
2422{
2423 s32 ret_val = E1000_SUCCESS;
2424

--- 6 unchanged lines hidden (view full) ---

2431 else
2432 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2433
2434 return ret_val;
2435}
2436
2437/**
2438 * e1000_get_cfg_done_ich8lan - Read config done bit
2432 * @hw - pointer to the HW structure
2439 * @hw: pointer to the HW structure
2433 *
2434 * Read the management control register for the config done bit for
2435 * completion status. NOTE: silicon which is EEPROM-less will fail trying
2436 * to read the config done bit, so an error is *ONLY* logged and returns
2437 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
2438 * would not be able to be reset or change link.
2439 **/
2440STATIC s32

--- 7 unchanged lines hidden (view full) ---

2448 e1000_phy_init_script_igp3(hw);
2449 }
2450
2451 return E1000_SUCCESS;
2452}
2453
2454/**
2455 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2440 *
2441 * Read the management control register for the config done bit for
2442 * completion status. NOTE: silicon which is EEPROM-less will fail trying
2443 * to read the config done bit, so an error is *ONLY* logged and returns
2444 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
2445 * would not be able to be reset or change link.
2446 **/
2447STATIC s32

--- 7 unchanged lines hidden (view full) ---

2455 e1000_phy_init_script_igp3(hw);
2456 }
2457
2458 return E1000_SUCCESS;
2459}
2460
2461/**
2462 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2456 * @hw - pointer to the HW structure
2463 * @hw: pointer to the HW structure
2457 *
2458 * Clears hardware counters specific to the silicon family and calls
2459 * clear_hw_cntrs_generic to clear all general purpose counters.
2460 **/
2461STATIC void
2462e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2463{
2464 volatile u32 temp;

--- 20 unchanged lines hidden --- 		2464 *
2465 * Clears hardware counters specific to the silicon family and calls
2466 * clear_hw_cntrs_generic to clear all general purpose counters.
2467 **/
2468STATIC void
2469e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2470{
2471 volatile u32 temp;

--- 20 unchanged lines hidden ---