1/******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
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7 modification, are permitted provided that the following conditions are met:
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9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.c 287990 2015-09-19 18:22:59Z sbruno $*/
34
35/* 82562G 10/100 Network Connection
36 * 82562G-2 10/100 Network Connection
37 * 82562GT 10/100 Network Connection
38 * 82562GT-2 10/100 Network Connection
39 * 82562V 10/100 Network Connection
40 * 82562V-2 10/100 Network Connection
41 * 82566DC-2 Gigabit Network Connection
42 * 82566DC Gigabit Network Connection
43 * 82566DM-2 Gigabit Network Connection
44 * 82566DM Gigabit Network Connection
45 * 82566MC Gigabit Network Connection
46 * 82566MM Gigabit Network Connection
47 * 82567LM Gigabit Network Connection
48 * 82567LF Gigabit Network Connection
49 * 82567V Gigabit Network Connection
50 * 82567LM-2 Gigabit Network Connection
51 * 82567LF-2 Gigabit Network Connection
52 * 82567V-2 Gigabit Network Connection
53 * 82567LF-3 Gigabit Network Connection
54 * 82567LM-3 Gigabit Network Connection
55 * 82567LM-4 Gigabit Network Connection
56 * 82577LM Gigabit Network Connection
57 * 82577LC Gigabit Network Connection
58 * 82578DM Gigabit Network Connection
59 * 82578DC Gigabit Network Connection
60 * 82579LM Gigabit Network Connection
61 * 82579V Gigabit Network Connection
62 * Ethernet Connection I217-LM
63 * Ethernet Connection I217-V
64 * Ethernet Connection I218-V
65 * Ethernet Connection I218-LM
66 * Ethernet Connection (2) I218-LM
67 * Ethernet Connection (2) I218-V
68 * Ethernet Connection (3) I218-LM
69 * Ethernet Connection (3) I218-V
70 */
71
72#include "e1000_api.h"
73
74static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
75static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
76static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
77static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
78static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
79static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
80static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
81static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
82static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
83static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
84 u8 *mc_addr_list,
85 u32 mc_addr_count);
86static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
87static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
88static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
89static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
90 bool active);
91static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
92 bool active);
93static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
94 u16 words, u16 *data);
95static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
96 u16 words, u16 *data);
97static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
98static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
99static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
100 u16 *data);
101static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
102static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
103static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
104static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
105static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
106static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
107static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
108static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
109 u16 *speed, u16 *duplex);
110static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
111static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
112static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
113static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
114static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
115static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
116static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
117static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
118static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
119static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
120static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
121static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
122static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
123 u32 offset, u8 *data);
124static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
125 u8 size, u16 *data);
126static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
127 u32 offset, u16 *data);
128static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
129 u32 offset, u8 byte);
130static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
131static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
132static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
133static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
134static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
135static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
136static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
137
138/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
139/* Offset 04h HSFSTS */
140union ich8_hws_flash_status {
141 struct ich8_hsfsts {
142 u16 flcdone:1; /* bit 0 Flash Cycle Done */
143 u16 flcerr:1; /* bit 1 Flash Cycle Error */
144 u16 dael:1; /* bit 2 Direct Access error Log */
145 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
146 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
147 u16 reserved1:2; /* bit 13:6 Reserved */
148 u16 reserved2:6; /* bit 13:6 Reserved */
149 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
150 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
151 } hsf_status;
152 u16 regval;
153};
154
155/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
156/* Offset 06h FLCTL */
157union ich8_hws_flash_ctrl {
158 struct ich8_hsflctl {
159 u16 flcgo:1; /* 0 Flash Cycle Go */
160 u16 flcycle:2; /* 2:1 Flash Cycle */
161 u16 reserved:5; /* 7:3 Reserved */
162 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
163 u16 flockdn:6; /* 15:10 Reserved */
164 } hsf_ctrl;
165 u16 regval;
166};
167
168/* ICH Flash Region Access Permissions */
169union ich8_hws_flash_regacc {
170 struct ich8_flracc {
171 u32 grra:8; /* 0:7 GbE region Read Access */
172 u32 grwa:8; /* 8:15 GbE region Write Access */
173 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
174 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
175 } hsf_flregacc;
176 u16 regval;
177};
178
179/**
180 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
181 * @hw: pointer to the HW structure
182 *
183 * Test access to the PHY registers by reading the PHY ID registers. If
184 * the PHY ID is already known (e.g. resume path) compare it with known ID,
185 * otherwise assume the read PHY ID is correct if it is valid.
186 *
187 * Assumes the sw/fw/hw semaphore is already acquired.
188 **/
189static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
190{
191 u16 phy_reg = 0;
192 u32 phy_id = 0;
193 s32 ret_val = 0;
194 u16 retry_count;
195 u32 mac_reg = 0;
196
197 for (retry_count = 0; retry_count < 2; retry_count++) {
198 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
199 if (ret_val || (phy_reg == 0xFFFF))
200 continue;
201 phy_id = (u32)(phy_reg << 16);
202
203 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
204 if (ret_val || (phy_reg == 0xFFFF)) {
205 phy_id = 0;
206 continue;
207 }
208 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
209 break;
210 }
211
212 if (hw->phy.id) {
213 if (hw->phy.id == phy_id)
214 goto out;
215 } else if (phy_id) {
216 hw->phy.id = phy_id;
217 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
218 goto out;
219 }
220
221 /* In case the PHY needs to be in mdio slow mode,
222 * set slow mode and try to get the PHY id again.
223 */
224 if (hw->mac.type < e1000_pch_lpt) {
225 hw->phy.ops.release(hw);
226 ret_val = e1000_set_mdio_slow_mode_hv(hw);
227 if (!ret_val)
228 ret_val = e1000_get_phy_id(hw);
229 hw->phy.ops.acquire(hw);
230 }
231
232 if (ret_val)
233 return FALSE;
234out:
235 if (hw->mac.type == e1000_pch_lpt) {
236 /* Unforce SMBus mode in PHY */
237 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
238 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
239 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
240
241 /* Unforce SMBus mode in MAC */
242 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
243 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
244 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
245 }
246
247 return TRUE;
248}
249
250/**
251 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
252 * @hw: pointer to the HW structure
253 *
254 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
255 * used to reset the PHY to a quiescent state when necessary.
256 **/
257static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
258{
259 u32 mac_reg;
260
261 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
262
263 /* Set Phy Config Counter to 50msec */
264 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
265 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
266 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
267 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
268
269 /* Toggle LANPHYPC Value bit */
270 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
271 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
272 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
273 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
274 E1000_WRITE_FLUSH(hw);
275 usec_delay(10);
276 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
277 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
278 E1000_WRITE_FLUSH(hw);
279
280 if (hw->mac.type < e1000_pch_lpt) {
281 msec_delay(50);
282 } else {
283 u16 count = 20;
284
285 do {
286 msec_delay(5);
287 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
288 E1000_CTRL_EXT_LPCD) && count--);
289
290 msec_delay(30);
291 }
292}
293
294/**
295 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
296 * @hw: pointer to the HW structure
297 *
298 * Workarounds/flow necessary for PHY initialization during driver load
299 * and resume paths.
300 **/
301static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
302{
303 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
304 s32 ret_val;
305
306 DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
307
308 /* Gate automatic PHY configuration by hardware on managed and
309 * non-managed 82579 and newer adapters.
310 */
311 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
312
313 /* It is not possible to be certain of the current state of ULP
314 * so forcibly disable it.
315 */
316 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
317 e1000_disable_ulp_lpt_lp(hw, TRUE);
318
319 ret_val = hw->phy.ops.acquire(hw);
320 if (ret_val) {
321 DEBUGOUT("Failed to initialize PHY flow\n");
322 goto out;
323 }
324
325 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
326 * inaccessible and resetting the PHY is not blocked, toggle the
327 * LANPHYPC Value bit to force the interconnect to PCIe mode.
328 */
329 switch (hw->mac.type) {
330 case e1000_pch_lpt:
331 if (e1000_phy_is_accessible_pchlan(hw))
332 break;
333
334 /* Before toggling LANPHYPC, see if PHY is accessible by
335 * forcing MAC to SMBus mode first.
336 */
337 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
338 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
339 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
340
341 /* Wait 50 milliseconds for MAC to finish any retries
342 * that it might be trying to perform from previous
343 * attempts to acknowledge any phy read requests.
344 */
345 msec_delay(50);
346
347 /* fall-through */
348 case e1000_pch2lan:
349 if (e1000_phy_is_accessible_pchlan(hw))
350 break;
351
352 /* fall-through */
353 case e1000_pchlan:
354 if ((hw->mac.type == e1000_pchlan) &&
355 (fwsm & E1000_ICH_FWSM_FW_VALID))
356 break;
357
358 if (hw->phy.ops.check_reset_block(hw)) {
359 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
360 ret_val = -E1000_ERR_PHY;
361 break;
362 }
363
364 /* Toggle LANPHYPC Value bit */
365 e1000_toggle_lanphypc_pch_lpt(hw);
366 if (hw->mac.type >= e1000_pch_lpt) {
367 if (e1000_phy_is_accessible_pchlan(hw))
368 break;
369
370 /* Toggling LANPHYPC brings the PHY out of SMBus mode
371 * so ensure that the MAC is also out of SMBus mode
372 */
373 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
374 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
375 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
376
377 if (e1000_phy_is_accessible_pchlan(hw))
378 break;
379
380 ret_val = -E1000_ERR_PHY;
381 }
382 break;
383 default:
384 break;
385 }
386
387 hw->phy.ops.release(hw);
388 if (!ret_val) {
389
390 /* Check to see if able to reset PHY. Print error if not */
391 if (hw->phy.ops.check_reset_block(hw)) {
392 ERROR_REPORT("Reset blocked by ME\n");
393 goto out;
394 }
395
396 /* Reset the PHY before any access to it. Doing so, ensures
397 * that the PHY is in a known good state before we read/write
398 * PHY registers. The generic reset is sufficient here,
399 * because we haven't determined the PHY type yet.
400 */
401 ret_val = e1000_phy_hw_reset_generic(hw);
402 if (ret_val)
403 goto out;
404
405 /* On a successful reset, possibly need to wait for the PHY
406 * to quiesce to an accessible state before returning control
407 * to the calling function. If the PHY does not quiesce, then
408 * return E1000E_BLK_PHY_RESET, as this is the condition that
409 * the PHY is in.
410 */
411 ret_val = hw->phy.ops.check_reset_block(hw);
412 if (ret_val)
413 ERROR_REPORT("ME blocked access to PHY after reset\n");
414 }
415
416out:
417 /* Ungate automatic PHY configuration on non-managed 82579 */
418 if ((hw->mac.type == e1000_pch2lan) &&
419 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
420 msec_delay(10);
421 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
422 }
423
424 return ret_val;
425}
426
427/**
428 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
429 * @hw: pointer to the HW structure
430 *
431 * Initialize family-specific PHY parameters and function pointers.
432 **/
433static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
434{
435 struct e1000_phy_info *phy = &hw->phy;
436 s32 ret_val;
437
438 DEBUGFUNC("e1000_init_phy_params_pchlan");
439
440 phy->addr = 1;
441 phy->reset_delay_us = 100;
442
443 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
444 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
445 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
446 phy->ops.set_page = e1000_set_page_igp;
447 phy->ops.read_reg = e1000_read_phy_reg_hv;
448 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
449 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
450 phy->ops.release = e1000_release_swflag_ich8lan;
451 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
452 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
453 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
454 phy->ops.write_reg = e1000_write_phy_reg_hv;
455 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
456 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
457 phy->ops.power_up = e1000_power_up_phy_copper;
458 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
459 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
460
461 phy->id = e1000_phy_unknown;
462
463 ret_val = e1000_init_phy_workarounds_pchlan(hw);
464 if (ret_val)
465 return ret_val;
466
467 if (phy->id == e1000_phy_unknown)
468 switch (hw->mac.type) {
469 default:
470 ret_val = e1000_get_phy_id(hw);
471 if (ret_val)
472 return ret_val;
473 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
474 break;
475 /* fall-through */
476 case e1000_pch2lan:
477 case e1000_pch_lpt:
478 /* In case the PHY needs to be in mdio slow mode,
479 * set slow mode and try to get the PHY id again.
480 */
481 ret_val = e1000_set_mdio_slow_mode_hv(hw);
482 if (ret_val)
483 return ret_val;
484 ret_val = e1000_get_phy_id(hw);
485 if (ret_val)
486 return ret_val;
487 break;
488 }
489 phy->type = e1000_get_phy_type_from_id(phy->id);
490
491 switch (phy->type) {
492 case e1000_phy_82577:
493 case e1000_phy_82579:
494 case e1000_phy_i217:
495 phy->ops.check_polarity = e1000_check_polarity_82577;
496 phy->ops.force_speed_duplex =
497 e1000_phy_force_speed_duplex_82577;
498 phy->ops.get_cable_length = e1000_get_cable_length_82577;
499 phy->ops.get_info = e1000_get_phy_info_82577;
500 phy->ops.commit = e1000_phy_sw_reset_generic;
501 break;
502 case e1000_phy_82578:
503 phy->ops.check_polarity = e1000_check_polarity_m88;
504 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
505 phy->ops.get_cable_length = e1000_get_cable_length_m88;
506 phy->ops.get_info = e1000_get_phy_info_m88;
507 break;
508 default:
509 ret_val = -E1000_ERR_PHY;
510 break;
511 }
512
513 return ret_val;
514}
515
516/**
517 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
518 * @hw: pointer to the HW structure
519 *
520 * Initialize family-specific PHY parameters and function pointers.
521 **/
522static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
523{
524 struct e1000_phy_info *phy = &hw->phy;
525 s32 ret_val;
526 u16 i = 0;
527
528 DEBUGFUNC("e1000_init_phy_params_ich8lan");
529
530 phy->addr = 1;
531 phy->reset_delay_us = 100;
532
533 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
534 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
535 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
536 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
537 phy->ops.read_reg = e1000_read_phy_reg_igp;
538 phy->ops.release = e1000_release_swflag_ich8lan;
539 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
540 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
541 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
542 phy->ops.write_reg = e1000_write_phy_reg_igp;
543 phy->ops.power_up = e1000_power_up_phy_copper;
544 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
545
546 /* We may need to do this twice - once for IGP and if that fails,
547 * we'll set BM func pointers and try again
548 */
549 ret_val = e1000_determine_phy_address(hw);
550 if (ret_val) {
551 phy->ops.write_reg = e1000_write_phy_reg_bm;
552 phy->ops.read_reg = e1000_read_phy_reg_bm;
553 ret_val = e1000_determine_phy_address(hw);
554 if (ret_val) {
555 DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
556 return ret_val;
557 }
558 }
559
560 phy->id = 0;
561 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
562 (i++ < 100)) {
563 msec_delay(1);
564 ret_val = e1000_get_phy_id(hw);
565 if (ret_val)
566 return ret_val;
567 }
568
569 /* Verify phy id */
570 switch (phy->id) {
571 case IGP03E1000_E_PHY_ID:
572 phy->type = e1000_phy_igp_3;
573 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
574 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
575 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
576 phy->ops.get_info = e1000_get_phy_info_igp;
577 phy->ops.check_polarity = e1000_check_polarity_igp;
578 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
579 break;
580 case IFE_E_PHY_ID:
581 case IFE_PLUS_E_PHY_ID:
582 case IFE_C_E_PHY_ID:
583 phy->type = e1000_phy_ife;
584 phy->autoneg_mask = E1000_ALL_NOT_GIG;
585 phy->ops.get_info = e1000_get_phy_info_ife;
586 phy->ops.check_polarity = e1000_check_polarity_ife;
587 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
588 break;
589 case BME1000_E_PHY_ID:
590 phy->type = e1000_phy_bm;
591 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
592 phy->ops.read_reg = e1000_read_phy_reg_bm;
593 phy->ops.write_reg = e1000_write_phy_reg_bm;
594 phy->ops.commit = e1000_phy_sw_reset_generic;
595 phy->ops.get_info = e1000_get_phy_info_m88;
596 phy->ops.check_polarity = e1000_check_polarity_m88;
597 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
598 break;
599 default:
600 return -E1000_ERR_PHY;
601 break;
602 }
603
604 return E1000_SUCCESS;
605}
606
607/**
608 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
609 * @hw: pointer to the HW structure
610 *
611 * Initialize family-specific NVM parameters and function
612 * pointers.
613 **/
614static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
615{
616 struct e1000_nvm_info *nvm = &hw->nvm;
617 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
618 u32 gfpreg, sector_base_addr, sector_end_addr;
619 u16 i;
620
621 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
622
623 /* Can't read flash registers if the register set isn't mapped. */
624 nvm->type = e1000_nvm_flash_sw;
625 if (!hw->flash_address) {
626 DEBUGOUT("ERROR: Flash registers not mapped\n");
627 return -E1000_ERR_CONFIG;
628 }
629
630 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
631
632 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
633 * Add 1 to sector_end_addr since this sector is included in
634 * the overall size.
635 */
636 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
637 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
638
639 /* flash_base_addr is byte-aligned */
640 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
641
642 /* find total size of the NVM, then cut in half since the total
643 * size represents two separate NVM banks.
644 */
645 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
646 << FLASH_SECTOR_ADDR_SHIFT);
647 nvm->flash_bank_size /= 2;
648 /* Adjust to word count */
649 nvm->flash_bank_size /= sizeof(u16);
650
651 nvm->word_size = E1000_SHADOW_RAM_WORDS;
652
653 /* Clear shadow ram */
654 for (i = 0; i < nvm->word_size; i++) {
655 dev_spec->shadow_ram[i].modified = FALSE;
656 dev_spec->shadow_ram[i].value = 0xFFFF;
657 }
658
659 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
660 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
661
662 /* Function Pointers */
663 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
664 nvm->ops.release = e1000_release_nvm_ich8lan;
665 nvm->ops.read = e1000_read_nvm_ich8lan;
666 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
667 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
668 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
669 nvm->ops.write = e1000_write_nvm_ich8lan;
670
671 return E1000_SUCCESS;
672}
673
674/**
675 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
676 * @hw: pointer to the HW structure
677 *
678 * Initialize family-specific MAC parameters and function
679 * pointers.
680 **/
681static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
682{
683 struct e1000_mac_info *mac = &hw->mac;
684#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
685 u16 pci_cfg;
686#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
687
688 DEBUGFUNC("e1000_init_mac_params_ich8lan");
689
690 /* Set media type function pointer */
691 hw->phy.media_type = e1000_media_type_copper;
692
693 /* Set mta register count */
694 mac->mta_reg_count = 32;
695 /* Set rar entry count */
696 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
697 if (mac->type == e1000_ich8lan)
698 mac->rar_entry_count--;
699 /* Set if part includes ASF firmware */
700 mac->asf_firmware_present = TRUE;
701 /* FWSM register */
702 mac->has_fwsm = TRUE;
703 /* ARC subsystem not supported */
704 mac->arc_subsystem_valid = FALSE;
705 /* Adaptive IFS supported */
706 mac->adaptive_ifs = TRUE;
707
708 /* Function pointers */
709
710 /* bus type/speed/width */
711 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
712 /* function id */
713 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
714 /* reset */
715 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
716 /* hw initialization */
717 mac->ops.init_hw = e1000_init_hw_ich8lan;
718 /* link setup */
719 mac->ops.setup_link = e1000_setup_link_ich8lan;
720 /* physical interface setup */
721 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
722 /* check for link */
723 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
724 /* link info */
725 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
726 /* multicast address update */
727 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
728 /* clear hardware counters */
729 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
730
731 /* LED and other operations */
732 switch (mac->type) {
733 case e1000_ich8lan:
734 case e1000_ich9lan:
735 case e1000_ich10lan:
736 /* check management mode */
737 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
738 /* ID LED init */
739 mac->ops.id_led_init = e1000_id_led_init_generic;
740 /* blink LED */
741 mac->ops.blink_led = e1000_blink_led_generic;
742 /* setup LED */
743 mac->ops.setup_led = e1000_setup_led_generic;
744 /* cleanup LED */
745 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
746 /* turn on/off LED */
747 mac->ops.led_on = e1000_led_on_ich8lan;
748 mac->ops.led_off = e1000_led_off_ich8lan;
749 break;
750 case e1000_pch2lan:
751 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
752 mac->ops.rar_set = e1000_rar_set_pch2lan;
753 /* fall-through */
754 case e1000_pch_lpt:
755 /* multicast address update for pch2 */
756 mac->ops.update_mc_addr_list =
757 e1000_update_mc_addr_list_pch2lan;
758 case e1000_pchlan:
759#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
760 /* save PCH revision_id */
761 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
762 hw->revision_id = (u8)(pci_cfg &= 0x000F);
763#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
764 /* check management mode */
765 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
766 /* ID LED init */
767 mac->ops.id_led_init = e1000_id_led_init_pchlan;
768 /* setup LED */
769 mac->ops.setup_led = e1000_setup_led_pchlan;
770 /* cleanup LED */
771 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
772 /* turn on/off LED */
773 mac->ops.led_on = e1000_led_on_pchlan;
774 mac->ops.led_off = e1000_led_off_pchlan;
775 break;
776 default:
777 break;
778 }
779
780 if (mac->type == e1000_pch_lpt) {
781 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
782 mac->ops.rar_set = e1000_rar_set_pch_lpt;
783 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
784 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
785 }
786
787 /* Enable PCS Lock-loss workaround for ICH8 */
788 if (mac->type == e1000_ich8lan)
789 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
790
791 return E1000_SUCCESS;
792}
793
794/**
795 * __e1000_access_emi_reg_locked - Read/write EMI register
796 * @hw: pointer to the HW structure
797 * @addr: EMI address to program
798 * @data: pointer to value to read/write from/to the EMI address
799 * @read: boolean flag to indicate read or write
800 *
801 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
802 **/
803static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
804 u16 *data, bool read)
805{
806 s32 ret_val;
807
808 DEBUGFUNC("__e1000_access_emi_reg_locked");
809
810 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
811 if (ret_val)
812 return ret_val;
813
814 if (read)
815 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
816 data);
817 else
818 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
819 *data);
820
821 return ret_val;
822}
823
824/**
825 * e1000_read_emi_reg_locked - Read Extended Management Interface register
826 * @hw: pointer to the HW structure
827 * @addr: EMI address to program
828 * @data: value to be read from the EMI address
829 *
830 * Assumes the SW/FW/HW Semaphore is already acquired.
831 **/
832s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
833{
834 DEBUGFUNC("e1000_read_emi_reg_locked");
835
836 return __e1000_access_emi_reg_locked(hw, addr, data, TRUE);
837}
838
839/**
840 * e1000_write_emi_reg_locked - Write Extended Management Interface register
841 * @hw: pointer to the HW structure
842 * @addr: EMI address to program
843 * @data: value to be written to the EMI address
844 *
845 * Assumes the SW/FW/HW Semaphore is already acquired.
846 **/
847s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
848{
849 DEBUGFUNC("e1000_read_emi_reg_locked");
850
851 return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE);
852}
853
854/**
855 * e1000_set_eee_pchlan - Enable/disable EEE support
856 * @hw: pointer to the HW structure
857 *
858 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
859 * the link and the EEE capabilities of the link partner. The LPI Control
860 * register bits will remain set only if/when link is up.
861 *
862 * EEE LPI must not be asserted earlier than one second after link is up.
863 * On 82579, EEE LPI should not be enabled until such time otherwise there
864 * can be link issues with some switches. Other devices can have EEE LPI
865 * enabled immediately upon link up since they have a timer in hardware which
866 * prevents LPI from being asserted too early.
867 **/
868s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
869{
870 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
871 s32 ret_val;
872 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
873
874 DEBUGFUNC("e1000_set_eee_pchlan");
875
876 switch (hw->phy.type) {
877 case e1000_phy_82579:
878 lpa = I82579_EEE_LP_ABILITY;
879 pcs_status = I82579_EEE_PCS_STATUS;
880 adv_addr = I82579_EEE_ADVERTISEMENT;
881 break;
882 case e1000_phy_i217:
883 lpa = I217_EEE_LP_ABILITY;
884 pcs_status = I217_EEE_PCS_STATUS;
885 adv_addr = I217_EEE_ADVERTISEMENT;
886 break;
887 default:
888 return E1000_SUCCESS;
889 }
890
891 ret_val = hw->phy.ops.acquire(hw);
892 if (ret_val)
893 return ret_val;
894
895 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
896 if (ret_val)
897 goto release;
898
899 /* Clear bits that enable EEE in various speeds */
900 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
901
902 /* Enable EEE if not disabled by user */
903 if (!dev_spec->eee_disable) {
904 /* Save off link partner's EEE ability */
905 ret_val = e1000_read_emi_reg_locked(hw, lpa,
906 &dev_spec->eee_lp_ability);
907 if (ret_val)
908 goto release;
909
910 /* Read EEE advertisement */
911 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
912 if (ret_val)
913 goto release;
914
915 /* Enable EEE only for speeds in which the link partner is
916 * EEE capable and for which we advertise EEE.
917 */
918 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
919 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
920
921 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
922 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
923 if (data & NWAY_LPAR_100TX_FD_CAPS)
924 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
925 else
926 /* EEE is not supported in 100Half, so ignore
927 * partner's EEE in 100 ability if full-duplex
928 * is not advertised.
929 */
930 dev_spec->eee_lp_ability &=
931 ~I82579_EEE_100_SUPPORTED;
932 }
933 }
934
935 if (hw->phy.type == e1000_phy_82579) {
936 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
937 &data);
938 if (ret_val)
939 goto release;
940
941 data &= ~I82579_LPI_100_PLL_SHUT;
942 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
943 data);
944 }
945
946 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
947 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
948 if (ret_val)
949 goto release;
950
951 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
952release:
953 hw->phy.ops.release(hw);
954
955 return ret_val;
956}
957
958/**
959 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
960 * @hw: pointer to the HW structure
961 * @link: link up bool flag
962 *
963 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
964 * preventing further DMA write requests. Workaround the issue by disabling
965 * the de-assertion of the clock request when in 1Gpbs mode.
966 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
967 * speeds in order to avoid Tx hangs.
968 **/
969static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
970{
971 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
972 u32 status = E1000_READ_REG(hw, E1000_STATUS);
973 s32 ret_val = E1000_SUCCESS;
974 u16 reg;
975
976 if (link && (status & E1000_STATUS_SPEED_1000)) {
977 ret_val = hw->phy.ops.acquire(hw);
978 if (ret_val)
979 return ret_val;
980
981 ret_val =
982 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
983 &reg);
984 if (ret_val)
985 goto release;
986
987 ret_val =
988 e1000_write_kmrn_reg_locked(hw,
989 E1000_KMRNCTRLSTA_K1_CONFIG,
990 reg &
991 ~E1000_KMRNCTRLSTA_K1_ENABLE);
992 if (ret_val)
993 goto release;
994
995 usec_delay(10);
996
997 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
998 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
999
1000 ret_val =
1001 e1000_write_kmrn_reg_locked(hw,
1002 E1000_KMRNCTRLSTA_K1_CONFIG,
1003 reg);
1004release:
1005 hw->phy.ops.release(hw);
1006 } else {
1007 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1008 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1009
1010 if (!link || ((status & E1000_STATUS_SPEED_100) &&
1011 (status & E1000_STATUS_FD)))
1012 goto update_fextnvm6;
1013
1014 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1015 if (ret_val)
1016 return ret_val;
1017
1018 /* Clear link status transmit timeout */
1019 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1020
1021 if (status & E1000_STATUS_SPEED_100) {
1022 /* Set inband Tx timeout to 5x10us for 100Half */
1023 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1024
1025 /* Do not extend the K1 entry latency for 100Half */
1026 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1027 } else {
1028 /* Set inband Tx timeout to 50x10us for 10Full/Half */
1029 reg |= 50 <<
1030 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1031
1032 /* Extend the K1 entry latency for 10 Mbps */
1033 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1034 }
1035
1036 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1037 if (ret_val)
1038 return ret_val;
1039
1040update_fextnvm6:
1041 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1042 }
1043
1044 return ret_val;
1045}
1046
1047static u64 e1000_ltr2ns(u16 ltr)
1048{
1049 u32 value, scale;
1050
1051 /* Determine the latency in nsec based on the LTR value & scale */
1052 value = ltr & E1000_LTRV_VALUE_MASK;
1053 scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT;
1054
1055 return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR));
1056}
1057
1058/**
1059 * e1000_platform_pm_pch_lpt - Set platform power management values
1060 * @hw: pointer to the HW structure
1061 * @link: bool indicating link status
1062 *
1063 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1064 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1065 * when link is up (which must not exceed the maximum latency supported
1066 * by the platform), otherwise specify there is no LTR requirement.
1067 * Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop
1068 * latencies in the LTR Extended Capability Structure in the PCIe Extended
1069 * Capability register set, on this device LTR is set by writing the
1070 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1071 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1072 * message to the PMC.
1073 *
1074 * Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF)
1075 * high-water mark.
1076 **/
1077static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1078{
1079 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1080 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1081 u16 lat_enc = 0; /* latency encoded */
1082 s32 obff_hwm = 0;
1083
1084 DEBUGFUNC("e1000_platform_pm_pch_lpt");
1085
1086 if (link) {
1087 u16 speed, duplex, scale = 0;
1088 u16 max_snoop, max_nosnoop;
1089 u16 max_ltr_enc; /* max LTR latency encoded */
1090 s64 lat_ns;
1091 s64 value;
1092 u32 rxa;
1093
1094 if (!hw->mac.max_frame_size) {
1095 DEBUGOUT("max_frame_size not set.\n");
1096 return -E1000_ERR_CONFIG;
1097 }
1098
1099 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1100 if (!speed) {
1101 DEBUGOUT("Speed not set.\n");
1102 return -E1000_ERR_CONFIG;
1103 }
1104
1105 /* Rx Packet Buffer Allocation size (KB) */
1106 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK;
1107
1108 /* Determine the maximum latency tolerated by the device.
1109 *
1110 * Per the PCIe spec, the tolerated latencies are encoded as
1111 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1112 * a 10-bit value (0-1023) to provide a range from 1 ns to
1113 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1114 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1115 */
1116 lat_ns = ((s64)rxa * 1024 -
1117 (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000;
1118 if (lat_ns < 0)
1119 lat_ns = 0;
1120 else
1121 lat_ns /= speed;
1122 value = lat_ns;
1123
1124 while (value > E1000_LTRV_VALUE_MASK) {
1125 scale++;
1126 value = E1000_DIVIDE_ROUND_UP(value, (1 << 5));
1127 }
1128 if (scale > E1000_LTRV_SCALE_MAX) {
1129 DEBUGOUT1("Invalid LTR latency scale %d\n", scale);
1130 return -E1000_ERR_CONFIG;
1131 }
1132 lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value);
1133
1134 /* Determine the maximum latency tolerated by the platform */
1135 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop);
1136 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1137 max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop);
1138
1139 if (lat_enc > max_ltr_enc) {
1140 lat_enc = max_ltr_enc;
1141 lat_ns = e1000_ltr2ns(max_ltr_enc);
1142 }
1143
1144 if (lat_ns) {
1145 lat_ns *= speed * 1000;
1146 lat_ns /= 8;
1147 lat_ns /= 1000000000;
1148 obff_hwm = (s32)(rxa - lat_ns);
1149 }
1150 if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) {
1151 DEBUGOUT1("Invalid high water mark %d\n", obff_hwm);
1152 return -E1000_ERR_CONFIG;
1153 }
1154 }
1155
1156 /* Set Snoop and No-Snoop latencies the same */
1157 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1158 E1000_WRITE_REG(hw, E1000_LTRV, reg);
1159
1160 /* Set OBFF high water mark */
1161 reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
1162 reg |= obff_hwm;
1163 E1000_WRITE_REG(hw, E1000_SVT, reg);
1164
1165 /* Enable OBFF */
1166 reg = E1000_READ_REG(hw, E1000_SVCR);
1167 reg |= E1000_SVCR_OFF_EN;
1168 /* Always unblock interrupts to the CPU even when the system is
1169 * in OBFF mode. This ensures that small round-robin traffic
1170 * (like ping) does not get dropped or experience long latency.
1171 */
1172 reg |= E1000_SVCR_OFF_MASKINT;
1173 E1000_WRITE_REG(hw, E1000_SVCR, reg);
1174
1175 return E1000_SUCCESS;
1176}
1177
1178/**
1179 * e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer
1180 * @hw: pointer to the HW structure
1181 * @itr: interrupt throttling rate
1182 *
1183 * Configure OBFF with the updated interrupt rate.
1184 **/
1185static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
1186{
1187 u32 svcr;
1188 s32 timer;
1189
1190 DEBUGFUNC("e1000_set_obff_timer_pch_lpt");
1191
1192 /* Convert ITR value into microseconds for OBFF timer */
1193 timer = itr & E1000_ITR_MASK;
1194 timer = (timer * E1000_ITR_MULT) / 1000;
1195
1196 if ((timer < 0) || (timer > E1000_ITR_MASK)) {
1197 DEBUGOUT1("Invalid OBFF timer %d\n", timer);
1198 return -E1000_ERR_CONFIG;
1199 }
1200
1201 svcr = E1000_READ_REG(hw, E1000_SVCR);
1202 svcr &= ~E1000_SVCR_OFF_TIMER_MASK;
1203 svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT;
1204 E1000_WRITE_REG(hw, E1000_SVCR, svcr);
1205
1206 return E1000_SUCCESS;
1207}
1208
1209/**
1210 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1211 * @hw: pointer to the HW structure
1212 * @to_sx: boolean indicating a system power state transition to Sx
1213 *
1214 * When link is down, configure ULP mode to significantly reduce the power
1215 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1216 * ME firmware to start the ULP configuration. If not on an ME enabled
1217 * system, configure the ULP mode by software.
1218 */
1219s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1220{
1221 u32 mac_reg;
1222 s32 ret_val = E1000_SUCCESS;
1223 u16 phy_reg;
1224
1225 if ((hw->mac.type < e1000_pch_lpt) ||
1226 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1227 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1228 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1229 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1230 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1231 return 0;
1232
1233 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1234 /* Request ME configure ULP mode in the PHY */
1235 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1236 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1237 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1238
1239 goto out;
1240 }
1241
1242 if (!to_sx) {
1243 int i = 0;
1244
1245 /* Poll up to 5 seconds for Cable Disconnected indication */
1246 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1247 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1248 /* Bail if link is re-acquired */
1249 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1250 return -E1000_ERR_PHY;
1251
1252 if (i++ == 100)
1253 break;
1254
1255 msec_delay(50);
1256 }
1257 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1258 (E1000_READ_REG(hw, E1000_FEXT) &
1259 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1260 i * 50);
1261 }
1262
1263 ret_val = hw->phy.ops.acquire(hw);
1264 if (ret_val)
1265 goto out;
1266
1267 /* Force SMBus mode in PHY */
1268 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1269 if (ret_val)
1270 goto release;
1271 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1272 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1273
1274 /* Force SMBus mode in MAC */
1275 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1276 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1277 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1278
1279 /* Set Inband ULP Exit, Reset to SMBus mode and
1280 * Disable SMBus Release on PERST# in PHY
1281 */
1282 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1283 if (ret_val)
1284 goto release;
1285 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1286 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1287 if (to_sx) {
1288 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1289 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1290
1291 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1292 } else {
1293 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1294 }
1295 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1296
1297 /* Set Disable SMBus Release on PERST# in MAC */
1298 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1299 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1300 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1301
1302 /* Commit ULP changes in PHY by starting auto ULP configuration */
1303 phy_reg |= I218_ULP_CONFIG1_START;
1304 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1305release:
1306 hw->phy.ops.release(hw);
1307out:
1308 if (ret_val)
1309 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1310 else
1311 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1312
1313 return ret_val;
1314}
1315
1316/**
1317 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1318 * @hw: pointer to the HW structure
1319 * @force: boolean indicating whether or not to force disabling ULP
1320 *
1321 * Un-configure ULP mode when link is up, the system is transitioned from
1322 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1323 * system, poll for an indication from ME that ULP has been un-configured.
1324 * If not on an ME enabled system, un-configure the ULP mode by software.
1325 *
1326 * During nominal operation, this function is called when link is acquired
1327 * to disable ULP mode (force=FALSE); otherwise, for example when unloading
1328 * the driver or during Sx->S0 transitions, this is called with force=TRUE
1329 * to forcibly disable ULP.
1330 */
1331s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1332{
1333 s32 ret_val = E1000_SUCCESS;
1334 u32 mac_reg;
1335 u16 phy_reg;
1336 int i = 0;
1337
1338 if ((hw->mac.type < e1000_pch_lpt) ||
1339 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1340 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1341 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1342 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1343 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1344 return 0;
1345
1346 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1347 if (force) {
1348 /* Request ME un-configure ULP mode in the PHY */
1349 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1350 mac_reg &= ~E1000_H2ME_ULP;
1351 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1352 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1353 }
1354
1355 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1356 while (E1000_READ_REG(hw, E1000_FWSM) &
1357 E1000_FWSM_ULP_CFG_DONE) {
1358 if (i++ == 10) {
1359 ret_val = -E1000_ERR_PHY;
1360 goto out;
1361 }
1362
1363 msec_delay(10);
1364 }
1365 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1366
1367 if (force) {
1368 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1369 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1370 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1371 } else {
1372 /* Clear H2ME.ULP after ME ULP configuration */
1373 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1374 mac_reg &= ~E1000_H2ME_ULP;
1375 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1376 }
1377
1378 goto out;
1379 }
1380
1381 ret_val = hw->phy.ops.acquire(hw);
1382 if (ret_val)
1383 goto out;
1384
1385 if (force)
1386 /* Toggle LANPHYPC Value bit */
1387 e1000_toggle_lanphypc_pch_lpt(hw);
1388
1389 /* Unforce SMBus mode in PHY */
1390 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1391 if (ret_val) {
1392 /* The MAC might be in PCIe mode, so temporarily force to
1393 * SMBus mode in order to access the PHY.
1394 */
1395 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1396 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1397 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1398
1399 msec_delay(50);
1400
1401 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1402 &phy_reg);
1403 if (ret_val)
1404 goto release;
1405 }
1406 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1407 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1408
1409 /* Unforce SMBus mode in MAC */
1410 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1411 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1412 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1413
1414 /* When ULP mode was previously entered, K1 was disabled by the
1415 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1416 */
1417 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1418 if (ret_val)
1419 goto release;
1420 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1421 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1422
1423 /* Clear ULP enabled configuration */
1424 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1425 if (ret_val)
1426 goto release;
1427 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1428 I218_ULP_CONFIG1_STICKY_ULP |
1429 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1430 I218_ULP_CONFIG1_WOL_HOST |
1431 I218_ULP_CONFIG1_INBAND_EXIT |
1432 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1433 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1434
1435 /* Commit ULP changes by starting auto ULP configuration */
1436 phy_reg |= I218_ULP_CONFIG1_START;
1437 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1438
1439 /* Clear Disable SMBus Release on PERST# in MAC */
1440 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1441 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1442 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1443
1444release:
1445 hw->phy.ops.release(hw);
1446 if (force) {
1447 hw->phy.ops.reset(hw);
1448 msec_delay(50);
1449 }
1450out:
1451 if (ret_val)
1452 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1453 else
1454 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1455
1456 return ret_val;
1457}
1458
1459/**
1460 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1461 * @hw: pointer to the HW structure
1462 *
1463 * Checks to see of the link status of the hardware has changed. If a
1464 * change in link status has been detected, then we read the PHY registers
1465 * to get the current speed/duplex if link exists.
1466 **/
1467static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1468{
1469 struct e1000_mac_info *mac = &hw->mac;
1470 s32 ret_val;
1471 bool link;
1472 u16 phy_reg;
1473
1474 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1475
1476 /* We only want to go out to the PHY registers to see if Auto-Neg
1477 * has completed and/or if our link status has changed. The
1478 * get_link_status flag is set upon receiving a Link Status
1479 * Change or Rx Sequence Error interrupt.
1480 */
1481 if (!mac->get_link_status)
1482 return E1000_SUCCESS;
1483
1484 /* First we want to see if the MII Status Register reports
1485 * link. If so, then we want to get the current speed/duplex
1486 * of the PHY.
1487 */
1488 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1489 if (ret_val)
1490 return ret_val;
1491
1492 if (hw->mac.type == e1000_pchlan) {
1493 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1494 if (ret_val)
1495 return ret_val;
1496 }
1497
1498 /* When connected at 10Mbps half-duplex, some parts are excessively
1499 * aggressive resulting in many collisions. To avoid this, increase
1500 * the IPG and reduce Rx latency in the PHY.
1501 */
1502 if (((hw->mac.type == e1000_pch2lan) ||
1503 (hw->mac.type == e1000_pch_lpt)) && link) {
1504 u32 reg;
1505 reg = E1000_READ_REG(hw, E1000_STATUS);
1506 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1507 u16 emi_addr;
1508
1509 reg = E1000_READ_REG(hw, E1000_TIPG);
1510 reg &= ~E1000_TIPG_IPGT_MASK;
1511 reg |= 0xFF;
1512 E1000_WRITE_REG(hw, E1000_TIPG, reg);
1513
1514 /* Reduce Rx latency in analog PHY */
1515 ret_val = hw->phy.ops.acquire(hw);
1516 if (ret_val)
1517 return ret_val;
1518
1519 if (hw->mac.type == e1000_pch2lan)
1520 emi_addr = I82579_RX_CONFIG;
1521 else
1522 emi_addr = I217_RX_CONFIG;
1523 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0);
1524
1525 hw->phy.ops.release(hw);
1526
1527 if (ret_val)
1528 return ret_val;
1529 }
1530 }
1531
1532 /* Work-around I218 hang issue */
1533 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1534 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1535 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1536 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1537 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1538 if (ret_val)
1539 return ret_val;
1540 }
1541 if (hw->mac.type == e1000_pch_lpt) {
1542 /* Set platform power management values for
1543 * Latency Tolerance Reporting (LTR)
1544 * Optimized Buffer Flush/Fill (OBFF)
1545 */
1546 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1547 if (ret_val)
1548 return ret_val;
1549 }
1550
1551 /* Clear link partner's EEE ability */
1552 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1553
1554 if (!link)
1555 return E1000_SUCCESS; /* No link detected */
1556
1557 mac->get_link_status = FALSE;
1558
1559 switch (hw->mac.type) {
1560 case e1000_pch2lan:
1561 ret_val = e1000_k1_workaround_lv(hw);
1562 if (ret_val)
1563 return ret_val;
1564 /* fall-thru */
1565 case e1000_pchlan:
1566 if (hw->phy.type == e1000_phy_82578) {
1567 ret_val = e1000_link_stall_workaround_hv(hw);
1568 if (ret_val)
1569 return ret_val;
1570 }
1571
1572 /* Workaround for PCHx parts in half-duplex:
1573 * Set the number of preambles removed from the packet
1574 * when it is passed from the PHY to the MAC to prevent
1575 * the MAC from misinterpreting the packet type.
1576 */
1577 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1578 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1579
1580 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1581 E1000_STATUS_FD)
1582 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1583
1584 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1585 break;
1586 default:
1587 break;
1588 }
1589
1590 /* Check if there was DownShift, must be checked
1591 * immediately after link-up
1592 */
1593 e1000_check_downshift_generic(hw);
1594
1595 /* Enable/Disable EEE after link up */
1596 if (hw->phy.type > e1000_phy_82579) {
1597 ret_val = e1000_set_eee_pchlan(hw);
1598 if (ret_val)
1599 return ret_val;
1600 }
1601
1602 /* If we are forcing speed/duplex, then we simply return since
1603 * we have already determined whether we have link or not.
1604 */
1605 if (!mac->autoneg)
1606 return -E1000_ERR_CONFIG;
1607
1608 /* Auto-Neg is enabled. Auto Speed Detection takes care
1609 * of MAC speed/duplex configuration. So we only need to
1610 * configure Collision Distance in the MAC.
1611 */
1612 mac->ops.config_collision_dist(hw);
1613
1614 /* Configure Flow Control now that Auto-Neg has completed.
1615 * First, we need to restore the desired flow control
1616 * settings because we may have had to re-autoneg with a
1617 * different link partner.
1618 */
1619 ret_val = e1000_config_fc_after_link_up_generic(hw);
1620 if (ret_val)
1621 DEBUGOUT("Error configuring flow control\n");
1622
1623 return ret_val;
1624}
1625
1626/**
1627 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1628 * @hw: pointer to the HW structure
1629 *
1630 * Initialize family-specific function pointers for PHY, MAC, and NVM.
1631 **/
1632void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1633{
1634 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1635
1636 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1637 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1638 switch (hw->mac.type) {
1639 case e1000_ich8lan:
1640 case e1000_ich9lan:
1641 case e1000_ich10lan:
1642 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1643 break;
1644 case e1000_pchlan:
1645 case e1000_pch2lan:
1646 case e1000_pch_lpt:
1647 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1648 break;
1649 default:
1650 break;
1651 }
1652}
1653
1654/**
1655 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1656 * @hw: pointer to the HW structure
1657 *
1658 * Acquires the mutex for performing NVM operations.
1659 **/
1660static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1661{
1662 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1663
1664 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1665
1666 return E1000_SUCCESS;
1667}
1668
1669/**
1670 * e1000_release_nvm_ich8lan - Release NVM mutex
1671 * @hw: pointer to the HW structure
1672 *
1673 * Releases the mutex used while performing NVM operations.
1674 **/
1675static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1676{
1677 DEBUGFUNC("e1000_release_nvm_ich8lan");
1678
1679 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1680
1681 return;
1682}
1683
1684/**
1685 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1686 * @hw: pointer to the HW structure
1687 *
1688 * Acquires the software control flag for performing PHY and select
1689 * MAC CSR accesses.
1690 **/
1691static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1692{
1693 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1694 s32 ret_val = E1000_SUCCESS;
1695
1696 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1697
1698 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1699
1700 while (timeout) {
1701 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1702 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1703 break;
1704
1705 msec_delay_irq(1);
1706 timeout--;
1707 }
1708
1709 if (!timeout) {
1710 DEBUGOUT("SW has already locked the resource.\n");
1711 ret_val = -E1000_ERR_CONFIG;
1712 goto out;
1713 }
1714
1715 timeout = SW_FLAG_TIMEOUT;
1716
1717 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1718 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1719
1720 while (timeout) {
1721 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1722 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1723 break;
1724
1725 msec_delay_irq(1);
1726 timeout--;
1727 }
1728
1729 if (!timeout) {
1730 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1731 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1732 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1733 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1734 ret_val = -E1000_ERR_CONFIG;
1735 goto out;
1736 }
1737
1738out:
1739 if (ret_val)
1740 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1741
1742 return ret_val;
1743}
1744
1745/**
1746 * e1000_release_swflag_ich8lan - Release software control flag
1747 * @hw: pointer to the HW structure
1748 *
1749 * Releases the software control flag for performing PHY and select
1750 * MAC CSR accesses.
1751 **/
1752static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1753{
1754 u32 extcnf_ctrl;
1755
1756 DEBUGFUNC("e1000_release_swflag_ich8lan");
1757
1758 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1759
1760 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1761 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1762 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1763 } else {
1764 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1765 }
1766
1767 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1768
1769 return;
1770}
1771
1772/**
1773 * e1000_check_mng_mode_ich8lan - Checks management mode
1774 * @hw: pointer to the HW structure
1775 *
1776 * This checks if the adapter has any manageability enabled.
1777 * This is a function pointer entry point only called by read/write
1778 * routines for the PHY and NVM parts.
1779 **/
1780static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1781{
1782 u32 fwsm;
1783
1784 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1785
1786 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1787
1788 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1789 ((fwsm & E1000_FWSM_MODE_MASK) ==
1790 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1791}
1792
1793/**
1794 * e1000_check_mng_mode_pchlan - Checks management mode
1795 * @hw: pointer to the HW structure
1796 *
1797 * This checks if the adapter has iAMT enabled.
1798 * This is a function pointer entry point only called by read/write
1799 * routines for the PHY and NVM parts.
1800 **/
1801static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1802{
1803 u32 fwsm;
1804
1805 DEBUGFUNC("e1000_check_mng_mode_pchlan");
1806
1807 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1808
1809 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1810 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1811}
1812
1813/**
1814 * e1000_rar_set_pch2lan - Set receive address register
1815 * @hw: pointer to the HW structure
1816 * @addr: pointer to the receive address
1817 * @index: receive address array register
1818 *
1819 * Sets the receive address array register at index to the address passed
1820 * in by addr. For 82579, RAR[0] is the base address register that is to
1821 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1822 * Use SHRA[0-3] in place of those reserved for ME.
1823 **/
1824static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1825{
1826 u32 rar_low, rar_high;
1827
1828 DEBUGFUNC("e1000_rar_set_pch2lan");
1829
1830 /* HW expects these in little endian so we reverse the byte order
1831 * from network order (big endian) to little endian
1832 */
1833 rar_low = ((u32) addr[0] |
1834 ((u32) addr[1] << 8) |
1835 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1836
1837 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1838
1839 /* If MAC address zero, no need to set the AV bit */
1840 if (rar_low || rar_high)
1841 rar_high |= E1000_RAH_AV;
1842
1843 if (index == 0) {
1844 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1845 E1000_WRITE_FLUSH(hw);
1846 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1847 E1000_WRITE_FLUSH(hw);
1848 return E1000_SUCCESS;
1849 }
1850
1851 /* RAR[1-6] are owned by manageability. Skip those and program the
1852 * next address into the SHRA register array.
1853 */
1854 if (index < (u32) (hw->mac.rar_entry_count)) {
1855 s32 ret_val;
1856
1857 ret_val = e1000_acquire_swflag_ich8lan(hw);
1858 if (ret_val)
1859 goto out;
1860
1861 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1862 E1000_WRITE_FLUSH(hw);
1863 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1864 E1000_WRITE_FLUSH(hw);
1865
1866 e1000_release_swflag_ich8lan(hw);
1867
1868 /* verify the register updates */
1869 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1870 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1871 return E1000_SUCCESS;
1872
1873 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1874 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1875 }
1876
1877out:
1878 DEBUGOUT1("Failed to write receive address at index %d\n", index);
1879 return -E1000_ERR_CONFIG;
1880}
1881
1882/**
1883 * e1000_rar_set_pch_lpt - Set receive address registers
1884 * @hw: pointer to the HW structure
1885 * @addr: pointer to the receive address
1886 * @index: receive address array register
1887 *
1888 * Sets the receive address register array at index to the address passed
1889 * in by addr. For LPT, RAR[0] is the base address register that is to
1890 * contain the MAC address. SHRA[0-10] are the shared receive address
1891 * registers that are shared between the Host and manageability engine (ME).
1892 **/
1893static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1894{
1895 u32 rar_low, rar_high;
1896 u32 wlock_mac;
1897
1898 DEBUGFUNC("e1000_rar_set_pch_lpt");
1899
1900 /* HW expects these in little endian so we reverse the byte order
1901 * from network order (big endian) to little endian
1902 */
1903 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
1904 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1905
1906 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1907
1908 /* If MAC address zero, no need to set the AV bit */
1909 if (rar_low || rar_high)
1910 rar_high |= E1000_RAH_AV;
1911
1912 if (index == 0) {
1913 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1914 E1000_WRITE_FLUSH(hw);
1915 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1916 E1000_WRITE_FLUSH(hw);
1917 return E1000_SUCCESS;
1918 }
1919
1920 /* The manageability engine (ME) can lock certain SHRAR registers that
1921 * it is using - those registers are unavailable for use.
1922 */
1923 if (index < hw->mac.rar_entry_count) {
1924 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
1925 E1000_FWSM_WLOCK_MAC_MASK;
1926 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1927
1928 /* Check if all SHRAR registers are locked */
1929 if (wlock_mac == 1)
1930 goto out;
1931
1932 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1933 s32 ret_val;
1934
1935 ret_val = e1000_acquire_swflag_ich8lan(hw);
1936
1937 if (ret_val)
1938 goto out;
1939
1940 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
1941 rar_low);
1942 E1000_WRITE_FLUSH(hw);
1943 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
1944 rar_high);
1945 E1000_WRITE_FLUSH(hw);
1946
1947 e1000_release_swflag_ich8lan(hw);
1948
1949 /* verify the register updates */
1950 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1951 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
1952 return E1000_SUCCESS;
1953 }
1954 }
1955
1956out:
1957 DEBUGOUT1("Failed to write receive address at index %d\n", index);
1958 return -E1000_ERR_CONFIG;
1959}
1960
1961/**
1962 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
1963 * @hw: pointer to the HW structure
1964 * @mc_addr_list: array of multicast addresses to program
1965 * @mc_addr_count: number of multicast addresses to program
1966 *
1967 * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
1968 * The caller must have a packed mc_addr_list of multicast addresses.
1969 **/
1970static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
1971 u8 *mc_addr_list,
1972 u32 mc_addr_count)
1973{
1974 u16 phy_reg = 0;
1975 int i;
1976 s32 ret_val;
1977
1978 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
1979
1980 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
1981
1982 ret_val = hw->phy.ops.acquire(hw);
1983 if (ret_val)
1984 return;
1985
1986 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1987 if (ret_val)
1988 goto release;
1989
1990 for (i = 0; i < hw->mac.mta_reg_count; i++) {
1991 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
1992 (u16)(hw->mac.mta_shadow[i] &
1993 0xFFFF));
1994 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
1995 (u16)((hw->mac.mta_shadow[i] >> 16) &
1996 0xFFFF));
1997 }
1998
1999 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2000
2001release:
2002 hw->phy.ops.release(hw);
2003}
2004
2005/**
2006 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2007 * @hw: pointer to the HW structure
2008 *
2009 * Checks if firmware is blocking the reset of the PHY.
2010 * This is a function pointer entry point only called by
2011 * reset routines.
2012 **/
2013static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2014{
2015 u32 fwsm;
2016 bool blocked = FALSE;
2017 int i = 0;
2018
2019 DEBUGFUNC("e1000_check_reset_block_ich8lan");
2020
2021 do {
2022 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2023 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2024 blocked = TRUE;
2025 msec_delay(10);
2026 continue;
2027 }
2028 blocked = FALSE;
2029 } while (blocked && (i++ < 10));
2030 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2031}
2032
2033/**
2034 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2035 * @hw: pointer to the HW structure
2036 *
2037 * Assumes semaphore already acquired.
2038 *
2039 **/
2040static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2041{
2042 u16 phy_data;
2043 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2044 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2045 E1000_STRAP_SMT_FREQ_SHIFT;
2046 s32 ret_val;
2047
2048 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2049
2050 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2051 if (ret_val)
2052 return ret_val;
2053
2054 phy_data &= ~HV_SMB_ADDR_MASK;
2055 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2056 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2057
2058 if (hw->phy.type == e1000_phy_i217) {
2059 /* Restore SMBus frequency */
2060 if (freq--) {
2061 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2062 phy_data |= (freq & (1 << 0)) <<
2063 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2064 phy_data |= (freq & (1 << 1)) <<
2065 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2066 } else {
2067 DEBUGOUT("Unsupported SMB frequency in PHY\n");
2068 }
2069 }
2070
2071 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2072}
2073
2074/**
2075 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2076 * @hw: pointer to the HW structure
2077 *
2078 * SW should configure the LCD from the NVM extended configuration region
2079 * as a workaround for certain parts.
2080 **/
2081static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2082{
2083 struct e1000_phy_info *phy = &hw->phy;
2084 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2085 s32 ret_val = E1000_SUCCESS;
2086 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2087
2088 DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2089
2090 /* Initialize the PHY from the NVM on ICH platforms. This
2091 * is needed due to an issue where the NVM configuration is
2092 * not properly autoloaded after power transitions.
2093 * Therefore, after each PHY reset, we will load the
2094 * configuration data out of the NVM manually.
2095 */
2096 switch (hw->mac.type) {
2097 case e1000_ich8lan:
2098 if (phy->type != e1000_phy_igp_3)
2099 return ret_val;
2100
2101 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2102 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2103 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2104 break;
2105 }
2106 /* Fall-thru */
2107 case e1000_pchlan:
2108 case e1000_pch2lan:
2109 case e1000_pch_lpt:
2110 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2111 break;
2112 default:
2113 return ret_val;
2114 }
2115
2116 ret_val = hw->phy.ops.acquire(hw);
2117 if (ret_val)
2118 return ret_val;
2119
2120 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2121 if (!(data & sw_cfg_mask))
2122 goto release;
2123
2124 /* Make sure HW does not configure LCD from PHY
2125 * extended configuration before SW configuration
2126 */
2127 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2128 if ((hw->mac.type < e1000_pch2lan) &&
2129 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2130 goto release;
2131
2132 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2133 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2134 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2135 if (!cnf_size)
2136 goto release;
2137
2138 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2139 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2140
2141 if (((hw->mac.type == e1000_pchlan) &&
2142 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2143 (hw->mac.type > e1000_pchlan)) {
2144 /* HW configures the SMBus address and LEDs when the
2145 * OEM and LCD Write Enable bits are set in the NVM.
2146 * When both NVM bits are cleared, SW will configure
2147 * them instead.
2148 */
2149 ret_val = e1000_write_smbus_addr(hw);
2150 if (ret_val)
2151 goto release;
2152
2153 data = E1000_READ_REG(hw, E1000_LEDCTL);
2154 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2155 (u16)data);
2156 if (ret_val)
2157 goto release;
2158 }
2159
2160 /* Configure LCD from extended configuration region. */
2161
2162 /* cnf_base_addr is in DWORD */
2163 word_addr = (u16)(cnf_base_addr << 1);
2164
2165 for (i = 0; i < cnf_size; i++) {
2166 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2167 &reg_data);
2168 if (ret_val)
2169 goto release;
2170
2171 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2172 1, &reg_addr);
2173 if (ret_val)
2174 goto release;
2175
2176 /* Save off the PHY page for future writes. */
2177 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2178 phy_page = reg_data;
2179 continue;
2180 }
2181
2182 reg_addr &= PHY_REG_MASK;
2183 reg_addr |= phy_page;
2184
2185 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2186 reg_data);
2187 if (ret_val)
2188 goto release;
2189 }
2190
2191release:
2192 hw->phy.ops.release(hw);
2193 return ret_val;
2194}
2195
2196/**
2197 * e1000_k1_gig_workaround_hv - K1 Si workaround
2198 * @hw: pointer to the HW structure
2199 * @link: link up bool flag
2200 *
2201 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2202 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2203 * If link is down, the function will restore the default K1 setting located
2204 * in the NVM.
2205 **/
2206static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2207{
2208 s32 ret_val = E1000_SUCCESS;
2209 u16 status_reg = 0;
2210 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2211
2212 DEBUGFUNC("e1000_k1_gig_workaround_hv");
2213
2214 if (hw->mac.type != e1000_pchlan)
2215 return E1000_SUCCESS;
2216
2217 /* Wrap the whole flow with the sw flag */
2218 ret_val = hw->phy.ops.acquire(hw);
2219 if (ret_val)
2220 return ret_val;
2221
2222 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2223 if (link) {
2224 if (hw->phy.type == e1000_phy_82578) {
2225 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2226 &status_reg);
2227 if (ret_val)
2228 goto release;
2229
2230 status_reg &= (BM_CS_STATUS_LINK_UP |
2231 BM_CS_STATUS_RESOLVED |
2232 BM_CS_STATUS_SPEED_MASK);
2233
2234 if (status_reg == (BM_CS_STATUS_LINK_UP |
2235 BM_CS_STATUS_RESOLVED |
2236 BM_CS_STATUS_SPEED_1000))
2237 k1_enable = FALSE;
2238 }
2239
2240 if (hw->phy.type == e1000_phy_82577) {
2241 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2242 &status_reg);
2243 if (ret_val)
2244 goto release;
2245
2246 status_reg &= (HV_M_STATUS_LINK_UP |
2247 HV_M_STATUS_AUTONEG_COMPLETE |
2248 HV_M_STATUS_SPEED_MASK);
2249
2250 if (status_reg == (HV_M_STATUS_LINK_UP |
2251 HV_M_STATUS_AUTONEG_COMPLETE |
2252 HV_M_STATUS_SPEED_1000))
2253 k1_enable = FALSE;
2254 }
2255
2256 /* Link stall fix for link up */
2257 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2258 0x0100);
2259 if (ret_val)
2260 goto release;
2261
2262 } else {
2263 /* Link stall fix for link down */
2264 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2265 0x4100);
2266 if (ret_val)
2267 goto release;
2268 }
2269
2270 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2271
2272release:
2273 hw->phy.ops.release(hw);
2274
2275 return ret_val;
2276}
2277
2278/**
2279 * e1000_configure_k1_ich8lan - Configure K1 power state
2280 * @hw: pointer to the HW structure
2281 * @enable: K1 state to configure
2282 *
2283 * Configure the K1 power state based on the provided parameter.
2284 * Assumes semaphore already acquired.
2285 *
2286 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2287 **/
2288s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2289{
2290 s32 ret_val;
2291 u32 ctrl_reg = 0;
2292 u32 ctrl_ext = 0;
2293 u32 reg = 0;
2294 u16 kmrn_reg = 0;
2295
2296 DEBUGFUNC("e1000_configure_k1_ich8lan");
2297
2298 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2299 &kmrn_reg);
2300 if (ret_val)
2301 return ret_val;
2302
2303 if (k1_enable)
2304 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2305 else
2306 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2307
2308 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2309 kmrn_reg);
2310 if (ret_val)
2311 return ret_val;
2312
2313 usec_delay(20);
2314 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2315 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2316
2317 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2318 reg |= E1000_CTRL_FRCSPD;
2319 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2320
2321 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2322 E1000_WRITE_FLUSH(hw);
2323 usec_delay(20);
2324 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2325 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2326 E1000_WRITE_FLUSH(hw);
2327 usec_delay(20);
2328
2329 return E1000_SUCCESS;
2330}
2331
2332/**
2333 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2334 * @hw: pointer to the HW structure
2335 * @d0_state: boolean if entering d0 or d3 device state
2336 *
2337 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2338 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2339 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2340 **/
2341static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2342{
2343 s32 ret_val = 0;
2344 u32 mac_reg;
2345 u16 oem_reg;
2346
2347 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2348
2349 if (hw->mac.type < e1000_pchlan)
2350 return ret_val;
2351
2352 ret_val = hw->phy.ops.acquire(hw);
2353 if (ret_val)
2354 return ret_val;
2355
2356 if (hw->mac.type == e1000_pchlan) {
2357 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2358 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2359 goto release;
2360 }
2361
2362 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2363 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2364 goto release;
2365
2366 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2367
2368 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2369 if (ret_val)
2370 goto release;
2371
2372 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2373
2374 if (d0_state) {
2375 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2376 oem_reg |= HV_OEM_BITS_GBE_DIS;
2377
2378 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2379 oem_reg |= HV_OEM_BITS_LPLU;
2380 } else {
2381 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2382 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2383 oem_reg |= HV_OEM_BITS_GBE_DIS;
2384
2385 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2386 E1000_PHY_CTRL_NOND0A_LPLU))
2387 oem_reg |= HV_OEM_BITS_LPLU;
2388 }
2389
2390 /* Set Restart auto-neg to activate the bits */
2391 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2392 !hw->phy.ops.check_reset_block(hw))
2393 oem_reg |= HV_OEM_BITS_RESTART_AN;
2394
2395 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2396
2397release:
2398 hw->phy.ops.release(hw);
2399
2400 return ret_val;
2401}
2402
2403
2404/**
2405 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2406 * @hw: pointer to the HW structure
2407 **/
2408static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2409{
2410 s32 ret_val;
2411 u16 data;
2412
2413 DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2414
2415 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2416 if (ret_val)
2417 return ret_val;
2418
2419 data |= HV_KMRN_MDIO_SLOW;
2420
2421 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2422
2423 return ret_val;
2424}
2425
2426/**
2427 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2428 * done after every PHY reset.
2429 **/
2430static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2431{
2432 s32 ret_val = E1000_SUCCESS;
2433 u16 phy_data;
2434
2435 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2436
2437 if (hw->mac.type != e1000_pchlan)
2438 return E1000_SUCCESS;
2439
2440 /* Set MDIO slow mode before any other MDIO access */
2441 if (hw->phy.type == e1000_phy_82577) {
2442 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2443 if (ret_val)
2444 return ret_val;
2445 }
2446
2447 if (((hw->phy.type == e1000_phy_82577) &&
2448 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2449 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2450 /* Disable generation of early preamble */
2451 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2452 if (ret_val)
2453 return ret_val;
2454
2455 /* Preamble tuning for SSC */
2456 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2457 0xA204);
2458 if (ret_val)
2459 return ret_val;
2460 }
2461
2462 if (hw->phy.type == e1000_phy_82578) {
2463 /* Return registers to default by doing a soft reset then
2464 * writing 0x3140 to the control register.
2465 */
2466 if (hw->phy.revision < 2) {
2467 e1000_phy_sw_reset_generic(hw);
2468 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2469 0x3140);
2470 }
2471 }
2472
2473 /* Select page 0 */
2474 ret_val = hw->phy.ops.acquire(hw);
2475 if (ret_val)
2476 return ret_val;
2477
2478 hw->phy.addr = 1;
2479 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2480 hw->phy.ops.release(hw);
2481 if (ret_val)
2482 return ret_val;
2483
2484 /* Configure the K1 Si workaround during phy reset assuming there is
2485 * link so that it disables K1 if link is in 1Gbps.
2486 */
2487 ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
2488 if (ret_val)
2489 return ret_val;
2490
2491 /* Workaround for link disconnects on a busy hub in half duplex */
2492 ret_val = hw->phy.ops.acquire(hw);
2493 if (ret_val)
2494 return ret_val;
2495 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2496 if (ret_val)
2497 goto release;
2498 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2499 phy_data & 0x00FF);
2500 if (ret_val)
2501 goto release;
2502
2503 /* set MSE higher to enable link to stay up when noise is high */
2504 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2505release:
2506 hw->phy.ops.release(hw);
2507
2508 return ret_val;
2509}
2510
2511/**
2512 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2513 * @hw: pointer to the HW structure
2514 **/
2515void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2516{
2517 u32 mac_reg;
2518 u16 i, phy_reg = 0;
2519 s32 ret_val;
2520
2521 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2522
2523 ret_val = hw->phy.ops.acquire(hw);
2524 if (ret_val)
2525 return;
2526 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2527 if (ret_val)
2528 goto release;
2529
2530 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2531 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2532 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2533 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2534 (u16)(mac_reg & 0xFFFF));
2535 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2536 (u16)((mac_reg >> 16) & 0xFFFF));
2537
2538 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2539 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2540 (u16)(mac_reg & 0xFFFF));
2541 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2542 (u16)((mac_reg & E1000_RAH_AV)
2543 >> 16));
2544 }
2545
2546 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2547
2548release:
2549 hw->phy.ops.release(hw);
2550}
2551
2552static u32 e1000_calc_rx_da_crc(u8 mac[])
2553{
2554 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
2555 u32 i, j, mask, crc;
2556
2557 DEBUGFUNC("e1000_calc_rx_da_crc");
2558
2559 crc = 0xffffffff;
2560 for (i = 0; i < 6; i++) {
2561 crc = crc ^ mac[i];
2562 for (j = 8; j > 0; j--) {
2563 mask = (crc & 1) * (-1);
2564 crc = (crc >> 1) ^ (poly & mask);
2565 }
2566 }
2567 return ~crc;
2568}
2569
2570/**
2571 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2572 * with 82579 PHY
2573 * @hw: pointer to the HW structure
2574 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2575 **/
2576s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2577{
2578 s32 ret_val = E1000_SUCCESS;
2579 u16 phy_reg, data;
2580 u32 mac_reg;
2581 u16 i;
2582
2583 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2584
2585 if (hw->mac.type < e1000_pch2lan)
2586 return E1000_SUCCESS;
2587
2588 /* disable Rx path while enabling/disabling workaround */
2589 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2590 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2591 phy_reg | (1 << 14));
2592 if (ret_val)
2593 return ret_val;
2594
2595 if (enable) {
2596 /* Write Rx addresses (rar_entry_count for RAL/H, and
2597 * SHRAL/H) and initial CRC values to the MAC
2598 */
2599 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2600 u8 mac_addr[ETH_ADDR_LEN] = {0};
2601 u32 addr_high, addr_low;
2602
2603 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2604 if (!(addr_high & E1000_RAH_AV))
2605 continue;
2606 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2607 mac_addr[0] = (addr_low & 0xFF);
2608 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2609 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2610 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2611 mac_addr[4] = (addr_high & 0xFF);
2612 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2613
2614 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2615 e1000_calc_rx_da_crc(mac_addr));
2616 }
2617
2618 /* Write Rx addresses to the PHY */
2619 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2620
2621 /* Enable jumbo frame workaround in the MAC */
2622 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2623 mac_reg &= ~(1 << 14);
2624 mac_reg |= (7 << 15);
2625 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2626
2627 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2628 mac_reg |= E1000_RCTL_SECRC;
2629 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2630
2631 ret_val = e1000_read_kmrn_reg_generic(hw,
2632 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2633 &data);
2634 if (ret_val)
2635 return ret_val;
2636 ret_val = e1000_write_kmrn_reg_generic(hw,
2637 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2638 data | (1 << 0));
2639 if (ret_val)
2640 return ret_val;
2641 ret_val = e1000_read_kmrn_reg_generic(hw,
2642 E1000_KMRNCTRLSTA_HD_CTRL,
2643 &data);
2644 if (ret_val)
2645 return ret_val;
2646 data &= ~(0xF << 8);
2647 data |= (0xB << 8);
2648 ret_val = e1000_write_kmrn_reg_generic(hw,
2649 E1000_KMRNCTRLSTA_HD_CTRL,
2650 data);
2651 if (ret_val)
2652 return ret_val;
2653
2654 /* Enable jumbo frame workaround in the PHY */
2655 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2656 data &= ~(0x7F << 5);
2657 data |= (0x37 << 5);
2658 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2659 if (ret_val)
2660 return ret_val;
2661 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2662 data &= ~(1 << 13);
2663 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2664 if (ret_val)
2665 return ret_val;
2666 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2667 data &= ~(0x3FF << 2);
2668 data |= (E1000_TX_PTR_GAP << 2);
2669 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2670 if (ret_val)
2671 return ret_val;
2672 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2673 if (ret_val)
2674 return ret_val;
2675 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2676 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2677 (1 << 10));
2678 if (ret_val)
2679 return ret_val;
2680 } else {
2681 /* Write MAC register values back to h/w defaults */
2682 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2683 mac_reg &= ~(0xF << 14);
2684 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2685
2686 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2687 mac_reg &= ~E1000_RCTL_SECRC;
2688 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2689
2690 ret_val = e1000_read_kmrn_reg_generic(hw,
2691 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2692 &data);
2693 if (ret_val)
2694 return ret_val;
2695 ret_val = e1000_write_kmrn_reg_generic(hw,
2696 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2697 data & ~(1 << 0));
2698 if (ret_val)
2699 return ret_val;
2700 ret_val = e1000_read_kmrn_reg_generic(hw,
2701 E1000_KMRNCTRLSTA_HD_CTRL,
2702 &data);
2703 if (ret_val)
2704 return ret_val;
2705 data &= ~(0xF << 8);
2706 data |= (0xB << 8);
2707 ret_val = e1000_write_kmrn_reg_generic(hw,
2708 E1000_KMRNCTRLSTA_HD_CTRL,
2709 data);
2710 if (ret_val)
2711 return ret_val;
2712
2713 /* Write PHY register values back to h/w defaults */
2714 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2715 data &= ~(0x7F << 5);
2716 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2717 if (ret_val)
2718 return ret_val;
2719 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2720 data |= (1 << 13);
2721 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2722 if (ret_val)
2723 return ret_val;
2724 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2725 data &= ~(0x3FF << 2);
2726 data |= (0x8 << 2);
2727 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2728 if (ret_val)
2729 return ret_val;
2730 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2731 if (ret_val)
2732 return ret_val;
2733 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2734 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2735 ~(1 << 10));
2736 if (ret_val)
2737 return ret_val;
2738 }
2739
2740 /* re-enable Rx path after enabling/disabling workaround */
2741 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2742 ~(1 << 14));
2743}
2744
2745/**
2746 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2747 * done after every PHY reset.
2748 **/
2749static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2750{
2751 s32 ret_val = E1000_SUCCESS;
2752
2753 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2754
2755 if (hw->mac.type != e1000_pch2lan)
2756 return E1000_SUCCESS;
2757
2758 /* Set MDIO slow mode before any other MDIO access */
2759 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2760 if (ret_val)
2761 return ret_val;
2762
2763 ret_val = hw->phy.ops.acquire(hw);
2764 if (ret_val)
2765 return ret_val;
2766 /* set MSE higher to enable link to stay up when noise is high */
2767 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2768 if (ret_val)
2769 goto release;
2770 /* drop link after 5 times MSE threshold was reached */
2771 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2772release:
2773 hw->phy.ops.release(hw);
2774
2775 return ret_val;
2776}
2777
2778/**
2779 * e1000_k1_gig_workaround_lv - K1 Si workaround
2780 * @hw: pointer to the HW structure
2781 *
2782 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2783 * Disable K1 for 1000 and 100 speeds
2784 **/
2785static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2786{
2787 s32 ret_val = E1000_SUCCESS;
2788 u16 status_reg = 0;
2789
2790 DEBUGFUNC("e1000_k1_workaround_lv");
2791
2792 if (hw->mac.type != e1000_pch2lan)
2793 return E1000_SUCCESS;
2794
2795 /* Set K1 beacon duration based on 10Mbs speed */
2796 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2797 if (ret_val)
2798 return ret_val;
2799
2800 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2801 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2802 if (status_reg &
2803 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2804 u16 pm_phy_reg;
2805
2806 /* LV 1G/100 Packet drop issue wa */
2807 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2808 &pm_phy_reg);
2809 if (ret_val)
2810 return ret_val;
2811 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2812 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2813 pm_phy_reg);
2814 if (ret_val)
2815 return ret_val;
2816 } else {
2817 u32 mac_reg;
2818 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2819 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2820 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2821 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2822 }
2823 }
2824
2825 return ret_val;
2826}
2827
2828/**
2829 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2830 * @hw: pointer to the HW structure
2831 * @gate: boolean set to TRUE to gate, FALSE to ungate
2832 *
2833 * Gate/ungate the automatic PHY configuration via hardware; perform
2834 * the configuration via software instead.
2835 **/
2836static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2837{
2838 u32 extcnf_ctrl;
2839
2840 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2841
2842 if (hw->mac.type < e1000_pch2lan)
2843 return;
2844
2845 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2846
2847 if (gate)
2848 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2849 else
2850 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2851
2852 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2853}
2854
2855/**
2856 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2857 * @hw: pointer to the HW structure
2858 *
2859 * Check the appropriate indication the MAC has finished configuring the
2860 * PHY after a software reset.
2861 **/
2862static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2863{
2864 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2865
2866 DEBUGFUNC("e1000_lan_init_done_ich8lan");
2867
2868 /* Wait for basic configuration completes before proceeding */
2869 do {
2870 data = E1000_READ_REG(hw, E1000_STATUS);
2871 data &= E1000_STATUS_LAN_INIT_DONE;
2872 usec_delay(100);
2873 } while ((!data) && --loop);
2874
2875 /* If basic configuration is incomplete before the above loop
2876 * count reaches 0, loading the configuration from NVM will
2877 * leave the PHY in a bad state possibly resulting in no link.
2878 */
2879 if (loop == 0)
2880 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
2881
2882 /* Clear the Init Done bit for the next init event */
2883 data = E1000_READ_REG(hw, E1000_STATUS);
2884 data &= ~E1000_STATUS_LAN_INIT_DONE;
2885 E1000_WRITE_REG(hw, E1000_STATUS, data);
2886}
2887
2888/**
2889 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2890 * @hw: pointer to the HW structure
2891 **/
2892static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2893{
2894 s32 ret_val = E1000_SUCCESS;
2895 u16 reg;
2896
2897 DEBUGFUNC("e1000_post_phy_reset_ich8lan");
2898
2899 if (hw->phy.ops.check_reset_block(hw))
2900 return E1000_SUCCESS;
2901
2902 /* Allow time for h/w to get to quiescent state after reset */
2903 msec_delay(10);
2904
2905 /* Perform any necessary post-reset workarounds */
2906 switch (hw->mac.type) {
2907 case e1000_pchlan:
2908 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2909 if (ret_val)
2910 return ret_val;
2911 break;
2912 case e1000_pch2lan:
2913 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2914 if (ret_val)
2915 return ret_val;
2916 break;
2917 default:
2918 break;
2919 }
2920
2921 /* Clear the host wakeup bit after lcd reset */
2922 if (hw->mac.type >= e1000_pchlan) {
2923 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
2924 reg &= ~BM_WUC_HOST_WU_BIT;
2925 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
2926 }
2927
2928 /* Configure the LCD with the extended configuration region in NVM */
2929 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2930 if (ret_val)
2931 return ret_val;
2932
2933 /* Configure the LCD with the OEM bits in NVM */
2934 ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
2935
2936 if (hw->mac.type == e1000_pch2lan) {
2937 /* Ungate automatic PHY configuration on non-managed 82579 */
2938 if (!(E1000_READ_REG(hw, E1000_FWSM) &
2939 E1000_ICH_FWSM_FW_VALID)) {
2940 msec_delay(10);
2941 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
2942 }
2943
2944 /* Set EEE LPI Update Timer to 200usec */
2945 ret_val = hw->phy.ops.acquire(hw);
2946 if (ret_val)
2947 return ret_val;
2948 ret_val = e1000_write_emi_reg_locked(hw,
2949 I82579_LPI_UPDATE_TIMER,
2950 0x1387);
2951 hw->phy.ops.release(hw);
2952 }
2953
2954 return ret_val;
2955}
2956
2957/**
2958 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2959 * @hw: pointer to the HW structure
2960 *
2961 * Resets the PHY
2962 * This is a function pointer entry point called by drivers
2963 * or other shared routines.
2964 **/
2965static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2966{
2967 s32 ret_val = E1000_SUCCESS;
2968
2969 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
2970
2971 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2972 if ((hw->mac.type == e1000_pch2lan) &&
2973 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
2974 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
2975
2976 ret_val = e1000_phy_hw_reset_generic(hw);
2977 if (ret_val)
2978 return ret_val;
2979
2980 return e1000_post_phy_reset_ich8lan(hw);
2981}
2982
2983/**
2984 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2985 * @hw: pointer to the HW structure
2986 * @active: TRUE to enable LPLU, FALSE to disable
2987 *
2988 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2989 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2990 * the phy speed. This function will manually set the LPLU bit and restart
2991 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2992 * since it configures the same bit.
2993 **/
2994static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2995{
2996 s32 ret_val;
2997 u16 oem_reg;
2998
2999 DEBUGFUNC("e1000_set_lplu_state_pchlan");
3000 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3001 if (ret_val)
3002 return ret_val;
3003
3004 if (active)
3005 oem_reg |= HV_OEM_BITS_LPLU;
3006 else
3007 oem_reg &= ~HV_OEM_BITS_LPLU;
3008
3009 if (!hw->phy.ops.check_reset_block(hw))
3010 oem_reg |= HV_OEM_BITS_RESTART_AN;
3011
3012 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3013}
3014
3015/**
3016 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3017 * @hw: pointer to the HW structure
3018 * @active: TRUE to enable LPLU, FALSE to disable
3019 *
3020 * Sets the LPLU D0 state according to the active flag. When
3021 * activating LPLU this function also disables smart speed
3022 * and vice versa. LPLU will not be activated unless the
3023 * device autonegotiation advertisement meets standards of
3024 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3025 * This is a function pointer entry point only called by
3026 * PHY setup routines.
3027 **/
3028static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3029{
3030 struct e1000_phy_info *phy = &hw->phy;
3031 u32 phy_ctrl;
3032 s32 ret_val = E1000_SUCCESS;
3033 u16 data;
3034
3035 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3036
3037 if (phy->type == e1000_phy_ife)
3038 return E1000_SUCCESS;
3039
3040 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3041
3042 if (active) {
3043 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3044 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3045
3046 if (phy->type != e1000_phy_igp_3)
3047 return E1000_SUCCESS;
3048
3049 /* Call gig speed drop workaround on LPLU before accessing
3050 * any PHY registers
3051 */
3052 if (hw->mac.type == e1000_ich8lan)
3053 e1000_gig_downshift_workaround_ich8lan(hw);
3054
3055 /* When LPLU is enabled, we should disable SmartSpeed */
3056 ret_val = phy->ops.read_reg(hw,
3057 IGP01E1000_PHY_PORT_CONFIG,
3058 &data);
3059 if (ret_val)
3060 return ret_val;
3061 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3062 ret_val = phy->ops.write_reg(hw,
3063 IGP01E1000_PHY_PORT_CONFIG,
3064 data);
3065 if (ret_val)
3066 return ret_val;
3067 } else {
3068 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3069 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3070
3071 if (phy->type != e1000_phy_igp_3)
3072 return E1000_SUCCESS;
3073
3074 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3075 * during Dx states where the power conservation is most
3076 * important. During driver activity we should enable
3077 * SmartSpeed, so performance is maintained.
3078 */
3079 if (phy->smart_speed == e1000_smart_speed_on) {
3080 ret_val = phy->ops.read_reg(hw,
3081 IGP01E1000_PHY_PORT_CONFIG,
3082 &data);
3083 if (ret_val)
3084 return ret_val;
3085
3086 data |= IGP01E1000_PSCFR_SMART_SPEED;
3087 ret_val = phy->ops.write_reg(hw,
3088 IGP01E1000_PHY_PORT_CONFIG,
3089 data);
3090 if (ret_val)
3091 return ret_val;
3092 } else if (phy->smart_speed == e1000_smart_speed_off) {
3093 ret_val = phy->ops.read_reg(hw,
3094 IGP01E1000_PHY_PORT_CONFIG,
3095 &data);
3096 if (ret_val)
3097 return ret_val;
3098
3099 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3100 ret_val = phy->ops.write_reg(hw,
3101 IGP01E1000_PHY_PORT_CONFIG,
3102 data);
3103 if (ret_val)
3104 return ret_val;
3105 }
3106 }
3107
3108 return E1000_SUCCESS;
3109}
3110
3111/**
3112 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3113 * @hw: pointer to the HW structure
3114 * @active: TRUE to enable LPLU, FALSE to disable
3115 *
3116 * Sets the LPLU D3 state according to the active flag. When
3117 * activating LPLU this function also disables smart speed
3118 * and vice versa. LPLU will not be activated unless the
3119 * device autonegotiation advertisement meets standards of
3120 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3121 * This is a function pointer entry point only called by
3122 * PHY setup routines.
3123 **/
3124static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3125{
3126 struct e1000_phy_info *phy = &hw->phy;
3127 u32 phy_ctrl;
3128 s32 ret_val = E1000_SUCCESS;
3129 u16 data;
3130
3131 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3132
3133 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3134
3135 if (!active) {
3136 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3137 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3138
3139 if (phy->type != e1000_phy_igp_3)
3140 return E1000_SUCCESS;
3141
3142 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3143 * during Dx states where the power conservation is most
3144 * important. During driver activity we should enable
3145 * SmartSpeed, so performance is maintained.
3146 */
3147 if (phy->smart_speed == e1000_smart_speed_on) {
3148 ret_val = phy->ops.read_reg(hw,
3149 IGP01E1000_PHY_PORT_CONFIG,
3150 &data);
3151 if (ret_val)
3152 return ret_val;
3153
3154 data |= IGP01E1000_PSCFR_SMART_SPEED;
3155 ret_val = phy->ops.write_reg(hw,
3156 IGP01E1000_PHY_PORT_CONFIG,
3157 data);
3158 if (ret_val)
3159 return ret_val;
3160 } else if (phy->smart_speed == e1000_smart_speed_off) {
3161 ret_val = phy->ops.read_reg(hw,
3162 IGP01E1000_PHY_PORT_CONFIG,
3163 &data);
3164 if (ret_val)
3165 return ret_val;
3166
3167 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3168 ret_val = phy->ops.write_reg(hw,
3169 IGP01E1000_PHY_PORT_CONFIG,
3170 data);
3171 if (ret_val)
3172 return ret_val;
3173 }
3174 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3175 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3176 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3177 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3178 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3179
3180 if (phy->type != e1000_phy_igp_3)
3181 return E1000_SUCCESS;
3182
3183 /* Call gig speed drop workaround on LPLU before accessing
3184 * any PHY registers
3185 */
3186 if (hw->mac.type == e1000_ich8lan)
3187 e1000_gig_downshift_workaround_ich8lan(hw);
3188
3189 /* When LPLU is enabled, we should disable SmartSpeed */
3190 ret_val = phy->ops.read_reg(hw,
3191 IGP01E1000_PHY_PORT_CONFIG,
3192 &data);
3193 if (ret_val)
3194 return ret_val;
3195
3196 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3197 ret_val = phy->ops.write_reg(hw,
3198 IGP01E1000_PHY_PORT_CONFIG,
3199 data);
3200 }
3201
3202 return ret_val;
3203}
3204
3205/**
3206 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3207 * @hw: pointer to the HW structure
3208 * @bank: pointer to the variable that returns the active bank
3209 *
3210 * Reads signature byte from the NVM using the flash access registers.
3211 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3212 **/
3213static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3214{
3215 u32 eecd;
3216 struct e1000_nvm_info *nvm = &hw->nvm;
3217 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3218 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3219 u8 sig_byte = 0;
3220 s32 ret_val;
3221
3222 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3223
3224 switch (hw->mac.type) {
3225 case e1000_ich8lan:
3226 case e1000_ich9lan:
3227 eecd = E1000_READ_REG(hw, E1000_EECD);
3228 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3229 E1000_EECD_SEC1VAL_VALID_MASK) {
3230 if (eecd & E1000_EECD_SEC1VAL)
3231 *bank = 1;
3232 else
3233 *bank = 0;
3234
3235 return E1000_SUCCESS;
3236 }
3237 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3238 /* fall-thru */
3239 default:
3240 /* set bank to 0 in case flash read fails */
3241 *bank = 0;
3242
3243 /* Check bank 0 */
3244 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3245 &sig_byte);
3246 if (ret_val)
3247 return ret_val;
3248 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3249 E1000_ICH_NVM_SIG_VALUE) {
3250 *bank = 0;
3251 return E1000_SUCCESS;
3252 }
3253
3254 /* Check bank 1 */
3255 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3256 bank1_offset,
3257 &sig_byte);
3258 if (ret_val)
3259 return ret_val;
3260 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3261 E1000_ICH_NVM_SIG_VALUE) {
3262 *bank = 1;
3263 return E1000_SUCCESS;
3264 }
3265
3266 DEBUGOUT("ERROR: No valid NVM bank present\n");
3267 return -E1000_ERR_NVM;
3268 }
3269}
3270
3271/**
3272 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3273 * @hw: pointer to the HW structure
3274 * @offset: The offset (in bytes) of the word(s) to read.
3275 * @words: Size of data to read in words
3276 * @data: Pointer to the word(s) to read at offset.
3277 *
3278 * Reads a word(s) from the NVM using the flash access registers.
3279 **/
3280static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3281 u16 *data)
3282{
3283 struct e1000_nvm_info *nvm = &hw->nvm;
3284 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3285 u32 act_offset;
3286 s32 ret_val = E1000_SUCCESS;
3287 u32 bank = 0;
3288 u16 i, word;
3289
3290 DEBUGFUNC("e1000_read_nvm_ich8lan");
3291
3292 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3293 (words == 0)) {
3294 DEBUGOUT("nvm parameter(s) out of bounds\n");
3295 ret_val = -E1000_ERR_NVM;
3296 goto out;
3297 }
3298
3299 nvm->ops.acquire(hw);
3300
3301 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3302 if (ret_val != E1000_SUCCESS) {
3303 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3304 bank = 0;
3305 }
3306
3307 act_offset = (bank) ? nvm->flash_bank_size : 0;
3308 act_offset += offset;
3309
3310 ret_val = E1000_SUCCESS;
3311 for (i = 0; i < words; i++) {
3312 if (dev_spec->shadow_ram[offset+i].modified) {
3313 data[i] = dev_spec->shadow_ram[offset+i].value;
3314 } else {
3315 ret_val = e1000_read_flash_word_ich8lan(hw,
3316 act_offset + i,
3317 &word);
3318 if (ret_val)
3319 break;
3320 data[i] = word;
3321 }
3322 }
3323
3324 nvm->ops.release(hw);
3325
3326out:
3327 if (ret_val)
3328 DEBUGOUT1("NVM read error: %d\n", ret_val);
3329
3330 return ret_val;
3331}
3332
3333/**
3334 * e1000_flash_cycle_init_ich8lan - Initialize flash
3335 * @hw: pointer to the HW structure
3336 *
3337 * This function does initial flash setup so that a new read/write/erase cycle
3338 * can be started.
3339 **/
3340static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3341{
3342 union ich8_hws_flash_status hsfsts;
3343 s32 ret_val = -E1000_ERR_NVM;
3344
3345 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3346
3347 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3348
3349 /* Check if the flash descriptor is valid */
3350 if (!hsfsts.hsf_status.fldesvalid) {
3351 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3352 return -E1000_ERR_NVM;
3353 }
3354
3355 /* Clear FCERR and DAEL in hw status by writing 1 */
3356 hsfsts.hsf_status.flcerr = 1;
3357 hsfsts.hsf_status.dael = 1;
3358 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3359
3360 /* Either we should have a hardware SPI cycle in progress
3361 * bit to check against, in order to start a new cycle or
3362 * FDONE bit should be changed in the hardware so that it
3363 * is 1 after hardware reset, which can then be used as an
3364 * indication whether a cycle is in progress or has been
3365 * completed.
3366 */
3367
3368 if (!hsfsts.hsf_status.flcinprog) {
3369 /* There is no cycle running at present,
3370 * so we can start a cycle.
3371 * Begin by setting Flash Cycle Done.
3372 */
3373 hsfsts.hsf_status.flcdone = 1;
3374 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3375 ret_val = E1000_SUCCESS;
3376 } else {
3377 s32 i;
3378
3379 /* Otherwise poll for sometime so the current
3380 * cycle has a chance to end before giving up.
3381 */
3382 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3383 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3384 ICH_FLASH_HSFSTS);
3385 if (!hsfsts.hsf_status.flcinprog) {
3386 ret_val = E1000_SUCCESS;
3387 break;
3388 }
3389 usec_delay(1);
3390 }
3391 if (ret_val == E1000_SUCCESS) {
3392 /* Successful in waiting for previous cycle to timeout,
3393 * now set the Flash Cycle Done.
3394 */
3395 hsfsts.hsf_status.flcdone = 1;
3396 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3397 hsfsts.regval);
3398 } else {
3399 DEBUGOUT("Flash controller busy, cannot get access\n");
3400 }
3401 }
3402
3403 return ret_val;
3404}
3405
3406/**
3407 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3408 * @hw: pointer to the HW structure
3409 * @timeout: maximum time to wait for completion
3410 *
3411 * This function starts a flash cycle and waits for its completion.
3412 **/
3413static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3414{
3415 union ich8_hws_flash_ctrl hsflctl;
3416 union ich8_hws_flash_status hsfsts;
3417 u32 i = 0;
3418
3419 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3420
3421 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3422 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3423 hsflctl.hsf_ctrl.flcgo = 1;
3424
3425 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3426
3427 /* wait till FDONE bit is set to 1 */
3428 do {
3429 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3430 if (hsfsts.hsf_status.flcdone)
3431 break;
3432 usec_delay(1);
3433 } while (i++ < timeout);
3434
3435 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3436 return E1000_SUCCESS;
3437
3438 return -E1000_ERR_NVM;
3439}
3440
3441/**
3442 * e1000_read_flash_word_ich8lan - Read word from flash
3443 * @hw: pointer to the HW structure
3444 * @offset: offset to data location
3445 * @data: pointer to the location for storing the data
3446 *
3447 * Reads the flash word at offset into data. Offset is converted
3448 * to bytes before read.
3449 **/
3450static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3451 u16 *data)
3452{
3453 DEBUGFUNC("e1000_read_flash_word_ich8lan");
3454
3455 if (!data)
3456 return -E1000_ERR_NVM;
3457
3458 /* Must convert offset into bytes. */
3459 offset <<= 1;
3460
3461 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3462}
3463
3464/**
3465 * e1000_read_flash_byte_ich8lan - Read byte from flash
3466 * @hw: pointer to the HW structure
3467 * @offset: The offset of the byte to read.
3468 * @data: Pointer to a byte to store the value read.
3469 *
3470 * Reads a single byte from the NVM using the flash access registers.
3471 **/
3472static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3473 u8 *data)
3474{
3475 s32 ret_val;
3476 u16 word = 0;
3477
3478 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3479
3480 if (ret_val)
3481 return ret_val;
3482
3483 *data = (u8)word;
3484
3485 return E1000_SUCCESS;
3486}
3487
3488/**
3489 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3490 * @hw: pointer to the HW structure
3491 * @offset: The offset (in bytes) of the byte or word to read.
3492 * @size: Size of data to read, 1=byte 2=word
3493 * @data: Pointer to the word to store the value read.
3494 *
3495 * Reads a byte or word from the NVM using the flash access registers.
3496 **/
3497static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3498 u8 size, u16 *data)
3499{
3500 union ich8_hws_flash_status hsfsts;
3501 union ich8_hws_flash_ctrl hsflctl;
3502 u32 flash_linear_addr;
3503 u32 flash_data = 0;
3504 s32 ret_val = -E1000_ERR_NVM;
3505 u8 count = 0;
3506
3507 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3508
3509 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3510 return -E1000_ERR_NVM;
3511 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3512 hw->nvm.flash_base_addr);
3513
3514 do {
3515 usec_delay(1);
3516 /* Steps */
3517 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3518 if (ret_val != E1000_SUCCESS)
3519 break;
3520 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3521
3522 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3523 hsflctl.hsf_ctrl.fldbcount = size - 1;
3524 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3525 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3526 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3527
3528 ret_val = e1000_flash_cycle_ich8lan(hw,
3529 ICH_FLASH_READ_COMMAND_TIMEOUT);
3530
3531 /* Check if FCERR is set to 1, if set to 1, clear it
3532 * and try the whole sequence a few more times, else
3533 * read in (shift in) the Flash Data0, the order is
3534 * least significant byte first msb to lsb
3535 */
3536 if (ret_val == E1000_SUCCESS) {
3537 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3538 if (size == 1)
3539 *data = (u8)(flash_data & 0x000000FF);
3540 else if (size == 2)
3541 *data = (u16)(flash_data & 0x0000FFFF);
3542 break;
3543 } else {
3544 /* If we've gotten here, then things are probably
3545 * completely hosed, but if the error condition is
3546 * detected, it won't hurt to give it another try...
3547 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3548 */
3549 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3550 ICH_FLASH_HSFSTS);
3551 if (hsfsts.hsf_status.flcerr) {
3552 /* Repeat for some time before giving up. */
3553 continue;
3554 } else if (!hsfsts.hsf_status.flcdone) {
3555 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3556 break;
3557 }
3558 }
3559 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3560
3561 return ret_val;
3562}
3563
3564
3565/**
3566 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3567 * @hw: pointer to the HW structure
3568 * @offset: The offset (in bytes) of the word(s) to write.
3569 * @words: Size of data to write in words
3570 * @data: Pointer to the word(s) to write at offset.
3571 *
3572 * Writes a byte or word to the NVM using the flash access registers.
3573 **/
3574static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3575 u16 *data)
3576{
3577 struct e1000_nvm_info *nvm = &hw->nvm;
3578 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3579 u16 i;
3580
3581 DEBUGFUNC("e1000_write_nvm_ich8lan");
3582
3583 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3584 (words == 0)) {
3585 DEBUGOUT("nvm parameter(s) out of bounds\n");
3586 return -E1000_ERR_NVM;
3587 }
3588
3589 nvm->ops.acquire(hw);
3590
3591 for (i = 0; i < words; i++) {
3592 dev_spec->shadow_ram[offset+i].modified = TRUE;
3593 dev_spec->shadow_ram[offset+i].value = data[i];
3594 }
3595
3596 nvm->ops.release(hw);
3597
3598 return E1000_SUCCESS;
3599}
3600
3601/**
3602 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3603 * @hw: pointer to the HW structure
3604 *
3605 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3606 * which writes the checksum to the shadow ram. The changes in the shadow
3607 * ram are then committed to the EEPROM by processing each bank at a time
3608 * checking for the modified bit and writing only the pending changes.
3609 * After a successful commit, the shadow ram is cleared and is ready for
3610 * future writes.
3611 **/
3612static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3613{
3614 struct e1000_nvm_info *nvm = &hw->nvm;
3615 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3616 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3617 s32 ret_val;
3618 u16 data = 0;
3619
3620 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
3621
3622 ret_val = e1000_update_nvm_checksum_generic(hw);
3623 if (ret_val)
3624 goto out;
3625
3626 if (nvm->type != e1000_nvm_flash_sw)
3627 goto out;
3628
3629 nvm->ops.acquire(hw);
3630
3631 /* We're writing to the opposite bank so if we're on bank 1,
3632 * write to bank 0 etc. We also need to erase the segment that
3633 * is going to be written
3634 */
3635 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3636 if (ret_val != E1000_SUCCESS) {
3637 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3638 bank = 0;
3639 }
3640
3641 if (bank == 0) {
3642 new_bank_offset = nvm->flash_bank_size;
3643 old_bank_offset = 0;
3644 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3645 if (ret_val)
3646 goto release;
3647 } else {
3648 old_bank_offset = nvm->flash_bank_size;
3649 new_bank_offset = 0;
3650 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3651 if (ret_val)
3652 goto release;
3653 }
3654 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3655 if (dev_spec->shadow_ram[i].modified) {
3656 data = dev_spec->shadow_ram[i].value;
3657 } else {
3658 ret_val = e1000_read_flash_word_ich8lan(hw, i +
3659 old_bank_offset,
3660 &data);
3661 if (ret_val)
3662 break;
3663 }
3664 /* If the word is 0x13, then make sure the signature bits
3665 * (15:14) are 11b until the commit has completed.
3666 * This will allow us to write 10b which indicates the
3667 * signature is valid. We want to do this after the write
3668 * has completed so that we don't mark the segment valid
3669 * while the write is still in progress
3670 */
3671 if (i == E1000_ICH_NVM_SIG_WORD)
3672 data |= E1000_ICH_NVM_SIG_MASK;
3673
3674 /* Convert offset to bytes. */
3675 act_offset = (i + new_bank_offset) << 1;
3676
3677 usec_delay(100);
3678
3679 /* Write the bytes to the new bank. */
3680 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3681 act_offset,
3682 (u8)data);
3683 if (ret_val)
3684 break;
3685
3686 usec_delay(100);
3687 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3688 act_offset + 1,
3689 (u8)(data >> 8));
3690 if (ret_val)
3691 break;
3692 }
3693
3694 /* Don't bother writing the segment valid bits if sector
3695 * programming failed.
3696 */
3697 if (ret_val) {
3698 DEBUGOUT("Flash commit failed.\n");
3699 goto release;
3700 }
3701
3702 /* Finally validate the new segment by setting bit 15:14
3703 * to 10b in word 0x13 , this can be done without an
3704 * erase as well since these bits are 11 to start with
3705 * and we need to change bit 14 to 0b
3706 */
3707 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3708 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3709 if (ret_val)
3710 goto release;
3711
3712 data &= 0xBFFF;
3713 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
3714 (u8)(data >> 8));
3715 if (ret_val)
3716 goto release;
3717
3718 /* And invalidate the previously valid segment by setting
3719 * its signature word (0x13) high_byte to 0b. This can be
3720 * done without an erase because flash erase sets all bits
3721 * to 1's. We can write 1's to 0's without an erase
3722 */
3723 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3724
3725 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3726
3727 if (ret_val)
3728 goto release;
3729
3730 /* Great! Everything worked, we can now clear the cached entries. */
3731 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3732 dev_spec->shadow_ram[i].modified = FALSE;
3733 dev_spec->shadow_ram[i].value = 0xFFFF;
3734 }
3735
3736release:
3737 nvm->ops.release(hw);
3738
3739 /* Reload the EEPROM, or else modifications will not appear
3740 * until after the next adapter reset.
3741 */
3742 if (!ret_val) {
3743 nvm->ops.reload(hw);
3744 msec_delay(10);
3745 }
3746
3747out:
3748 if (ret_val)
3749 DEBUGOUT1("NVM update error: %d\n", ret_val);
3750
3751 return ret_val;
3752}
3753
3754/**
3755 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3756 * @hw: pointer to the HW structure
3757 *
3758 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3759 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
3760 * calculated, in which case we need to calculate the checksum and set bit 6.
3761 **/
3762static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3763{
3764 s32 ret_val;
3765 u16 data;
3766 u16 word;
3767 u16 valid_csum_mask;
3768
3769 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
3770
3771 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
3772 * the checksum needs to be fixed. This bit is an indication that
3773 * the NVM was prepared by OEM software and did not calculate
3774 * the checksum...a likely scenario.
3775 */
3776 switch (hw->mac.type) {
3777 case e1000_pch_lpt:
3778 word = NVM_COMPAT;
3779 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3780 break;
3781 default:
3782 word = NVM_FUTURE_INIT_WORD1;
3783 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3784 break;
3785 }
3786
3787 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
3788 if (ret_val)
3789 return ret_val;
3790
3791 if (!(data & valid_csum_mask)) {
3792 data |= valid_csum_mask;
3793 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
3794 if (ret_val)
3795 return ret_val;
3796 ret_val = hw->nvm.ops.update(hw);
3797 if (ret_val)
3798 return ret_val;
3799 }
3800
3801 return e1000_validate_nvm_checksum_generic(hw);
3802}
3803
3804/**
3805 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3806 * @hw: pointer to the HW structure
3807 * @offset: The offset (in bytes) of the byte/word to read.
3808 * @size: Size of data to read, 1=byte 2=word
3809 * @data: The byte(s) to write to the NVM.
3810 *
3811 * Writes one/two bytes to the NVM using the flash access registers.
3812 **/
3813static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3814 u8 size, u16 data)
3815{
3816 union ich8_hws_flash_status hsfsts;
3817 union ich8_hws_flash_ctrl hsflctl;
3818 u32 flash_linear_addr;
3819 u32 flash_data = 0;
3820 s32 ret_val;
3821 u8 count = 0;
3822
3823 DEBUGFUNC("e1000_write_ich8_data");
3824
3825 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3826 return -E1000_ERR_NVM;
3827
3828 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3829 hw->nvm.flash_base_addr);
3830
3831 do {
3832 usec_delay(1);
3833 /* Steps */
3834 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3835 if (ret_val != E1000_SUCCESS)
3836 break;
3837 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3838
3839 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3840 hsflctl.hsf_ctrl.fldbcount = size - 1;
3841 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3842 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3843
3844 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3845
3846 if (size == 1)
3847 flash_data = (u32)data & 0x00FF;
3848 else
3849 flash_data = (u32)data;
3850
3851 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
3852
3853 /* check if FCERR is set to 1 , if set to 1, clear it
3854 * and try the whole sequence a few more times else done
3855 */
3856 ret_val =
3857 e1000_flash_cycle_ich8lan(hw,
3858 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3859 if (ret_val == E1000_SUCCESS)
3860 break;
3861
3862 /* If we're here, then things are most likely
3863 * completely hosed, but if the error condition
3864 * is detected, it won't hurt to give it another
3865 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3866 */
3867 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3868 if (hsfsts.hsf_status.flcerr)
3869 /* Repeat for some time before giving up. */
3870 continue;
3871 if (!hsfsts.hsf_status.flcdone) {
3872 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3873 break;
3874 }
3875 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3876
3877 return ret_val;
3878}
3879
3880
3881/**
3882 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3883 * @hw: pointer to the HW structure
3884 * @offset: The index of the byte to read.
3885 * @data: The byte to write to the NVM.
3886 *
3887 * Writes a single byte to the NVM using the flash access registers.
3888 **/
3889static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3890 u8 data)
3891{
3892 u16 word = (u16)data;
3893
3894 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3895
3896 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3897}
3898
3899
3900
3901/**
3902 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3903 * @hw: pointer to the HW structure
3904 * @offset: The offset of the byte to write.
3905 * @byte: The byte to write to the NVM.
3906 *
3907 * Writes a single byte to the NVM using the flash access registers.
3908 * Goes through a retry algorithm before giving up.
3909 **/
3910static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3911 u32 offset, u8 byte)
3912{
3913 s32 ret_val;
3914 u16 program_retries;
3915
3916 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
3917
3918 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3919 if (!ret_val)
3920 return ret_val;
3921
3922 for (program_retries = 0; program_retries < 100; program_retries++) {
3923 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
3924 usec_delay(100);
3925 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3926 if (ret_val == E1000_SUCCESS)
3927 break;
3928 }
3929 if (program_retries == 100)
3930 return -E1000_ERR_NVM;
3931
3932 return E1000_SUCCESS;
3933}
3934
3935/**
3936 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3937 * @hw: pointer to the HW structure
3938 * @bank: 0 for first bank, 1 for second bank, etc.
3939 *
3940 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3941 * bank N is 4096 * N + flash_reg_addr.
3942 **/
3943static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3944{
3945 struct e1000_nvm_info *nvm = &hw->nvm;
3946 union ich8_hws_flash_status hsfsts;
3947 union ich8_hws_flash_ctrl hsflctl;
3948 u32 flash_linear_addr;
3949 /* bank size is in 16bit words - adjust to bytes */
3950 u32 flash_bank_size = nvm->flash_bank_size * 2;
3951 s32 ret_val;
3952 s32 count = 0;
3953 s32 j, iteration, sector_size;
3954
3955 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
3956
3957 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3958
3959 /* Determine HW Sector size: Read BERASE bits of hw flash status
3960 * register
3961 * 00: The Hw sector is 256 bytes, hence we need to erase 16
3962 * consecutive sectors. The start index for the nth Hw sector
3963 * can be calculated as = bank * 4096 + n * 256
3964 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3965 * The start index for the nth Hw sector can be calculated
3966 * as = bank * 4096
3967 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3968 * (ich9 only, otherwise error condition)
3969 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3970 */
3971 switch (hsfsts.hsf_status.berasesz) {
3972 case 0:
3973 /* Hw sector size 256 */
3974 sector_size = ICH_FLASH_SEG_SIZE_256;
3975 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3976 break;
3977 case 1:
3978 sector_size = ICH_FLASH_SEG_SIZE_4K;
3979 iteration = 1;
3980 break;
3981 case 2:
3982 sector_size = ICH_FLASH_SEG_SIZE_8K;
3983 iteration = 1;
3984 break;
3985 case 3:
3986 sector_size = ICH_FLASH_SEG_SIZE_64K;
3987 iteration = 1;
3988 break;
3989 default:
3990 return -E1000_ERR_NVM;
3991 }
3992
3993 /* Start with the base address, then add the sector offset. */
3994 flash_linear_addr = hw->nvm.flash_base_addr;
3995 flash_linear_addr += (bank) ? flash_bank_size : 0;
3996
3997 for (j = 0; j < iteration; j++) {
3998 do {
3999 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4000
4001 /* Steps */
4002 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4003 if (ret_val)
4004 return ret_val;
4005
4006 /* Write a value 11 (block Erase) in Flash
4007 * Cycle field in hw flash control
4008 */
4009 hsflctl.regval =
4010 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4011
4012 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4013 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4014 hsflctl.regval);
4015
4016 /* Write the last 24 bits of an index within the
4017 * block into Flash Linear address field in Flash
4018 * Address.
4019 */
4020 flash_linear_addr += (j * sector_size);
4021 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4022 flash_linear_addr);
4023
4024 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4025 if (ret_val == E1000_SUCCESS)
4026 break;
4027
4028 /* Check if FCERR is set to 1. If 1,
4029 * clear it and try the whole sequence
4030 * a few more times else Done
4031 */
4032 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4033 ICH_FLASH_HSFSTS);
4034 if (hsfsts.hsf_status.flcerr)
4035 /* repeat for some time before giving up */
4036 continue;
4037 else if (!hsfsts.hsf_status.flcdone)
4038 return ret_val;
4039 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4040 }
4041
4042 return E1000_SUCCESS;
4043}
4044
4045/**
4046 * e1000_valid_led_default_ich8lan - Set the default LED settings
4047 * @hw: pointer to the HW structure
4048 * @data: Pointer to the LED settings
4049 *
4050 * Reads the LED default settings from the NVM to data. If the NVM LED
4051 * settings is all 0's or F's, set the LED default to a valid LED default
4052 * setting.
4053 **/
4054static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4055{
4056 s32 ret_val;
4057
4058 DEBUGFUNC("e1000_valid_led_default_ich8lan");
4059
4060 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4061 if (ret_val) {
4062 DEBUGOUT("NVM Read Error\n");
4063 return ret_val;
4064 }
4065
4066 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4067 *data = ID_LED_DEFAULT_ICH8LAN;
4068
4069 return E1000_SUCCESS;
4070}
4071
4072/**
4073 * e1000_id_led_init_pchlan - store LED configurations
4074 * @hw: pointer to the HW structure
4075 *
4076 * PCH does not control LEDs via the LEDCTL register, rather it uses
4077 * the PHY LED configuration register.
4078 *
4079 * PCH also does not have an "always on" or "always off" mode which
4080 * complicates the ID feature. Instead of using the "on" mode to indicate
4081 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4082 * use "link_up" mode. The LEDs will still ID on request if there is no
4083 * link based on logic in e1000_led_[on|off]_pchlan().
4084 **/
4085static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4086{
4087 struct e1000_mac_info *mac = &hw->mac;
4088 s32 ret_val;
4089 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4090 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4091 u16 data, i, temp, shift;
4092
4093 DEBUGFUNC("e1000_id_led_init_pchlan");
4094
4095 /* Get default ID LED modes */
4096 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4097 if (ret_val)
4098 return ret_val;
4099
4100 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4101 mac->ledctl_mode1 = mac->ledctl_default;
4102 mac->ledctl_mode2 = mac->ledctl_default;
4103
4104 for (i = 0; i < 4; i++) {
4105 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4106 shift = (i * 5);
4107 switch (temp) {
4108 case ID_LED_ON1_DEF2:
4109 case ID_LED_ON1_ON2:
4110 case ID_LED_ON1_OFF2:
4111 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4112 mac->ledctl_mode1 |= (ledctl_on << shift);
4113 break;
4114 case ID_LED_OFF1_DEF2:
4115 case ID_LED_OFF1_ON2:
4116 case ID_LED_OFF1_OFF2:
4117 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4118 mac->ledctl_mode1 |= (ledctl_off << shift);
4119 break;
4120 default:
4121 /* Do nothing */
4122 break;
4123 }
4124 switch (temp) {
4125 case ID_LED_DEF1_ON2:
4126 case ID_LED_ON1_ON2:
4127 case ID_LED_OFF1_ON2:
4128 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4129 mac->ledctl_mode2 |= (ledctl_on << shift);
4130 break;
4131 case ID_LED_DEF1_OFF2:
4132 case ID_LED_ON1_OFF2:
4133 case ID_LED_OFF1_OFF2:
4134 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4135 mac->ledctl_mode2 |= (ledctl_off << shift);
4136 break;
4137 default:
4138 /* Do nothing */
4139 break;
4140 }
4141 }
4142
4143 return E1000_SUCCESS;
4144}
4145
4146/**
4147 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4148 * @hw: pointer to the HW structure
4149 *
4150 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4151 * register, so the the bus width is hard coded.
4152 **/
4153static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4154{
4155 struct e1000_bus_info *bus = &hw->bus;
4156 s32 ret_val;
4157
4158 DEBUGFUNC("e1000_get_bus_info_ich8lan");
4159
4160 ret_val = e1000_get_bus_info_pcie_generic(hw);
4161
4162 /* ICH devices are "PCI Express"-ish. They have
4163 * a configuration space, but do not contain
4164 * PCI Express Capability registers, so bus width
4165 * must be hardcoded.
4166 */
4167 if (bus->width == e1000_bus_width_unknown)
4168 bus->width = e1000_bus_width_pcie_x1;
4169
4170 return ret_val;
4171}
4172
4173/**
4174 * e1000_reset_hw_ich8lan - Reset the hardware
4175 * @hw: pointer to the HW structure
4176 *
4177 * Does a full reset of the hardware which includes a reset of the PHY and
4178 * MAC.
4179 **/
4180static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4181{
4182 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4183 u16 kum_cfg;
4184 u32 ctrl, reg;
4185 s32 ret_val;
4186
4187 DEBUGFUNC("e1000_reset_hw_ich8lan");
4188
4189 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4190 * on the last TLP read/write transaction when MAC is reset.
4191 */
4192 ret_val = e1000_disable_pcie_master_generic(hw);
4193 if (ret_val)
4194 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4195
4196 DEBUGOUT("Masking off all interrupts\n");
4197 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4198
4199 /* Disable the Transmit and Receive units. Then delay to allow
4200 * any pending transactions to complete before we hit the MAC
4201 * with the global reset.
4202 */
4203 E1000_WRITE_REG(hw, E1000_RCTL, 0);
4204 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4205 E1000_WRITE_FLUSH(hw);
4206
4207 msec_delay(10);
4208
4209 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4210 if (hw->mac.type == e1000_ich8lan) {
4211 /* Set Tx and Rx buffer allocation to 8k apiece. */
4212 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4213 /* Set Packet Buffer Size to 16k. */
4214 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4215 }
4216
4217 if (hw->mac.type == e1000_pchlan) {
4218 /* Save the NVM K1 bit setting*/
4219 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4220 if (ret_val)
4221 return ret_val;
4222
4223 if (kum_cfg & E1000_NVM_K1_ENABLE)
4224 dev_spec->nvm_k1_enabled = TRUE;
4225 else
4226 dev_spec->nvm_k1_enabled = FALSE;
4227 }
4228
4229 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4230
4231 if (!hw->phy.ops.check_reset_block(hw)) {
4232 /* Full-chip reset requires MAC and PHY reset at the same
4233 * time to make sure the interface between MAC and the
4234 * external PHY is reset.
4235 */
4236 ctrl |= E1000_CTRL_PHY_RST;
4237
4238 /* Gate automatic PHY configuration by hardware on
4239 * non-managed 82579
4240 */
4241 if ((hw->mac.type == e1000_pch2lan) &&
4242 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4243 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
4244 }
4245 ret_val = e1000_acquire_swflag_ich8lan(hw);
4246 DEBUGOUT("Issuing a global reset to ich8lan\n");
4247 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4248 /* cannot issue a flush here because it hangs the hardware */
4249 msec_delay(20);
4250
4251 /* Set Phy Config Counter to 50msec */
4252 if (hw->mac.type == e1000_pch2lan) {
4253 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4254 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4255 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4256 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4257 }
4258
4259 if (!ret_val)
4260 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4261
4262 if (ctrl & E1000_CTRL_PHY_RST) {
4263 ret_val = hw->phy.ops.get_cfg_done(hw);
4264 if (ret_val)
4265 return ret_val;
4266
4267 ret_val = e1000_post_phy_reset_ich8lan(hw);
4268 if (ret_val)
4269 return ret_val;
4270 }
4271
4272 /* For PCH, this write will make sure that any noise
4273 * will be detected as a CRC error and be dropped rather than show up
4274 * as a bad packet to the DMA engine.
4275 */
4276 if (hw->mac.type == e1000_pchlan)
4277 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4278
4279 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4280 E1000_READ_REG(hw, E1000_ICR);
4281
4282 reg = E1000_READ_REG(hw, E1000_KABGTXD);
4283 reg |= E1000_KABGTXD_BGSQLBIAS;
4284 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
4285
4286 return E1000_SUCCESS;
4287}
4288
4289/**
4290 * e1000_init_hw_ich8lan - Initialize the hardware
4291 * @hw: pointer to the HW structure
4292 *
4293 * Prepares the hardware for transmit and receive by doing the following:
4294 * - initialize hardware bits
4295 * - initialize LED identification
4296 * - setup receive address registers
4297 * - setup flow control
4298 * - setup transmit descriptors
4299 * - clear statistics
4300 **/
4301static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4302{
4303 struct e1000_mac_info *mac = &hw->mac;
4304 u32 ctrl_ext, txdctl, snoop;
4305 s32 ret_val;
4306 u16 i;
4307
4308 DEBUGFUNC("e1000_init_hw_ich8lan");
4309
4310 e1000_initialize_hw_bits_ich8lan(hw);
4311
4312 /* Initialize identification LED */
4313 ret_val = mac->ops.id_led_init(hw);
4314 /* An error is not fatal and we should not stop init due to this */
4315 if (ret_val)
4316 DEBUGOUT("Error initializing identification LED\n");
4317
4318 /* Setup the receive address. */
4319 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
4320
4321 /* Zero out the Multicast HASH table */
4322 DEBUGOUT("Zeroing the MTA\n");
4323 for (i = 0; i < mac->mta_reg_count; i++)
4324 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4325
4326 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4327 * the ME. Disable wakeup by clearing the host wakeup bit.
4328 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4329 */
4330 if (hw->phy.type == e1000_phy_82578) {
4331 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
4332 i &= ~BM_WUC_HOST_WU_BIT;
4333 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
4334 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4335 if (ret_val)
4336 return ret_val;
4337 }
4338
4339 /* Setup link and flow control */
4340 ret_val = mac->ops.setup_link(hw);
4341
4342 /* Set the transmit descriptor write-back policy for both queues */
4343 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
4344 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4345 E1000_TXDCTL_FULL_TX_DESC_WB);
4346 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4347 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4348 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
4349 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
4350 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4351 E1000_TXDCTL_FULL_TX_DESC_WB);
4352 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4353 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4354 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
4355
4356 /* ICH8 has opposite polarity of no_snoop bits.
4357 * By default, we should use snoop behavior.
4358 */
4359 if (mac->type == e1000_ich8lan)
4360 snoop = PCIE_ICH8_SNOOP_ALL;
4361 else
4362 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
4363 e1000_set_pcie_no_snoop_generic(hw, snoop);
4364
4365 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
4366 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4367 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
4368
4369 /* Clear all of the statistics registers (clear on read). It is
4370 * important that we do this after we have tried to establish link
4371 * because the symbol error count will increment wildly if there
4372 * is no link.
4373 */
4374 e1000_clear_hw_cntrs_ich8lan(hw);
4375
4376 return ret_val;
4377}
4378
4379/**
4380 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4381 * @hw: pointer to the HW structure
4382 *
4383 * Sets/Clears required hardware bits necessary for correctly setting up the
4384 * hardware for transmit and receive.
4385 **/
4386static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4387{
4388 u32 reg;
4389
4390 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
4391
4392 /* Extended Device Control */
4393 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
4394 reg |= (1 << 22);
4395 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4396 if (hw->mac.type >= e1000_pchlan)
4397 reg |= E1000_CTRL_EXT_PHYPDEN;
4398 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
4399
4400 /* Transmit Descriptor Control 0 */
4401 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
4402 reg |= (1 << 22);
4403 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
4404
4405 /* Transmit Descriptor Control 1 */
4406 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
4407 reg |= (1 << 22);
4408 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
4409
4410 /* Transmit Arbitration Control 0 */
4411 reg = E1000_READ_REG(hw, E1000_TARC(0));
4412 if (hw->mac.type == e1000_ich8lan)
4413 reg |= (1 << 28) | (1 << 29);
4414 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4415 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
4416
4417 /* Transmit Arbitration Control 1 */
4418 reg = E1000_READ_REG(hw, E1000_TARC(1));
4419 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
4420 reg &= ~(1 << 28);
4421 else
4422 reg |= (1 << 28);
4423 reg |= (1 << 24) | (1 << 26) | (1 << 30);
4424 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
4425
4426 /* Device Status */
4427 if (hw->mac.type == e1000_ich8lan) {
4428 reg = E1000_READ_REG(hw, E1000_STATUS);
4429 reg &= ~(1 << 31);
4430 E1000_WRITE_REG(hw, E1000_STATUS, reg);
4431 }
4432
4433 /* work-around descriptor data corruption issue during nfs v2 udp
4434 * traffic, just disable the nfs filtering capability
4435 */
4436 reg = E1000_READ_REG(hw, E1000_RFCTL);
4437 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4438
4439 /* Disable IPv6 extension header parsing because some malformed
4440 * IPv6 headers can hang the Rx.
4441 */
4442 if (hw->mac.type == e1000_ich8lan)
4443 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4444 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
4445
4446 /* Enable ECC on Lynxpoint */
4447 if (hw->mac.type == e1000_pch_lpt) {
4448 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
4449 reg |= E1000_PBECCSTS_ECC_ENABLE;
4450 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
4451
4452 reg = E1000_READ_REG(hw, E1000_CTRL);
4453 reg |= E1000_CTRL_MEHE;
4454 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4455 }
4456
4457 return;
4458}
4459
4460/**
4461 * e1000_setup_link_ich8lan - Setup flow control and link settings
4462 * @hw: pointer to the HW structure
4463 *
4464 * Determines which flow control settings to use, then configures flow
4465 * control. Calls the appropriate media-specific link configuration
4466 * function. Assuming the adapter has a valid link partner, a valid link
4467 * should be established. Assumes the hardware has previously been reset
4468 * and the transmitter and receiver are not enabled.
4469 **/
4470static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4471{
4472 s32 ret_val;
4473
4474 DEBUGFUNC("e1000_setup_link_ich8lan");
4475
4476 if (hw->phy.ops.check_reset_block(hw))
4477 return E1000_SUCCESS;
4478
4479 /* ICH parts do not have a word in the NVM to determine
4480 * the default flow control setting, so we explicitly
4481 * set it to full.
4482 */
4483 if (hw->fc.requested_mode == e1000_fc_default)
4484 hw->fc.requested_mode = e1000_fc_full;
4485
4486 /* Save off the requested flow control mode for use later. Depending
4487 * on the link partner's capabilities, we may or may not use this mode.
4488 */
4489 hw->fc.current_mode = hw->fc.requested_mode;
4490
4491 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
4492 hw->fc.current_mode);
4493
4494 /* Continue to configure the copper link. */
4495 ret_val = hw->mac.ops.setup_physical_interface(hw);
4496 if (ret_val)
4497 return ret_val;
4498
4499 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
4500 if ((hw->phy.type == e1000_phy_82578) ||
4501 (hw->phy.type == e1000_phy_82579) ||
4502 (hw->phy.type == e1000_phy_i217) ||
4503 (hw->phy.type == e1000_phy_82577)) {
4504 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
4505
4506 ret_val = hw->phy.ops.write_reg(hw,
4507 PHY_REG(BM_PORT_CTRL_PAGE, 27),
4508 hw->fc.pause_time);
4509 if (ret_val)
4510 return ret_val;
4511 }
4512
4513 return e1000_set_fc_watermarks_generic(hw);
4514}
4515
4516/**
4517 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4518 * @hw: pointer to the HW structure
4519 *
4520 * Configures the kumeran interface to the PHY to wait the appropriate time
4521 * when polling the PHY, then call the generic setup_copper_link to finish
4522 * configuring the copper link.
4523 **/
4524static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4525{
4526 u32 ctrl;
4527 s32 ret_val;
4528 u16 reg_data;
4529
4530 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
4531
4532 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4533 ctrl |= E1000_CTRL_SLU;
4534 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4535 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4536
4537 /* Set the mac to wait the maximum time between each iteration
4538 * and increase the max iterations when polling the phy;
4539 * this fixes erroneous timeouts at 10Mbps.
4540 */
4541 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
4542 0xFFFF);
4543 if (ret_val)
4544 return ret_val;
4545 ret_val = e1000_read_kmrn_reg_generic(hw,
4546 E1000_KMRNCTRLSTA_INBAND_PARAM,
4547 &reg_data);
4548 if (ret_val)
4549 return ret_val;
4550 reg_data |= 0x3F;
4551 ret_val = e1000_write_kmrn_reg_generic(hw,
4552 E1000_KMRNCTRLSTA_INBAND_PARAM,
4553 reg_data);
4554 if (ret_val)
4555 return ret_val;
4556
4557 switch (hw->phy.type) {
4558 case e1000_phy_igp_3:
4559 ret_val = e1000_copper_link_setup_igp(hw);
4560 if (ret_val)
4561 return ret_val;
4562 break;
4563 case e1000_phy_bm:
4564 case e1000_phy_82578:
4565 ret_val = e1000_copper_link_setup_m88(hw);
4566 if (ret_val)
4567 return ret_val;
4568 break;
4569 case e1000_phy_82577:
4570 case e1000_phy_82579:
4571 ret_val = e1000_copper_link_setup_82577(hw);
4572 if (ret_val)
4573 return ret_val;
4574 break;
4575 case e1000_phy_ife:
4576 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
4577 &reg_data);
4578 if (ret_val)
4579 return ret_val;
4580
4581 reg_data &= ~IFE_PMC_AUTO_MDIX;
4582
4583 switch (hw->phy.mdix) {
4584 case 1:
4585 reg_data &= ~IFE_PMC_FORCE_MDIX;
4586 break;
4587 case 2:
4588 reg_data |= IFE_PMC_FORCE_MDIX;
4589 break;
4590 case 0:
4591 default:
4592 reg_data |= IFE_PMC_AUTO_MDIX;
4593 break;
4594 }
4595 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
4596 reg_data);
4597 if (ret_val)
4598 return ret_val;
4599 break;
4600 default:
4601 break;
4602 }
4603
4604 return e1000_setup_copper_link_generic(hw);
4605}
4606
4607/**
4608 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4609 * @hw: pointer to the HW structure
4610 *
4611 * Calls the PHY specific link setup function and then calls the
4612 * generic setup_copper_link to finish configuring the link for
4613 * Lynxpoint PCH devices
4614 **/
4615static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4616{
4617 u32 ctrl;
4618 s32 ret_val;
4619
4620 DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
4621
4622 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4623 ctrl |= E1000_CTRL_SLU;
4624 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4625 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4626
4627 ret_val = e1000_copper_link_setup_82577(hw);
4628 if (ret_val)
4629 return ret_val;
4630
4631 return e1000_setup_copper_link_generic(hw);
4632}
4633
4634/**
4635 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4636 * @hw: pointer to the HW structure
4637 * @speed: pointer to store current link speed
4638 * @duplex: pointer to store the current link duplex
4639 *
4640 * Calls the generic get_speed_and_duplex to retrieve the current link
4641 * information and then calls the Kumeran lock loss workaround for links at
4642 * gigabit speeds.
4643 **/
4644static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4645 u16 *duplex)
4646{
4647 s32 ret_val;
4648
4649 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
4650
4651 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
4652 if (ret_val)
4653 return ret_val;
4654
4655 if ((hw->mac.type == e1000_ich8lan) &&
4656 (hw->phy.type == e1000_phy_igp_3) &&
4657 (*speed == SPEED_1000)) {
4658 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4659 }
4660
4661 return ret_val;
4662}
4663
4664/**
4665 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4666 * @hw: pointer to the HW structure
4667 *
4668 * Work-around for 82566 Kumeran PCS lock loss:
4669 * On link status change (i.e. PCI reset, speed change) and link is up and
4670 * speed is gigabit-
4671 * 0) if workaround is optionally disabled do nothing
4672 * 1) wait 1ms for Kumeran link to come up
4673 * 2) check Kumeran Diagnostic register PCS lock loss bit
4674 * 3) if not set the link is locked (all is good), otherwise...
4675 * 4) reset the PHY
4676 * 5) repeat up to 10 times
4677 * Note: this is only called for IGP3 copper when speed is 1gb.
4678 **/
4679static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4680{
4681 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4682 u32 phy_ctrl;
4683 s32 ret_val;
4684 u16 i, data;
4685 bool link;
4686
4687 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
4688
4689 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4690 return E1000_SUCCESS;
4691
4692 /* Make sure link is up before proceeding. If not just return.
4693 * Attempting this while link is negotiating fouled up link
4694 * stability
4695 */
4696 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
4697 if (!link)
4698 return E1000_SUCCESS;
4699
4700 for (i = 0; i < 10; i++) {
4701 /* read once to clear */
4702 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4703 if (ret_val)
4704 return ret_val;
4705 /* and again to get new status */
4706 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4707 if (ret_val)
4708 return ret_val;
4709
4710 /* check for PCS lock */
4711 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4712 return E1000_SUCCESS;
4713
4714 /* Issue PHY reset */
4715 hw->phy.ops.reset(hw);
4716 msec_delay_irq(5);
4717 }
4718 /* Disable GigE link negotiation */
4719 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4720 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4721 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4722 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4723
4724 /* Call gig speed drop workaround on Gig disable before accessing
4725 * any PHY registers
4726 */
4727 e1000_gig_downshift_workaround_ich8lan(hw);
4728
4729 /* unable to acquire PCS lock */
4730 return -E1000_ERR_PHY;
4731}
4732
4733/**
4734 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4735 * @hw: pointer to the HW structure
4736 * @state: boolean value used to set the current Kumeran workaround state
4737 *
4738 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
4739 * /disabled - FALSE).
4740 **/
4741void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4742 bool state)
4743{
4744 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4745
4746 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
4747
4748 if (hw->mac.type != e1000_ich8lan) {
4749 DEBUGOUT("Workaround applies to ICH8 only.\n");
4750 return;
4751 }
4752
4753 dev_spec->kmrn_lock_loss_workaround_enabled = state;
4754
4755 return;
4756}
4757
4758/**
4759 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4760 * @hw: pointer to the HW structure
4761 *
4762 * Workaround for 82566 power-down on D3 entry:
4763 * 1) disable gigabit link
4764 * 2) write VR power-down enable
4765 * 3) read it back
4766 * Continue if successful, else issue LCD reset and repeat
4767 **/
4768void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4769{
4770 u32 reg;
4771 u16 data;
4772 u8 retry = 0;
4773
4774 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
4775
4776 if (hw->phy.type != e1000_phy_igp_3)
4777 return;
4778
4779 /* Try the workaround twice (if needed) */
4780 do {
4781 /* Disable link */
4782 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
4783 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4784 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4785 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
4786
4787 /* Call gig speed drop workaround on Gig disable before
4788 * accessing any PHY registers
4789 */
4790 if (hw->mac.type == e1000_ich8lan)
4791 e1000_gig_downshift_workaround_ich8lan(hw);
4792
4793 /* Write VR power-down enable */
4794 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4795 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4796 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
4797 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4798
4799 /* Read it back and test */
4800 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4801 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4802 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4803 break;
4804
4805 /* Issue PHY reset and repeat at most one more time */
4806 reg = E1000_READ_REG(hw, E1000_CTRL);
4807 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
4808 retry++;
4809 } while (retry);
4810}
4811
4812/**
4813 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4814 * @hw: pointer to the HW structure
4815 *
4816 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4817 * LPLU, Gig disable, MDIC PHY reset):
4818 * 1) Set Kumeran Near-end loopback
4819 * 2) Clear Kumeran Near-end loopback
4820 * Should only be called for ICH8[m] devices with any 1G Phy.
4821 **/
4822void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4823{
4824 s32 ret_val;
4825 u16 reg_data;
4826
4827 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
4828
4829 if ((hw->mac.type != e1000_ich8lan) ||
4830 (hw->phy.type == e1000_phy_ife))
4831 return;
4832
4833 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4834 &reg_data);
4835 if (ret_val)
4836 return;
4837 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4838 ret_val = e1000_write_kmrn_reg_generic(hw,
4839 E1000_KMRNCTRLSTA_DIAG_OFFSET,
4840 reg_data);
4841 if (ret_val)
4842 return;
4843 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4844 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4845 reg_data);
4846}
4847
4848/**
4849 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4850 * @hw: pointer to the HW structure
4851 *
4852 * During S0 to Sx transition, it is possible the link remains at gig
4853 * instead of negotiating to a lower speed. Before going to Sx, set
4854 * 'Gig Disable' to force link speed negotiation to a lower speed based on
4855 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
4856 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4857 * needs to be written.
4858 * Parts that support (and are linked to a partner which support) EEE in
4859 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4860 * than 10Mbps w/o EEE.
4861 **/
4862void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4863{
4864 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4865 u32 phy_ctrl;
4866 s32 ret_val;
4867
4868 DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
4869
4870 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4871 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4872
4873 if (hw->phy.type == e1000_phy_i217) {
4874 u16 phy_reg, device_id = hw->device_id;
4875
4876 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4877 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4878 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4879 (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4880 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4881
4882 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
4883 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4884 }
4885
4886 ret_val = hw->phy.ops.acquire(hw);
4887 if (ret_val)
4888 goto out;
4889
4890 if (!dev_spec->eee_disable) {
4891 u16 eee_advert;
4892
4893 ret_val =
4894 e1000_read_emi_reg_locked(hw,
4895 I217_EEE_ADVERTISEMENT,
4896 &eee_advert);
4897 if (ret_val)
4898 goto release;
4899
4900 /* Disable LPLU if both link partners support 100BaseT
4901 * EEE and 100Full is advertised on both ends of the
4902 * link, and enable Auto Enable LPI since there will
4903 * be no driver to enable LPI while in Sx.
4904 */
4905 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4906 (dev_spec->eee_lp_ability &
4907 I82579_EEE_100_SUPPORTED) &&
4908 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
4909 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4910 E1000_PHY_CTRL_NOND0A_LPLU);
4911
4912 /* Set Auto Enable LPI after link up */
4913 hw->phy.ops.read_reg_locked(hw,
4914 I217_LPI_GPIO_CTRL,
4915 &phy_reg);
4916 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4917 hw->phy.ops.write_reg_locked(hw,
4918 I217_LPI_GPIO_CTRL,
4919 phy_reg);
4920 }
4921 }
4922
4923 /* For i217 Intel Rapid Start Technology support,
4924 * when the system is going into Sx and no manageability engine
4925 * is present, the driver must configure proxy to reset only on
4926 * power good. LPI (Low Power Idle) state must also reset only
4927 * on power good, as well as the MTA (Multicast table array).
4928 * The SMBus release must also be disabled on LCD reset.
4929 */
4930 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4931 E1000_ICH_FWSM_FW_VALID)) {
4932 /* Enable proxy to reset only on power good. */
4933 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
4934 &phy_reg);
4935 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4936 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
4937 phy_reg);
4938
4939 /* Set bit enable LPI (EEE) to reset only on
4940 * power good.
4941 */
4942 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
4943 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4944 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
4945
4946 /* Disable the SMB release on LCD reset. */
4947 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
4948 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4949 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4950 }
4951
4952 /* Enable MTA to reset for Intel Rapid Start Technology
4953 * Support
4954 */
4955 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
4956 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4957 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4958
4959release:
4960 hw->phy.ops.release(hw);
4961 }
4962out:
4963 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4964
4965 if (hw->mac.type == e1000_ich8lan)
4966 e1000_gig_downshift_workaround_ich8lan(hw);
4967
4968 if (hw->mac.type >= e1000_pchlan) {
4969 e1000_oem_bits_config_ich8lan(hw, FALSE);
4970
4971 /* Reset PHY to activate OEM bits on 82577/8 */
4972 if (hw->mac.type == e1000_pchlan)
4973 e1000_phy_hw_reset_generic(hw);
4974
4975 ret_val = hw->phy.ops.acquire(hw);
4976 if (ret_val)
4977 return;
4978 e1000_write_smbus_addr(hw);
4979 hw->phy.ops.release(hw);
4980 }
4981
4982 return;
4983}
4984
4985/**
4986 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4987 * @hw: pointer to the HW structure
4988 *
4989 * During Sx to S0 transitions on non-managed devices or managed devices
4990 * on which PHY resets are not blocked, if the PHY registers cannot be
4991 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4992 * the PHY.
4993 * On i217, setup Intel Rapid Start Technology.
4994 **/
4995void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4996{
4997 s32 ret_val;
4998
4999 DEBUGFUNC("e1000_resume_workarounds_pchlan");
5000 if (hw->mac.type < e1000_pch2lan)
5001 return;
5002
5003 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5004 if (ret_val) {
5005 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5006 return;
5007 }
5008
5009 /* For i217 Intel Rapid Start Technology support when the system
5010 * is transitioning from Sx and no manageability engine is present
5011 * configure SMBus to restore on reset, disable proxy, and enable
5012 * the reset on MTA (Multicast table array).
5013 */
5014 if (hw->phy.type == e1000_phy_i217) {
5015 u16 phy_reg;
5016
5017 ret_val = hw->phy.ops.acquire(hw);
5018 if (ret_val) {
5019 DEBUGOUT("Failed to setup iRST\n");
5020 return;
5021 }
5022
5023 /* Clear Auto Enable LPI after link up */
5024 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5025 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5026 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5027
5028 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5029 E1000_ICH_FWSM_FW_VALID)) {
5030 /* Restore clear on SMB if no manageability engine
5031 * is present
5032 */
5033 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5034 &phy_reg);
5035 if (ret_val)
5036 goto release;
5037 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5038 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5039
5040 /* Disable Proxy */
5041 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5042 }
5043 /* Enable reset on MTA */
5044 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5045 &phy_reg);
5046 if (ret_val)
5047 goto release;
5048 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5049 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5050release:
5051 if (ret_val)
5052 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5053 hw->phy.ops.release(hw);
5054 }
5055}
5056
5057/**
5058 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5059 * @hw: pointer to the HW structure
5060 *
5061 * Return the LED back to the default configuration.
5062 **/
5063static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5064{
5065 DEBUGFUNC("e1000_cleanup_led_ich8lan");
5066
5067 if (hw->phy.type == e1000_phy_ife)
5068 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5069 0);
5070
5071 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5072 return E1000_SUCCESS;
5073}
5074
5075/**
5076 * e1000_led_on_ich8lan - Turn LEDs on
5077 * @hw: pointer to the HW structure
5078 *
5079 * Turn on the LEDs.
5080 **/
5081static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5082{
5083 DEBUGFUNC("e1000_led_on_ich8lan");
5084
5085 if (hw->phy.type == e1000_phy_ife)
5086 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5087 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5088
5089 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5090 return E1000_SUCCESS;
5091}
5092
5093/**
5094 * e1000_led_off_ich8lan - Turn LEDs off
5095 * @hw: pointer to the HW structure
5096 *
5097 * Turn off the LEDs.
5098 **/
5099static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5100{
5101 DEBUGFUNC("e1000_led_off_ich8lan");
5102
5103 if (hw->phy.type == e1000_phy_ife)
5104 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5105 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5106
5107 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5108 return E1000_SUCCESS;
5109}
5110
5111/**
5112 * e1000_setup_led_pchlan - Configures SW controllable LED
5113 * @hw: pointer to the HW structure
5114 *
5115 * This prepares the SW controllable LED for use.
5116 **/
5117static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5118{
5119 DEBUGFUNC("e1000_setup_led_pchlan");
5120
5121 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5122 (u16)hw->mac.ledctl_mode1);
5123}
5124
5125/**
5126 * e1000_cleanup_led_pchlan - Restore the default LED operation
5127 * @hw: pointer to the HW structure
5128 *
5129 * Return the LED back to the default configuration.
5130 **/
5131static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5132{
5133 DEBUGFUNC("e1000_cleanup_led_pchlan");
5134
5135 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5136 (u16)hw->mac.ledctl_default);
5137}
5138
5139/**
5140 * e1000_led_on_pchlan - Turn LEDs on
5141 * @hw: pointer to the HW structure
5142 *
5143 * Turn on the LEDs.
5144 **/
5145static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5146{
5147 u16 data = (u16)hw->mac.ledctl_mode2;
5148 u32 i, led;
5149
5150 DEBUGFUNC("e1000_led_on_pchlan");
5151
5152 /* If no link, then turn LED on by setting the invert bit
5153 * for each LED that's mode is "link_up" in ledctl_mode2.
5154 */
5155 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5156 for (i = 0; i < 3; i++) {
5157 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5158 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5159 E1000_LEDCTL_MODE_LINK_UP)
5160 continue;
5161 if (led & E1000_PHY_LED0_IVRT)
5162 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5163 else
5164 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5165 }
5166 }
5167
5168 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5169}
5170
5171/**
5172 * e1000_led_off_pchlan - Turn LEDs off
5173 * @hw: pointer to the HW structure
5174 *
5175 * Turn off the LEDs.
5176 **/
5177static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5178{
5179 u16 data = (u16)hw->mac.ledctl_mode1;
5180 u32 i, led;
5181
5182 DEBUGFUNC("e1000_led_off_pchlan");
5183
5184 /* If no link, then turn LED off by clearing the invert bit
5185 * for each LED that's mode is "link_up" in ledctl_mode1.
5186 */
5187 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5188 for (i = 0; i < 3; i++) {
5189 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5190 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5191 E1000_LEDCTL_MODE_LINK_UP)
5192 continue;
5193 if (led & E1000_PHY_LED0_IVRT)
5194 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5195 else
5196 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5197 }
5198 }
5199
5200 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5201}
5202
5203/**
5204 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5205 * @hw: pointer to the HW structure
5206 *
5207 * Read appropriate register for the config done bit for completion status
5208 * and configure the PHY through s/w for EEPROM-less parts.
5209 *
5210 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5211 * config done bit, so only an error is logged and continues. If we were
5212 * to return with error, EEPROM-less silicon would not be able to be reset
5213 * or change link.
5214 **/
5215static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5216{
5217 s32 ret_val = E1000_SUCCESS;
5218 u32 bank = 0;
5219 u32 status;
5220
5221 DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5222
5223 e1000_get_cfg_done_generic(hw);
5224
5225 /* Wait for indication from h/w that it has completed basic config */
5226 if (hw->mac.type >= e1000_ich10lan) {
5227 e1000_lan_init_done_ich8lan(hw);
5228 } else {
5229 ret_val = e1000_get_auto_rd_done_generic(hw);
5230 if (ret_val) {
5231 /* When auto config read does not complete, do not
5232 * return with an error. This can happen in situations
5233 * where there is no eeprom and prevents getting link.
5234 */
5235 DEBUGOUT("Auto Read Done did not complete\n");
5236 ret_val = E1000_SUCCESS;
5237 }
5238 }
5239
5240 /* Clear PHY Reset Asserted bit */
5241 status = E1000_READ_REG(hw, E1000_STATUS);
5242 if (status & E1000_STATUS_PHYRA)
5243 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5244 else
5245 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5246
5247 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5248 if (hw->mac.type <= e1000_ich9lan) {
5249 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5250 (hw->phy.type == e1000_phy_igp_3)) {
5251 e1000_phy_init_script_igp3(hw);
5252 }
5253 } else {
5254 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5255 /* Maybe we should do a basic PHY config */
5256 DEBUGOUT("EEPROM not present\n");
5257 ret_val = -E1000_ERR_CONFIG;
5258 }
5259 }
5260
5261 return ret_val;
5262}
5263
5264/**
5265 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5266 * @hw: pointer to the HW structure
5267 *
5268 * In the case of a PHY power down to save power, or to turn off link during a
5269 * driver unload, or wake on lan is not enabled, remove the link.
5270 **/
5271static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5272{
5273 /* If the management interface is not enabled, then power down */
5274 if (!(hw->mac.ops.check_mng_mode(hw) ||
5275 hw->phy.ops.check_reset_block(hw)))
5276 e1000_power_down_phy_copper(hw);
5277
5278 return;
5279}
5280
5281/**
5282 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5283 * @hw: pointer to the HW structure
5284 *
5285 * Clears hardware counters specific to the silicon family and calls
5286 * clear_hw_cntrs_generic to clear all general purpose counters.
5287 **/
5288static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5289{
5290 u16 phy_data;
5291 s32 ret_val;
5292
5293 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
5294
5295 e1000_clear_hw_cntrs_base_generic(hw);
5296
5297 E1000_READ_REG(hw, E1000_ALGNERRC);
5298 E1000_READ_REG(hw, E1000_RXERRC);
5299 E1000_READ_REG(hw, E1000_TNCRS);
5300 E1000_READ_REG(hw, E1000_CEXTERR);
5301 E1000_READ_REG(hw, E1000_TSCTC);
5302 E1000_READ_REG(hw, E1000_TSCTFC);
5303
5304 E1000_READ_REG(hw, E1000_MGTPRC);
5305 E1000_READ_REG(hw, E1000_MGTPDC);
5306 E1000_READ_REG(hw, E1000_MGTPTC);
5307
5308 E1000_READ_REG(hw, E1000_IAC);
5309 E1000_READ_REG(hw, E1000_ICRXOC);
5310
5311 /* Clear PHY statistics registers */
5312 if ((hw->phy.type == e1000_phy_82578) ||
5313 (hw->phy.type == e1000_phy_82579) ||
5314 (hw->phy.type == e1000_phy_i217) ||
5315 (hw->phy.type == e1000_phy_82577)) {
5316 ret_val = hw->phy.ops.acquire(hw);
5317 if (ret_val)
5318 return;
5319 ret_val = hw->phy.ops.set_page(hw,
5320 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5321 if (ret_val)
5322 goto release;
5323 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5324 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5325 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5326 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5327 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5328 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5329 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5330 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5331 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5332 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5333 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5334 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5335 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5336 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5337release:
5338 hw->phy.ops.release(hw);
5339 }
5340}
5341