1/******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
--- 16 unchanged lines hidden (view full) ---
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.c 287990 2015-09-19 18:22:59Z sbruno $*/
34
35/* 82562G 10/100 Network Connection
36 * 82562G-2 10/100 Network Connection
37 * 82562GT 10/100 Network Connection
38 * 82562GT-2 10/100 Network Connection
39 * 82562V 10/100 Network Connection
40 * 82562V-2 10/100 Network Connection
41 * 82566DC-2 Gigabit Network Connection
--- 45 unchanged lines hidden (view full) ---
87static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
88static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
89static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
90 bool active);
91static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
92 bool active);
93static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
94 u16 words, u16 *data);
95static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
96 u16 words, u16 *data);
97static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
98static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
99static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
100 u16 *data);
101static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
102static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
103static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
104static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
105static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
106static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
--- 11 unchanged lines hidden (view full) ---
118static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
119static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
120static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
121static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
122static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
123 u32 offset, u8 *data);
124static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
125 u8 size, u16 *data);
126static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
127 u32 offset, u16 *data);
128static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
129 u32 offset, u8 byte);
130static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
131static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
132static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
133static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
--- 93 unchanged lines hidden (view full) ---
227 if (!ret_val)
228 ret_val = e1000_get_phy_id(hw);
229 hw->phy.ops.acquire(hw);
230 }
231
232 if (ret_val)
233 return FALSE;
234out:
235 if (hw->mac.type == e1000_pch_lpt) {
236 /* Unforce SMBus mode in PHY */
237 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
238 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
239 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
240
241 /* Unforce SMBus mode in MAC */
242 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
243 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
244 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
245 }
246
247 return TRUE;
248}
249
250/**
251 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
252 * @hw: pointer to the HW structure
--- 70 unchanged lines hidden (view full) ---
323 }
324
325 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
326 * inaccessible and resetting the PHY is not blocked, toggle the
327 * LANPHYPC Value bit to force the interconnect to PCIe mode.
328 */
329 switch (hw->mac.type) {
330 case e1000_pch_lpt:
331 if (e1000_phy_is_accessible_pchlan(hw))
332 break;
333
334 /* Before toggling LANPHYPC, see if PHY is accessible by
335 * forcing MAC to SMBus mode first.
336 */
337 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
338 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
--- 131 unchanged lines hidden (view full) ---
470 ret_val = e1000_get_phy_id(hw);
471 if (ret_val)
472 return ret_val;
473 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
474 break;
475 /* fall-through */
476 case e1000_pch2lan:
477 case e1000_pch_lpt:
478 /* In case the PHY needs to be in mdio slow mode,
479 * set slow mode and try to get the PHY id again.
480 */
481 ret_val = e1000_set_mdio_slow_mode_hv(hw);
482 if (ret_val)
483 return ret_val;
484 ret_val = e1000_get_phy_id(hw);
485 if (ret_val)
--- 126 unchanged lines hidden (view full) ---
612 * pointers.
613 **/
614static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
615{
616 struct e1000_nvm_info *nvm = &hw->nvm;
617 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
618 u32 gfpreg, sector_base_addr, sector_end_addr;
619 u16 i;
620
621 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
622
623 /* Can't read flash registers if the register set isn't mapped. */
624 nvm->type = e1000_nvm_flash_sw;
625 if (!hw->flash_address) {
626 DEBUGOUT("ERROR: Flash registers not mapped\n");
627 return -E1000_ERR_CONFIG;
628 }
629
630 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
631
632 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
633 * Add 1 to sector_end_addr since this sector is included in
634 * the overall size.
635 */
636 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
637 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
638
639 /* flash_base_addr is byte-aligned */
640 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
641
642 /* find total size of the NVM, then cut in half since the total
643 * size represents two separate NVM banks.
644 */
645 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
646 << FLASH_SECTOR_ADDR_SHIFT);
647 nvm->flash_bank_size /= 2;
648 /* Adjust to word count */
649 nvm->flash_bank_size /= sizeof(u16);
650
651 nvm->word_size = E1000_SHADOW_RAM_WORDS;
652
653 /* Clear shadow ram */
654 for (i = 0; i < nvm->word_size; i++) {
655 dev_spec->shadow_ram[i].modified = FALSE;
656 dev_spec->shadow_ram[i].value = 0xFFFF;
657 }
658
659 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
660 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
661
662 /* Function Pointers */
663 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
664 nvm->ops.release = e1000_release_nvm_ich8lan;
665 nvm->ops.read = e1000_read_nvm_ich8lan;
666 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
667 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
668 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
669 nvm->ops.write = e1000_write_nvm_ich8lan;
670
671 return E1000_SUCCESS;
672}
673
674/**
675 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
676 * @hw: pointer to the HW structure
677 *
678 * Initialize family-specific MAC parameters and function
679 * pointers.
680 **/
681static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
682{
683 struct e1000_mac_info *mac = &hw->mac;
684#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
685 u16 pci_cfg;
686#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
687
688 DEBUGFUNC("e1000_init_mac_params_ich8lan");
689
690 /* Set media type function pointer */
691 hw->phy.media_type = e1000_media_type_copper;
692
693 /* Set mta register count */
694 mac->mta_reg_count = 32;
--- 52 unchanged lines hidden (view full) ---
747 mac->ops.led_on = e1000_led_on_ich8lan;
748 mac->ops.led_off = e1000_led_off_ich8lan;
749 break;
750 case e1000_pch2lan:
751 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
752 mac->ops.rar_set = e1000_rar_set_pch2lan;
753 /* fall-through */
754 case e1000_pch_lpt:
755 /* multicast address update for pch2 */
756 mac->ops.update_mc_addr_list =
757 e1000_update_mc_addr_list_pch2lan;
758 case e1000_pchlan:
759#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
760 /* save PCH revision_id */
761 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
762 hw->revision_id = (u8)(pci_cfg &= 0x000F);
763#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
764 /* check management mode */
765 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
766 /* ID LED init */
767 mac->ops.id_led_init = e1000_id_led_init_pchlan;
768 /* setup LED */
769 mac->ops.setup_led = e1000_setup_led_pchlan;
770 /* cleanup LED */
771 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
772 /* turn on/off LED */
773 mac->ops.led_on = e1000_led_on_pchlan;
774 mac->ops.led_off = e1000_led_off_pchlan;
775 break;
776 default:
777 break;
778 }
779
780 if (mac->type == e1000_pch_lpt) {
781 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
782 mac->ops.rar_set = e1000_rar_set_pch_lpt;
783 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
784 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
785 }
786
787 /* Enable PCS Lock-loss workaround for ICH8 */
788 if (mac->type == e1000_ich8lan)
--- 213 unchanged lines hidden (view full) ---
1002 E1000_KMRNCTRLSTA_K1_CONFIG,
1003 reg);
1004release:
1005 hw->phy.ops.release(hw);
1006 } else {
1007 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1008 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1009
1010 if (!link || ((status & E1000_STATUS_SPEED_100) &&
1011 (status & E1000_STATUS_FD)))
1012 goto update_fextnvm6;
1013
1014 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1015 if (ret_val)
1016 return ret_val;
1017
1018 /* Clear link status transmit timeout */
1019 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
--- 196 unchanged lines hidden (view full) ---
1216 * ME firmware to start the ULP configuration. If not on an ME enabled
1217 * system, configure the ULP mode by software.
1218 */
1219s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1220{
1221 u32 mac_reg;
1222 s32 ret_val = E1000_SUCCESS;
1223 u16 phy_reg;
1224
1225 if ((hw->mac.type < e1000_pch_lpt) ||
1226 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1227 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1228 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1229 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1230 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1231 return 0;
--- 39 unchanged lines hidden (view full) ---
1271 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1272 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1273
1274 /* Force SMBus mode in MAC */
1275 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1276 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1277 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1278
1279 /* Set Inband ULP Exit, Reset to SMBus mode and
1280 * Disable SMBus Release on PERST# in PHY
1281 */
1282 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1283 if (ret_val)
1284 goto release;
1285 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1286 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1287 if (to_sx) {
1288 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1289 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1290
1291 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1292 } else {
1293 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1294 }
1295 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1296
1297 /* Set Disable SMBus Release on PERST# in MAC */
1298 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1299 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1300 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1301
1302 /* Commit ULP changes in PHY by starting auto ULP configuration */
1303 phy_reg |= I218_ULP_CONFIG1_START;
1304 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1305release:
1306 hw->phy.ops.release(hw);
1307out:
1308 if (ret_val)
1309 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1310 else
1311 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1312
--- 34 unchanged lines hidden (view full) ---
1347 if (force) {
1348 /* Request ME un-configure ULP mode in the PHY */
1349 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1350 mac_reg &= ~E1000_H2ME_ULP;
1351 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1352 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1353 }
1354
1355 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1356 while (E1000_READ_REG(hw, E1000_FWSM) &
1357 E1000_FWSM_ULP_CFG_DONE) {
1358 if (i++ == 10) {
1359 ret_val = -E1000_ERR_PHY;
1360 goto out;
1361 }
1362
1363 msec_delay(10);
1364 }
1365 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1366
--- 57 unchanged lines hidden (view full) ---
1424 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1425 if (ret_val)
1426 goto release;
1427 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1428 I218_ULP_CONFIG1_STICKY_ULP |
1429 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1430 I218_ULP_CONFIG1_WOL_HOST |
1431 I218_ULP_CONFIG1_INBAND_EXIT |
1432 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1433 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1434
1435 /* Commit ULP changes by starting auto ULP configuration */
1436 phy_reg |= I218_ULP_CONFIG1_START;
1437 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1438
1439 /* Clear Disable SMBus Release on PERST# in MAC */
--- 22 unchanged lines hidden (view full) ---
1462 *
1463 * Checks to see of the link status of the hardware has changed. If a
1464 * change in link status has been detected, then we read the PHY registers
1465 * to get the current speed/duplex if link exists.
1466 **/
1467static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1468{
1469 struct e1000_mac_info *mac = &hw->mac;
1470 s32 ret_val;
1471 bool link;
1472 u16 phy_reg;
1473
1474 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1475
1476 /* We only want to go out to the PHY registers to see if Auto-Neg
1477 * has completed and/or if our link status has changed. The
1478 * get_link_status flag is set upon receiving a Link Status
--- 16 unchanged lines hidden (view full) ---
1495 return ret_val;
1496 }
1497
1498 /* When connected at 10Mbps half-duplex, some parts are excessively
1499 * aggressive resulting in many collisions. To avoid this, increase
1500 * the IPG and reduce Rx latency in the PHY.
1501 */
1502 if (((hw->mac.type == e1000_pch2lan) ||
1503 (hw->mac.type == e1000_pch_lpt)) && link) {
1504 u32 reg;
1505 reg = E1000_READ_REG(hw, E1000_STATUS);
1506 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1507 u16 emi_addr;
1508
1509 reg = E1000_READ_REG(hw, E1000_TIPG);
1510 reg &= ~E1000_TIPG_IPGT_MASK;
1511 reg |= 0xFF;
1512 E1000_WRITE_REG(hw, E1000_TIPG, reg);
1513
1514 /* Reduce Rx latency in analog PHY */
1515 ret_val = hw->phy.ops.acquire(hw);
1516 if (ret_val)
1517 return ret_val;
1518
1519 if (hw->mac.type == e1000_pch2lan)
1520 emi_addr = I82579_RX_CONFIG;
1521 else
1522 emi_addr = I217_RX_CONFIG;
1523 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0);
1524
1525 hw->phy.ops.release(hw);
1526
1527 if (ret_val)
1528 return ret_val;
1529 }
1530 }
1531
1532 /* Work-around I218 hang issue */
1533 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1534 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1535 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1536 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1537 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1538 if (ret_val)
1539 return ret_val;
1540 }
1541 if (hw->mac.type == e1000_pch_lpt) {
1542 /* Set platform power management values for
1543 * Latency Tolerance Reporting (LTR)
1544 * Optimized Buffer Flush/Fill (OBFF)
1545 */
1546 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1547 if (ret_val)
1548 return ret_val;
1549 }
1550
1551 /* Clear link partner's EEE ability */
1552 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1553
1554 if (!link)
1555 return E1000_SUCCESS; /* No link detected */
1556
1557 mac->get_link_status = FALSE;
1558
1559 switch (hw->mac.type) {
1560 case e1000_pch2lan:
1561 ret_val = e1000_k1_workaround_lv(hw);
--- 77 unchanged lines hidden (view full) ---
1639 case e1000_ich8lan:
1640 case e1000_ich9lan:
1641 case e1000_ich10lan:
1642 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1643 break;
1644 case e1000_pchlan:
1645 case e1000_pch2lan:
1646 case e1000_pch_lpt:
1647 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1648 break;
1649 default:
1650 break;
1651 }
1652}
1653
1654/**
--- 366 unchanged lines hidden (view full) ---
2021 do {
2022 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2023 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2024 blocked = TRUE;
2025 msec_delay(10);
2026 continue;
2027 }
2028 blocked = FALSE;
2029 } while (blocked && (i++ < 10));
2030 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2031}
2032
2033/**
2034 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2035 * @hw: pointer to the HW structure
2036 *
2037 * Assumes semaphore already acquired.
--- 64 unchanged lines hidden (view full) ---
2102 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2103 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2104 break;
2105 }
2106 /* Fall-thru */
2107 case e1000_pchlan:
2108 case e1000_pch2lan:
2109 case e1000_pch_lpt:
2110 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2111 break;
2112 default:
2113 return ret_val;
2114 }
2115
2116 ret_val = hw->phy.ops.acquire(hw);
2117 if (ret_val)
--- 1093 unchanged lines hidden (view full) ---
3211 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3212 **/
3213static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3214{
3215 u32 eecd;
3216 struct e1000_nvm_info *nvm = &hw->nvm;
3217 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3218 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3219 u8 sig_byte = 0;
3220 s32 ret_val;
3221
3222 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3223
3224 switch (hw->mac.type) {
3225 case e1000_ich8lan:
3226 case e1000_ich9lan:
3227 eecd = E1000_READ_REG(hw, E1000_EECD);
3228 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3229 E1000_EECD_SEC1VAL_VALID_MASK) {
3230 if (eecd & E1000_EECD_SEC1VAL)
3231 *bank = 1;
3232 else
--- 31 unchanged lines hidden (view full) ---
3264 }
3265
3266 DEBUGOUT("ERROR: No valid NVM bank present\n");
3267 return -E1000_ERR_NVM;
3268 }
3269}
3270
3271/**
3272 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3273 * @hw: pointer to the HW structure
3274 * @offset: The offset (in bytes) of the word(s) to read.
3275 * @words: Size of data to read in words
3276 * @data: Pointer to the word(s) to read at offset.
3277 *
3278 * Reads a word(s) from the NVM using the flash access registers.
3279 **/
--- 70 unchanged lines hidden (view full) ---
3350 if (!hsfsts.hsf_status.fldesvalid) {
3351 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3352 return -E1000_ERR_NVM;
3353 }
3354
3355 /* Clear FCERR and DAEL in hw status by writing 1 */
3356 hsfsts.hsf_status.flcerr = 1;
3357 hsfsts.hsf_status.dael = 1;
3358 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3359
3360 /* Either we should have a hardware SPI cycle in progress
3361 * bit to check against, in order to start a new cycle or
3362 * FDONE bit should be changed in the hardware so that it
3363 * is 1 after hardware reset, which can then be used as an
3364 * indication whether a cycle is in progress or has been
3365 * completed.
3366 */
3367
3368 if (!hsfsts.hsf_status.flcinprog) {
3369 /* There is no cycle running at present,
3370 * so we can start a cycle.
3371 * Begin by setting Flash Cycle Done.
3372 */
3373 hsfsts.hsf_status.flcdone = 1;
3374 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3375 ret_val = E1000_SUCCESS;
3376 } else {
3377 s32 i;
3378
3379 /* Otherwise poll for sometime so the current
3380 * cycle has a chance to end before giving up.
3381 */
3382 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
--- 5 unchanged lines hidden (view full) ---
3388 }
3389 usec_delay(1);
3390 }
3391 if (ret_val == E1000_SUCCESS) {
3392 /* Successful in waiting for previous cycle to timeout,
3393 * now set the Flash Cycle Done.
3394 */
3395 hsfsts.hsf_status.flcdone = 1;
3396 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3397 hsfsts.regval);
3398 } else {
3399 DEBUGOUT("Flash controller busy, cannot get access\n");
3400 }
3401 }
3402
3403 return ret_val;
3404}
3405
--- 8 unchanged lines hidden (view full) ---
3414{
3415 union ich8_hws_flash_ctrl hsflctl;
3416 union ich8_hws_flash_status hsfsts;
3417 u32 i = 0;
3418
3419 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3420
3421 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3422 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3423 hsflctl.hsf_ctrl.flcgo = 1;
3424
3425 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3426
3427 /* wait till FDONE bit is set to 1 */
3428 do {
3429 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3430 if (hsfsts.hsf_status.flcdone)
3431 break;
3432 usec_delay(1);
3433 } while (i++ < timeout);
3434
3435 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3436 return E1000_SUCCESS;
3437
3438 return -E1000_ERR_NVM;
3439}
3440
3441/**
3442 * e1000_read_flash_word_ich8lan - Read word from flash
3443 * @hw: pointer to the HW structure
3444 * @offset: offset to data location
3445 * @data: pointer to the location for storing the data
3446 *
3447 * Reads the flash word at offset into data. Offset is converted
3448 * to bytes before read.
3449 **/
--- 20 unchanged lines hidden (view full) ---
3470 * Reads a single byte from the NVM using the flash access registers.
3471 **/
3472static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3473 u8 *data)
3474{
3475 s32 ret_val;
3476 u16 word = 0;
3477
3478 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3479
3480 if (ret_val)
3481 return ret_val;
3482
3483 *data = (u8)word;
3484
3485 return E1000_SUCCESS;
3486}
--- 69 unchanged lines hidden (view full) ---
3556 break;
3557 }
3558 }
3559 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3560
3561 return ret_val;
3562}
3563
3564
3565/**
3566 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3567 * @hw: pointer to the HW structure
3568 * @offset: The offset (in bytes) of the word(s) to write.
3569 * @words: Size of data to write in words
3570 * @data: Pointer to the word(s) to write at offset.
3571 *
3572 * Writes a byte or word to the NVM using the flash access registers.
--- 21 unchanged lines hidden (view full) ---
3594 }
3595
3596 nvm->ops.release(hw);
3597
3598 return E1000_SUCCESS;
3599}
3600
3601/**
3602 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3603 * @hw: pointer to the HW structure
3604 *
3605 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3606 * which writes the checksum to the shadow ram. The changes in the shadow
3607 * ram are then committed to the EEPROM by processing each bank at a time
3608 * checking for the modified bit and writing only the pending changes.
3609 * After a successful commit, the shadow ram is cleared and is ready for
--- 160 unchanged lines hidden (view full) ---
3770
3771 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
3772 * the checksum needs to be fixed. This bit is an indication that
3773 * the NVM was prepared by OEM software and did not calculate
3774 * the checksum...a likely scenario.
3775 */
3776 switch (hw->mac.type) {
3777 case e1000_pch_lpt:
3778 word = NVM_COMPAT;
3779 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3780 break;
3781 default:
3782 word = NVM_FUTURE_INIT_WORD1;
3783 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3784 break;
3785 }
--- 31 unchanged lines hidden (view full) ---
3817 union ich8_hws_flash_ctrl hsflctl;
3818 u32 flash_linear_addr;
3819 u32 flash_data = 0;
3820 s32 ret_val;
3821 u8 count = 0;
3822
3823 DEBUGFUNC("e1000_write_ich8_data");
3824
3825 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3826 return -E1000_ERR_NVM;
3827
3828 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3829 hw->nvm.flash_base_addr);
3830
3831 do {
3832 usec_delay(1);
3833 /* Steps */
3834 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3835 if (ret_val != E1000_SUCCESS)
3836 break;
3837 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3838
3839 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3840 hsflctl.hsf_ctrl.fldbcount = size - 1;
3841 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3842 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3843
3844 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3845
3846 if (size == 1)
3847 flash_data = (u32)data & 0x00FF;
3848 else
3849 flash_data = (u32)data;
3850
--- 21 unchanged lines hidden (view full) ---
3872 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3873 break;
3874 }
3875 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3876
3877 return ret_val;
3878}
3879
3880
3881/**
3882 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3883 * @hw: pointer to the HW structure
3884 * @offset: The index of the byte to read.
3885 * @data: The byte to write to the NVM.
3886 *
3887 * Writes a single byte to the NVM using the flash access registers.
3888 **/
3889static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3890 u8 data)
3891{
3892 u16 word = (u16)data;
3893
3894 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3895
3896 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3897}
3898
3899
3900
3901/**
3902 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3903 * @hw: pointer to the HW structure
3904 * @offset: The offset of the byte to write.
3905 * @byte: The byte to write to the NVM.
3906 *
3907 * Writes a single byte to the NVM using the flash access registers.
3908 * Goes through a retry algorithm before giving up.
--- 92 unchanged lines hidden (view full) ---
4001 /* Steps */
4002 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4003 if (ret_val)
4004 return ret_val;
4005
4006 /* Write a value 11 (block Erase) in Flash
4007 * Cycle field in hw flash control
4008 */
4009 hsflctl.regval =
4010 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4011
4012 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4013 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4014 hsflctl.regval);
4015
4016 /* Write the last 24 bits of an index within the
4017 * block into Flash Linear address field in Flash
4018 * Address.
4019 */
4020 flash_linear_addr += (j * sector_size);
4021 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4022 flash_linear_addr);
--- 416 unchanged lines hidden (view full) ---
4439 /* Disable IPv6 extension header parsing because some malformed
4440 * IPv6 headers can hang the Rx.
4441 */
4442 if (hw->mac.type == e1000_ich8lan)
4443 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4444 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
4445
4446 /* Enable ECC on Lynxpoint */
4447 if (hw->mac.type == e1000_pch_lpt) {
4448 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
4449 reg |= E1000_PBECCSTS_ECC_ENABLE;
4450 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
4451
4452 reg = E1000_READ_REG(hw, E1000_CTRL);
4453 reg |= E1000_CTRL_MEHE;
4454 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4455 }
--- 415 unchanged lines hidden (view full) ---
4871 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4872
4873 if (hw->phy.type == e1000_phy_i217) {
4874 u16 phy_reg, device_id = hw->device_id;
4875
4876 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4877 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4878 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4879 (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4880 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4881
4882 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
4883 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4884 }
4885
4886 ret_val = hw->phy.ops.acquire(hw);
4887 if (ret_val)
--- 99 unchanged lines hidden (view full) ---
4987 * @hw: pointer to the HW structure
4988 *
4989 * During Sx to S0 transitions on non-managed devices or managed devices
4990 * on which PHY resets are not blocked, if the PHY registers cannot be
4991 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4992 * the PHY.
4993 * On i217, setup Intel Rapid Start Technology.
4994 **/
4995void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4996{
4997 s32 ret_val;
4998
4999 DEBUGFUNC("e1000_resume_workarounds_pchlan");
5000 if (hw->mac.type < e1000_pch2lan)
5001 return;
5002
5003 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5004 if (ret_val) {
5005 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5006 return;
5007 }
5008
5009 /* For i217 Intel Rapid Start Technology support when the system
5010 * is transitioning from Sx and no manageability engine is present
5011 * configure SMBus to restore on reset, disable proxy, and enable
5012 * the reset on MTA (Multicast table array).
5013 */
5014 if (hw->phy.type == e1000_phy_i217) {
5015 u16 phy_reg;
5016
5017 ret_val = hw->phy.ops.acquire(hw);
5018 if (ret_val) {
5019 DEBUGOUT("Failed to setup iRST\n");
5020 return;
5021 }
5022
5023 /* Clear Auto Enable LPI after link up */
5024 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5025 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5026 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5027
5028 if (!(E1000_READ_REG(hw, E1000_FWSM) &
--- 17 unchanged lines hidden (view full) ---
5046 if (ret_val)
5047 goto release;
5048 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5049 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5050release:
5051 if (ret_val)
5052 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5053 hw->phy.ops.release(hw);
5054 }
5055}
5056
5057/**
5058 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5059 * @hw: pointer to the HW structure
5060 *
5061 * Return the LED back to the default configuration.
5062 **/
--- 279 unchanged lines hidden ---
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
--- 16 unchanged lines hidden (view full) ---
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.c 287990 2015-09-19 18:22:59Z sbruno $*/
34
35/* 82562G 10/100 Network Connection
36 * 82562G-2 10/100 Network Connection
37 * 82562GT 10/100 Network Connection
38 * 82562GT-2 10/100 Network Connection
39 * 82562V 10/100 Network Connection
40 * 82562V-2 10/100 Network Connection
41 * 82566DC-2 Gigabit Network Connection
--- 45 unchanged lines hidden (view full) ---
87static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
88static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
89static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
90 bool active);
91static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
92 bool active);
93static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
94 u16 words, u16 *data);
95static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
96 u16 words, u16 *data);
97static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
98static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
99static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
100 u16 *data);
101static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
102static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
103static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
104static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
105static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
106static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
--- 11 unchanged lines hidden (view full) ---
118static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
119static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
120static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
121static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
122static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
123 u32 offset, u8 *data);
124static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
125 u8 size, u16 *data);
126static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
127 u32 offset, u16 *data);
128static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
129 u32 offset, u8 byte);
130static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
131static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
132static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
133static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
--- 93 unchanged lines hidden (view full) ---
227 if (!ret_val)
228 ret_val = e1000_get_phy_id(hw);
229 hw->phy.ops.acquire(hw);
230 }
231
232 if (ret_val)
233 return FALSE;
234out:
235 if (hw->mac.type == e1000_pch_lpt) {
236 /* Unforce SMBus mode in PHY */
237 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
238 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
239 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
240
241 /* Unforce SMBus mode in MAC */
242 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
243 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
244 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
245 }
246
247 return TRUE;
248}
249
250/**
251 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
252 * @hw: pointer to the HW structure
--- 70 unchanged lines hidden (view full) ---
323 }
324
325 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
326 * inaccessible and resetting the PHY is not blocked, toggle the
327 * LANPHYPC Value bit to force the interconnect to PCIe mode.
328 */
329 switch (hw->mac.type) {
330 case e1000_pch_lpt:
331 if (e1000_phy_is_accessible_pchlan(hw))
332 break;
333
334 /* Before toggling LANPHYPC, see if PHY is accessible by
335 * forcing MAC to SMBus mode first.
336 */
337 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
338 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
--- 131 unchanged lines hidden (view full) ---
470 ret_val = e1000_get_phy_id(hw);
471 if (ret_val)
472 return ret_val;
473 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
474 break;
475 /* fall-through */
476 case e1000_pch2lan:
477 case e1000_pch_lpt:
478 /* In case the PHY needs to be in mdio slow mode,
479 * set slow mode and try to get the PHY id again.
480 */
481 ret_val = e1000_set_mdio_slow_mode_hv(hw);
482 if (ret_val)
483 return ret_val;
484 ret_val = e1000_get_phy_id(hw);
485 if (ret_val)
--- 126 unchanged lines hidden (view full) ---
612 * pointers.
613 **/
614static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
615{
616 struct e1000_nvm_info *nvm = &hw->nvm;
617 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
618 u32 gfpreg, sector_base_addr, sector_end_addr;
619 u16 i;
620
621 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
622
623 /* Can't read flash registers if the register set isn't mapped. */
624 nvm->type = e1000_nvm_flash_sw;
625 if (!hw->flash_address) {
626 DEBUGOUT("ERROR: Flash registers not mapped\n");
627 return -E1000_ERR_CONFIG;
628 }
629
630 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
631
632 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
633 * Add 1 to sector_end_addr since this sector is included in
634 * the overall size.
635 */
636 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
637 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
638
639 /* flash_base_addr is byte-aligned */
640 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
641
642 /* find total size of the NVM, then cut in half since the total
643 * size represents two separate NVM banks.
644 */
645 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
646 << FLASH_SECTOR_ADDR_SHIFT);
647 nvm->flash_bank_size /= 2;
648 /* Adjust to word count */
649 nvm->flash_bank_size /= sizeof(u16);
650
651 nvm->word_size = E1000_SHADOW_RAM_WORDS;
652
653 /* Clear shadow ram */
654 for (i = 0; i < nvm->word_size; i++) {
655 dev_spec->shadow_ram[i].modified = FALSE;
656 dev_spec->shadow_ram[i].value = 0xFFFF;
657 }
658
659 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
660 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
661
662 /* Function Pointers */
663 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
664 nvm->ops.release = e1000_release_nvm_ich8lan;
665 nvm->ops.read = e1000_read_nvm_ich8lan;
666 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
667 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
668 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
669 nvm->ops.write = e1000_write_nvm_ich8lan;
670
671 return E1000_SUCCESS;
672}
673
674/**
675 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
676 * @hw: pointer to the HW structure
677 *
678 * Initialize family-specific MAC parameters and function
679 * pointers.
680 **/
681static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
682{
683 struct e1000_mac_info *mac = &hw->mac;
684#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
685 u16 pci_cfg;
686#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
687
688 DEBUGFUNC("e1000_init_mac_params_ich8lan");
689
690 /* Set media type function pointer */
691 hw->phy.media_type = e1000_media_type_copper;
692
693 /* Set mta register count */
694 mac->mta_reg_count = 32;
--- 52 unchanged lines hidden (view full) ---
747 mac->ops.led_on = e1000_led_on_ich8lan;
748 mac->ops.led_off = e1000_led_off_ich8lan;
749 break;
750 case e1000_pch2lan:
751 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
752 mac->ops.rar_set = e1000_rar_set_pch2lan;
753 /* fall-through */
754 case e1000_pch_lpt:
755 /* multicast address update for pch2 */
756 mac->ops.update_mc_addr_list =
757 e1000_update_mc_addr_list_pch2lan;
758 case e1000_pchlan:
759#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
760 /* save PCH revision_id */
761 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
762 hw->revision_id = (u8)(pci_cfg &= 0x000F);
763#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
764 /* check management mode */
765 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
766 /* ID LED init */
767 mac->ops.id_led_init = e1000_id_led_init_pchlan;
768 /* setup LED */
769 mac->ops.setup_led = e1000_setup_led_pchlan;
770 /* cleanup LED */
771 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
772 /* turn on/off LED */
773 mac->ops.led_on = e1000_led_on_pchlan;
774 mac->ops.led_off = e1000_led_off_pchlan;
775 break;
776 default:
777 break;
778 }
779
780 if (mac->type == e1000_pch_lpt) {
781 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
782 mac->ops.rar_set = e1000_rar_set_pch_lpt;
783 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
784 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
785 }
786
787 /* Enable PCS Lock-loss workaround for ICH8 */
788 if (mac->type == e1000_ich8lan)
--- 213 unchanged lines hidden (view full) ---
1002 E1000_KMRNCTRLSTA_K1_CONFIG,
1003 reg);
1004release:
1005 hw->phy.ops.release(hw);
1006 } else {
1007 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1008 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1009
1010 if (!link || ((status & E1000_STATUS_SPEED_100) &&
1011 (status & E1000_STATUS_FD)))
1012 goto update_fextnvm6;
1013
1014 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1015 if (ret_val)
1016 return ret_val;
1017
1018 /* Clear link status transmit timeout */
1019 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
--- 196 unchanged lines hidden (view full) ---
1216 * ME firmware to start the ULP configuration. If not on an ME enabled
1217 * system, configure the ULP mode by software.
1218 */
1219s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1220{
1221 u32 mac_reg;
1222 s32 ret_val = E1000_SUCCESS;
1223 u16 phy_reg;
1224
1225 if ((hw->mac.type < e1000_pch_lpt) ||
1226 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1227 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1228 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1229 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1230 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1231 return 0;
--- 39 unchanged lines hidden (view full) ---
1271 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1272 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1273
1274 /* Force SMBus mode in MAC */
1275 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1276 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1277 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1278
1279 /* Set Inband ULP Exit, Reset to SMBus mode and
1280 * Disable SMBus Release on PERST# in PHY
1281 */
1282 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1283 if (ret_val)
1284 goto release;
1285 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1286 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1287 if (to_sx) {
1288 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1289 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1290
1291 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1292 } else {
1293 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1294 }
1295 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1296
1297 /* Set Disable SMBus Release on PERST# in MAC */
1298 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1299 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1300 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1301
1302 /* Commit ULP changes in PHY by starting auto ULP configuration */
1303 phy_reg |= I218_ULP_CONFIG1_START;
1304 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1305release:
1306 hw->phy.ops.release(hw);
1307out:
1308 if (ret_val)
1309 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1310 else
1311 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1312
--- 34 unchanged lines hidden (view full) ---
1347 if (force) {
1348 /* Request ME un-configure ULP mode in the PHY */
1349 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1350 mac_reg &= ~E1000_H2ME_ULP;
1351 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1352 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1353 }
1354
1355 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1356 while (E1000_READ_REG(hw, E1000_FWSM) &
1357 E1000_FWSM_ULP_CFG_DONE) {
1358 if (i++ == 10) {
1359 ret_val = -E1000_ERR_PHY;
1360 goto out;
1361 }
1362
1363 msec_delay(10);
1364 }
1365 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1366
--- 57 unchanged lines hidden (view full) ---
1424 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1425 if (ret_val)
1426 goto release;
1427 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1428 I218_ULP_CONFIG1_STICKY_ULP |
1429 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1430 I218_ULP_CONFIG1_WOL_HOST |
1431 I218_ULP_CONFIG1_INBAND_EXIT |
1432 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1433 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1434
1435 /* Commit ULP changes by starting auto ULP configuration */
1436 phy_reg |= I218_ULP_CONFIG1_START;
1437 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1438
1439 /* Clear Disable SMBus Release on PERST# in MAC */
--- 22 unchanged lines hidden (view full) ---
1462 *
1463 * Checks to see of the link status of the hardware has changed. If a
1464 * change in link status has been detected, then we read the PHY registers
1465 * to get the current speed/duplex if link exists.
1466 **/
1467static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1468{
1469 struct e1000_mac_info *mac = &hw->mac;
1470 s32 ret_val;
1471 bool link;
1472 u16 phy_reg;
1473
1474 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1475
1476 /* We only want to go out to the PHY registers to see if Auto-Neg
1477 * has completed and/or if our link status has changed. The
1478 * get_link_status flag is set upon receiving a Link Status
--- 16 unchanged lines hidden (view full) ---
1495 return ret_val;
1496 }
1497
1498 /* When connected at 10Mbps half-duplex, some parts are excessively
1499 * aggressive resulting in many collisions. To avoid this, increase
1500 * the IPG and reduce Rx latency in the PHY.
1501 */
1502 if (((hw->mac.type == e1000_pch2lan) ||
1503 (hw->mac.type == e1000_pch_lpt)) && link) {
1504 u32 reg;
1505 reg = E1000_READ_REG(hw, E1000_STATUS);
1506 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1507 u16 emi_addr;
1508
1509 reg = E1000_READ_REG(hw, E1000_TIPG);
1510 reg &= ~E1000_TIPG_IPGT_MASK;
1511 reg |= 0xFF;
1512 E1000_WRITE_REG(hw, E1000_TIPG, reg);
1513
1514 /* Reduce Rx latency in analog PHY */
1515 ret_val = hw->phy.ops.acquire(hw);
1516 if (ret_val)
1517 return ret_val;
1518
1519 if (hw->mac.type == e1000_pch2lan)
1520 emi_addr = I82579_RX_CONFIG;
1521 else
1522 emi_addr = I217_RX_CONFIG;
1523 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0);
1524
1525 hw->phy.ops.release(hw);
1526
1527 if (ret_val)
1528 return ret_val;
1529 }
1530 }
1531
1532 /* Work-around I218 hang issue */
1533 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1534 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1535 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1536 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1537 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1538 if (ret_val)
1539 return ret_val;
1540 }
1541 if (hw->mac.type == e1000_pch_lpt) {
1542 /* Set platform power management values for
1543 * Latency Tolerance Reporting (LTR)
1544 * Optimized Buffer Flush/Fill (OBFF)
1545 */
1546 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1547 if (ret_val)
1548 return ret_val;
1549 }
1550
1551 /* Clear link partner's EEE ability */
1552 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1553
1554 if (!link)
1555 return E1000_SUCCESS; /* No link detected */
1556
1557 mac->get_link_status = FALSE;
1558
1559 switch (hw->mac.type) {
1560 case e1000_pch2lan:
1561 ret_val = e1000_k1_workaround_lv(hw);
--- 77 unchanged lines hidden (view full) ---
1639 case e1000_ich8lan:
1640 case e1000_ich9lan:
1641 case e1000_ich10lan:
1642 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1643 break;
1644 case e1000_pchlan:
1645 case e1000_pch2lan:
1646 case e1000_pch_lpt:
1647 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1648 break;
1649 default:
1650 break;
1651 }
1652}
1653
1654/**
--- 366 unchanged lines hidden (view full) ---
2021 do {
2022 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2023 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2024 blocked = TRUE;
2025 msec_delay(10);
2026 continue;
2027 }
2028 blocked = FALSE;
2029 } while (blocked && (i++ < 10));
2030 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2031}
2032
2033/**
2034 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2035 * @hw: pointer to the HW structure
2036 *
2037 * Assumes semaphore already acquired.
--- 64 unchanged lines hidden (view full) ---
2102 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2103 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2104 break;
2105 }
2106 /* Fall-thru */
2107 case e1000_pchlan:
2108 case e1000_pch2lan:
2109 case e1000_pch_lpt:
2110 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2111 break;
2112 default:
2113 return ret_val;
2114 }
2115
2116 ret_val = hw->phy.ops.acquire(hw);
2117 if (ret_val)
--- 1093 unchanged lines hidden (view full) ---
3211 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3212 **/
3213static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3214{
3215 u32 eecd;
3216 struct e1000_nvm_info *nvm = &hw->nvm;
3217 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3218 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3219 u8 sig_byte = 0;
3220 s32 ret_val;
3221
3222 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3223
3224 switch (hw->mac.type) {
3225 case e1000_ich8lan:
3226 case e1000_ich9lan:
3227 eecd = E1000_READ_REG(hw, E1000_EECD);
3228 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3229 E1000_EECD_SEC1VAL_VALID_MASK) {
3230 if (eecd & E1000_EECD_SEC1VAL)
3231 *bank = 1;
3232 else
--- 31 unchanged lines hidden (view full) ---
3264 }
3265
3266 DEBUGOUT("ERROR: No valid NVM bank present\n");
3267 return -E1000_ERR_NVM;
3268 }
3269}
3270
3271/**
3272 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3273 * @hw: pointer to the HW structure
3274 * @offset: The offset (in bytes) of the word(s) to read.
3275 * @words: Size of data to read in words
3276 * @data: Pointer to the word(s) to read at offset.
3277 *
3278 * Reads a word(s) from the NVM using the flash access registers.
3279 **/
--- 70 unchanged lines hidden (view full) ---
3350 if (!hsfsts.hsf_status.fldesvalid) {
3351 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3352 return -E1000_ERR_NVM;
3353 }
3354
3355 /* Clear FCERR and DAEL in hw status by writing 1 */
3356 hsfsts.hsf_status.flcerr = 1;
3357 hsfsts.hsf_status.dael = 1;
3358 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3359
3360 /* Either we should have a hardware SPI cycle in progress
3361 * bit to check against, in order to start a new cycle or
3362 * FDONE bit should be changed in the hardware so that it
3363 * is 1 after hardware reset, which can then be used as an
3364 * indication whether a cycle is in progress or has been
3365 * completed.
3366 */
3367
3368 if (!hsfsts.hsf_status.flcinprog) {
3369 /* There is no cycle running at present,
3370 * so we can start a cycle.
3371 * Begin by setting Flash Cycle Done.
3372 */
3373 hsfsts.hsf_status.flcdone = 1;
3374 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3375 ret_val = E1000_SUCCESS;
3376 } else {
3377 s32 i;
3378
3379 /* Otherwise poll for sometime so the current
3380 * cycle has a chance to end before giving up.
3381 */
3382 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
--- 5 unchanged lines hidden (view full) ---
3388 }
3389 usec_delay(1);
3390 }
3391 if (ret_val == E1000_SUCCESS) {
3392 /* Successful in waiting for previous cycle to timeout,
3393 * now set the Flash Cycle Done.
3394 */
3395 hsfsts.hsf_status.flcdone = 1;
3396 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3397 hsfsts.regval);
3398 } else {
3399 DEBUGOUT("Flash controller busy, cannot get access\n");
3400 }
3401 }
3402
3403 return ret_val;
3404}
3405
--- 8 unchanged lines hidden (view full) ---
3414{
3415 union ich8_hws_flash_ctrl hsflctl;
3416 union ich8_hws_flash_status hsfsts;
3417 u32 i = 0;
3418
3419 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3420
3421 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3422 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3423 hsflctl.hsf_ctrl.flcgo = 1;
3424
3425 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3426
3427 /* wait till FDONE bit is set to 1 */
3428 do {
3429 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3430 if (hsfsts.hsf_status.flcdone)
3431 break;
3432 usec_delay(1);
3433 } while (i++ < timeout);
3434
3435 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3436 return E1000_SUCCESS;
3437
3438 return -E1000_ERR_NVM;
3439}
3440
3441/**
3442 * e1000_read_flash_word_ich8lan - Read word from flash
3443 * @hw: pointer to the HW structure
3444 * @offset: offset to data location
3445 * @data: pointer to the location for storing the data
3446 *
3447 * Reads the flash word at offset into data. Offset is converted
3448 * to bytes before read.
3449 **/
--- 20 unchanged lines hidden (view full) ---
3470 * Reads a single byte from the NVM using the flash access registers.
3471 **/
3472static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3473 u8 *data)
3474{
3475 s32 ret_val;
3476 u16 word = 0;
3477
3478 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3479
3480 if (ret_val)
3481 return ret_val;
3482
3483 *data = (u8)word;
3484
3485 return E1000_SUCCESS;
3486}
--- 69 unchanged lines hidden (view full) ---
3556 break;
3557 }
3558 }
3559 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3560
3561 return ret_val;
3562}
3563
3564
3565/**
3566 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3567 * @hw: pointer to the HW structure
3568 * @offset: The offset (in bytes) of the word(s) to write.
3569 * @words: Size of data to write in words
3570 * @data: Pointer to the word(s) to write at offset.
3571 *
3572 * Writes a byte or word to the NVM using the flash access registers.
--- 21 unchanged lines hidden (view full) ---
3594 }
3595
3596 nvm->ops.release(hw);
3597
3598 return E1000_SUCCESS;
3599}
3600
3601/**
3602 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3603 * @hw: pointer to the HW structure
3604 *
3605 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3606 * which writes the checksum to the shadow ram. The changes in the shadow
3607 * ram are then committed to the EEPROM by processing each bank at a time
3608 * checking for the modified bit and writing only the pending changes.
3609 * After a successful commit, the shadow ram is cleared and is ready for
--- 160 unchanged lines hidden (view full) ---
3770
3771 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
3772 * the checksum needs to be fixed. This bit is an indication that
3773 * the NVM was prepared by OEM software and did not calculate
3774 * the checksum...a likely scenario.
3775 */
3776 switch (hw->mac.type) {
3777 case e1000_pch_lpt:
3778 word = NVM_COMPAT;
3779 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3780 break;
3781 default:
3782 word = NVM_FUTURE_INIT_WORD1;
3783 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3784 break;
3785 }
--- 31 unchanged lines hidden (view full) ---
3817 union ich8_hws_flash_ctrl hsflctl;
3818 u32 flash_linear_addr;
3819 u32 flash_data = 0;
3820 s32 ret_val;
3821 u8 count = 0;
3822
3823 DEBUGFUNC("e1000_write_ich8_data");
3824
3825 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3826 return -E1000_ERR_NVM;
3827
3828 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3829 hw->nvm.flash_base_addr);
3830
3831 do {
3832 usec_delay(1);
3833 /* Steps */
3834 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3835 if (ret_val != E1000_SUCCESS)
3836 break;
3837 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3838
3839 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3840 hsflctl.hsf_ctrl.fldbcount = size - 1;
3841 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3842 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3843
3844 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3845
3846 if (size == 1)
3847 flash_data = (u32)data & 0x00FF;
3848 else
3849 flash_data = (u32)data;
3850
--- 21 unchanged lines hidden (view full) ---
3872 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3873 break;
3874 }
3875 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3876
3877 return ret_val;
3878}
3879
3880
3881/**
3882 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3883 * @hw: pointer to the HW structure
3884 * @offset: The index of the byte to read.
3885 * @data: The byte to write to the NVM.
3886 *
3887 * Writes a single byte to the NVM using the flash access registers.
3888 **/
3889static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3890 u8 data)
3891{
3892 u16 word = (u16)data;
3893
3894 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3895
3896 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3897}
3898
3899
3900
3901/**
3902 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3903 * @hw: pointer to the HW structure
3904 * @offset: The offset of the byte to write.
3905 * @byte: The byte to write to the NVM.
3906 *
3907 * Writes a single byte to the NVM using the flash access registers.
3908 * Goes through a retry algorithm before giving up.
--- 92 unchanged lines hidden (view full) ---
4001 /* Steps */
4002 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4003 if (ret_val)
4004 return ret_val;
4005
4006 /* Write a value 11 (block Erase) in Flash
4007 * Cycle field in hw flash control
4008 */
4009 hsflctl.regval =
4010 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4011
4012 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4013 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4014 hsflctl.regval);
4015
4016 /* Write the last 24 bits of an index within the
4017 * block into Flash Linear address field in Flash
4018 * Address.
4019 */
4020 flash_linear_addr += (j * sector_size);
4021 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4022 flash_linear_addr);
--- 416 unchanged lines hidden (view full) ---
4439 /* Disable IPv6 extension header parsing because some malformed
4440 * IPv6 headers can hang the Rx.
4441 */
4442 if (hw->mac.type == e1000_ich8lan)
4443 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4444 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
4445
4446 /* Enable ECC on Lynxpoint */
4447 if (hw->mac.type == e1000_pch_lpt) {
4448 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
4449 reg |= E1000_PBECCSTS_ECC_ENABLE;
4450 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
4451
4452 reg = E1000_READ_REG(hw, E1000_CTRL);
4453 reg |= E1000_CTRL_MEHE;
4454 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4455 }
--- 415 unchanged lines hidden (view full) ---
4871 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4872
4873 if (hw->phy.type == e1000_phy_i217) {
4874 u16 phy_reg, device_id = hw->device_id;
4875
4876 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4877 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4878 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4879 (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4880 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4881
4882 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
4883 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4884 }
4885
4886 ret_val = hw->phy.ops.acquire(hw);
4887 if (ret_val)
--- 99 unchanged lines hidden (view full) ---
4987 * @hw: pointer to the HW structure
4988 *
4989 * During Sx to S0 transitions on non-managed devices or managed devices
4990 * on which PHY resets are not blocked, if the PHY registers cannot be
4991 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4992 * the PHY.
4993 * On i217, setup Intel Rapid Start Technology.
4994 **/
4995void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4996{
4997 s32 ret_val;
4998
4999 DEBUGFUNC("e1000_resume_workarounds_pchlan");
5000 if (hw->mac.type < e1000_pch2lan)
5001 return;
5002
5003 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5004 if (ret_val) {
5005 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5006 return;
5007 }
5008
5009 /* For i217 Intel Rapid Start Technology support when the system
5010 * is transitioning from Sx and no manageability engine is present
5011 * configure SMBus to restore on reset, disable proxy, and enable
5012 * the reset on MTA (Multicast table array).
5013 */
5014 if (hw->phy.type == e1000_phy_i217) {
5015 u16 phy_reg;
5016
5017 ret_val = hw->phy.ops.acquire(hw);
5018 if (ret_val) {
5019 DEBUGOUT("Failed to setup iRST\n");
5020 return;
5021 }
5022
5023 /* Clear Auto Enable LPI after link up */
5024 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5025 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5026 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5027
5028 if (!(E1000_READ_REG(hw, E1000_FWSM) &
--- 17 unchanged lines hidden (view full) ---
5046 if (ret_val)
5047 goto release;
5048 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5049 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5050release:
5051 if (ret_val)
5052 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5053 hw->phy.ops.release(hw);
5054 }
5055}
5056
5057/**
5058 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5059 * @hw: pointer to the HW structure
5060 *
5061 * Return the LED back to the default configuration.
5062 **/
--- 279 unchanged lines hidden ---