| socfpga-sockit-beri.dts (275049) | socfpga-sockit-beri.dts (275647) |
|---|---|
| 1/*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * --- 13 unchanged lines hidden (view full) --- 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * | 1/*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * --- 13 unchanged lines hidden (view full) --- 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * |
| 30 * $FreeBSD: head/sys/boot/fdt/dts/arm/socfpga-sockit-beri.dts 275049 2014-11-25 16:06:19Z br $ | 30 * $FreeBSD: head/sys/boot/fdt/dts/arm/socfpga-sockit-beri.dts 275647 2014-12-09 16:39:21Z br $ |
| 31 */ 32 33/dts-v1/; 34 35/include/ "socfpga.dtsi" 36 37/ { 38 model = "Terasic SoCKit"; 39 compatible = "altr,socfpga-cyclone5", "altr,socfpga"; 40 41 memreserve = < 0x00000000 0x1000 >, /* SMP trampoline */ | 31 */ 32 33/dts-v1/; 34 35/include/ "socfpga.dtsi" 36 37/ { 38 model = "Terasic SoCKit"; 39 compatible = "altr,socfpga-cyclone5", "altr,socfpga"; 40 41 memreserve = < 0x00000000 0x1000 >, /* SMP trampoline */ |
| 42 < 0x00001000 0x1000 >; /* virtio block */ | 42 < 0x00001000 0x1000 >, /* virtio block */ 43 < 0x00002000 0x1000 >; /* virtio net */ |
| 43 44 memory { 45 device_type = "memory"; 46 reg = < 0x00000000 0x40000000 >; /* 1G RAM */ 47 }; 48 49 SOC: socfpga { 50 serial0: serial@ffc02000 { --- 55 unchanged lines hidden (view full) --- 106 }; 107 108 beri_vtblk: vtblk@00001000 { 109 compatible = "sri-cambridge,beri-vtblk"; 110 reg = <0x00001000 0x1000>; 111 pio-recv = <&pio0>; 112 pio-send = <&pio1>; 113 beri-mem = <&beri_mem0>; | 44 45 memory { 46 device_type = "memory"; 47 reg = < 0x00000000 0x40000000 >; /* 1G RAM */ 48 }; 49 50 SOC: socfpga { 51 serial0: serial@ffc02000 { --- 55 unchanged lines hidden (view full) --- 107 }; 108 109 beri_vtblk: vtblk@00001000 { 110 compatible = "sri-cambridge,beri-vtblk"; 111 reg = <0x00001000 0x1000>; 112 pio-recv = <&pio0>; 113 pio-send = <&pio1>; 114 beri-mem = <&beri_mem0>; |
| 115 status = "disabled"; 116 }; 117 118 beri_vtnet: vtnet@00002000 { 119 compatible = "sri-cambridge,beri-vtnet"; 120 reg = <0x00002000 0x1000>; 121 pio-recv = <&pio0>; 122 pio-send = <&pio1>; 123 beri-mem = <&beri_mem0>; |
|
| 114 status = "okay"; 115 }; 116 117 beri_debug: ring@c0000000 { 118 compatible = "sri-cambridge,beri-ring"; 119 reg = <0xc0000000 0x3000>; 120 interrupts = < 72 73 >; 121 interrupt-parent = <&GIC>; --- 30 unchanged lines hidden --- | 124 status = "okay"; 125 }; 126 127 beri_debug: ring@c0000000 { 128 compatible = "sri-cambridge,beri-ring"; 129 reg = <0xc0000000 0x3000>; 130 interrupts = < 72 73 >; 131 interrupt-parent = <&GIC>; --- 30 unchanged lines hidden --- |