| socfpga-sockit-beri.dts (273469) | socfpga-sockit-beri.dts (275049) |
|---|---|
| 1/*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * --- 13 unchanged lines hidden (view full) --- 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * | 1/*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * --- 13 unchanged lines hidden (view full) --- 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * |
| 30 * $FreeBSD: head/sys/boot/fdt/dts/arm/socfpga-sockit-beri.dts 273469 2014-10-22 11:30:03Z br $ | 30 * $FreeBSD: head/sys/boot/fdt/dts/arm/socfpga-sockit-beri.dts 275049 2014-11-25 16:06:19Z br $ |
| 31 */ 32 33/dts-v1/; 34 35/include/ "socfpga.dtsi" 36 37/ { 38 model = "Terasic SoCKit"; 39 compatible = "altr,socfpga-cyclone5", "altr,socfpga"; 40 | 31 */ 32 33/dts-v1/; 34 35/include/ "socfpga.dtsi" 36 37/ { 38 model = "Terasic SoCKit"; 39 compatible = "altr,socfpga-cyclone5", "altr,socfpga"; 40 |
| 41 /* Reserve first page for secondary CPU trampoline code */ 42 memreserve = < 0x00000000 0x1000 >; | 41 memreserve = < 0x00000000 0x1000 >, /* SMP trampoline */ 42 < 0x00001000 0x1000 >; /* virtio block */ |
| 43 44 memory { 45 device_type = "memory"; 46 reg = < 0x00000000 0x40000000 >; /* 1G RAM */ 47 }; 48 49 SOC: socfpga { 50 serial0: serial@ffc02000 { --- 13 unchanged lines hidden (view full) --- 64 rxd3-skew-ps = <0>; 65 txen-skew-ps = <0>; 66 txc-skew-ps = <2600>; 67 rxdv-skew-ps = <0>; 68 rxc-skew-ps = <2000>; 69 }; 70 71 mmc: dwmmc@ff704000 { | 43 44 memory { 45 device_type = "memory"; 46 reg = < 0x00000000 0x40000000 >; /* 1G RAM */ 47 }; 48 49 SOC: socfpga { 50 serial0: serial@ffc02000 { --- 13 unchanged lines hidden (view full) --- 64 rxd3-skew-ps = <0>; 65 txen-skew-ps = <0>; 66 txc-skew-ps = <2600>; 67 rxdv-skew-ps = <0>; 68 rxc-skew-ps = <2000>; 69 }; 70 71 mmc: dwmmc@ff704000 { |
| 72 #address-cells = <1>; 73 #size-cells = <0>; |
|
| 72 status = "okay"; 73 num-slots = <1>; 74 supports-highspeed; 75 broken-cd; 76 bus-frequency = <25000000>; 77 78 slot@0 { 79 reg = <0>; 80 bus-width = <4>; 81 }; 82 }; 83 | 74 status = "okay"; 75 num-slots = <1>; 76 supports-highspeed; 77 broken-cd; 78 bus-frequency = <25000000>; 79 80 slot@0 { 81 reg = <0>; 82 bus-width = <4>; 83 }; 84 }; 85 |
| 84 beri_mem: mem@d0000000 { | 86 beri_mem0: mem@d0000000 { |
| 85 compatible = "sri-cambridge,beri-mem"; | 87 compatible = "sri-cambridge,beri-mem"; |
| 86 reg = <0xd0000000 0x10000000>; | 88 reg = <0xd0000000 0x10000000>; /* 256mb */ |
| 87 status = "okay"; 88 }; 89 | 89 status = "okay"; 90 }; 91 |
| 92 pio0: pio@c0020000 { 93 compatible = "altr,pio"; 94 reg = <0xc0020000 0x1000>; /* recv */ 95 interrupts = < 76 >; 96 interrupt-parent = <&GIC>; 97 status = "okay"; 98 }; 99 100 pio1: pio@c0021000 { 101 compatible = "altr,pio"; 102 reg = <0xc0021000 0x1000>; /* send */ 103 interrupts = < 82 >; /* not in use on arm side */ 104 interrupt-parent = <&GIC>; 105 status = "okay"; 106 }; 107 108 beri_vtblk: vtblk@00001000 { 109 compatible = "sri-cambridge,beri-vtblk"; 110 reg = <0x00001000 0x1000>; 111 pio-recv = <&pio0>; 112 pio-send = <&pio1>; 113 beri-mem = <&beri_mem0>; 114 status = "okay"; 115 }; 116 |
|
| 90 beri_debug: ring@c0000000 { 91 compatible = "sri-cambridge,beri-ring"; 92 reg = <0xc0000000 0x3000>; 93 interrupts = < 72 73 >; 94 interrupt-parent = <&GIC>; 95 device_name = "beri_debug"; 96 data_size = <0x1000>; 97 data_read = <0x0>; --- 27 unchanged lines hidden --- | 117 beri_debug: ring@c0000000 { 118 compatible = "sri-cambridge,beri-ring"; 119 reg = <0xc0000000 0x3000>; 120 interrupts = < 72 73 >; 121 interrupt-parent = <&GIC>; 122 device_name = "beri_debug"; 123 data_size = <0x1000>; 124 data_read = <0x0>; --- 27 unchanged lines hidden --- |