1/*-
2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
| 1/*-
2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
|
31 */
32
33/dts-v1/;
34
35/include/ "socfpga.dtsi"
36
37/ {
38 model = "Terasic SoCKit";
39 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
40
41 /* Reserve first page for secondary CPU trampoline code */
42 memreserve = < 0x00000000 0x1000 >;
43
44 memory {
45 device_type = "memory";
46 reg = < 0x00000000 0x40000000 >; /* 1G RAM */
47 };
48
49 SOC: socfpga {
50 serial0: serial@ffc02000 {
51 status = "okay";
52 };
53
54 usb1: usb@ffb40000 {
55 status = "okay";
56 };
57
58 gmac1: ethernet@ff702000 {
59 status = "okay";
| 31 */
32
33/dts-v1/;
34
35/include/ "socfpga.dtsi"
36
37/ {
38 model = "Terasic SoCKit";
39 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
40
41 /* Reserve first page for secondary CPU trampoline code */
42 memreserve = < 0x00000000 0x1000 >;
43
44 memory {
45 device_type = "memory";
46 reg = < 0x00000000 0x40000000 >; /* 1G RAM */
47 };
48
49 SOC: socfpga {
50 serial0: serial@ffc02000 {
51 status = "okay";
52 };
53
54 usb1: usb@ffb40000 {
55 status = "okay";
56 };
57
58 gmac1: ethernet@ff702000 {
59 status = "okay";
|
73 };
74
75 beri_debug: ring@c0000000 {
76 compatible = "sri-cambridge,beri-ring";
77 reg = <0xc0000000 0x3000>;
78 interrupts = < 72 73 >;
79 interrupt-parent = <&GIC>;
80 device_name = "beri_debug";
81 data_size = <0x1000>;
82 data_read = <0x0>;
83 data_write = <0x1000>;
84 control_read = <0x2000>;
85 control_write = <0x2010>;
86 status = "okay";
87 };
88
89 beri_console: ring@c0004000 {
90 compatible = "sri-cambridge,beri-ring";
91 reg = <0xc0004000 0x3000>;
92 interrupts = < 74 75 >;
93 interrupt-parent = <&GIC>;
94 device_name = "beri_console";
95 data_size = <0x1000>;
96 data_read = <0x0>;
97 data_write = <0x1000>;
98 control_read = <0x2000>;
99 control_write = <0x2010>;
100 status = "okay";
101 };
102 };
103
104 chosen {
105 bootargs = "-v";
106 stdin = "serial0";
107 stdout = "serial0";
108 };
109};
| 82 };
83
84 beri_debug: ring@c0000000 {
85 compatible = "sri-cambridge,beri-ring";
86 reg = <0xc0000000 0x3000>;
87 interrupts = < 72 73 >;
88 interrupt-parent = <&GIC>;
89 device_name = "beri_debug";
90 data_size = <0x1000>;
91 data_read = <0x0>;
92 data_write = <0x1000>;
93 control_read = <0x2000>;
94 control_write = <0x2010>;
95 status = "okay";
96 };
97
98 beri_console: ring@c0004000 {
99 compatible = "sri-cambridge,beri-ring";
100 reg = <0xc0004000 0x3000>;
101 interrupts = < 74 75 >;
102 interrupt-parent = <&GIC>;
103 device_name = "beri_console";
104 data_size = <0x1000>;
105 data_read = <0x0>;
106 data_write = <0x1000>;
107 control_read = <0x2000>;
108 control_write = <0x2010>;
109 status = "okay";
110 };
111 };
112
113 chosen {
114 bootargs = "-v";
115 stdin = "serial0";
116 stdout = "serial0";
117 };
118};
|