1/*-
2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
3 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
| 1/*-
2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
3 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
|
28 */
29
30#ifndef _MACHINE_CPUINFO_H_
31#define _MACHINE_CPUINFO_H_
32
33#include <sys/types.h>
34
35struct cpuinfo {
36 /* raw id registers */
37 uint32_t midr;
38 uint32_t ctr;
39 uint32_t tcmtr;
40 uint32_t tlbtr;
41 uint32_t mpidr;
42 uint32_t revidr;
43 uint32_t id_pfr0;
44 uint32_t id_pfr1;
45 uint32_t id_dfr0;
46 uint32_t id_afr0;
47 uint32_t id_mmfr0;
48 uint32_t id_mmfr1;
49 uint32_t id_mmfr2;
50 uint32_t id_mmfr3;
51 uint32_t id_isar0;
52 uint32_t id_isar1;
53 uint32_t id_isar2;
54 uint32_t id_isar3;
55 uint32_t id_isar4;
56 uint32_t id_isar5;
57 uint32_t cbar;
58
59 /* Parsed bits of above registers... */
60
61 /* midr */
62 int implementer;
63 int revision;
64 int architecture;
65 int part_number;
66 int patch;
67
68 /* id_mmfr0 */
69 int outermost_shareability;
70 int shareability_levels;
71 int auxiliary_registers;
72 int innermost_shareability;
73
74 /* id_mmfr1 */
75 int mem_barrier;
76
77 /* id_mmfr3 */
78 int coherent_walk;
79 int maintenance_broadcast;
80
81 /* id_pfr1 */
82 int generic_timer_ext;
83 int virtualization_ext;
84 int security_ext;
| 28 */
29
30#ifndef _MACHINE_CPUINFO_H_
31#define _MACHINE_CPUINFO_H_
32
33#include <sys/types.h>
34
35struct cpuinfo {
36 /* raw id registers */
37 uint32_t midr;
38 uint32_t ctr;
39 uint32_t tcmtr;
40 uint32_t tlbtr;
41 uint32_t mpidr;
42 uint32_t revidr;
43 uint32_t id_pfr0;
44 uint32_t id_pfr1;
45 uint32_t id_dfr0;
46 uint32_t id_afr0;
47 uint32_t id_mmfr0;
48 uint32_t id_mmfr1;
49 uint32_t id_mmfr2;
50 uint32_t id_mmfr3;
51 uint32_t id_isar0;
52 uint32_t id_isar1;
53 uint32_t id_isar2;
54 uint32_t id_isar3;
55 uint32_t id_isar4;
56 uint32_t id_isar5;
57 uint32_t cbar;
58
59 /* Parsed bits of above registers... */
60
61 /* midr */
62 int implementer;
63 int revision;
64 int architecture;
65 int part_number;
66 int patch;
67
68 /* id_mmfr0 */
69 int outermost_shareability;
70 int shareability_levels;
71 int auxiliary_registers;
72 int innermost_shareability;
73
74 /* id_mmfr1 */
75 int mem_barrier;
76
77 /* id_mmfr3 */
78 int coherent_walk;
79 int maintenance_broadcast;
80
81 /* id_pfr1 */
82 int generic_timer_ext;
83 int virtualization_ext;
84 int security_ext;
|