1/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */
2
3/*-
4 * Copyright (c) 1997 Mark Brinicombe.
5 * Copyright (c) 1997 Causality Limited
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Causality Limited.
19 * 4. The name of Causality Limited may not be used to endorse or promote
20 * products derived from this software without specific prior written
21 * permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * RiscBSD kernel project
36 *
37 * cpufunc.h
38 *
39 * Prototypes for cpu, mmu and tlb related functions.
40 *
|
41 * $FreeBSD: head/sys/arm/include/cpufunc.h 243576 2012-11-27 00:41:39Z marcel $
|
| 41 * $FreeBSD: head/sys/arm/include/cpufunc.h 244480 2012-12-20 04:32:02Z gonzo $ |
42 */
43
44#ifndef _MACHINE_CPUFUNC_H_
45#define _MACHINE_CPUFUNC_H_
46
47#ifdef _KERNEL
48
49#include <sys/types.h>
50#include <machine/cpuconf.h>
51#include <machine/katelib.h> /* For in[bwl] and out[bwl] */
52
53static __inline void
54breakpoint(void)
55{
56 __asm(".word 0xe7ffffff");
57}
58
59struct cpu_functions {
60
61 /* CPU functions */
62
63 u_int (*cf_id) (void);
64 void (*cf_cpwait) (void);
65
66 /* MMU functions */
67
68 u_int (*cf_control) (u_int bic, u_int eor);
69 void (*cf_domains) (u_int domains);
70 void (*cf_setttb) (u_int ttb);
71 u_int (*cf_faultstatus) (void);
72 u_int (*cf_faultaddress) (void);
73
74 /* TLB functions */
75
76 void (*cf_tlb_flushID) (void);
77 void (*cf_tlb_flushID_SE) (u_int va);
78 void (*cf_tlb_flushI) (void);
79 void (*cf_tlb_flushI_SE) (u_int va);
80 void (*cf_tlb_flushD) (void);
81 void (*cf_tlb_flushD_SE) (u_int va);
82
83 /*
84 * Cache operations:
85 *
86 * We define the following primitives:
87 *
88 * icache_sync_all Synchronize I-cache
89 * icache_sync_range Synchronize I-cache range
90 *
91 * dcache_wbinv_all Write-back and Invalidate D-cache
92 * dcache_wbinv_range Write-back and Invalidate D-cache range
93 * dcache_inv_range Invalidate D-cache range
94 * dcache_wb_range Write-back D-cache range
95 *
96 * idcache_wbinv_all Write-back and Invalidate D-cache,
97 * Invalidate I-cache
98 * idcache_wbinv_range Write-back and Invalidate D-cache,
99 * Invalidate I-cache range
100 *
101 * Note that the ARM term for "write-back" is "clean". We use
102 * the term "write-back" since it's a more common way to describe
103 * the operation.
104 *
105 * There are some rules that must be followed:
106 *
107 * I-cache Synch (all or range):
108 * The goal is to synchronize the instruction stream,
109 * so you may beed to write-back dirty D-cache blocks
110 * first. If a range is requested, and you can't
111 * synchronize just a range, you have to hit the whole
112 * thing.
113 *
114 * D-cache Write-Back and Invalidate range:
115 * If you can't WB-Inv a range, you must WB-Inv the
116 * entire D-cache.
117 *
118 * D-cache Invalidate:
119 * If you can't Inv the D-cache, you must Write-Back
120 * and Invalidate. Code that uses this operation
121 * MUST NOT assume that the D-cache will not be written
122 * back to memory.
123 *
124 * D-cache Write-Back:
125 * If you can't Write-back without doing an Inv,
126 * that's fine. Then treat this as a WB-Inv.
127 * Skipping the invalidate is merely an optimization.
128 *
129 * All operations:
130 * Valid virtual addresses must be passed to each
131 * cache operation.
132 */
133 void (*cf_icache_sync_all) (void);
134 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t);
135
136 void (*cf_dcache_wbinv_all) (void);
137 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t);
138 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t);
139 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t);
140
141 void (*cf_idcache_wbinv_all) (void);
142 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
143 void (*cf_l2cache_wbinv_all) (void);
144 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
145 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t);
146 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t);
147
148 /* Other functions */
149
150 void (*cf_flush_prefetchbuf) (void);
151 void (*cf_drain_writebuf) (void);
152 void (*cf_flush_brnchtgt_C) (void);
153 void (*cf_flush_brnchtgt_E) (u_int va);
154
155 void (*cf_sleep) (int mode);
156
157 /* Soft functions */
158
159 int (*cf_dataabt_fixup) (void *arg);
160 int (*cf_prefetchabt_fixup) (void *arg);
161
162 void (*cf_context_switch) (void);
163
164 void (*cf_setup) (char *string);
165};
166
167extern struct cpu_functions cpufuncs;
168extern u_int cputype;
169
170#define cpu_id() cpufuncs.cf_id()
171#define cpu_cpwait() cpufuncs.cf_cpwait()
172
173#define cpu_control(c, e) cpufuncs.cf_control(c, e)
174#define cpu_domains(d) cpufuncs.cf_domains(d)
175#define cpu_setttb(t) cpufuncs.cf_setttb(t)
176#define cpu_faultstatus() cpufuncs.cf_faultstatus()
177#define cpu_faultaddress() cpufuncs.cf_faultaddress()
178
179#ifndef SMP
180
181#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
182#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e)
183#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI()
184#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e)
185#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()
186#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)
187
188#else
189void tlb_broadcast(int);
190
191#ifdef CPU_CORTEXA
192#define TLB_BROADCAST /* No need to explicitely send an IPI */
193#else
194#define TLB_BROADCAST tlb_broadcast(7)
195#endif
196
197#define cpu_tlb_flushID() do { \
198 cpufuncs.cf_tlb_flushID(); \
199 TLB_BROADCAST; \
200} while(0)
201
202#define cpu_tlb_flushID_SE(e) do { \
203 cpufuncs.cf_tlb_flushID_SE(e); \
204 TLB_BROADCAST; \
205} while(0)
206
207
208#define cpu_tlb_flushI() do { \
209 cpufuncs.cf_tlb_flushI(); \
210 TLB_BROADCAST; \
211} while(0)
212
213
214#define cpu_tlb_flushI_SE(e) do { \
215 cpufuncs.cf_tlb_flushI_SE(e); \
216 TLB_BROADCAST; \
217} while(0)
218
219
220#define cpu_tlb_flushD() do { \
221 cpufuncs.cf_tlb_flushD(); \
222 TLB_BROADCAST; \
223} while(0)
224
225
226#define cpu_tlb_flushD_SE(e) do { \
227 cpufuncs.cf_tlb_flushD_SE(e); \
228 TLB_BROADCAST; \
229} while(0)
230
231#endif
232
233#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all()
234#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
235
236#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all()
237#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
238#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
239#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
240
241#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
242#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
243#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all()
244#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
245#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
246#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
247
248#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf()
249#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
250#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C()
251#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e)
252
253#define cpu_sleep(m) cpufuncs.cf_sleep(m)
254
255#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a)
256#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a)
257#define ABORT_FIXUP_OK 0 /* fixup succeeded */
258#define ABORT_FIXUP_FAILED 1 /* fixup failed */
259#define ABORT_FIXUP_RETURN 2 /* abort handler should return */
260
261#define cpu_setup(a) cpufuncs.cf_setup(a)
262
263int set_cpufuncs (void);
264#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
265#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
266
267void cpufunc_nullop (void);
268int cpufunc_null_fixup (void *);
269int early_abort_fixup (void *);
270int late_abort_fixup (void *);
271u_int cpufunc_id (void);
272u_int cpufunc_cpuid (void);
273u_int cpufunc_control (u_int clear, u_int bic);
274void cpufunc_domains (u_int domains);
275u_int cpufunc_faultstatus (void);
276u_int cpufunc_faultaddress (void);
277u_int cpu_pfr (int);
278
279#ifdef CPU_ARM3
280u_int arm3_control (u_int clear, u_int bic);
281void arm3_cache_flush (void);
282#endif /* CPU_ARM3 */
283
284#if defined(CPU_ARM6) || defined(CPU_ARM7)
285void arm67_setttb (u_int ttb);
286void arm67_tlb_flush (void);
287void arm67_tlb_purge (u_int va);
288void arm67_cache_flush (void);
289void arm67_context_switch (void);
290#endif /* CPU_ARM6 || CPU_ARM7 */
291
292#ifdef CPU_ARM6
293void arm6_setup (char *string);
294#endif /* CPU_ARM6 */
295
296#ifdef CPU_ARM7
297void arm7_setup (char *string);
298#endif /* CPU_ARM7 */
299
300#ifdef CPU_ARM7TDMI
301int arm7_dataabt_fixup (void *arg);
302void arm7tdmi_setup (char *string);
303void arm7tdmi_setttb (u_int ttb);
304void arm7tdmi_tlb_flushID (void);
305void arm7tdmi_tlb_flushID_SE (u_int va);
306void arm7tdmi_cache_flushID (void);
307void arm7tdmi_context_switch (void);
308#endif /* CPU_ARM7TDMI */
309
310#ifdef CPU_ARM8
311void arm8_setttb (u_int ttb);
312void arm8_tlb_flushID (void);
313void arm8_tlb_flushID_SE (u_int va);
314void arm8_cache_flushID (void);
315void arm8_cache_flushID_E (u_int entry);
316void arm8_cache_cleanID (void);
317void arm8_cache_cleanID_E (u_int entry);
318void arm8_cache_purgeID (void);
319void arm8_cache_purgeID_E (u_int entry);
320
321void arm8_cache_syncI (void);
322void arm8_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
323void arm8_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
324void arm8_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
325void arm8_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
326void arm8_cache_syncI_rng (vm_offset_t start, vm_size_t end);
327
328void arm8_context_switch (void);
329
330void arm8_setup (char *string);
331
332u_int arm8_clock_config (u_int, u_int);
333#endif
334
335
336#if defined(CPU_FA526) || defined(CPU_FA626TE)
337void fa526_setup (char *arg);
338void fa526_setttb (u_int ttb);
339void fa526_context_switch (void);
340void fa526_cpu_sleep (int);
341void fa526_tlb_flushI_SE (u_int);
342void fa526_tlb_flushID_SE (u_int);
343void fa526_flush_prefetchbuf (void);
344void fa526_flush_brnchtgt_E (u_int);
345
346void fa526_icache_sync_all (void);
347void fa526_icache_sync_range(vm_offset_t start, vm_size_t end);
348void fa526_dcache_wbinv_all (void);
349void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end);
350void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end);
351void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end);
352void fa526_idcache_wbinv_all(void);
353void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end);
354#endif
355
356
357#ifdef CPU_SA110
358void sa110_setup (char *string);
359void sa110_context_switch (void);
360#endif /* CPU_SA110 */
361
362#if defined(CPU_SA1100) || defined(CPU_SA1110)
363void sa11x0_drain_readbuf (void);
364
365void sa11x0_context_switch (void);
366void sa11x0_cpu_sleep (int mode);
367
368void sa11x0_setup (char *string);
369#endif
370
371#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
372void sa1_setttb (u_int ttb);
373
374void sa1_tlb_flushID_SE (u_int va);
375
376void sa1_cache_flushID (void);
377void sa1_cache_flushI (void);
378void sa1_cache_flushD (void);
379void sa1_cache_flushD_SE (u_int entry);
380
381void sa1_cache_cleanID (void);
382void sa1_cache_cleanD (void);
383void sa1_cache_cleanD_E (u_int entry);
384
385void sa1_cache_purgeID (void);
386void sa1_cache_purgeID_E (u_int entry);
387void sa1_cache_purgeD (void);
388void sa1_cache_purgeD_E (u_int entry);
389
390void sa1_cache_syncI (void);
391void sa1_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
392void sa1_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
393void sa1_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
394void sa1_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
395void sa1_cache_syncI_rng (vm_offset_t start, vm_size_t end);
396
397#endif
398
399#ifdef CPU_ARM9
400void arm9_setttb (u_int);
401
402void arm9_tlb_flushID_SE (u_int va);
403
404void arm9_icache_sync_all (void);
405void arm9_icache_sync_range (vm_offset_t, vm_size_t);
406
407void arm9_dcache_wbinv_all (void);
408void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t);
409void arm9_dcache_inv_range (vm_offset_t, vm_size_t);
410void arm9_dcache_wb_range (vm_offset_t, vm_size_t);
411
412void arm9_idcache_wbinv_all (void);
413void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t);
414
415void arm9_context_switch (void);
416
417void arm9_setup (char *string);
418
419extern unsigned arm9_dcache_sets_max;
420extern unsigned arm9_dcache_sets_inc;
421extern unsigned arm9_dcache_index_max;
422extern unsigned arm9_dcache_index_inc;
423#endif
424
425#if defined(CPU_ARM9E) || defined(CPU_ARM10)
426void arm10_setttb (u_int);
427
428void arm10_tlb_flushID_SE (u_int);
429void arm10_tlb_flushI_SE (u_int);
430
431void arm10_icache_sync_all (void);
432void arm10_icache_sync_range (vm_offset_t, vm_size_t);
433
434void arm10_dcache_wbinv_all (void);
435void arm10_dcache_wbinv_range (vm_offset_t, vm_size_t);
436void arm10_dcache_inv_range (vm_offset_t, vm_size_t);
437void arm10_dcache_wb_range (vm_offset_t, vm_size_t);
438
439void arm10_idcache_wbinv_all (void);
440void arm10_idcache_wbinv_range (vm_offset_t, vm_size_t);
441
442void arm10_context_switch (void);
443
444void arm10_setup (char *string);
445
446extern unsigned arm10_dcache_sets_max;
447extern unsigned arm10_dcache_sets_inc;
448extern unsigned arm10_dcache_index_max;
449extern unsigned arm10_dcache_index_inc;
450
451u_int sheeva_control_ext (u_int, u_int);
452void sheeva_cpu_sleep (int);
453void sheeva_setttb (u_int);
454void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t);
455void sheeva_dcache_inv_range (vm_offset_t, vm_size_t);
456void sheeva_dcache_wb_range (vm_offset_t, vm_size_t);
457void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t);
458
459void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t);
460void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t);
461void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t);
462void sheeva_l2cache_wbinv_all (void);
463#endif
464
|
465#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA)
|
465#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || \
466 defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) |
467void arm11_setttb (u_int);
468void arm11_sleep (int);
469
470void arm11_tlb_flushID_SE (u_int);
471void arm11_tlb_flushI_SE (u_int);
472
473void arm11_context_switch (void);
474
475void arm11_setup (char *string);
476void arm11_tlb_flushID (void);
477void arm11_tlb_flushI (void);
478void arm11_tlb_flushD (void);
479void arm11_tlb_flushD_SE (u_int va);
480
481void arm11_drain_writebuf (void);
482
483void pj4b_setttb (u_int);
484
485void pj4b_icache_sync_range (vm_offset_t, vm_size_t);
486
487void pj4b_dcache_wbinv_range (vm_offset_t, vm_size_t);
488void pj4b_dcache_inv_range (vm_offset_t, vm_size_t);
489void pj4b_dcache_wb_range (vm_offset_t, vm_size_t);
490
491void pj4b_idcache_wbinv_range (vm_offset_t, vm_size_t);
492
493void pj4b_drain_readbuf (void);
494void pj4b_flush_brnchtgt_all (void);
495void pj4b_flush_brnchtgt_va (u_int);
496void pj4b_sleep (int);
497
498void armv6_icache_sync_all (void);
499void armv6_icache_sync_range (vm_offset_t, vm_size_t);
500
501void armv6_dcache_wbinv_all (void);
502void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t);
503void armv6_dcache_inv_range (vm_offset_t, vm_size_t);
504void armv6_dcache_wb_range (vm_offset_t, vm_size_t);
505
506void armv6_idcache_wbinv_all (void);
507void armv6_idcache_wbinv_range (vm_offset_t, vm_size_t);
508
509void armv7_setttb (u_int);
510void armv7_tlb_flushID (void);
511void armv7_tlb_flushID_SE (u_int);
512void armv7_icache_sync_range (vm_offset_t, vm_size_t);
513void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t);
514void armv7_dcache_wbinv_all (void);
515void armv7_idcache_wbinv_all (void);
516void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t);
517void armv7_dcache_inv_range (vm_offset_t, vm_size_t);
518void armv7_dcache_wb_range (vm_offset_t, vm_size_t);
519void armv7_cpu_sleep (int);
520void armv7_setup (char *string);
521void armv7_context_switch (void);
522void armv7_drain_writebuf (void);
523void armv7_sev (void);
524u_int armv7_auxctrl (u_int, u_int);
525void pj4bv7_setup (char *string);
526void pj4bv6_setup (char *string);
527void pj4b_config (void);
528
529int get_core_id (void);
530
531void armadaxp_idcache_wbinv_all (void);
532
533void cortexa_setup (char *);
534#endif
535
|
536#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
537void arm11x6_setttb (u_int);
538void arm11x6_idcache_wbinv_all (void);
539void arm11x6_dcache_wbinv_all (void);
540void arm11x6_icache_sync_all (void);
541void arm11x6_flush_prefetchbuf (void);
542void arm11x6_icache_sync_range (vm_offset_t, vm_size_t);
543void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t);
544void arm11x6_setup (char *string);
545void arm11x6_sleep (int); /* no ref. for errata */
546#endif
547#if defined(CPU_ARM1136)
548void arm1136_sleep_rev0 (int); /* for errata 336501 */
549#endif
550 |
551#if defined(CPU_ARM9E) || defined (CPU_ARM10)
552void armv5_ec_setttb(u_int);
553
554void armv5_ec_icache_sync_all(void);
555void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t);
556
557void armv5_ec_dcache_wbinv_all(void);
558void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t);
559void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t);
560void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t);
561
562void armv5_ec_idcache_wbinv_all(void);
563void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t);
564#endif
565
566#if defined (CPU_ARM10)
567void armv5_setttb(u_int);
568
569void armv5_icache_sync_all(void);
570void armv5_icache_sync_range(vm_offset_t, vm_size_t);
571
572void armv5_dcache_wbinv_all(void);
573void armv5_dcache_wbinv_range(vm_offset_t, vm_size_t);
574void armv5_dcache_inv_range(vm_offset_t, vm_size_t);
575void armv5_dcache_wb_range(vm_offset_t, vm_size_t);
576
577void armv5_idcache_wbinv_all(void);
578void armv5_idcache_wbinv_range(vm_offset_t, vm_size_t);
579
580extern unsigned armv5_dcache_sets_max;
581extern unsigned armv5_dcache_sets_inc;
582extern unsigned armv5_dcache_index_max;
583extern unsigned armv5_dcache_index_inc;
584#endif
585
586#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \
587 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
588 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
589 defined(CPU_FA526) || defined(CPU_FA626TE) || \
590 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
591 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
592
593void armv4_tlb_flushID (void);
594void armv4_tlb_flushI (void);
595void armv4_tlb_flushD (void);
596void armv4_tlb_flushD_SE (u_int va);
597
598void armv4_drain_writebuf (void);
599#endif
600
601#if defined(CPU_IXP12X0)
602void ixp12x0_drain_readbuf (void);
603void ixp12x0_context_switch (void);
604void ixp12x0_setup (char *string);
605#endif
606
607#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
608 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
609 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
610void xscale_cpwait (void);
611
612void xscale_cpu_sleep (int mode);
613
614u_int xscale_control (u_int clear, u_int bic);
615
616void xscale_setttb (u_int ttb);
617
618void xscale_tlb_flushID_SE (u_int va);
619
620void xscale_cache_flushID (void);
621void xscale_cache_flushI (void);
622void xscale_cache_flushD (void);
623void xscale_cache_flushD_SE (u_int entry);
624
625void xscale_cache_cleanID (void);
626void xscale_cache_cleanD (void);
627void xscale_cache_cleanD_E (u_int entry);
628
629void xscale_cache_clean_minidata (void);
630
631void xscale_cache_purgeID (void);
632void xscale_cache_purgeID_E (u_int entry);
633void xscale_cache_purgeD (void);
634void xscale_cache_purgeD_E (u_int entry);
635
636void xscale_cache_syncI (void);
637void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
638void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
639void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
640void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
641void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end);
642void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end);
643
644void xscale_context_switch (void);
645
646void xscale_setup (char *string);
647#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
648 CPU_XSCALE_80219 */
649
650#ifdef CPU_XSCALE_81342
651
652void xscalec3_l2cache_purge (void);
653void xscalec3_cache_purgeID (void);
654void xscalec3_cache_purgeD (void);
655void xscalec3_cache_cleanID (void);
656void xscalec3_cache_cleanD (void);
657void xscalec3_cache_syncI (void);
658
659void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
660void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
661void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
662void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
663void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end);
664
665void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t);
666void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end);
667void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end);
668
669
670void xscalec3_setttb (u_int ttb);
671void xscalec3_context_switch (void);
672
673#endif /* CPU_XSCALE_81342 */
674
675#define tlb_flush cpu_tlb_flushID
676#define setttb cpu_setttb
677#define drain_writebuf cpu_drain_writebuf
678
679/*
680 * Macros for manipulating CPU interrupts
681 */
682static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__));
683
684static __inline u_int32_t
685__set_cpsr_c(u_int bic, u_int eor)
686{
687 u_int32_t tmp, ret;
688
689 __asm __volatile(
690 "mrs %0, cpsr\n" /* Get the CPSR */
691 "bic %1, %0, %2\n" /* Clear bits */
692 "eor %1, %1, %3\n" /* XOR bits */
693 "msr cpsr_c, %1\n" /* Set the control field of CPSR */
694 : "=&r" (ret), "=&r" (tmp)
695 : "r" (bic), "r" (eor) : "memory");
696
697 return ret;
698}
699
700#define ARM_CPSR_F32 (1 << 6) /* FIQ disable */
701#define ARM_CPSR_I32 (1 << 7) /* IRQ disable */
702
703#define disable_interrupts(mask) \
704 (__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), \
705 (mask) & (ARM_CPSR_I32 | ARM_CPSR_F32)))
706
707#define enable_interrupts(mask) \
708 (__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), 0))
709
710#define restore_interrupts(old_cpsr) \
711 (__set_cpsr_c((ARM_CPSR_I32 | ARM_CPSR_F32), \
712 (old_cpsr) & (ARM_CPSR_I32 | ARM_CPSR_F32)))
713
714static __inline register_t
715intr_disable(void)
716{
717 register_t s;
718
719 s = disable_interrupts(ARM_CPSR_I32 | ARM_CPSR_F32);
720 return (s);
721}
722
723static __inline void
724intr_restore(register_t s)
725{
726
727 restore_interrupts(s);
728}
729
730/* Functions to manipulate the CPSR. */
731u_int SetCPSR(u_int bic, u_int eor);
732u_int GetCPSR(void);
733
734/*
735 * Functions to manipulate cpu r13
736 * (in arm/arm32/setstack.S)
737 */
738
739void set_stackptr (u_int mode, u_int address);
740u_int get_stackptr (u_int mode);
741
742/*
743 * Miscellany
744 */
745
746int get_pc_str_offset (void);
747
748/*
749 * CPU functions from locore.S
750 */
751
752void cpu_reset (void) __attribute__((__noreturn__));
753
754/*
755 * Cache info variables.
756 */
757
758/* PRIMARY CACHE VARIABLES */
759extern int arm_picache_size;
760extern int arm_picache_line_size;
761extern int arm_picache_ways;
762
763extern int arm_pdcache_size; /* and unified */
764extern int arm_pdcache_line_size;
765extern int arm_pdcache_ways;
766
767extern int arm_pcache_type;
768extern int arm_pcache_unified;
769
770extern int arm_dcache_align;
771extern int arm_dcache_align_mask;
772
773extern u_int arm_cache_level;
774extern u_int arm_cache_loc;
775extern u_int arm_cache_type[14];
776
777#endif /* _KERNEL */
778#endif /* _MACHINE_CPUFUNC_H_ */
779
780/* End of cpufunc.h */
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