1/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */
2
3/*-
4 * Copyright (c) 1997 Mark Brinicombe.
5 * Copyright (c) 1997 Causality Limited
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Causality Limited.
19 * 4. The name of Causality Limited may not be used to endorse or promote
20 * products derived from this software without specific prior written
21 * permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * RiscBSD kernel project
36 *
37 * cpufunc.h
38 *
39 * Prototypes for cpu, mmu and tlb related functions.
40 *
| 1/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */
2
3/*-
4 * Copyright (c) 1997 Mark Brinicombe.
5 * Copyright (c) 1997 Causality Limited
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Causality Limited.
19 * 4. The name of Causality Limited may not be used to endorse or promote
20 * products derived from this software without specific prior written
21 * permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * RiscBSD kernel project
36 *
37 * cpufunc.h
38 *
39 * Prototypes for cpu, mmu and tlb related functions.
40 *
|
41 * $FreeBSD: head/sys/arm/include/cpufunc.h 212825 2010-09-18 16:57:05Z mav $
| 41 * $FreeBSD: head/sys/arm/include/cpufunc.h 236992 2012-06-13 05:02:51Z imp $
|
42 */
43
44#ifndef _MACHINE_CPUFUNC_H_
45#define _MACHINE_CPUFUNC_H_
46
47#ifdef _KERNEL
48
49#include <sys/types.h>
50#include <machine/cpuconf.h>
51#include <machine/katelib.h> /* For in[bwl] and out[bwl] */
52
53static __inline void
54breakpoint(void)
55{
56 __asm(".word 0xe7ffffff");
57}
58
59struct cpu_functions {
60
61 /* CPU functions */
62
63 u_int (*cf_id) (void);
64 void (*cf_cpwait) (void);
65
66 /* MMU functions */
67
68 u_int (*cf_control) (u_int bic, u_int eor);
69 void (*cf_domains) (u_int domains);
70 void (*cf_setttb) (u_int ttb);
71 u_int (*cf_faultstatus) (void);
72 u_int (*cf_faultaddress) (void);
73
74 /* TLB functions */
75
76 void (*cf_tlb_flushID) (void);
77 void (*cf_tlb_flushID_SE) (u_int va);
78 void (*cf_tlb_flushI) (void);
79 void (*cf_tlb_flushI_SE) (u_int va);
80 void (*cf_tlb_flushD) (void);
81 void (*cf_tlb_flushD_SE) (u_int va);
82
83 /*
84 * Cache operations:
85 *
86 * We define the following primitives:
87 *
88 * icache_sync_all Synchronize I-cache
89 * icache_sync_range Synchronize I-cache range
90 *
91 * dcache_wbinv_all Write-back and Invalidate D-cache
92 * dcache_wbinv_range Write-back and Invalidate D-cache range
93 * dcache_inv_range Invalidate D-cache range
94 * dcache_wb_range Write-back D-cache range
95 *
96 * idcache_wbinv_all Write-back and Invalidate D-cache,
97 * Invalidate I-cache
98 * idcache_wbinv_range Write-back and Invalidate D-cache,
99 * Invalidate I-cache range
100 *
101 * Note that the ARM term for "write-back" is "clean". We use
102 * the term "write-back" since it's a more common way to describe
103 * the operation.
104 *
105 * There are some rules that must be followed:
106 *
107 * I-cache Synch (all or range):
108 * The goal is to synchronize the instruction stream,
109 * so you may beed to write-back dirty D-cache blocks
110 * first. If a range is requested, and you can't
111 * synchronize just a range, you have to hit the whole
112 * thing.
113 *
114 * D-cache Write-Back and Invalidate range:
115 * If you can't WB-Inv a range, you must WB-Inv the
116 * entire D-cache.
117 *
118 * D-cache Invalidate:
119 * If you can't Inv the D-cache, you must Write-Back
120 * and Invalidate. Code that uses this operation
121 * MUST NOT assume that the D-cache will not be written
122 * back to memory.
123 *
124 * D-cache Write-Back:
125 * If you can't Write-back without doing an Inv,
126 * that's fine. Then treat this as a WB-Inv.
127 * Skipping the invalidate is merely an optimization.
128 *
129 * All operations:
130 * Valid virtual addresses must be passed to each
131 * cache operation.
132 */
133 void (*cf_icache_sync_all) (void);
134 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t);
135
136 void (*cf_dcache_wbinv_all) (void);
137 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t);
138 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t);
139 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t);
140
141 void (*cf_idcache_wbinv_all) (void);
142 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
143 void (*cf_l2cache_wbinv_all) (void);
144 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
145 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t);
146 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t);
147
148 /* Other functions */
149
150 void (*cf_flush_prefetchbuf) (void);
151 void (*cf_drain_writebuf) (void);
152 void (*cf_flush_brnchtgt_C) (void);
153 void (*cf_flush_brnchtgt_E) (u_int va);
154
155 void (*cf_sleep) (int mode);
156
157 /* Soft functions */
158
159 int (*cf_dataabt_fixup) (void *arg);
160 int (*cf_prefetchabt_fixup) (void *arg);
161
162 void (*cf_context_switch) (void);
163
164 void (*cf_setup) (char *string);
165};
166
167extern struct cpu_functions cpufuncs;
168extern u_int cputype;
169
170#define cpu_id() cpufuncs.cf_id()
171#define cpu_cpwait() cpufuncs.cf_cpwait()
172
173#define cpu_control(c, e) cpufuncs.cf_control(c, e)
174#define cpu_domains(d) cpufuncs.cf_domains(d)
175#define cpu_setttb(t) cpufuncs.cf_setttb(t)
176#define cpu_faultstatus() cpufuncs.cf_faultstatus()
177#define cpu_faultaddress() cpufuncs.cf_faultaddress()
178
179#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
180#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e)
181#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI()
182#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e)
183#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()
184#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)
185
186#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all()
187#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
188
189#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all()
190#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
191#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
192#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
193
194#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
195#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
196#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all()
197#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
198#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
199#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
200
201#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf()
202#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
203#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C()
204#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e)
205
206#define cpu_sleep(m) cpufuncs.cf_sleep(m)
207
208#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a)
209#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a)
210#define ABORT_FIXUP_OK 0 /* fixup succeeded */
211#define ABORT_FIXUP_FAILED 1 /* fixup failed */
212#define ABORT_FIXUP_RETURN 2 /* abort handler should return */
213
214#define cpu_setup(a) cpufuncs.cf_setup(a)
215
216int set_cpufuncs (void);
217#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
218#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
219
220void cpufunc_nullop (void);
221int cpufunc_null_fixup (void *);
222int early_abort_fixup (void *);
223int late_abort_fixup (void *);
224u_int cpufunc_id (void);
225u_int cpufunc_control (u_int clear, u_int bic);
226void cpufunc_domains (u_int domains);
227u_int cpufunc_faultstatus (void);
228u_int cpufunc_faultaddress (void);
229
230#ifdef CPU_ARM3
231u_int arm3_control (u_int clear, u_int bic);
232void arm3_cache_flush (void);
233#endif /* CPU_ARM3 */
234
235#if defined(CPU_ARM6) || defined(CPU_ARM7)
236void arm67_setttb (u_int ttb);
237void arm67_tlb_flush (void);
238void arm67_tlb_purge (u_int va);
239void arm67_cache_flush (void);
240void arm67_context_switch (void);
241#endif /* CPU_ARM6 || CPU_ARM7 */
242
243#ifdef CPU_ARM6
244void arm6_setup (char *string);
245#endif /* CPU_ARM6 */
246
247#ifdef CPU_ARM7
248void arm7_setup (char *string);
249#endif /* CPU_ARM7 */
250
251#ifdef CPU_ARM7TDMI
252int arm7_dataabt_fixup (void *arg);
253void arm7tdmi_setup (char *string);
254void arm7tdmi_setttb (u_int ttb);
255void arm7tdmi_tlb_flushID (void);
256void arm7tdmi_tlb_flushID_SE (u_int va);
257void arm7tdmi_cache_flushID (void);
258void arm7tdmi_context_switch (void);
259#endif /* CPU_ARM7TDMI */
260
261#ifdef CPU_ARM8
262void arm8_setttb (u_int ttb);
263void arm8_tlb_flushID (void);
264void arm8_tlb_flushID_SE (u_int va);
265void arm8_cache_flushID (void);
266void arm8_cache_flushID_E (u_int entry);
267void arm8_cache_cleanID (void);
268void arm8_cache_cleanID_E (u_int entry);
269void arm8_cache_purgeID (void);
270void arm8_cache_purgeID_E (u_int entry);
271
272void arm8_cache_syncI (void);
273void arm8_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
274void arm8_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
275void arm8_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
276void arm8_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
277void arm8_cache_syncI_rng (vm_offset_t start, vm_size_t end);
278
279void arm8_context_switch (void);
280
281void arm8_setup (char *string);
282
283u_int arm8_clock_config (u_int, u_int);
284#endif
285
286
287#if defined(CPU_FA526) || defined(CPU_FA626TE)
288void fa526_setup (char *arg);
289void fa526_setttb (u_int ttb);
290void fa526_context_switch (void);
291void fa526_cpu_sleep (int);
292void fa526_tlb_flushI_SE (u_int);
293void fa526_tlb_flushID_SE (u_int);
294void fa526_flush_prefetchbuf (void);
295void fa526_flush_brnchtgt_E (u_int);
296
297void fa526_icache_sync_all (void);
298void fa526_icache_sync_range(vm_offset_t start, vm_size_t end);
299void fa526_dcache_wbinv_all (void);
300void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end);
301void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end);
302void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end);
303void fa526_idcache_wbinv_all(void);
304void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end);
305#endif
306
307
308#ifdef CPU_SA110
309void sa110_setup (char *string);
310void sa110_context_switch (void);
311#endif /* CPU_SA110 */
312
313#if defined(CPU_SA1100) || defined(CPU_SA1110)
314void sa11x0_drain_readbuf (void);
315
316void sa11x0_context_switch (void);
317void sa11x0_cpu_sleep (int mode);
| 42 */
43
44#ifndef _MACHINE_CPUFUNC_H_
45#define _MACHINE_CPUFUNC_H_
46
47#ifdef _KERNEL
48
49#include <sys/types.h>
50#include <machine/cpuconf.h>
51#include <machine/katelib.h> /* For in[bwl] and out[bwl] */
52
53static __inline void
54breakpoint(void)
55{
56 __asm(".word 0xe7ffffff");
57}
58
59struct cpu_functions {
60
61 /* CPU functions */
62
63 u_int (*cf_id) (void);
64 void (*cf_cpwait) (void);
65
66 /* MMU functions */
67
68 u_int (*cf_control) (u_int bic, u_int eor);
69 void (*cf_domains) (u_int domains);
70 void (*cf_setttb) (u_int ttb);
71 u_int (*cf_faultstatus) (void);
72 u_int (*cf_faultaddress) (void);
73
74 /* TLB functions */
75
76 void (*cf_tlb_flushID) (void);
77 void (*cf_tlb_flushID_SE) (u_int va);
78 void (*cf_tlb_flushI) (void);
79 void (*cf_tlb_flushI_SE) (u_int va);
80 void (*cf_tlb_flushD) (void);
81 void (*cf_tlb_flushD_SE) (u_int va);
82
83 /*
84 * Cache operations:
85 *
86 * We define the following primitives:
87 *
88 * icache_sync_all Synchronize I-cache
89 * icache_sync_range Synchronize I-cache range
90 *
91 * dcache_wbinv_all Write-back and Invalidate D-cache
92 * dcache_wbinv_range Write-back and Invalidate D-cache range
93 * dcache_inv_range Invalidate D-cache range
94 * dcache_wb_range Write-back D-cache range
95 *
96 * idcache_wbinv_all Write-back and Invalidate D-cache,
97 * Invalidate I-cache
98 * idcache_wbinv_range Write-back and Invalidate D-cache,
99 * Invalidate I-cache range
100 *
101 * Note that the ARM term for "write-back" is "clean". We use
102 * the term "write-back" since it's a more common way to describe
103 * the operation.
104 *
105 * There are some rules that must be followed:
106 *
107 * I-cache Synch (all or range):
108 * The goal is to synchronize the instruction stream,
109 * so you may beed to write-back dirty D-cache blocks
110 * first. If a range is requested, and you can't
111 * synchronize just a range, you have to hit the whole
112 * thing.
113 *
114 * D-cache Write-Back and Invalidate range:
115 * If you can't WB-Inv a range, you must WB-Inv the
116 * entire D-cache.
117 *
118 * D-cache Invalidate:
119 * If you can't Inv the D-cache, you must Write-Back
120 * and Invalidate. Code that uses this operation
121 * MUST NOT assume that the D-cache will not be written
122 * back to memory.
123 *
124 * D-cache Write-Back:
125 * If you can't Write-back without doing an Inv,
126 * that's fine. Then treat this as a WB-Inv.
127 * Skipping the invalidate is merely an optimization.
128 *
129 * All operations:
130 * Valid virtual addresses must be passed to each
131 * cache operation.
132 */
133 void (*cf_icache_sync_all) (void);
134 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t);
135
136 void (*cf_dcache_wbinv_all) (void);
137 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t);
138 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t);
139 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t);
140
141 void (*cf_idcache_wbinv_all) (void);
142 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
143 void (*cf_l2cache_wbinv_all) (void);
144 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
145 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t);
146 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t);
147
148 /* Other functions */
149
150 void (*cf_flush_prefetchbuf) (void);
151 void (*cf_drain_writebuf) (void);
152 void (*cf_flush_brnchtgt_C) (void);
153 void (*cf_flush_brnchtgt_E) (u_int va);
154
155 void (*cf_sleep) (int mode);
156
157 /* Soft functions */
158
159 int (*cf_dataabt_fixup) (void *arg);
160 int (*cf_prefetchabt_fixup) (void *arg);
161
162 void (*cf_context_switch) (void);
163
164 void (*cf_setup) (char *string);
165};
166
167extern struct cpu_functions cpufuncs;
168extern u_int cputype;
169
170#define cpu_id() cpufuncs.cf_id()
171#define cpu_cpwait() cpufuncs.cf_cpwait()
172
173#define cpu_control(c, e) cpufuncs.cf_control(c, e)
174#define cpu_domains(d) cpufuncs.cf_domains(d)
175#define cpu_setttb(t) cpufuncs.cf_setttb(t)
176#define cpu_faultstatus() cpufuncs.cf_faultstatus()
177#define cpu_faultaddress() cpufuncs.cf_faultaddress()
178
179#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
180#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e)
181#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI()
182#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e)
183#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()
184#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)
185
186#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all()
187#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
188
189#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all()
190#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
191#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
192#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
193
194#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
195#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
196#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all()
197#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
198#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
199#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
200
201#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf()
202#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
203#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C()
204#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e)
205
206#define cpu_sleep(m) cpufuncs.cf_sleep(m)
207
208#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a)
209#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a)
210#define ABORT_FIXUP_OK 0 /* fixup succeeded */
211#define ABORT_FIXUP_FAILED 1 /* fixup failed */
212#define ABORT_FIXUP_RETURN 2 /* abort handler should return */
213
214#define cpu_setup(a) cpufuncs.cf_setup(a)
215
216int set_cpufuncs (void);
217#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
218#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
219
220void cpufunc_nullop (void);
221int cpufunc_null_fixup (void *);
222int early_abort_fixup (void *);
223int late_abort_fixup (void *);
224u_int cpufunc_id (void);
225u_int cpufunc_control (u_int clear, u_int bic);
226void cpufunc_domains (u_int domains);
227u_int cpufunc_faultstatus (void);
228u_int cpufunc_faultaddress (void);
229
230#ifdef CPU_ARM3
231u_int arm3_control (u_int clear, u_int bic);
232void arm3_cache_flush (void);
233#endif /* CPU_ARM3 */
234
235#if defined(CPU_ARM6) || defined(CPU_ARM7)
236void arm67_setttb (u_int ttb);
237void arm67_tlb_flush (void);
238void arm67_tlb_purge (u_int va);
239void arm67_cache_flush (void);
240void arm67_context_switch (void);
241#endif /* CPU_ARM6 || CPU_ARM7 */
242
243#ifdef CPU_ARM6
244void arm6_setup (char *string);
245#endif /* CPU_ARM6 */
246
247#ifdef CPU_ARM7
248void arm7_setup (char *string);
249#endif /* CPU_ARM7 */
250
251#ifdef CPU_ARM7TDMI
252int arm7_dataabt_fixup (void *arg);
253void arm7tdmi_setup (char *string);
254void arm7tdmi_setttb (u_int ttb);
255void arm7tdmi_tlb_flushID (void);
256void arm7tdmi_tlb_flushID_SE (u_int va);
257void arm7tdmi_cache_flushID (void);
258void arm7tdmi_context_switch (void);
259#endif /* CPU_ARM7TDMI */
260
261#ifdef CPU_ARM8
262void arm8_setttb (u_int ttb);
263void arm8_tlb_flushID (void);
264void arm8_tlb_flushID_SE (u_int va);
265void arm8_cache_flushID (void);
266void arm8_cache_flushID_E (u_int entry);
267void arm8_cache_cleanID (void);
268void arm8_cache_cleanID_E (u_int entry);
269void arm8_cache_purgeID (void);
270void arm8_cache_purgeID_E (u_int entry);
271
272void arm8_cache_syncI (void);
273void arm8_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
274void arm8_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
275void arm8_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
276void arm8_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
277void arm8_cache_syncI_rng (vm_offset_t start, vm_size_t end);
278
279void arm8_context_switch (void);
280
281void arm8_setup (char *string);
282
283u_int arm8_clock_config (u_int, u_int);
284#endif
285
286
287#if defined(CPU_FA526) || defined(CPU_FA626TE)
288void fa526_setup (char *arg);
289void fa526_setttb (u_int ttb);
290void fa526_context_switch (void);
291void fa526_cpu_sleep (int);
292void fa526_tlb_flushI_SE (u_int);
293void fa526_tlb_flushID_SE (u_int);
294void fa526_flush_prefetchbuf (void);
295void fa526_flush_brnchtgt_E (u_int);
296
297void fa526_icache_sync_all (void);
298void fa526_icache_sync_range(vm_offset_t start, vm_size_t end);
299void fa526_dcache_wbinv_all (void);
300void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end);
301void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end);
302void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end);
303void fa526_idcache_wbinv_all(void);
304void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end);
305#endif
306
307
308#ifdef CPU_SA110
309void sa110_setup (char *string);
310void sa110_context_switch (void);
311#endif /* CPU_SA110 */
312
313#if defined(CPU_SA1100) || defined(CPU_SA1110)
314void sa11x0_drain_readbuf (void);
315
316void sa11x0_context_switch (void);
317void sa11x0_cpu_sleep (int mode);
|
318
| 318
|
319void sa11x0_setup (char *string);
320#endif
321
322#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
323void sa1_setttb (u_int ttb);
324
325void sa1_tlb_flushID_SE (u_int va);
326
327void sa1_cache_flushID (void);
328void sa1_cache_flushI (void);
329void sa1_cache_flushD (void);
330void sa1_cache_flushD_SE (u_int entry);
331
332void sa1_cache_cleanID (void);
333void sa1_cache_cleanD (void);
334void sa1_cache_cleanD_E (u_int entry);
335
336void sa1_cache_purgeID (void);
337void sa1_cache_purgeID_E (u_int entry);
338void sa1_cache_purgeD (void);
339void sa1_cache_purgeD_E (u_int entry);
340
341void sa1_cache_syncI (void);
342void sa1_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
343void sa1_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
344void sa1_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
345void sa1_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
346void sa1_cache_syncI_rng (vm_offset_t start, vm_size_t end);
347
348#endif
349
350#ifdef CPU_ARM9
351void arm9_setttb (u_int);
352
353void arm9_tlb_flushID_SE (u_int va);
354
355void arm9_icache_sync_all (void);
356void arm9_icache_sync_range (vm_offset_t, vm_size_t);
357
358void arm9_dcache_wbinv_all (void);
359void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t);
360void arm9_dcache_inv_range (vm_offset_t, vm_size_t);
361void arm9_dcache_wb_range (vm_offset_t, vm_size_t);
362
363void arm9_idcache_wbinv_all (void);
364void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t);
365
366void arm9_context_switch (void);
367
368void arm9_setup (char *string);
369
370extern unsigned arm9_dcache_sets_max;
371extern unsigned arm9_dcache_sets_inc;
372extern unsigned arm9_dcache_index_max;
373extern unsigned arm9_dcache_index_inc;
374#endif
375
376#if defined(CPU_ARM9E) || defined(CPU_ARM10)
377void arm10_setttb (u_int);
378
379void arm10_tlb_flushID_SE (u_int);
380void arm10_tlb_flushI_SE (u_int);
381
382void arm10_icache_sync_all (void);
383void arm10_icache_sync_range (vm_offset_t, vm_size_t);
384
385void arm10_dcache_wbinv_all (void);
386void arm10_dcache_wbinv_range (vm_offset_t, vm_size_t);
387void arm10_dcache_inv_range (vm_offset_t, vm_size_t);
388void arm10_dcache_wb_range (vm_offset_t, vm_size_t);
389
390void arm10_idcache_wbinv_all (void);
391void arm10_idcache_wbinv_range (vm_offset_t, vm_size_t);
392
393void arm10_context_switch (void);
394
395void arm10_setup (char *string);
396
397extern unsigned arm10_dcache_sets_max;
398extern unsigned arm10_dcache_sets_inc;
399extern unsigned arm10_dcache_index_max;
400extern unsigned arm10_dcache_index_inc;
401
402u_int sheeva_control_ext (u_int, u_int);
403void sheeva_cpu_sleep (int);
404void sheeva_setttb (u_int);
405void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t);
406void sheeva_dcache_inv_range (vm_offset_t, vm_size_t);
407void sheeva_dcache_wb_range (vm_offset_t, vm_size_t);
408void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t);
409
410void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t);
411void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t);
412void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t);
413void sheeva_l2cache_wbinv_all (void);
414#endif
415
416#ifdef CPU_ARM11
417void arm11_setttb (u_int);
418
419void arm11_tlb_flushID_SE (u_int);
420void arm11_tlb_flushI_SE (u_int);
421
422void arm11_context_switch (void);
423
424void arm11_setup (char *string);
425void arm11_tlb_flushID (void);
426void arm11_tlb_flushI (void);
427void arm11_tlb_flushD (void);
428void arm11_tlb_flushD_SE (u_int va);
429
430void arm11_drain_writebuf (void);
431#endif
432
433#if defined(CPU_ARM9E) || defined (CPU_ARM10)
434void armv5_ec_setttb(u_int);
435
436void armv5_ec_icache_sync_all(void);
437void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t);
438
439void armv5_ec_dcache_wbinv_all(void);
440void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t);
441void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t);
442void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t);
443
444void armv5_ec_idcache_wbinv_all(void);
445void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t);
446#endif
447
448#if defined (CPU_ARM10) || defined (CPU_ARM11)
449void armv5_setttb(u_int);
450
451void armv5_icache_sync_all(void);
452void armv5_icache_sync_range(vm_offset_t, vm_size_t);
453
454void armv5_dcache_wbinv_all(void);
455void armv5_dcache_wbinv_range(vm_offset_t, vm_size_t);
456void armv5_dcache_inv_range(vm_offset_t, vm_size_t);
457void armv5_dcache_wb_range(vm_offset_t, vm_size_t);
458
459void armv5_idcache_wbinv_all(void);
460void armv5_idcache_wbinv_range(vm_offset_t, vm_size_t);
461
462extern unsigned armv5_dcache_sets_max;
463extern unsigned armv5_dcache_sets_inc;
464extern unsigned armv5_dcache_index_max;
465extern unsigned armv5_dcache_index_inc;
466#endif
467
468#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \
469 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
470 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
471 defined(CPU_FA526) || defined(CPU_FA626TE) || \
472 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
473 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
| 319void sa11x0_setup (char *string);
320#endif
321
322#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
323void sa1_setttb (u_int ttb);
324
325void sa1_tlb_flushID_SE (u_int va);
326
327void sa1_cache_flushID (void);
328void sa1_cache_flushI (void);
329void sa1_cache_flushD (void);
330void sa1_cache_flushD_SE (u_int entry);
331
332void sa1_cache_cleanID (void);
333void sa1_cache_cleanD (void);
334void sa1_cache_cleanD_E (u_int entry);
335
336void sa1_cache_purgeID (void);
337void sa1_cache_purgeID_E (u_int entry);
338void sa1_cache_purgeD (void);
339void sa1_cache_purgeD_E (u_int entry);
340
341void sa1_cache_syncI (void);
342void sa1_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
343void sa1_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
344void sa1_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
345void sa1_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
346void sa1_cache_syncI_rng (vm_offset_t start, vm_size_t end);
347
348#endif
349
350#ifdef CPU_ARM9
351void arm9_setttb (u_int);
352
353void arm9_tlb_flushID_SE (u_int va);
354
355void arm9_icache_sync_all (void);
356void arm9_icache_sync_range (vm_offset_t, vm_size_t);
357
358void arm9_dcache_wbinv_all (void);
359void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t);
360void arm9_dcache_inv_range (vm_offset_t, vm_size_t);
361void arm9_dcache_wb_range (vm_offset_t, vm_size_t);
362
363void arm9_idcache_wbinv_all (void);
364void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t);
365
366void arm9_context_switch (void);
367
368void arm9_setup (char *string);
369
370extern unsigned arm9_dcache_sets_max;
371extern unsigned arm9_dcache_sets_inc;
372extern unsigned arm9_dcache_index_max;
373extern unsigned arm9_dcache_index_inc;
374#endif
375
376#if defined(CPU_ARM9E) || defined(CPU_ARM10)
377void arm10_setttb (u_int);
378
379void arm10_tlb_flushID_SE (u_int);
380void arm10_tlb_flushI_SE (u_int);
381
382void arm10_icache_sync_all (void);
383void arm10_icache_sync_range (vm_offset_t, vm_size_t);
384
385void arm10_dcache_wbinv_all (void);
386void arm10_dcache_wbinv_range (vm_offset_t, vm_size_t);
387void arm10_dcache_inv_range (vm_offset_t, vm_size_t);
388void arm10_dcache_wb_range (vm_offset_t, vm_size_t);
389
390void arm10_idcache_wbinv_all (void);
391void arm10_idcache_wbinv_range (vm_offset_t, vm_size_t);
392
393void arm10_context_switch (void);
394
395void arm10_setup (char *string);
396
397extern unsigned arm10_dcache_sets_max;
398extern unsigned arm10_dcache_sets_inc;
399extern unsigned arm10_dcache_index_max;
400extern unsigned arm10_dcache_index_inc;
401
402u_int sheeva_control_ext (u_int, u_int);
403void sheeva_cpu_sleep (int);
404void sheeva_setttb (u_int);
405void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t);
406void sheeva_dcache_inv_range (vm_offset_t, vm_size_t);
407void sheeva_dcache_wb_range (vm_offset_t, vm_size_t);
408void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t);
409
410void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t);
411void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t);
412void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t);
413void sheeva_l2cache_wbinv_all (void);
414#endif
415
416#ifdef CPU_ARM11
417void arm11_setttb (u_int);
418
419void arm11_tlb_flushID_SE (u_int);
420void arm11_tlb_flushI_SE (u_int);
421
422void arm11_context_switch (void);
423
424void arm11_setup (char *string);
425void arm11_tlb_flushID (void);
426void arm11_tlb_flushI (void);
427void arm11_tlb_flushD (void);
428void arm11_tlb_flushD_SE (u_int va);
429
430void arm11_drain_writebuf (void);
431#endif
432
433#if defined(CPU_ARM9E) || defined (CPU_ARM10)
434void armv5_ec_setttb(u_int);
435
436void armv5_ec_icache_sync_all(void);
437void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t);
438
439void armv5_ec_dcache_wbinv_all(void);
440void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t);
441void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t);
442void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t);
443
444void armv5_ec_idcache_wbinv_all(void);
445void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t);
446#endif
447
448#if defined (CPU_ARM10) || defined (CPU_ARM11)
449void armv5_setttb(u_int);
450
451void armv5_icache_sync_all(void);
452void armv5_icache_sync_range(vm_offset_t, vm_size_t);
453
454void armv5_dcache_wbinv_all(void);
455void armv5_dcache_wbinv_range(vm_offset_t, vm_size_t);
456void armv5_dcache_inv_range(vm_offset_t, vm_size_t);
457void armv5_dcache_wb_range(vm_offset_t, vm_size_t);
458
459void armv5_idcache_wbinv_all(void);
460void armv5_idcache_wbinv_range(vm_offset_t, vm_size_t);
461
462extern unsigned armv5_dcache_sets_max;
463extern unsigned armv5_dcache_sets_inc;
464extern unsigned armv5_dcache_index_max;
465extern unsigned armv5_dcache_index_inc;
466#endif
467
468#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \
469 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
470 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
471 defined(CPU_FA526) || defined(CPU_FA626TE) || \
472 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
473 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
|
474
| 474
|
475void armv4_tlb_flushID (void);
476void armv4_tlb_flushI (void);
477void armv4_tlb_flushD (void);
478void armv4_tlb_flushD_SE (u_int va);
479
480void armv4_drain_writebuf (void);
481#endif
482
483#if defined(CPU_IXP12X0)
484void ixp12x0_drain_readbuf (void);
485void ixp12x0_context_switch (void);
486void ixp12x0_setup (char *string);
487#endif
488
489#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
490 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
491 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
492void xscale_cpwait (void);
493
494void xscale_cpu_sleep (int mode);
495
496u_int xscale_control (u_int clear, u_int bic);
497
498void xscale_setttb (u_int ttb);
499
500void xscale_tlb_flushID_SE (u_int va);
501
502void xscale_cache_flushID (void);
503void xscale_cache_flushI (void);
504void xscale_cache_flushD (void);
505void xscale_cache_flushD_SE (u_int entry);
506
507void xscale_cache_cleanID (void);
508void xscale_cache_cleanD (void);
509void xscale_cache_cleanD_E (u_int entry);
510
511void xscale_cache_clean_minidata (void);
512
513void xscale_cache_purgeID (void);
514void xscale_cache_purgeID_E (u_int entry);
515void xscale_cache_purgeD (void);
516void xscale_cache_purgeD_E (u_int entry);
517
518void xscale_cache_syncI (void);
519void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
520void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
521void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
522void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
523void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end);
524void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end);
525
526void xscale_context_switch (void);
527
528void xscale_setup (char *string);
| 475void armv4_tlb_flushID (void);
476void armv4_tlb_flushI (void);
477void armv4_tlb_flushD (void);
478void armv4_tlb_flushD_SE (u_int va);
479
480void armv4_drain_writebuf (void);
481#endif
482
483#if defined(CPU_IXP12X0)
484void ixp12x0_drain_readbuf (void);
485void ixp12x0_context_switch (void);
486void ixp12x0_setup (char *string);
487#endif
488
489#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
490 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
491 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
492void xscale_cpwait (void);
493
494void xscale_cpu_sleep (int mode);
495
496u_int xscale_control (u_int clear, u_int bic);
497
498void xscale_setttb (u_int ttb);
499
500void xscale_tlb_flushID_SE (u_int va);
501
502void xscale_cache_flushID (void);
503void xscale_cache_flushI (void);
504void xscale_cache_flushD (void);
505void xscale_cache_flushD_SE (u_int entry);
506
507void xscale_cache_cleanID (void);
508void xscale_cache_cleanD (void);
509void xscale_cache_cleanD_E (u_int entry);
510
511void xscale_cache_clean_minidata (void);
512
513void xscale_cache_purgeID (void);
514void xscale_cache_purgeID_E (u_int entry);
515void xscale_cache_purgeD (void);
516void xscale_cache_purgeD_E (u_int entry);
517
518void xscale_cache_syncI (void);
519void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
520void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
521void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
522void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
523void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end);
524void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end);
525
526void xscale_context_switch (void);
527
528void xscale_setup (char *string);
|
529#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
| 529#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
|
530 CPU_XSCALE_80219 */
531
532#ifdef CPU_XSCALE_81342
533
534void xscalec3_l2cache_purge (void);
535void xscalec3_cache_purgeID (void);
536void xscalec3_cache_purgeD (void);
537void xscalec3_cache_cleanID (void);
538void xscalec3_cache_cleanD (void);
539void xscalec3_cache_syncI (void);
540
541void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
542void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
543void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
544void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
545void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end);
546
547void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t);
548void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end);
549void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end);
550
551
552void xscalec3_setttb (u_int ttb);
553void xscalec3_context_switch (void);
554
555#endif /* CPU_XSCALE_81342 */
556
557#define tlb_flush cpu_tlb_flushID
558#define setttb cpu_setttb
559#define drain_writebuf cpu_drain_writebuf
560
561/*
562 * Macros for manipulating CPU interrupts
563 */
564static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__));
565
566static __inline u_int32_t
567__set_cpsr_c(u_int bic, u_int eor)
568{
569 u_int32_t tmp, ret;
570
571 __asm __volatile(
572 "mrs %0, cpsr\n" /* Get the CPSR */
573 "bic %1, %0, %2\n" /* Clear bits */
574 "eor %1, %1, %3\n" /* XOR bits */
575 "msr cpsr_c, %1\n" /* Set the control field of CPSR */
576 : "=&r" (ret), "=&r" (tmp)
577 : "r" (bic), "r" (eor) : "memory");
578
579 return ret;
580}
581
582#define disable_interrupts(mask) \
583 (__set_cpsr_c((mask) & (I32_bit | F32_bit), \
584 (mask) & (I32_bit | F32_bit)))
585
586#define enable_interrupts(mask) \
587 (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0))
588
589#define restore_interrupts(old_cpsr) \
590 (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))
591
592#define intr_disable() \
593 disable_interrupts(I32_bit | F32_bit)
594#define intr_restore(s) \
595 restore_interrupts(s)
596/* Functions to manipulate the CPSR. */
597u_int SetCPSR(u_int bic, u_int eor);
598u_int GetCPSR(void);
599
600/*
601 * Functions to manipulate cpu r13
602 * (in arm/arm32/setstack.S)
603 */
604
605void set_stackptr (u_int mode, u_int address);
606u_int get_stackptr (u_int mode);
607
608/*
609 * Miscellany
610 */
611
612int get_pc_str_offset (void);
613
614/*
615 * CPU functions from locore.S
616 */
617
618void cpu_reset (void) __attribute__((__noreturn__));
619
620/*
621 * Cache info variables.
622 */
623
624/* PRIMARY CACHE VARIABLES */
625extern int arm_picache_size;
626extern int arm_picache_line_size;
627extern int arm_picache_ways;
628
629extern int arm_pdcache_size; /* and unified */
630extern int arm_pdcache_line_size;
| 530 CPU_XSCALE_80219 */
531
532#ifdef CPU_XSCALE_81342
533
534void xscalec3_l2cache_purge (void);
535void xscalec3_cache_purgeID (void);
536void xscalec3_cache_purgeD (void);
537void xscalec3_cache_cleanID (void);
538void xscalec3_cache_cleanD (void);
539void xscalec3_cache_syncI (void);
540
541void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
542void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
543void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
544void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
545void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end);
546
547void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t);
548void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end);
549void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end);
550
551
552void xscalec3_setttb (u_int ttb);
553void xscalec3_context_switch (void);
554
555#endif /* CPU_XSCALE_81342 */
556
557#define tlb_flush cpu_tlb_flushID
558#define setttb cpu_setttb
559#define drain_writebuf cpu_drain_writebuf
560
561/*
562 * Macros for manipulating CPU interrupts
563 */
564static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__));
565
566static __inline u_int32_t
567__set_cpsr_c(u_int bic, u_int eor)
568{
569 u_int32_t tmp, ret;
570
571 __asm __volatile(
572 "mrs %0, cpsr\n" /* Get the CPSR */
573 "bic %1, %0, %2\n" /* Clear bits */
574 "eor %1, %1, %3\n" /* XOR bits */
575 "msr cpsr_c, %1\n" /* Set the control field of CPSR */
576 : "=&r" (ret), "=&r" (tmp)
577 : "r" (bic), "r" (eor) : "memory");
578
579 return ret;
580}
581
582#define disable_interrupts(mask) \
583 (__set_cpsr_c((mask) & (I32_bit | F32_bit), \
584 (mask) & (I32_bit | F32_bit)))
585
586#define enable_interrupts(mask) \
587 (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0))
588
589#define restore_interrupts(old_cpsr) \
590 (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))
591
592#define intr_disable() \
593 disable_interrupts(I32_bit | F32_bit)
594#define intr_restore(s) \
595 restore_interrupts(s)
596/* Functions to manipulate the CPSR. */
597u_int SetCPSR(u_int bic, u_int eor);
598u_int GetCPSR(void);
599
600/*
601 * Functions to manipulate cpu r13
602 * (in arm/arm32/setstack.S)
603 */
604
605void set_stackptr (u_int mode, u_int address);
606u_int get_stackptr (u_int mode);
607
608/*
609 * Miscellany
610 */
611
612int get_pc_str_offset (void);
613
614/*
615 * CPU functions from locore.S
616 */
617
618void cpu_reset (void) __attribute__((__noreturn__));
619
620/*
621 * Cache info variables.
622 */
623
624/* PRIMARY CACHE VARIABLES */
625extern int arm_picache_size;
626extern int arm_picache_line_size;
627extern int arm_picache_ways;
628
629extern int arm_pdcache_size; /* and unified */
630extern int arm_pdcache_line_size;
|
631extern int arm_pdcache_ways;
| 631extern int arm_pdcache_ways;
|
632
633extern int arm_pcache_type;
634extern int arm_pcache_unified;
635
636extern int arm_dcache_align;
637extern int arm_dcache_align_mask;
638
639#endif /* _KERNEL */
640#endif /* _MACHINE_CPUFUNC_H_ */
641
642/* End of cpufunc.h */
| 632
633extern int arm_pcache_type;
634extern int arm_pcache_unified;
635
636extern int arm_dcache_align;
637extern int arm_dcache_align_mask;
638
639#endif /* _KERNEL */
640#endif /* _MACHINE_CPUFUNC_H_ */
641
642/* End of cpufunc.h */
|