1/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */
2
3/*-
4 * Copyright (c) 1997 Mark Brinicombe.
5 * Copyright (c) 1997 Causality Limited
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without

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33 * SUCH DAMAGE.
34 *
35 * RiscBSD kernel project
36 *
37 * cpufunc.h
38 *
39 * Prototypes for cpu, mmu and tlb related functions.
40 *
41 * $FreeBSD: head/sys/arm/include/cpufunc.h 243576 2012-11-27 00:41:39Z marcel $
42 */
43
44#ifndef _MACHINE_CPUFUNC_H_
45#define _MACHINE_CPUFUNC_H_
46
47#ifdef _KERNEL
48
49#include <sys/types.h>

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457void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t);
458
459void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t);
460void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t);
461void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t);
462void sheeva_l2cache_wbinv_all (void);
463#endif
464
465#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA)
466void arm11_setttb (u_int);
467void arm11_sleep (int);
468
469void arm11_tlb_flushID_SE (u_int);
470void arm11_tlb_flushI_SE (u_int);
471
472void arm11_context_switch (void);
473

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527
528int get_core_id (void);
529
530void armadaxp_idcache_wbinv_all (void);
531
532void cortexa_setup (char *);
533#endif
534
535#if defined(CPU_ARM9E) || defined (CPU_ARM10)
536void armv5_ec_setttb(u_int);
537
538void armv5_ec_icache_sync_all(void);
539void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t);
540
541void armv5_ec_dcache_wbinv_all(void);
542void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t);

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