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ARMAsmBackend.cpp (303975) ARMAsmBackend.cpp (304690)
1//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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85 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
86 {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
87 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
88 // - 19.
89 {"fixup_arm_movt_hi16", 0, 20, 0},
90 {"fixup_arm_movw_lo16", 0, 20, 0},
91 {"fixup_t2_movt_hi16", 0, 20, 0},
92 {"fixup_t2_movw_lo16", 0, 20, 0},
1//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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85 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
86 {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
87 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
88 // - 19.
89 {"fixup_arm_movt_hi16", 0, 20, 0},
90 {"fixup_arm_movw_lo16", 0, 20, 0},
91 {"fixup_t2_movt_hi16", 0, 20, 0},
92 {"fixup_t2_movw_lo16", 0, 20, 0},
93 {"fixup_arm_mod_imm", 0, 12, 0},
93 };
94 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
95 // This table *must* be in the order that the fixup_* kinds are defined in
96 // ARMFixupKinds.h.
97 //
98 // Name Offset (bits) Size (bits) Flags
99 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
100 {"fixup_t2_ldst_pcrel_12", 0, 32,

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128 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
129 {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
130 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
131 // - 19.
132 {"fixup_arm_movt_hi16", 12, 20, 0},
133 {"fixup_arm_movw_lo16", 12, 20, 0},
134 {"fixup_t2_movt_hi16", 12, 20, 0},
135 {"fixup_t2_movw_lo16", 12, 20, 0},
94 };
95 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
96 // This table *must* be in the order that the fixup_* kinds are defined in
97 // ARMFixupKinds.h.
98 //
99 // Name Offset (bits) Size (bits) Flags
100 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
101 {"fixup_t2_ldst_pcrel_12", 0, 32,

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129 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
130 {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
131 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
132 // - 19.
133 {"fixup_arm_movt_hi16", 12, 20, 0},
134 {"fixup_arm_movw_lo16", 12, 20, 0},
135 {"fixup_t2_movt_hi16", 12, 20, 0},
136 {"fixup_t2_movw_lo16", 12, 20, 0},
137 {"fixup_arm_mod_imm", 20, 12, 0},
136 };
137
138 if (Kind < FirstTargetFixupKind)
139 return MCAsmBackend::getFixupKindInfo(Kind);
140
141 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
142 "Invalid kind!");
143 return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind];

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619
620 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
621 // swapped.
622 if (Kind == ARM::fixup_t2_pcrel_10)
623 return swapHalfWords(Value, IsLittleEndian);
624
625 return Value;
626 }
138 };
139
140 if (Kind < FirstTargetFixupKind)
141 return MCAsmBackend::getFixupKindInfo(Kind);
142
143 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
144 "Invalid kind!");
145 return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind];

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621
622 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
623 // swapped.
624 if (Kind == ARM::fixup_t2_pcrel_10)
625 return swapHalfWords(Value, IsLittleEndian);
626
627 return Value;
628 }
629 case ARM::fixup_arm_mod_imm:
630 Value = ARM_AM::getSOImmVal(Value);
631 if (Ctx && Value >> 12) {
632 Ctx->reportError(Fixup.getLoc(), "out of range immediate fixup value");
633 return 0;
634 }
635 return Value;
627 }
628}
629
630void ARMAsmBackend::processFixupValue(const MCAssembler &Asm,
631 const MCAsmLayout &Layout,
632 const MCFixup &Fixup,
633 const MCFragment *DF,
634 const MCValue &Target, uint64_t &Value,

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685 case ARM::fixup_arm_thumb_bcc:
686 case ARM::fixup_arm_thumb_cp:
687 case ARM::fixup_thumb_adr_pcrel_10:
688 return 1;
689
690 case FK_Data_2:
691 case ARM::fixup_arm_thumb_br:
692 case ARM::fixup_arm_thumb_cb:
636 }
637}
638
639void ARMAsmBackend::processFixupValue(const MCAssembler &Asm,
640 const MCAsmLayout &Layout,
641 const MCFixup &Fixup,
642 const MCFragment *DF,
643 const MCValue &Target, uint64_t &Value,

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694 case ARM::fixup_arm_thumb_bcc:
695 case ARM::fixup_arm_thumb_cp:
696 case ARM::fixup_thumb_adr_pcrel_10:
697 return 1;
698
699 case FK_Data_2:
700 case ARM::fixup_arm_thumb_br:
701 case ARM::fixup_arm_thumb_cb:
702 case ARM::fixup_arm_mod_imm:
693 return 2;
694
695 case ARM::fixup_arm_pcrel_10_unscaled:
696 case ARM::fixup_arm_ldst_pcrel_12:
697 case ARM::fixup_arm_pcrel_10:
698 case ARM::fixup_arm_adr_pcrel_12:
699 case ARM::fixup_arm_uncondbl:
700 case ARM::fixup_arm_condbl:

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761 case ARM::fixup_t2_pcrel_10:
762 case ARM::fixup_t2_adr_pcrel_12:
763 case ARM::fixup_arm_thumb_bl:
764 case ARM::fixup_arm_thumb_blx:
765 case ARM::fixup_arm_movt_hi16:
766 case ARM::fixup_arm_movw_lo16:
767 case ARM::fixup_t2_movt_hi16:
768 case ARM::fixup_t2_movw_lo16:
703 return 2;
704
705 case ARM::fixup_arm_pcrel_10_unscaled:
706 case ARM::fixup_arm_ldst_pcrel_12:
707 case ARM::fixup_arm_pcrel_10:
708 case ARM::fixup_arm_adr_pcrel_12:
709 case ARM::fixup_arm_uncondbl:
710 case ARM::fixup_arm_condbl:

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771 case ARM::fixup_t2_pcrel_10:
772 case ARM::fixup_t2_adr_pcrel_12:
773 case ARM::fixup_arm_thumb_bl:
774 case ARM::fixup_arm_thumb_blx:
775 case ARM::fixup_arm_movt_hi16:
776 case ARM::fixup_arm_movw_lo16:
777 case ARM::fixup_t2_movt_hi16:
778 case ARM::fixup_t2_movw_lo16:
779 case ARM::fixup_arm_mod_imm:
769 // Instruction size is 4 bytes.
770 return 4;
771 }
772}
773
774void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
775 unsigned DataSize, uint64_t Value,
776 bool IsPCRel) const {

--- 313 unchanged lines hidden --- 		780 // Instruction size is 4 bytes.
781 return 4;
782 }
783}
784
785void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
786 unsigned DataSize, uint64_t Value,
787 bool IsPCRel) const {

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