1//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMMCTargetDesc.h"
11#include "MCTargetDesc/ARMBaseInfo.h"
12#include "MCTargetDesc/ARMFixupKinds.h"
13#include "MCTargetDesc/ARMAddressingModes.h"
14#include "llvm/MC/MCAssembler.h"
15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCDirectives.h"
17#include "llvm/MC/MCELFObjectWriter.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCFixupKindInfo.h"
20#include "llvm/MC/MCMachObjectWriter.h"
21#include "llvm/MC/MCObjectWriter.h"
22#include "llvm/MC/MCSectionELF.h"
23#include "llvm/MC/MCSectionMachO.h"
24#include "llvm/MC/MCAsmBackend.h"
25#include "llvm/MC/MCSubtargetInfo.h"
26#include "llvm/MC/MCValue.h"
27#include "llvm/Object/MachOFormat.h"
28#include "llvm/Support/ELF.h"
29#include "llvm/Support/ErrorHandling.h"
30#include "llvm/Support/raw_ostream.h"
31using namespace llvm;
32
33namespace {
34class ARMELFObjectWriter : public MCELFObjectTargetWriter {
35public:
36 ARMELFObjectWriter(uint8_t OSABI)
37 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
38 /*HasRelocationAddend*/ false) {}
39};
40
41class ARMAsmBackend : public MCAsmBackend {
42 const MCSubtargetInfo* STI;
43 bool isThumbMode; // Currently emitting Thumb code.
44public:
45 ARMAsmBackend(const Target &T, const StringRef TT)
46 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
47 isThumbMode(TT.startswith("thumb")) {}
48
49 ~ARMAsmBackend() {
50 delete STI;
51 }
52
53 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
54
55 bool hasNOP() const {
56 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
57 }
58
59 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
60 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
61// This table *must* be in the order that the fixup_* kinds are defined in
62// ARMFixupKinds.h.
63//
64// Name Offset (bits) Size (bits) Flags
65{ "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
66{ "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
67 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
68{ "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
69{ "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
70{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
71 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
72{ "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
73 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
74{ "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
75{ "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
76 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
77{ "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
78{ "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
79{ "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
80{ "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
81{ "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
82{ "fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
83{ "fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
84{ "fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
85{ "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
86{ "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
87{ "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
88{ "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel |
89 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
90{ "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
91// movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
92{ "fixup_arm_movt_hi16", 0, 20, 0 },
93{ "fixup_arm_movw_lo16", 0, 20, 0 },
94{ "fixup_t2_movt_hi16", 0, 20, 0 },
95{ "fixup_t2_movw_lo16", 0, 20, 0 },
96{ "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
97{ "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
98{ "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
99{ "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
100 };
101
102 if (Kind < FirstTargetFixupKind)
103 return MCAsmBackend::getFixupKindInfo(Kind);
104
105 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
106 "Invalid kind!");
107 return Infos[Kind - FirstTargetFixupKind];
108 }
109
110 /// processFixupValue - Target hook to process the literal value of a fixup
111 /// if necessary.
112 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
113 const MCFixup &Fixup, const MCFragment *DF,
114 MCValue &Target, uint64_t &Value,
115 bool &IsResolved);
116
117 bool mayNeedRelaxation(const MCInst &Inst) const;
118
119 bool fixupNeedsRelaxation(const MCFixup &Fixup,
120 uint64_t Value,
121 const MCInstFragment *DF,
122 const MCAsmLayout &Layout) const;
123
124 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
125
126 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
127
128 void handleAssemblerFlag(MCAssemblerFlag Flag) {
129 switch (Flag) {
130 default: break;
131 case MCAF_Code16:
132 setIsThumb(true);
133 break;
134 case MCAF_Code32:
135 setIsThumb(false);
136 break;
137 }
138 }
139
140 unsigned getPointerSize() const { return 4; }
141 bool isThumb() const { return isThumbMode; }
142 void setIsThumb(bool it) { isThumbMode = it; }
143};
144} // end anonymous namespace
145
146static unsigned getRelaxedOpcode(unsigned Op) {
147 switch (Op) {
148 default: return Op;
149 case ARM::tBcc: return ARM::t2Bcc;
150 case ARM::tLDRpciASM: return ARM::t2LDRpci;
151 case ARM::tADR: return ARM::t2ADR;
152 case ARM::tB: return ARM::t2B;
153 }
154}
155
156bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
157 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
158 return true;
159 return false;
160}
161
162bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
163 uint64_t Value,
164 const MCInstFragment *DF,
165 const MCAsmLayout &Layout) const {
166 switch ((unsigned)Fixup.getKind()) {
167 case ARM::fixup_arm_thumb_br: {
168 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
169 // low bit being an implied zero. There's an implied +4 offset for the
170 // branch, so we adjust the other way here to determine what's
171 // encodable.
172 //
173 // Relax if the value is too big for a (signed) i8.
174 int64_t Offset = int64_t(Value) - 4;
175 return Offset > 2046 || Offset < -2048;
176 }
177 case ARM::fixup_arm_thumb_bcc: {
178 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
179 // low bit being an implied zero. There's an implied +4 offset for the
180 // branch, so we adjust the other way here to determine what's
181 // encodable.
182 //
183 // Relax if the value is too big for a (signed) i8.
184 int64_t Offset = int64_t(Value) - 4;
185 return Offset > 254 || Offset < -256;
186 }
187 case ARM::fixup_thumb_adr_pcrel_10:
188 case ARM::fixup_arm_thumb_cp: {
189 // If the immediate is negative, greater than 1020, or not a multiple
190 // of four, the wide version of the instruction must be used.
191 int64_t Offset = int64_t(Value) - 4;
192 return Offset > 1020 || Offset < 0 || Offset & 3;
193 }
194 }
195 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!");
196}
197
198void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
199 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
200
201 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
202 if (RelaxedOp == Inst.getOpcode()) {
203 SmallString<256> Tmp;
204 raw_svector_ostream OS(Tmp);
205 Inst.dump_pretty(OS);
206 OS << "\n";
207 report_fatal_error("unexpected instruction to relax: " + OS.str());
208 }
209
210 // The instructions we're relaxing have (so far) the same operands.
211 // We just need to update to the proper opcode.
212 Res = Inst;
213 Res.setOpcode(RelaxedOp);
214}
215
216bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
217 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
218 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
219 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0
220 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
221 if (isThumb()) {
222 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding
223 : Thumb1_16bitNopEncoding;
224 uint64_t NumNops = Count / 2;
225 for (uint64_t i = 0; i != NumNops; ++i)
226 OW->Write16(nopEncoding);
227 if (Count & 1)
228 OW->Write8(0);
229 return true;
230 }
231 // ARM mode
232 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding
233 : ARMv4_NopEncoding;
234 uint64_t NumNops = Count / 4;
235 for (uint64_t i = 0; i != NumNops; ++i)
236 OW->Write32(nopEncoding);
237 // FIXME: should this function return false when unable to write exactly
238 // 'Count' bytes with NOP encodings?
239 switch (Count % 4) {
240 default: break; // No leftover bytes to write
241 case 1: OW->Write8(0); break;
242 case 2: OW->Write16(0); break;
243 case 3: OW->Write16(0); OW->Write8(0xa0); break;
244 }
245
246 return true;
247}
248
249static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
250 MCContext *Ctx = NULL) {
251 unsigned Kind = Fixup.getKind();
252 switch (Kind) {
253 default:
254 llvm_unreachable("Unknown fixup kind!");
255 case FK_Data_1:
256 case FK_Data_2:
257 case FK_Data_4:
258 return Value;
259 case ARM::fixup_arm_movt_hi16:
260 Value >>= 16;
261 // Fallthrough
262 case ARM::fixup_arm_movw_lo16:
263 case ARM::fixup_arm_movt_hi16_pcrel:
264 case ARM::fixup_arm_movw_lo16_pcrel: {
265 unsigned Hi4 = (Value & 0xF000) >> 12;
266 unsigned Lo12 = Value & 0x0FFF;
267 // inst{19-16} = Hi4;
268 // inst{11-0} = Lo12;
269 Value = (Hi4 << 16) | (Lo12);
270 return Value;
271 }
272 case ARM::fixup_t2_movt_hi16:
273 Value >>= 16;
274 // Fallthrough
275 case ARM::fixup_t2_movw_lo16:
276 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
277 // the other hi16 fixup?
278 case ARM::fixup_t2_movw_lo16_pcrel: {
279 unsigned Hi4 = (Value & 0xF000) >> 12;
280 unsigned i = (Value & 0x800) >> 11;
281 unsigned Mid3 = (Value & 0x700) >> 8;
282 unsigned Lo8 = Value & 0x0FF;
283 // inst{19-16} = Hi4;
284 // inst{26} = i;
285 // inst{14-12} = Mid3;
286 // inst{7-0} = Lo8;
287 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
288 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
289 swapped |= (Value & 0x0000FFFF) << 16;
290 return swapped;
291 }
292 case ARM::fixup_arm_ldst_pcrel_12:
293 // ARM PC-relative values are offset by 8.
294 Value -= 4;
295 // FALLTHROUGH
296 case ARM::fixup_t2_ldst_pcrel_12: {
297 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
298 Value -= 4;
299 bool isAdd = true;
300 if ((int64_t)Value < 0) {
301 Value = -Value;
302 isAdd = false;
303 }
304 if (Ctx && Value >= 4096)
305 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
306 Value |= isAdd << 23;
307
308 // Same addressing mode as fixup_arm_pcrel_10,
309 // but with 16-bit halfwords swapped.
310 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
311 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
312 swapped |= (Value & 0x0000FFFF) << 16;
313 return swapped;
314 }
315
316 return Value;
317 }
318 case ARM::fixup_thumb_adr_pcrel_10:
319 return ((Value - 4) >> 2) & 0xff;
320 case ARM::fixup_arm_adr_pcrel_12: {
321 // ARM PC-relative values are offset by 8.
322 Value -= 8;
323 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
324 if ((int64_t)Value < 0) {
325 Value = -Value;
326 opc = 2; // 0b0010
327 }
328 if (Ctx && ARM_AM::getSOImmVal(Value) == -1)
329 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
330 // Encode the immediate and shift the opcode into place.
331 return ARM_AM::getSOImmVal(Value) | (opc << 21);
332 }
333
334 case ARM::fixup_t2_adr_pcrel_12: {
335 Value -= 4;
336 unsigned opc = 0;
337 if ((int64_t)Value < 0) {
338 Value = -Value;
339 opc = 5;
340 }
341
342 uint32_t out = (opc << 21);
343 out |= (Value & 0x800) << 15;
344 out |= (Value & 0x700) << 4;
345 out |= (Value & 0x0FF);
346
347 uint64_t swapped = (out & 0xFFFF0000) >> 16;
348 swapped |= (out & 0x0000FFFF) << 16;
349 return swapped;
350 }
351
352 case ARM::fixup_arm_condbranch:
353 case ARM::fixup_arm_uncondbranch:
354 case ARM::fixup_arm_uncondbl:
355 case ARM::fixup_arm_condbl:
356 case ARM::fixup_arm_blx:
357 // These values don't encode the low two bits since they're always zero.
358 // Offset by 8 just as above.
359 return 0xffffff & ((Value - 8) >> 2);
360 case ARM::fixup_t2_uncondbranch: {
361 Value = Value - 4;
362 Value >>= 1; // Low bit is not encoded.
363
364 uint32_t out = 0;
365 bool I = Value & 0x800000;
366 bool J1 = Value & 0x400000;
367 bool J2 = Value & 0x200000;
368 J1 ^= I;
369 J2 ^= I;
370
371 out |= I << 26; // S bit
372 out |= !J1 << 13; // J1 bit
373 out |= !J2 << 11; // J2 bit
374 out |= (Value & 0x1FF800) << 5; // imm6 field
375 out |= (Value & 0x0007FF); // imm11 field
376
377 uint64_t swapped = (out & 0xFFFF0000) >> 16;
378 swapped |= (out & 0x0000FFFF) << 16;
379 return swapped;
380 }
381 case ARM::fixup_t2_condbranch: {
382 Value = Value - 4;
383 Value >>= 1; // Low bit is not encoded.
384
385 uint64_t out = 0;
386 out |= (Value & 0x80000) << 7; // S bit
387 out |= (Value & 0x40000) >> 7; // J2 bit
388 out |= (Value & 0x20000) >> 4; // J1 bit
389 out |= (Value & 0x1F800) << 5; // imm6 field
390 out |= (Value & 0x007FF); // imm11 field
391
392 uint32_t swapped = (out & 0xFFFF0000) >> 16;
393 swapped |= (out & 0x0000FFFF) << 16;
394 return swapped;
395 }
396 case ARM::fixup_arm_thumb_bl: {
397 // The value doesn't encode the low bit (always zero) and is offset by
398 // four. The 32-bit immediate value is encoded as
399 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
400 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
401 // The value is encoded into disjoint bit positions in the destination
402 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
403 // J = either J1 or J2 bit
404 //
405 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
406 //
407 // Note that the halfwords are stored high first, low second; so we need
408 // to transpose the fixup value here to map properly.
409 uint32_t offset = (Value - 4) >> 1;
410 uint32_t signBit = (offset & 0x800000) >> 23;
411 uint32_t I1Bit = (offset & 0x400000) >> 22;
412 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
413 uint32_t I2Bit = (offset & 0x200000) >> 21;
414 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
415 uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
416 uint32_t imm11Bits = (offset & 0x000007FF);
417
418 uint32_t Binary = 0;
419 uint32_t firstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
420 uint32_t secondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
421 (uint16_t)imm11Bits);
422 Binary |= secondHalf << 16;
423 Binary |= firstHalf;
424 return Binary;
425
426 }
427 case ARM::fixup_arm_thumb_blx: {
428 // The value doesn't encode the low two bits (always zero) and is offset by
429 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
430 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
431 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
432 // The value is encoded into disjoint bit positions in the destination
433 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
434 // J = either J1 or J2 bit, 0 = zero.
435 //
436 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
437 //
438 // Note that the halfwords are stored high first, low second; so we need
439 // to transpose the fixup value here to map properly.
440 uint32_t offset = (Value - 2) >> 2;
441 uint32_t signBit = (offset & 0x400000) >> 22;
442 uint32_t I1Bit = (offset & 0x200000) >> 21;
443 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
444 uint32_t I2Bit = (offset & 0x100000) >> 20;
445 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
446 uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
447 uint32_t imm10LBits = (offset & 0x3FF);
448
449 uint32_t Binary = 0;
450 uint32_t firstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
451 uint32_t secondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
452 ((uint16_t)imm10LBits) << 1);
453 Binary |= secondHalf << 16;
454 Binary |= firstHalf;
455 return Binary;
456 }
457 case ARM::fixup_arm_thumb_cp:
458 // Offset by 4, and don't encode the low two bits. Two bytes of that
459 // 'off by 4' is implicitly handled by the half-word ordering of the
460 // Thumb encoding, so we only need to adjust by 2 here.
461 return ((Value - 2) >> 2) & 0xff;
462 case ARM::fixup_arm_thumb_cb: {
463 // Offset by 4 and don't encode the lower bit, which is always 0.
464 uint32_t Binary = (Value - 4) >> 1;
465 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
466 }
467 case ARM::fixup_arm_thumb_br:
468 // Offset by 4 and don't encode the lower bit, which is always 0.
469 return ((Value - 4) >> 1) & 0x7ff;
470 case ARM::fixup_arm_thumb_bcc:
471 // Offset by 4 and don't encode the lower bit, which is always 0.
472 return ((Value - 4) >> 1) & 0xff;
473 case ARM::fixup_arm_pcrel_10_unscaled: {
474 Value = Value - 8; // ARM fixups offset by an additional word and don't
475 // need to adjust for the half-word ordering.
476 bool isAdd = true;
477 if ((int64_t)Value < 0) {
478 Value = -Value;
479 isAdd = false;
480 }
481 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
482 if (Ctx && Value >= 256)
483 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
484 Value = (Value & 0xf) | ((Value & 0xf0) << 4);
485 return Value | (isAdd << 23);
486 }
487 case ARM::fixup_arm_pcrel_10:
488 Value = Value - 4; // ARM fixups offset by an additional word and don't
489 // need to adjust for the half-word ordering.
490 // Fall through.
491 case ARM::fixup_t2_pcrel_10: {
492 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
493 Value = Value - 4;
494 bool isAdd = true;
495 if ((int64_t)Value < 0) {
496 Value = -Value;
497 isAdd = false;
498 }
499 // These values don't encode the low two bits since they're always zero.
500 Value >>= 2;
501 if (Ctx && Value >= 256)
502 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
503 Value |= isAdd << 23;
504
505 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
506 // swapped.
507 if (Kind == ARM::fixup_t2_pcrel_10) {
508 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
509 swapped |= (Value & 0x0000FFFF) << 16;
510 return swapped;
511 }
512
513 return Value;
514 }
515 }
516}
517
518void ARMAsmBackend::processFixupValue(const MCAssembler &Asm,
519 const MCAsmLayout &Layout,
520 const MCFixup &Fixup,
521 const MCFragment *DF,
522 MCValue &Target, uint64_t &Value,
523 bool &IsResolved) {
524 const MCSymbolRefExpr *A = Target.getSymA();
525 // Some fixups to thumb function symbols need the low bit (thumb bit)
526 // twiddled.
527 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
528 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
529 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 &&
530 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 &&
531 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 &&
532 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
533 if (A) {
534 const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
535 if (Asm.isThumbFunc(&Sym))
536 Value |= 1;
537 }
538 }
539 // We must always generate a relocation for BL/BLX instructions if we have
540 // a symbol to reference, as the linker relies on knowing the destination
541 // symbol's thumb-ness to get interworking right.
542 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx ||
543 (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl ||
544 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx ||
545 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl ||
546 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl))
547 IsResolved = false;
548
549 // Try to get the encoded value for the fixup as-if we're mapping it into
550 // the instruction. This allows adjustFixupValue() to issue a diagnostic
551 // if the value aren't invalid.
552 (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
553}
554
555namespace {
556
557// FIXME: This should be in a separate file.
558// ELF is an ELF of course...
559class ELFARMAsmBackend : public ARMAsmBackend {
560public:
561 uint8_t OSABI;
562 ELFARMAsmBackend(const Target &T, const StringRef TT,
563 uint8_t _OSABI)
564 : ARMAsmBackend(T, TT), OSABI(_OSABI) { }
565
566 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
567 uint64_t Value) const;
568
569 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
570 return createARMELFObjectWriter(OS, OSABI);
571 }
572};
573
574// FIXME: Raise this to share code between Darwin and ELF.
575void ELFARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
576 unsigned DataSize, uint64_t Value) const {
577 unsigned NumBytes = 4; // FIXME: 2 for Thumb
578 Value = adjustFixupValue(Fixup, Value);
579 if (!Value) return; // Doesn't change encoding.
580
581 unsigned Offset = Fixup.getOffset();
582
583 // For each byte of the fragment that the fixup touches, mask in the bits from
584 // the fixup value. The Value has been "split up" into the appropriate
585 // bitfields above.
586 for (unsigned i = 0; i != NumBytes; ++i)
587 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
588}
589
590// FIXME: This should be in a separate file.
591class DarwinARMAsmBackend : public ARMAsmBackend {
592public:
593 const object::mach::CPUSubtypeARM Subtype;
594 DarwinARMAsmBackend(const Target &T, const StringRef TT,
595 object::mach::CPUSubtypeARM st)
596 : ARMAsmBackend(T, TT), Subtype(st) { }
597
598 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
599 return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
600 object::mach::CTM_ARM,
601 Subtype);
602 }
603
604 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
605 uint64_t Value) const;
606
607 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
608 return false;
609 }
610};
611
612/// getFixupKindNumBytes - The number of bytes the fixup may change.
613static unsigned getFixupKindNumBytes(unsigned Kind) {
614 switch (Kind) {
615 default:
616 llvm_unreachable("Unknown fixup kind!");
617
618 case FK_Data_1:
619 case ARM::fixup_arm_thumb_bcc:
620 case ARM::fixup_arm_thumb_cp:
621 case ARM::fixup_thumb_adr_pcrel_10:
622 return 1;
623
624 case FK_Data_2:
625 case ARM::fixup_arm_thumb_br:
626 case ARM::fixup_arm_thumb_cb:
627 return 2;
628
629 case ARM::fixup_arm_pcrel_10_unscaled:
630 case ARM::fixup_arm_ldst_pcrel_12:
631 case ARM::fixup_arm_pcrel_10:
632 case ARM::fixup_arm_adr_pcrel_12:
633 case ARM::fixup_arm_uncondbl:
634 case ARM::fixup_arm_condbl:
635 case ARM::fixup_arm_blx:
636 case ARM::fixup_arm_condbranch:
637 case ARM::fixup_arm_uncondbranch:
638 return 3;
639
640 case FK_Data_4:
641 case ARM::fixup_t2_ldst_pcrel_12:
642 case ARM::fixup_t2_condbranch:
643 case ARM::fixup_t2_uncondbranch:
644 case ARM::fixup_t2_pcrel_10:
645 case ARM::fixup_t2_adr_pcrel_12:
646 case ARM::fixup_arm_thumb_bl:
647 case ARM::fixup_arm_thumb_blx:
648 case ARM::fixup_arm_movt_hi16:
649 case ARM::fixup_arm_movw_lo16:
650 case ARM::fixup_arm_movt_hi16_pcrel:
651 case ARM::fixup_arm_movw_lo16_pcrel:
652 case ARM::fixup_t2_movt_hi16:
653 case ARM::fixup_t2_movw_lo16:
654 case ARM::fixup_t2_movt_hi16_pcrel:
655 case ARM::fixup_t2_movw_lo16_pcrel:
656 return 4;
657 }
658}
659
660void DarwinARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
661 unsigned DataSize, uint64_t Value) const {
662 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
663 Value = adjustFixupValue(Fixup, Value);
664 if (!Value) return; // Doesn't change encoding.
665
666 unsigned Offset = Fixup.getOffset();
667 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
668
669 // For each byte of the fragment that the fixup touches, mask in the
670 // bits from the fixup value.
671 for (unsigned i = 0; i != NumBytes; ++i)
672 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
673}
674
675} // end anonymous namespace
676
| 1//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMMCTargetDesc.h"
11#include "MCTargetDesc/ARMBaseInfo.h"
12#include "MCTargetDesc/ARMFixupKinds.h"
13#include "MCTargetDesc/ARMAddressingModes.h"
14#include "llvm/MC/MCAssembler.h"
15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCDirectives.h"
17#include "llvm/MC/MCELFObjectWriter.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCFixupKindInfo.h"
20#include "llvm/MC/MCMachObjectWriter.h"
21#include "llvm/MC/MCObjectWriter.h"
22#include "llvm/MC/MCSectionELF.h"
23#include "llvm/MC/MCSectionMachO.h"
24#include "llvm/MC/MCAsmBackend.h"
25#include "llvm/MC/MCSubtargetInfo.h"
26#include "llvm/MC/MCValue.h"
27#include "llvm/Object/MachOFormat.h"
28#include "llvm/Support/ELF.h"
29#include "llvm/Support/ErrorHandling.h"
30#include "llvm/Support/raw_ostream.h"
31using namespace llvm;
32
33namespace {
34class ARMELFObjectWriter : public MCELFObjectTargetWriter {
35public:
36 ARMELFObjectWriter(uint8_t OSABI)
37 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
38 /*HasRelocationAddend*/ false) {}
39};
40
41class ARMAsmBackend : public MCAsmBackend {
42 const MCSubtargetInfo* STI;
43 bool isThumbMode; // Currently emitting Thumb code.
44public:
45 ARMAsmBackend(const Target &T, const StringRef TT)
46 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
47 isThumbMode(TT.startswith("thumb")) {}
48
49 ~ARMAsmBackend() {
50 delete STI;
51 }
52
53 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
54
55 bool hasNOP() const {
56 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
57 }
58
59 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
60 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
61// This table *must* be in the order that the fixup_* kinds are defined in
62// ARMFixupKinds.h.
63//
64// Name Offset (bits) Size (bits) Flags
65{ "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
66{ "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
67 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
68{ "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
69{ "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
70{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
71 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
72{ "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
73 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
74{ "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
75{ "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
76 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
77{ "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
78{ "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
79{ "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
80{ "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
81{ "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
82{ "fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
83{ "fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
84{ "fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
85{ "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
86{ "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
87{ "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
88{ "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel |
89 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
90{ "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
91// movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
92{ "fixup_arm_movt_hi16", 0, 20, 0 },
93{ "fixup_arm_movw_lo16", 0, 20, 0 },
94{ "fixup_t2_movt_hi16", 0, 20, 0 },
95{ "fixup_t2_movw_lo16", 0, 20, 0 },
96{ "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
97{ "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
98{ "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
99{ "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
100 };
101
102 if (Kind < FirstTargetFixupKind)
103 return MCAsmBackend::getFixupKindInfo(Kind);
104
105 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
106 "Invalid kind!");
107 return Infos[Kind - FirstTargetFixupKind];
108 }
109
110 /// processFixupValue - Target hook to process the literal value of a fixup
111 /// if necessary.
112 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
113 const MCFixup &Fixup, const MCFragment *DF,
114 MCValue &Target, uint64_t &Value,
115 bool &IsResolved);
116
117 bool mayNeedRelaxation(const MCInst &Inst) const;
118
119 bool fixupNeedsRelaxation(const MCFixup &Fixup,
120 uint64_t Value,
121 const MCInstFragment *DF,
122 const MCAsmLayout &Layout) const;
123
124 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
125
126 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
127
128 void handleAssemblerFlag(MCAssemblerFlag Flag) {
129 switch (Flag) {
130 default: break;
131 case MCAF_Code16:
132 setIsThumb(true);
133 break;
134 case MCAF_Code32:
135 setIsThumb(false);
136 break;
137 }
138 }
139
140 unsigned getPointerSize() const { return 4; }
141 bool isThumb() const { return isThumbMode; }
142 void setIsThumb(bool it) { isThumbMode = it; }
143};
144} // end anonymous namespace
145
146static unsigned getRelaxedOpcode(unsigned Op) {
147 switch (Op) {
148 default: return Op;
149 case ARM::tBcc: return ARM::t2Bcc;
150 case ARM::tLDRpciASM: return ARM::t2LDRpci;
151 case ARM::tADR: return ARM::t2ADR;
152 case ARM::tB: return ARM::t2B;
153 }
154}
155
156bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
157 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
158 return true;
159 return false;
160}
161
162bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
163 uint64_t Value,
164 const MCInstFragment *DF,
165 const MCAsmLayout &Layout) const {
166 switch ((unsigned)Fixup.getKind()) {
167 case ARM::fixup_arm_thumb_br: {
168 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
169 // low bit being an implied zero. There's an implied +4 offset for the
170 // branch, so we adjust the other way here to determine what's
171 // encodable.
172 //
173 // Relax if the value is too big for a (signed) i8.
174 int64_t Offset = int64_t(Value) - 4;
175 return Offset > 2046 || Offset < -2048;
176 }
177 case ARM::fixup_arm_thumb_bcc: {
178 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
179 // low bit being an implied zero. There's an implied +4 offset for the
180 // branch, so we adjust the other way here to determine what's
181 // encodable.
182 //
183 // Relax if the value is too big for a (signed) i8.
184 int64_t Offset = int64_t(Value) - 4;
185 return Offset > 254 || Offset < -256;
186 }
187 case ARM::fixup_thumb_adr_pcrel_10:
188 case ARM::fixup_arm_thumb_cp: {
189 // If the immediate is negative, greater than 1020, or not a multiple
190 // of four, the wide version of the instruction must be used.
191 int64_t Offset = int64_t(Value) - 4;
192 return Offset > 1020 || Offset < 0 || Offset & 3;
193 }
194 }
195 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!");
196}
197
198void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
199 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
200
201 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
202 if (RelaxedOp == Inst.getOpcode()) {
203 SmallString<256> Tmp;
204 raw_svector_ostream OS(Tmp);
205 Inst.dump_pretty(OS);
206 OS << "\n";
207 report_fatal_error("unexpected instruction to relax: " + OS.str());
208 }
209
210 // The instructions we're relaxing have (so far) the same operands.
211 // We just need to update to the proper opcode.
212 Res = Inst;
213 Res.setOpcode(RelaxedOp);
214}
215
216bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
217 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
218 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
219 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0
220 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
221 if (isThumb()) {
222 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding
223 : Thumb1_16bitNopEncoding;
224 uint64_t NumNops = Count / 2;
225 for (uint64_t i = 0; i != NumNops; ++i)
226 OW->Write16(nopEncoding);
227 if (Count & 1)
228 OW->Write8(0);
229 return true;
230 }
231 // ARM mode
232 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding
233 : ARMv4_NopEncoding;
234 uint64_t NumNops = Count / 4;
235 for (uint64_t i = 0; i != NumNops; ++i)
236 OW->Write32(nopEncoding);
237 // FIXME: should this function return false when unable to write exactly
238 // 'Count' bytes with NOP encodings?
239 switch (Count % 4) {
240 default: break; // No leftover bytes to write
241 case 1: OW->Write8(0); break;
242 case 2: OW->Write16(0); break;
243 case 3: OW->Write16(0); OW->Write8(0xa0); break;
244 }
245
246 return true;
247}
248
249static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
250 MCContext *Ctx = NULL) {
251 unsigned Kind = Fixup.getKind();
252 switch (Kind) {
253 default:
254 llvm_unreachable("Unknown fixup kind!");
255 case FK_Data_1:
256 case FK_Data_2:
257 case FK_Data_4:
258 return Value;
259 case ARM::fixup_arm_movt_hi16:
260 Value >>= 16;
261 // Fallthrough
262 case ARM::fixup_arm_movw_lo16:
263 case ARM::fixup_arm_movt_hi16_pcrel:
264 case ARM::fixup_arm_movw_lo16_pcrel: {
265 unsigned Hi4 = (Value & 0xF000) >> 12;
266 unsigned Lo12 = Value & 0x0FFF;
267 // inst{19-16} = Hi4;
268 // inst{11-0} = Lo12;
269 Value = (Hi4 << 16) | (Lo12);
270 return Value;
271 }
272 case ARM::fixup_t2_movt_hi16:
273 Value >>= 16;
274 // Fallthrough
275 case ARM::fixup_t2_movw_lo16:
276 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
277 // the other hi16 fixup?
278 case ARM::fixup_t2_movw_lo16_pcrel: {
279 unsigned Hi4 = (Value & 0xF000) >> 12;
280 unsigned i = (Value & 0x800) >> 11;
281 unsigned Mid3 = (Value & 0x700) >> 8;
282 unsigned Lo8 = Value & 0x0FF;
283 // inst{19-16} = Hi4;
284 // inst{26} = i;
285 // inst{14-12} = Mid3;
286 // inst{7-0} = Lo8;
287 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
288 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
289 swapped |= (Value & 0x0000FFFF) << 16;
290 return swapped;
291 }
292 case ARM::fixup_arm_ldst_pcrel_12:
293 // ARM PC-relative values are offset by 8.
294 Value -= 4;
295 // FALLTHROUGH
296 case ARM::fixup_t2_ldst_pcrel_12: {
297 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
298 Value -= 4;
299 bool isAdd = true;
300 if ((int64_t)Value < 0) {
301 Value = -Value;
302 isAdd = false;
303 }
304 if (Ctx && Value >= 4096)
305 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
306 Value |= isAdd << 23;
307
308 // Same addressing mode as fixup_arm_pcrel_10,
309 // but with 16-bit halfwords swapped.
310 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
311 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
312 swapped |= (Value & 0x0000FFFF) << 16;
313 return swapped;
314 }
315
316 return Value;
317 }
318 case ARM::fixup_thumb_adr_pcrel_10:
319 return ((Value - 4) >> 2) & 0xff;
320 case ARM::fixup_arm_adr_pcrel_12: {
321 // ARM PC-relative values are offset by 8.
322 Value -= 8;
323 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
324 if ((int64_t)Value < 0) {
325 Value = -Value;
326 opc = 2; // 0b0010
327 }
328 if (Ctx && ARM_AM::getSOImmVal(Value) == -1)
329 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
330 // Encode the immediate and shift the opcode into place.
331 return ARM_AM::getSOImmVal(Value) | (opc << 21);
332 }
333
334 case ARM::fixup_t2_adr_pcrel_12: {
335 Value -= 4;
336 unsigned opc = 0;
337 if ((int64_t)Value < 0) {
338 Value = -Value;
339 opc = 5;
340 }
341
342 uint32_t out = (opc << 21);
343 out |= (Value & 0x800) << 15;
344 out |= (Value & 0x700) << 4;
345 out |= (Value & 0x0FF);
346
347 uint64_t swapped = (out & 0xFFFF0000) >> 16;
348 swapped |= (out & 0x0000FFFF) << 16;
349 return swapped;
350 }
351
352 case ARM::fixup_arm_condbranch:
353 case ARM::fixup_arm_uncondbranch:
354 case ARM::fixup_arm_uncondbl:
355 case ARM::fixup_arm_condbl:
356 case ARM::fixup_arm_blx:
357 // These values don't encode the low two bits since they're always zero.
358 // Offset by 8 just as above.
359 return 0xffffff & ((Value - 8) >> 2);
360 case ARM::fixup_t2_uncondbranch: {
361 Value = Value - 4;
362 Value >>= 1; // Low bit is not encoded.
363
364 uint32_t out = 0;
365 bool I = Value & 0x800000;
366 bool J1 = Value & 0x400000;
367 bool J2 = Value & 0x200000;
368 J1 ^= I;
369 J2 ^= I;
370
371 out |= I << 26; // S bit
372 out |= !J1 << 13; // J1 bit
373 out |= !J2 << 11; // J2 bit
374 out |= (Value & 0x1FF800) << 5; // imm6 field
375 out |= (Value & 0x0007FF); // imm11 field
376
377 uint64_t swapped = (out & 0xFFFF0000) >> 16;
378 swapped |= (out & 0x0000FFFF) << 16;
379 return swapped;
380 }
381 case ARM::fixup_t2_condbranch: {
382 Value = Value - 4;
383 Value >>= 1; // Low bit is not encoded.
384
385 uint64_t out = 0;
386 out |= (Value & 0x80000) << 7; // S bit
387 out |= (Value & 0x40000) >> 7; // J2 bit
388 out |= (Value & 0x20000) >> 4; // J1 bit
389 out |= (Value & 0x1F800) << 5; // imm6 field
390 out |= (Value & 0x007FF); // imm11 field
391
392 uint32_t swapped = (out & 0xFFFF0000) >> 16;
393 swapped |= (out & 0x0000FFFF) << 16;
394 return swapped;
395 }
396 case ARM::fixup_arm_thumb_bl: {
397 // The value doesn't encode the low bit (always zero) and is offset by
398 // four. The 32-bit immediate value is encoded as
399 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
400 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
401 // The value is encoded into disjoint bit positions in the destination
402 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
403 // J = either J1 or J2 bit
404 //
405 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
406 //
407 // Note that the halfwords are stored high first, low second; so we need
408 // to transpose the fixup value here to map properly.
409 uint32_t offset = (Value - 4) >> 1;
410 uint32_t signBit = (offset & 0x800000) >> 23;
411 uint32_t I1Bit = (offset & 0x400000) >> 22;
412 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
413 uint32_t I2Bit = (offset & 0x200000) >> 21;
414 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
415 uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
416 uint32_t imm11Bits = (offset & 0x000007FF);
417
418 uint32_t Binary = 0;
419 uint32_t firstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
420 uint32_t secondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
421 (uint16_t)imm11Bits);
422 Binary |= secondHalf << 16;
423 Binary |= firstHalf;
424 return Binary;
425
426 }
427 case ARM::fixup_arm_thumb_blx: {
428 // The value doesn't encode the low two bits (always zero) and is offset by
429 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
430 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
431 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
432 // The value is encoded into disjoint bit positions in the destination
433 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
434 // J = either J1 or J2 bit, 0 = zero.
435 //
436 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
437 //
438 // Note that the halfwords are stored high first, low second; so we need
439 // to transpose the fixup value here to map properly.
440 uint32_t offset = (Value - 2) >> 2;
441 uint32_t signBit = (offset & 0x400000) >> 22;
442 uint32_t I1Bit = (offset & 0x200000) >> 21;
443 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
444 uint32_t I2Bit = (offset & 0x100000) >> 20;
445 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
446 uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
447 uint32_t imm10LBits = (offset & 0x3FF);
448
449 uint32_t Binary = 0;
450 uint32_t firstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
451 uint32_t secondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
452 ((uint16_t)imm10LBits) << 1);
453 Binary |= secondHalf << 16;
454 Binary |= firstHalf;
455 return Binary;
456 }
457 case ARM::fixup_arm_thumb_cp:
458 // Offset by 4, and don't encode the low two bits. Two bytes of that
459 // 'off by 4' is implicitly handled by the half-word ordering of the
460 // Thumb encoding, so we only need to adjust by 2 here.
461 return ((Value - 2) >> 2) & 0xff;
462 case ARM::fixup_arm_thumb_cb: {
463 // Offset by 4 and don't encode the lower bit, which is always 0.
464 uint32_t Binary = (Value - 4) >> 1;
465 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
466 }
467 case ARM::fixup_arm_thumb_br:
468 // Offset by 4 and don't encode the lower bit, which is always 0.
469 return ((Value - 4) >> 1) & 0x7ff;
470 case ARM::fixup_arm_thumb_bcc:
471 // Offset by 4 and don't encode the lower bit, which is always 0.
472 return ((Value - 4) >> 1) & 0xff;
473 case ARM::fixup_arm_pcrel_10_unscaled: {
474 Value = Value - 8; // ARM fixups offset by an additional word and don't
475 // need to adjust for the half-word ordering.
476 bool isAdd = true;
477 if ((int64_t)Value < 0) {
478 Value = -Value;
479 isAdd = false;
480 }
481 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
482 if (Ctx && Value >= 256)
483 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
484 Value = (Value & 0xf) | ((Value & 0xf0) << 4);
485 return Value | (isAdd << 23);
486 }
487 case ARM::fixup_arm_pcrel_10:
488 Value = Value - 4; // ARM fixups offset by an additional word and don't
489 // need to adjust for the half-word ordering.
490 // Fall through.
491 case ARM::fixup_t2_pcrel_10: {
492 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
493 Value = Value - 4;
494 bool isAdd = true;
495 if ((int64_t)Value < 0) {
496 Value = -Value;
497 isAdd = false;
498 }
499 // These values don't encode the low two bits since they're always zero.
500 Value >>= 2;
501 if (Ctx && Value >= 256)
502 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
503 Value |= isAdd << 23;
504
505 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
506 // swapped.
507 if (Kind == ARM::fixup_t2_pcrel_10) {
508 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
509 swapped |= (Value & 0x0000FFFF) << 16;
510 return swapped;
511 }
512
513 return Value;
514 }
515 }
516}
517
518void ARMAsmBackend::processFixupValue(const MCAssembler &Asm,
519 const MCAsmLayout &Layout,
520 const MCFixup &Fixup,
521 const MCFragment *DF,
522 MCValue &Target, uint64_t &Value,
523 bool &IsResolved) {
524 const MCSymbolRefExpr *A = Target.getSymA();
525 // Some fixups to thumb function symbols need the low bit (thumb bit)
526 // twiddled.
527 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
528 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
529 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 &&
530 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 &&
531 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 &&
532 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
533 if (A) {
534 const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
535 if (Asm.isThumbFunc(&Sym))
536 Value |= 1;
537 }
538 }
539 // We must always generate a relocation for BL/BLX instructions if we have
540 // a symbol to reference, as the linker relies on knowing the destination
541 // symbol's thumb-ness to get interworking right.
542 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx ||
543 (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl ||
544 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx ||
545 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl ||
546 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl))
547 IsResolved = false;
548
549 // Try to get the encoded value for the fixup as-if we're mapping it into
550 // the instruction. This allows adjustFixupValue() to issue a diagnostic
551 // if the value aren't invalid.
552 (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
553}
554
555namespace {
556
557// FIXME: This should be in a separate file.
558// ELF is an ELF of course...
559class ELFARMAsmBackend : public ARMAsmBackend {
560public:
561 uint8_t OSABI;
562 ELFARMAsmBackend(const Target &T, const StringRef TT,
563 uint8_t _OSABI)
564 : ARMAsmBackend(T, TT), OSABI(_OSABI) { }
565
566 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
567 uint64_t Value) const;
568
569 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
570 return createARMELFObjectWriter(OS, OSABI);
571 }
572};
573
574// FIXME: Raise this to share code between Darwin and ELF.
575void ELFARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
576 unsigned DataSize, uint64_t Value) const {
577 unsigned NumBytes = 4; // FIXME: 2 for Thumb
578 Value = adjustFixupValue(Fixup, Value);
579 if (!Value) return; // Doesn't change encoding.
580
581 unsigned Offset = Fixup.getOffset();
582
583 // For each byte of the fragment that the fixup touches, mask in the bits from
584 // the fixup value. The Value has been "split up" into the appropriate
585 // bitfields above.
586 for (unsigned i = 0; i != NumBytes; ++i)
587 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
588}
589
590// FIXME: This should be in a separate file.
591class DarwinARMAsmBackend : public ARMAsmBackend {
592public:
593 const object::mach::CPUSubtypeARM Subtype;
594 DarwinARMAsmBackend(const Target &T, const StringRef TT,
595 object::mach::CPUSubtypeARM st)
596 : ARMAsmBackend(T, TT), Subtype(st) { }
597
598 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
599 return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
600 object::mach::CTM_ARM,
601 Subtype);
602 }
603
604 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
605 uint64_t Value) const;
606
607 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
608 return false;
609 }
610};
611
612/// getFixupKindNumBytes - The number of bytes the fixup may change.
613static unsigned getFixupKindNumBytes(unsigned Kind) {
614 switch (Kind) {
615 default:
616 llvm_unreachable("Unknown fixup kind!");
617
618 case FK_Data_1:
619 case ARM::fixup_arm_thumb_bcc:
620 case ARM::fixup_arm_thumb_cp:
621 case ARM::fixup_thumb_adr_pcrel_10:
622 return 1;
623
624 case FK_Data_2:
625 case ARM::fixup_arm_thumb_br:
626 case ARM::fixup_arm_thumb_cb:
627 return 2;
628
629 case ARM::fixup_arm_pcrel_10_unscaled:
630 case ARM::fixup_arm_ldst_pcrel_12:
631 case ARM::fixup_arm_pcrel_10:
632 case ARM::fixup_arm_adr_pcrel_12:
633 case ARM::fixup_arm_uncondbl:
634 case ARM::fixup_arm_condbl:
635 case ARM::fixup_arm_blx:
636 case ARM::fixup_arm_condbranch:
637 case ARM::fixup_arm_uncondbranch:
638 return 3;
639
640 case FK_Data_4:
641 case ARM::fixup_t2_ldst_pcrel_12:
642 case ARM::fixup_t2_condbranch:
643 case ARM::fixup_t2_uncondbranch:
644 case ARM::fixup_t2_pcrel_10:
645 case ARM::fixup_t2_adr_pcrel_12:
646 case ARM::fixup_arm_thumb_bl:
647 case ARM::fixup_arm_thumb_blx:
648 case ARM::fixup_arm_movt_hi16:
649 case ARM::fixup_arm_movw_lo16:
650 case ARM::fixup_arm_movt_hi16_pcrel:
651 case ARM::fixup_arm_movw_lo16_pcrel:
652 case ARM::fixup_t2_movt_hi16:
653 case ARM::fixup_t2_movw_lo16:
654 case ARM::fixup_t2_movt_hi16_pcrel:
655 case ARM::fixup_t2_movw_lo16_pcrel:
656 return 4;
657 }
658}
659
660void DarwinARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
661 unsigned DataSize, uint64_t Value) const {
662 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
663 Value = adjustFixupValue(Fixup, Value);
664 if (!Value) return; // Doesn't change encoding.
665
666 unsigned Offset = Fixup.getOffset();
667 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
668
669 // For each byte of the fragment that the fixup touches, mask in the
670 // bits from the fixup value.
671 for (unsigned i = 0; i != NumBytes; ++i)
672 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
673}
674
675} // end anonymous namespace
676
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