421 if (TARGET_SSE_MATH && TARGET_SSE) \
422 builtin_define ("__SSE_MATH__"); \
423 if (TARGET_SSE_MATH && TARGET_SSE2) \
424 builtin_define ("__SSE2_MATH__"); \
425 \
426 /* Built-ins based on -march=. */ \
427 if (ix86_arch == PROCESSOR_I486) \
428 { \
429 builtin_define ("__i486"); \
430 builtin_define ("__i486__"); \
431 } \
432 else if (ix86_arch == PROCESSOR_PENTIUM) \
433 { \
434 builtin_define ("__i586"); \
435 builtin_define ("__i586__"); \
436 builtin_define ("__pentium"); \
437 builtin_define ("__pentium__"); \
438 if (last_arch_char == 'x') \
439 builtin_define ("__pentium_mmx__"); \
440 } \
441 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
442 { \
443 builtin_define ("__i686"); \
444 builtin_define ("__i686__"); \
445 builtin_define ("__pentiumpro"); \
446 builtin_define ("__pentiumpro__"); \
447 } \
448 else if (ix86_arch == PROCESSOR_GEODE) \
449 { \
450 builtin_define ("__geode"); \
451 builtin_define ("__geode__"); \
452 } \
453 else if (ix86_arch == PROCESSOR_K6) \
454 { \
455 \
456 builtin_define ("__k6"); \
457 builtin_define ("__k6__"); \
458 if (last_arch_char == '2') \
459 builtin_define ("__k6_2__"); \
460 else if (last_arch_char == '3') \
461 builtin_define ("__k6_3__"); \
462 } \
463 else if (ix86_arch == PROCESSOR_ATHLON) \
464 { \
465 builtin_define ("__athlon"); \
466 builtin_define ("__athlon__"); \
467 /* Plain "athlon" & "athlon-tbird" lacks SSE. */ \
468 if (last_tune_char != 'n' && last_tune_char != 'd') \
469 builtin_define ("__athlon_sse__"); \
470 } \
471 else if (ix86_arch == PROCESSOR_K8) \
472 { \
473 builtin_define ("__k8"); \
474 builtin_define ("__k8__"); \
475 } \
476 else if (ix86_arch == PROCESSOR_PENTIUM4) \
477 { \
478 builtin_define ("__pentium4"); \
479 builtin_define ("__pentium4__"); \
480 } \
481 else if (ix86_arch == PROCESSOR_NOCONA) \
482 { \
483 builtin_define ("__nocona"); \
484 builtin_define ("__nocona__"); \
485 } \
486 else if (ix86_arch == PROCESSOR_CORE2) \
487 { \
488 builtin_define ("__core2"); \
489 builtin_define ("__core2__"); \
490 } \
491 } \
492 while (0)
493
494#define TARGET_CPU_DEFAULT_i386 0
495#define TARGET_CPU_DEFAULT_i486 1
496#define TARGET_CPU_DEFAULT_pentium 2
497#define TARGET_CPU_DEFAULT_pentium_mmx 3
498#define TARGET_CPU_DEFAULT_pentiumpro 4
499#define TARGET_CPU_DEFAULT_pentium2 5
500#define TARGET_CPU_DEFAULT_pentium3 6
501#define TARGET_CPU_DEFAULT_pentium4 7
502#define TARGET_CPU_DEFAULT_geode 8
503#define TARGET_CPU_DEFAULT_k6 9
504#define TARGET_CPU_DEFAULT_k6_2 10
505#define TARGET_CPU_DEFAULT_k6_3 11
506#define TARGET_CPU_DEFAULT_athlon 12
507#define TARGET_CPU_DEFAULT_athlon_sse 13
508#define TARGET_CPU_DEFAULT_k8 14
509#define TARGET_CPU_DEFAULT_pentium_m 15
510#define TARGET_CPU_DEFAULT_prescott 16
511#define TARGET_CPU_DEFAULT_nocona 17
512#define TARGET_CPU_DEFAULT_core2 18
513#define TARGET_CPU_DEFAULT_generic 19
514
515#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
516 "pentiumpro", "pentium2", "pentium3", \
517 "pentium4", "geode", "k6", "k6-2", "k6-3", \
518 "athlon", "athlon-4", "k8", \
519 "pentium-m", "prescott", "nocona", \
520 "core2", "generic"}
521
522#ifndef CC1_SPEC
523#define CC1_SPEC "%(cc1_cpu) "
524#endif
525
526/* This macro defines names of additional specifications to put in the
527 specs that can be used in various specifications like CC1_SPEC. Its
528 definition is an initializer with a subgrouping for each command option.
529
530 Each subgrouping contains a string constant, that defines the
531 specification name, and a string constant that used by the GCC driver
532 program.
533
534 Do not define this macro if it does not need to do anything. */
535
536#ifndef SUBTARGET_EXTRA_SPECS
537#define SUBTARGET_EXTRA_SPECS
538#endif
539
540#define EXTRA_SPECS \
541 { "cc1_cpu", CC1_CPU_SPEC }, \
542 SUBTARGET_EXTRA_SPECS
543
544/* target machine storage layout */
545
546#define LONG_DOUBLE_TYPE_SIZE 80
547
548/* Set the value of FLT_EVAL_METHOD in float.h. When using only the
549 FPU, assume that the fpcw is set to extended precision; when using
550 only SSE, rounding is correct; when using both SSE and the FPU,
551 the rounding precision is indeterminate, since either may be chosen
552 apparently at random. */
553#define TARGET_FLT_EVAL_METHOD \
554 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
555
556#define SHORT_TYPE_SIZE 16
557#define INT_TYPE_SIZE 32
558#define FLOAT_TYPE_SIZE 32
559#ifndef LONG_TYPE_SIZE
560#define LONG_TYPE_SIZE BITS_PER_WORD
561#endif
562#define DOUBLE_TYPE_SIZE 64
563#define LONG_LONG_TYPE_SIZE 64
564
565#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
566#define MAX_BITS_PER_WORD 64
567#else
568#define MAX_BITS_PER_WORD 32
569#endif
570
571/* Define this if most significant byte of a word is the lowest numbered. */
572/* That is true on the 80386. */
573
574#define BITS_BIG_ENDIAN 0
575
576/* Define this if most significant byte of a word is the lowest numbered. */
577/* That is not true on the 80386. */
578#define BYTES_BIG_ENDIAN 0
579
580/* Define this if most significant word of a multiword number is the lowest
581 numbered. */
582/* Not true for 80386 */
583#define WORDS_BIG_ENDIAN 0
584
585/* Width of a word, in units (bytes). */
586#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
587#ifdef IN_LIBGCC2
588#define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
589#else
590#define MIN_UNITS_PER_WORD 4
591#endif
592
593/* Allocation boundary (in *bits*) for storing arguments in argument list. */
594#define PARM_BOUNDARY BITS_PER_WORD
595
596/* Boundary (in *bits*) on which stack pointer should be aligned. */
597#define STACK_BOUNDARY BITS_PER_WORD
598
599/* Boundary (in *bits*) on which the stack pointer prefers to be
600 aligned; the compiler cannot rely on having this alignment. */
601#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
602
603/* As of July 2001, many runtimes do not align the stack properly when
604 entering main. This causes expand_main_function to forcibly align
605 the stack, which results in aligned frames for functions called from
606 main, though it does nothing for the alignment of main itself. */
607#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
608 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
609
610/* Minimum allocation boundary for the code of a function. */
611#define FUNCTION_BOUNDARY 8
612
613/* C++ stores the virtual bit in the lowest bit of function pointers. */
614#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
615
616/* Alignment of field after `int : 0' in a structure. */
617
618#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
619
620/* Minimum size in bits of the largest boundary to which any
621 and all fundamental data types supported by the hardware
622 might need to be aligned. No data type wants to be aligned
623 rounder than this.
624
625 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
626 and Pentium Pro XFmode values at 128 bit boundaries. */
627
628#define BIGGEST_ALIGNMENT 128
629
630/* Decide whether a variable of mode MODE should be 128 bit aligned. */
631#define ALIGN_MODE_128(MODE) \
632 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
633
634/* The published ABIs say that doubles should be aligned on word
635 boundaries, so lower the alignment for structure fields unless
636 -malign-double is set. */
637
638/* ??? Blah -- this macro is used directly by libobjc. Since it
639 supports no vector modes, cut out the complexity and fall back
640 on BIGGEST_FIELD_ALIGNMENT. */
641#ifdef IN_TARGET_LIBS
642#ifdef __x86_64__
643#define BIGGEST_FIELD_ALIGNMENT 128
644#else
645#define BIGGEST_FIELD_ALIGNMENT 32
646#endif
647#else
648#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
649 x86_field_alignment (FIELD, COMPUTED)
650#endif
651
652/* If defined, a C expression to compute the alignment given to a
653 constant that is being placed in memory. EXP is the constant
654 and ALIGN is the alignment that the object would ordinarily have.
655 The value of this macro is used instead of that alignment to align
656 the object.
657
658 If this macro is not defined, then ALIGN is used.
659
660 The typical use of this macro is to increase alignment for string
661 constants to be word aligned so that `strcpy' calls that copy
662 constants can be done inline. */
663
664#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
665
666/* If defined, a C expression to compute the alignment for a static
667 variable. TYPE is the data type, and ALIGN is the alignment that
668 the object would ordinarily have. The value of this macro is used
669 instead of that alignment to align the object.
670
671 If this macro is not defined, then ALIGN is used.
672
673 One use of this macro is to increase alignment of medium-size
674 data to make it all fit in fewer cache lines. Another is to
675 cause character arrays to be word-aligned so that `strcpy' calls
676 that copy constants to character arrays can be done inline. */
677
678#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
679
680/* If defined, a C expression to compute the alignment for a local
681 variable. TYPE is the data type, and ALIGN is the alignment that
682 the object would ordinarily have. The value of this macro is used
683 instead of that alignment to align the object.
684
685 If this macro is not defined, then ALIGN is used.
686
687 One use of this macro is to increase alignment of medium-size
688 data to make it all fit in fewer cache lines. */
689
690#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
691
692/* If defined, a C expression that gives the alignment boundary, in
693 bits, of an argument with the specified mode and type. If it is
694 not defined, `PARM_BOUNDARY' is used for all arguments. */
695
696#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
697 ix86_function_arg_boundary ((MODE), (TYPE))
698
699/* Set this nonzero if move instructions will actually fail to work
700 when given unaligned data. */
701#define STRICT_ALIGNMENT 0
702
703/* If bit field type is int, don't let it cross an int,
704 and give entire struct the alignment of an int. */
705/* Required on the 386 since it doesn't have bit-field insns. */
706#define PCC_BITFIELD_TYPE_MATTERS 1
707
708/* Standard register usage. */
709
710/* This processor has special stack-like registers. See reg-stack.c
711 for details. */
712
713#define STACK_REGS
714#define IS_STACK_MODE(MODE) \
715 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
716 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
717 || (MODE) == XFmode)
718
719/* Number of actual hardware registers.
720 The hardware registers are assigned numbers for the compiler
721 from 0 to just below FIRST_PSEUDO_REGISTER.
722 All registers that the compiler knows about must be given numbers,
723 even those that are not normally considered general registers.
724
725 In the 80386 we give the 8 general purpose registers the numbers 0-7.
726 We number the floating point registers 8-15.
727 Note that registers 0-7 can be accessed as a short or int,
728 while only 0-3 may be used with byte `mov' instructions.
729
730 Reg 16 does not correspond to any hardware register, but instead
731 appears in the RTL as an argument pointer prior to reload, and is
732 eliminated during reloading in favor of either the stack or frame
733 pointer. */
734
735#define FIRST_PSEUDO_REGISTER 53
736
737/* Number of hardware registers that go into the DWARF-2 unwind info.
738 If not defined, equals FIRST_PSEUDO_REGISTER. */
739
740#define DWARF_FRAME_REGISTERS 17
741
742/* 1 for registers that have pervasive standard uses
743 and are not available for the register allocator.
744 On the 80386, the stack pointer is such, as is the arg pointer.
745
746 The value is zero if the register is not fixed on either 32 or
747 64 bit targets, one if the register if fixed on both 32 and 64
748 bit targets, two if it is only fixed on 32bit targets and three
749 if its only fixed on 64bit targets.
750 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
751 */
752#define FIXED_REGISTERS \
753/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
754{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
755/*arg,flags,fpsr,dir,frame*/ \
756 1, 1, 1, 1, 1, \
757/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
758 0, 0, 0, 0, 0, 0, 0, 0, \
759/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
760 0, 0, 0, 0, 0, 0, 0, 0, \
761/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
762 2, 2, 2, 2, 2, 2, 2, 2, \
763/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
764 2, 2, 2, 2, 2, 2, 2, 2}
765
766
767/* 1 for registers not available across function calls.
768 These must include the FIXED_REGISTERS and also any
769 registers that can be used without being saved.
770 The latter must include the registers where values are returned
771 and the register where structure-value addresses are passed.
772 Aside from that, you can include as many other registers as you like.
773
774 The value is zero if the register is not call used on either 32 or
775 64 bit targets, one if the register if call used on both 32 and 64
776 bit targets, two if it is only call used on 32bit targets and three
777 if its only call used on 64bit targets.
778 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
779*/
780#define CALL_USED_REGISTERS \
781/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
782{ 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
783/*arg,flags,fpsr,dir,frame*/ \
784 1, 1, 1, 1, 1, \
785/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
786 1, 1, 1, 1, 1, 1, 1, 1, \
787/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
788 1, 1, 1, 1, 1, 1, 1, 1, \
789/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
790 1, 1, 1, 1, 2, 2, 2, 2, \
791/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
792 1, 1, 1, 1, 1, 1, 1, 1} \
793
794/* Order in which to allocate registers. Each register must be
795 listed once, even those in FIXED_REGISTERS. List frame pointer
796 late and fixed registers last. Note that, in general, we prefer
797 registers listed in CALL_USED_REGISTERS, keeping the others
798 available for storage of persistent values.
799
800 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
801 so this is just empty initializer for array. */
802
803#define REG_ALLOC_ORDER \
804{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
805 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
806 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
807 48, 49, 50, 51, 52 }
808
809/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
810 to be rearranged based on a particular function. When using sse math,
811 we want to allocate SSE before x87 registers and vice vera. */
812
813#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
814
815
816/* Macro to conditionally modify fixed_regs/call_used_regs. */
817#define CONDITIONAL_REGISTER_USAGE \
818do { \
819 int i; \
820 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
821 { \
822 if (fixed_regs[i] > 1) \
823 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
824 if (call_used_regs[i] > 1) \
825 call_used_regs[i] = (call_used_regs[i] \
826 == (TARGET_64BIT ? 3 : 2)); \
827 } \
828 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
829 { \
830 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
831 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
832 } \
833 if (! TARGET_MMX) \
834 { \
835 int i; \
836 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
837 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
838 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
839 } \
840 if (! TARGET_SSE) \
841 { \
842 int i; \
843 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
844 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
845 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
846 } \
847 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
848 { \
849 int i; \
850 HARD_REG_SET x; \
851 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
852 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
853 if (TEST_HARD_REG_BIT (x, i)) \
854 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
855 } \
856 if (! TARGET_64BIT) \
857 { \
858 int i; \
859 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
860 reg_names[i] = ""; \
861 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
862 reg_names[i] = ""; \
863 } \
864 } while (0)
865
866/* Return number of consecutive hard regs needed starting at reg REGNO
867 to hold something of mode MODE.
868 This is ordinarily the length in words of a value of mode MODE
869 but can be less for certain modes in special long registers.
870
871 Actually there are no two word move instructions for consecutive
872 registers. And only registers 0-3 may have mov byte instructions
873 applied to them.
874 */
875
876#define HARD_REGNO_NREGS(REGNO, MODE) \
877 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
878 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
879 : ((MODE) == XFmode \
880 ? (TARGET_64BIT ? 2 : 3) \
881 : (MODE) == XCmode \
882 ? (TARGET_64BIT ? 4 : 6) \
883 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
884
885#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
886 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
887 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
888 ? 0 \
889 : ((MODE) == XFmode || (MODE) == XCmode)) \
890 : 0)
891
892#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
893
894#define VALID_SSE2_REG_MODE(MODE) \
895 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
896 || (MODE) == V2DImode || (MODE) == DFmode)
897
898#define VALID_SSE_REG_MODE(MODE) \
899 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
900 || (MODE) == SFmode || (MODE) == TFmode)
901
902#define VALID_MMX_REG_MODE_3DNOW(MODE) \
903 ((MODE) == V2SFmode || (MODE) == SFmode)
904
905#define VALID_MMX_REG_MODE(MODE) \
906 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
907 || (MODE) == V2SImode || (MODE) == SImode)
908
909/* ??? No autovectorization into MMX or 3DNOW until we can reliably
910 place emms and femms instructions. */
911#define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD)
912
913#define VALID_FP_MODE_P(MODE) \
914 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
915 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
916
917#define VALID_INT_MODE_P(MODE) \
918 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
919 || (MODE) == DImode \
920 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
921 || (MODE) == CDImode \
922 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
923 || (MODE) == TFmode || (MODE) == TCmode)))
924
925/* Return true for modes passed in SSE registers. */
926#define SSE_REG_MODE_P(MODE) \
927 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
928 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
929 || (MODE) == V4SFmode || (MODE) == V4SImode)
930
931/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
932
933#define HARD_REGNO_MODE_OK(REGNO, MODE) \
934 ix86_hard_regno_mode_ok ((REGNO), (MODE))
935
936/* Value is 1 if it is a good idea to tie two pseudo registers
937 when one has mode MODE1 and one has mode MODE2.
938 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
939 for any hard reg, then this must be 0 for correct output. */
940
941#define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
942
943/* It is possible to write patterns to move flags; but until someone
944 does it, */
945#define AVOID_CCMODE_COPIES
946
947/* Specify the modes required to caller save a given hard regno.
948 We do this on i386 to prevent flags from being saved at all.
949
950 Kill any attempts to combine saving of modes. */
951
952#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
953 (CC_REGNO_P (REGNO) ? VOIDmode \
954 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
955 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
956 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
957 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
958 : (MODE))
959/* Specify the registers used for certain standard purposes.
960 The values of these macros are register numbers. */
961
962/* on the 386 the pc register is %eip, and is not usable as a general
963 register. The ordinary mov instructions won't work */
964/* #define PC_REGNUM */
965
966/* Register to use for pushing function arguments. */
967#define STACK_POINTER_REGNUM 7
968
969/* Base register for access to local variables of the function. */
970#define HARD_FRAME_POINTER_REGNUM 6
971
972/* Base register for access to local variables of the function. */
973#define FRAME_POINTER_REGNUM 20
974
975/* First floating point reg */
976#define FIRST_FLOAT_REG 8
977
978/* First & last stack-like regs */
979#define FIRST_STACK_REG FIRST_FLOAT_REG
980#define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
981
982#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
983#define LAST_SSE_REG (FIRST_SSE_REG + 7)
984
985#define FIRST_MMX_REG (LAST_SSE_REG + 1)
986#define LAST_MMX_REG (FIRST_MMX_REG + 7)
987
988#define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
989#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
990
991#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
992#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
993
994/* Value should be nonzero if functions must have frame pointers.
995 Zero means the frame pointer need not be set up (and parms
996 may be accessed via the stack pointer) in functions that seem suitable.
997 This is computed in `reload', in reload1.c. */
998#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
999
1000/* Override this in other tm.h files to cope with various OS lossage
1001 requiring a frame pointer. */
1002#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1003#define SUBTARGET_FRAME_POINTER_REQUIRED 0
1004#endif
1005
1006/* Make sure we can access arbitrary call frames. */
1007#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1008
1009/* Base register for access to arguments of the function. */
1010#define ARG_POINTER_REGNUM 16
1011
1012/* Register in which static-chain is passed to a function.
1013 We do use ECX as static chain register for 32 bit ABI. On the
1014 64bit ABI, ECX is an argument register, so we use R10 instead. */
1015#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1016
1017/* Register to hold the addressing base for position independent
1018 code access to data items. We don't use PIC pointer for 64bit
1019 mode. Define the regnum to dummy value to prevent gcc from
1020 pessimizing code dealing with EBX.
1021
1022 To avoid clobbering a call-saved register unnecessarily, we renumber
1023 the pic register when possible. The change is visible after the
1024 prologue has been emitted. */
1025
1026#define REAL_PIC_OFFSET_TABLE_REGNUM 3
1027
1028#define PIC_OFFSET_TABLE_REGNUM \
1029 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1030 || !flag_pic ? INVALID_REGNUM \
1031 : reload_completed ? REGNO (pic_offset_table_rtx) \
1032 : REAL_PIC_OFFSET_TABLE_REGNUM)
1033
1034#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1035
1036/* A C expression which can inhibit the returning of certain function
1037 values in registers, based on the type of value. A nonzero value
1038 says to return the function value in memory, just as large
1039 structures are always returned. Here TYPE will be a C expression
1040 of type `tree', representing the data type of the value.
1041
1042 Note that values of mode `BLKmode' must be explicitly handled by
1043 this macro. Also, the option `-fpcc-struct-return' takes effect
1044 regardless of this macro. On most systems, it is possible to
1045 leave the macro undefined; this causes a default definition to be
1046 used, whose value is the constant 1 for `BLKmode' values, and 0
1047 otherwise.
1048
1049 Do not use this macro to indicate that structures and unions
1050 should always be returned in memory. You should instead use
1051 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1052
1053#define RETURN_IN_MEMORY(TYPE) \
1054 ix86_return_in_memory (TYPE)
1055
1056/* This is overridden by <cygwin.h>. */
1057#define MS_AGGREGATE_RETURN 0
1058
1059/* This is overridden by <netware.h>. */
1060#define KEEP_AGGREGATE_RETURN_POINTER 0
1061
1062/* Define the classes of registers for register constraints in the
1063 machine description. Also define ranges of constants.
1064
1065 One of the classes must always be named ALL_REGS and include all hard regs.
1066 If there is more than one class, another class must be named NO_REGS
1067 and contain no registers.
1068
1069 The name GENERAL_REGS must be the name of a class (or an alias for
1070 another name such as ALL_REGS). This is the class of registers
1071 that is allowed by "g" or "r" in a register constraint.
1072 Also, registers outside this class are allocated only when
1073 instructions express preferences for them.
1074
1075 The classes must be numbered in nondecreasing order; that is,
1076 a larger-numbered class must never be contained completely
1077 in a smaller-numbered class.
1078
1079 For any two classes, it is very desirable that there be another
1080 class that represents their union.
1081
1082 It might seem that class BREG is unnecessary, since no useful 386
1083 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1084 and the "b" register constraint is useful in asms for syscalls.
1085
1086 The flags and fpsr registers are in no class. */
1087
1088enum reg_class
1089{
1090 NO_REGS,
1091 AREG, DREG, CREG, BREG, SIREG, DIREG,
1092 AD_REGS, /* %eax/%edx for DImode */
1093 Q_REGS, /* %eax %ebx %ecx %edx */
1094 NON_Q_REGS, /* %esi %edi %ebp %esp */
1095 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1096 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1097 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1098 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1099 FLOAT_REGS,
1100 SSE_REGS,
1101 MMX_REGS,
1102 FP_TOP_SSE_REGS,
1103 FP_SECOND_SSE_REGS,
1104 FLOAT_SSE_REGS,
1105 FLOAT_INT_REGS,
1106 INT_SSE_REGS,
1107 FLOAT_INT_SSE_REGS,
1108 ALL_REGS, LIM_REG_CLASSES
1109};
1110
1111#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1112
1113#define INTEGER_CLASS_P(CLASS) \
1114 reg_class_subset_p ((CLASS), GENERAL_REGS)
1115#define FLOAT_CLASS_P(CLASS) \
1116 reg_class_subset_p ((CLASS), FLOAT_REGS)
1117#define SSE_CLASS_P(CLASS) \
1118 ((CLASS) == SSE_REGS)
1119#define MMX_CLASS_P(CLASS) \
1120 ((CLASS) == MMX_REGS)
1121#define MAYBE_INTEGER_CLASS_P(CLASS) \
1122 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1123#define MAYBE_FLOAT_CLASS_P(CLASS) \
1124 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1125#define MAYBE_SSE_CLASS_P(CLASS) \
1126 reg_classes_intersect_p (SSE_REGS, (CLASS))
1127#define MAYBE_MMX_CLASS_P(CLASS) \
1128 reg_classes_intersect_p (MMX_REGS, (CLASS))
1129
1130#define Q_CLASS_P(CLASS) \
1131 reg_class_subset_p ((CLASS), Q_REGS)
1132
1133/* Give names of register classes as strings for dump file. */
1134
1135#define REG_CLASS_NAMES \
1136{ "NO_REGS", \
1137 "AREG", "DREG", "CREG", "BREG", \
1138 "SIREG", "DIREG", \
1139 "AD_REGS", \
1140 "Q_REGS", "NON_Q_REGS", \
1141 "INDEX_REGS", \
1142 "LEGACY_REGS", \
1143 "GENERAL_REGS", \
1144 "FP_TOP_REG", "FP_SECOND_REG", \
1145 "FLOAT_REGS", \
1146 "SSE_REGS", \
1147 "MMX_REGS", \
1148 "FP_TOP_SSE_REGS", \
1149 "FP_SECOND_SSE_REGS", \
1150 "FLOAT_SSE_REGS", \
1151 "FLOAT_INT_REGS", \
1152 "INT_SSE_REGS", \
1153 "FLOAT_INT_SSE_REGS", \
1154 "ALL_REGS" }
1155
1156/* Define which registers fit in which classes.
1157 This is an initializer for a vector of HARD_REG_SET
1158 of length N_REG_CLASSES. */
1159
1160#define REG_CLASS_CONTENTS \
1161{ { 0x00, 0x0 }, \
1162 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1163 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1164 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1165 { 0x03, 0x0 }, /* AD_REGS */ \
1166 { 0x0f, 0x0 }, /* Q_REGS */ \
1167 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1168 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1169 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1170 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1171 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1172 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1173{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1174{ 0xe0000000, 0x1f }, /* MMX_REGS */ \
1175{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1176{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1177{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1178 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1179{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1180{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1181{ 0xffffffff,0x1fffff } \
1182}
1183
1184/* The same information, inverted:
1185 Return the class number of the smallest class containing
1186 reg number REGNO. This could be a conditional expression
1187 or could index an array. */
1188
1189#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1190
1191/* When defined, the compiler allows registers explicitly used in the
1192 rtl to be used as spill registers but prevents the compiler from
1193 extending the lifetime of these registers. */
1194
1195#define SMALL_REGISTER_CLASSES 1
1196
1197#define QI_REG_P(X) \
1198 (REG_P (X) && REGNO (X) < 4)
1199
1200#define GENERAL_REGNO_P(N) \
1201 ((N) < 8 || REX_INT_REGNO_P (N))
1202
1203#define GENERAL_REG_P(X) \
1204 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1205
1206#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1207
1208#define NON_QI_REG_P(X) \
1209 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1210
1211#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1212#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1213
1214#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1215#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1216#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1217#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1218
1219#define SSE_REGNO_P(N) \
1220 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1221 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1222
1223#define REX_SSE_REGNO_P(N) \
1224 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)
1225
1226#define SSE_REGNO(N) \
1227 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1228#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1229
1230#define SSE_FLOAT_MODE_P(MODE) \
1231 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1232
1233#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1234#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1235
1236#define STACK_REG_P(XOP) \
1237 (REG_P (XOP) && \
1238 REGNO (XOP) >= FIRST_STACK_REG && \
1239 REGNO (XOP) <= LAST_STACK_REG)
1240
1241#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1242
1243#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1244
1245#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1246#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1247
1248/* The class value for index registers, and the one for base regs. */
1249
1250#define INDEX_REG_CLASS INDEX_REGS
1251#define BASE_REG_CLASS GENERAL_REGS
1252
1253/* Place additional restrictions on the register class to use when it
1254 is necessary to be able to hold a value of mode MODE in a reload
1255 register for which class CLASS would ordinarily be used. */
1256
1257#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1258 ((MODE) == QImode && !TARGET_64BIT \
1259 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1260 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1261 ? Q_REGS : (CLASS))
1262
1263/* Given an rtx X being reloaded into a reg required to be
1264 in class CLASS, return the class of reg to actually use.
1265 In general this is just CLASS; but on some machines
1266 in some cases it is preferable to use a more restrictive class.
1267 On the 80386 series, we prevent floating constants from being
1268 reloaded into floating registers (since no move-insn can do that)
1269 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1270
1271/* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1272 QImode must go into class Q_REGS.
1273 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1274 movdf to do mem-to-mem moves through integer regs. */
1275
1276#define PREFERRED_RELOAD_CLASS(X, CLASS) \
1277 ix86_preferred_reload_class ((X), (CLASS))
1278
1279/* Discourage putting floating-point values in SSE registers unless
1280 SSE math is being used, and likewise for the 387 registers. */
1281
1282#define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1283 ix86_preferred_output_reload_class ((X), (CLASS))
1284
1285/* If we are copying between general and FP registers, we need a memory
1286 location. The same is true for SSE and MMX registers. */
1287#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1288 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1289
1290/* QImode spills from non-QI registers need a scratch. This does not
1291 happen often -- the only example so far requires an uninitialized
1292 pseudo. */
1293
1294#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1295 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1296 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1297 ? Q_REGS : NO_REGS)
1298
1299/* Return the maximum number of consecutive registers
1300 needed to represent mode MODE in a register of class CLASS. */
1301/* On the 80386, this is the size of MODE in words,
1302 except in the FP regs, where a single reg is always enough. */
1303#define CLASS_MAX_NREGS(CLASS, MODE) \
1304 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1305 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1306 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1307 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1308
1309/* A C expression whose value is nonzero if pseudos that have been
1310 assigned to registers of class CLASS would likely be spilled
1311 because registers of CLASS are needed for spill registers.
1312
1313 The default value of this macro returns 1 if CLASS has exactly one
1314 register and zero otherwise. On most machines, this default
1315 should be used. Only define this macro to some other expression
1316 if pseudo allocated by `local-alloc.c' end up in memory because
1317 their hard registers were needed for spill registers. If this
1318 macro returns nonzero for those classes, those pseudos will only
1319 be allocated by `global.c', which knows how to reallocate the
1320 pseudo to another register. If there would not be another
1321 register available for reallocation, you should not change the
1322 definition of this macro since the only effect of such a
1323 definition would be to slow down register allocation. */
1324
1325#define CLASS_LIKELY_SPILLED_P(CLASS) \
1326 (((CLASS) == AREG) \
1327 || ((CLASS) == DREG) \
1328 || ((CLASS) == CREG) \
1329 || ((CLASS) == BREG) \
1330 || ((CLASS) == AD_REGS) \
1331 || ((CLASS) == SIREG) \
1332 || ((CLASS) == DIREG) \
1333 || ((CLASS) == FP_TOP_REG) \
1334 || ((CLASS) == FP_SECOND_REG))
1335
1336/* Return a class of registers that cannot change FROM mode to TO mode. */
1337
1338#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1339 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1340
1341/* Stack layout; function entry, exit and calling. */
1342
1343/* Define this if pushing a word on the stack
1344 makes the stack pointer a smaller address. */
1345#define STACK_GROWS_DOWNWARD
1346
1347/* Define this to nonzero if the nominal address of the stack frame
1348 is at the high-address end of the local variables;
1349 that is, each additional local variable allocated
1350 goes at a more negative offset in the frame. */
1351#define FRAME_GROWS_DOWNWARD 1
1352
1353/* Offset within stack frame to start allocating local variables at.
1354 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1355 first local allocated. Otherwise, it is the offset to the BEGINNING
1356 of the first local allocated. */
1357#define STARTING_FRAME_OFFSET 0
1358
1359/* If we generate an insn to push BYTES bytes,
1360 this says how many the stack pointer really advances by.
1361 On 386, we have pushw instruction that decrements by exactly 2 no
1362 matter what the position was, there is no pushb.
1363 But as CIE data alignment factor on this arch is -4, we need to make
1364 sure all stack pointer adjustments are in multiple of 4.
1365
1366 For 64bit ABI we round up to 8 bytes.
1367 */
1368
1369#define PUSH_ROUNDING(BYTES) \
1370 (TARGET_64BIT \
1371 ? (((BYTES) + 7) & (-8)) \
1372 : (((BYTES) + 3) & (-4)))
1373
1374/* If defined, the maximum amount of space required for outgoing arguments will
1375 be computed and placed into the variable
1376 `current_function_outgoing_args_size'. No space will be pushed onto the
1377 stack for each call; instead, the function prologue should increase the stack
1378 frame size by this amount. */
1379
1380#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1381
1382/* If defined, a C expression whose value is nonzero when we want to use PUSH
1383 instructions to pass outgoing arguments. */
1384
1385#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1386
1387/* We want the stack and args grow in opposite directions, even if
1388 PUSH_ARGS is 0. */
1389#define PUSH_ARGS_REVERSED 1
1390
1391/* Offset of first parameter from the argument pointer register value. */
1392#define FIRST_PARM_OFFSET(FNDECL) 0
1393
1394/* Define this macro if functions should assume that stack space has been
1395 allocated for arguments even when their values are passed in registers.
1396
1397 The value of this macro is the size, in bytes, of the area reserved for
1398 arguments passed in registers for the function represented by FNDECL.
1399
1400 This space can be allocated by the caller, or be a part of the
1401 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1402 which. */
1403#define REG_PARM_STACK_SPACE(FNDECL) 0
1404
1405/* Value is the number of bytes of arguments automatically
1406 popped when returning from a subroutine call.
1407 FUNDECL is the declaration node of the function (as a tree),
1408 FUNTYPE is the data type of the function (as a tree),
1409 or for a library call it is an identifier node for the subroutine name.
1410 SIZE is the number of bytes of arguments passed on the stack.
1411
1412 On the 80386, the RTD insn may be used to pop them if the number
1413 of args is fixed, but if the number is variable then the caller
1414 must pop them all. RTD can't be used for library calls now
1415 because the library is compiled with the Unix compiler.
1416 Use of RTD is a selectable option, since it is incompatible with
1417 standard Unix calling sequences. If the option is not selected,
1418 the caller must always pop the args.
1419
1420 The attribute stdcall is equivalent to RTD on a per module basis. */
1421
1422#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1423 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1424
1425#define FUNCTION_VALUE_REGNO_P(N) \
1426 ix86_function_value_regno_p (N)
1427
1428/* Define how to find the value returned by a library function
1429 assuming the value has mode MODE. */
1430
1431#define LIBCALL_VALUE(MODE) \
1432 ix86_libcall_value (MODE)
1433
1434/* Define the size of the result block used for communication between
1435 untyped_call and untyped_return. The block contains a DImode value
1436 followed by the block used by fnsave and frstor. */
1437
1438#define APPLY_RESULT_SIZE (8+108)
1439
1440/* 1 if N is a possible register number for function argument passing. */
1441#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1442
1443/* Define a data type for recording info about an argument list
1444 during the scan of that argument list. This data type should
1445 hold all necessary information about the function itself
1446 and about the args processed so far, enough to enable macros
1447 such as FUNCTION_ARG to determine where the next arg should go. */
1448
1449typedef struct ix86_args {
1450 int words; /* # words passed so far */
1451 int nregs; /* # registers available for passing */
1452 int regno; /* next available register number */
1453 int fastcall; /* fastcall calling convention is used */
1454 int sse_words; /* # sse words passed so far */
1455 int sse_nregs; /* # sse registers available for passing */
1456 int warn_sse; /* True when we want to warn about SSE ABI. */
1457 int warn_mmx; /* True when we want to warn about MMX ABI. */
1458 int sse_regno; /* next available sse register number */
1459 int mmx_words; /* # mmx words passed so far */
1460 int mmx_nregs; /* # mmx registers available for passing */
1461 int mmx_regno; /* next available mmx register number */
1462 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1463 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1464 be passed in SSE registers. Otherwise 0. */
1465} CUMULATIVE_ARGS;
1466
1467/* Initialize a variable CUM of type CUMULATIVE_ARGS
1468 for a call to a function whose data type is FNTYPE.
1469 For a library call, FNTYPE is 0. */
1470
1471#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1472 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1473
1474/* Update the data in CUM to advance over an argument
1475 of mode MODE and data type TYPE.
1476 (TYPE is null for libcalls where that information may not be available.) */
1477
1478#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1479 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1480
1481/* Define where to put the arguments to a function.
1482 Value is zero to push the argument on the stack,
1483 or a hard register in which to store the argument.
1484
1485 MODE is the argument's machine mode.
1486 TYPE is the data type of the argument (as a tree).
1487 This is null for libcalls where that information may
1488 not be available.
1489 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1490 the preceding args and about the function being called.
1491 NAMED is nonzero if this argument is a named parameter
1492 (otherwise it is an extra parameter matching an ellipsis). */
1493
1494#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1495 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1496
1497/* Implement `va_start' for varargs and stdarg. */
1498#define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1499 ix86_va_start (VALIST, NEXTARG)
1500
1501#define TARGET_ASM_FILE_END ix86_file_end
1502#define NEED_INDICATE_EXEC_STACK 0
1503
1504/* Output assembler code to FILE to increment profiler label # LABELNO
1505 for profiling a function entry. */
1506
1507#define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1508
1509#define MCOUNT_NAME "_mcount"
1510
1511#define PROFILE_COUNT_REGISTER "edx"
1512
1513/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1514 the stack pointer does not matter. The value is tested only in
1515 functions that have frame pointers.
1516 No definition is equivalent to always zero. */
1517/* Note on the 386 it might be more efficient not to define this since
1518 we have to restore it ourselves from the frame pointer, in order to
1519 use pop */
1520
1521#define EXIT_IGNORE_STACK 1
1522
1523/* Output assembler code for a block containing the constant parts
1524 of a trampoline, leaving space for the variable parts. */
1525
1526/* On the 386, the trampoline contains two instructions:
1527 mov #STATIC,ecx
1528 jmp FUNCTION
1529 The trampoline is generated entirely at runtime. The operand of JMP
1530 is the address of FUNCTION relative to the instruction following the
1531 JMP (which is 5 bytes long). */
1532
1533/* Length in units of the trampoline for entering a nested function. */
1534
1535#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1536
1537/* Emit RTL insns to initialize the variable parts of a trampoline.
1538 FNADDR is an RTX for the address of the function's pure code.
1539 CXT is an RTX for the static chain value for the function. */
1540
1541#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1542 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1543
1544/* Definitions for register eliminations.
1545
1546 This is an array of structures. Each structure initializes one pair
1547 of eliminable registers. The "from" register number is given first,
1548 followed by "to". Eliminations of the same "from" register are listed
1549 in order of preference.
1550
1551 There are two registers that can always be eliminated on the i386.
1552 The frame pointer and the arg pointer can be replaced by either the
1553 hard frame pointer or to the stack pointer, depending upon the
1554 circumstances. The hard frame pointer is not used before reload and
1555 so it is not eligible for elimination. */
1556
1557#define ELIMINABLE_REGS \
1558{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1559 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1560 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1561 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1562
1563/* Given FROM and TO register numbers, say whether this elimination is
1564 allowed. Frame pointer elimination is automatically handled.
1565
1566 All other eliminations are valid. */
1567
1568#define CAN_ELIMINATE(FROM, TO) \
1569 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1570
1571/* Define the offset between two registers, one to be eliminated, and the other
1572 its replacement, at the start of a routine. */
1573
1574#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1575 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1576
1577/* Addressing modes, and classification of registers for them. */
1578
1579/* Macros to check register numbers against specific register classes. */
1580
1581/* These assume that REGNO is a hard or pseudo reg number.
1582 They give nonzero only if REGNO is a hard reg of the suitable class
1583 or a pseudo reg currently allocated to a suitable hard reg.
1584 Since they use reg_renumber, they are safe only once reg_renumber
1585 has been allocated, which happens in local-alloc.c. */
1586
1587#define REGNO_OK_FOR_INDEX_P(REGNO) \
1588 ((REGNO) < STACK_POINTER_REGNUM \
1589 || (REGNO >= FIRST_REX_INT_REG \
1590 && (REGNO) <= LAST_REX_INT_REG) \
1591 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1592 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1593 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1594
1595#define REGNO_OK_FOR_BASE_P(REGNO) \
1596 ((REGNO) <= STACK_POINTER_REGNUM \
1597 || (REGNO) == ARG_POINTER_REGNUM \
1598 || (REGNO) == FRAME_POINTER_REGNUM \
1599 || (REGNO >= FIRST_REX_INT_REG \
1600 && (REGNO) <= LAST_REX_INT_REG) \
1601 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1602 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1603 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1604
1605#define REGNO_OK_FOR_SIREG_P(REGNO) \
1606 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1607#define REGNO_OK_FOR_DIREG_P(REGNO) \
1608 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1609
1610/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1611 and check its validity for a certain class.
1612 We have two alternate definitions for each of them.
1613 The usual definition accepts all pseudo regs; the other rejects
1614 them unless they have been allocated suitable hard regs.
1615 The symbol REG_OK_STRICT causes the latter definition to be used.
1616
1617 Most source files want to accept pseudo regs in the hope that
1618 they will get allocated to the class that the insn wants them to be in.
1619 Source files for reload pass need to be strict.
1620 After reload, it makes no difference, since pseudo regs have
1621 been eliminated by then. */
1622
1623
1624/* Non strict versions, pseudos are ok. */
1625#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1626 (REGNO (X) < STACK_POINTER_REGNUM \
1627 || (REGNO (X) >= FIRST_REX_INT_REG \
1628 && REGNO (X) <= LAST_REX_INT_REG) \
1629 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1630
1631#define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1632 (REGNO (X) <= STACK_POINTER_REGNUM \
1633 || REGNO (X) == ARG_POINTER_REGNUM \
1634 || REGNO (X) == FRAME_POINTER_REGNUM \
1635 || (REGNO (X) >= FIRST_REX_INT_REG \
1636 && REGNO (X) <= LAST_REX_INT_REG) \
1637 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1638
1639/* Strict versions, hard registers only */
1640#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1641#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1642
1643#ifndef REG_OK_STRICT
1644#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1645#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1646
1647#else
1648#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1649#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1650#endif
1651
1652/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1653 that is a valid memory address for an instruction.
1654 The MODE argument is the machine mode for the MEM expression
1655 that wants to use this address.
1656
1657 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1658 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1659
1660 See legitimize_pic_address in i386.c for details as to what
1661 constitutes a legitimate address when -fpic is used. */
1662
1663#define MAX_REGS_PER_ADDRESS 2
1664
1665#define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1666
1667/* Nonzero if the constant value X is a legitimate general operand.
1668 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1669
1670#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1671
1672#ifdef REG_OK_STRICT
1673#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1674do { \
1675 if (legitimate_address_p ((MODE), (X), 1)) \
1676 goto ADDR; \
1677} while (0)
1678
1679#else
1680#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1681do { \
1682 if (legitimate_address_p ((MODE), (X), 0)) \
1683 goto ADDR; \
1684} while (0)
1685
1686#endif
1687
1688/* If defined, a C expression to determine the base term of address X.
1689 This macro is used in only one place: `find_base_term' in alias.c.
1690
1691 It is always safe for this macro to not be defined. It exists so
1692 that alias analysis can understand machine-dependent addresses.
1693
1694 The typical use of this macro is to handle addresses containing
1695 a label_ref or symbol_ref within an UNSPEC. */
1696
1697#define FIND_BASE_TERM(X) ix86_find_base_term (X)
1698
1699/* Try machine-dependent ways of modifying an illegitimate address
1700 to be legitimate. If we find one, return the new, valid address.
1701 This macro is used in only one place: `memory_address' in explow.c.
1702
1703 OLDX is the address as it was before break_out_memory_refs was called.
1704 In some cases it is useful to look at this to decide what needs to be done.
1705
1706 MODE and WIN are passed so that this macro can use
1707 GO_IF_LEGITIMATE_ADDRESS.
1708
1709 It is always safe for this macro to do nothing. It exists to recognize
1710 opportunities to optimize the output.
1711
1712 For the 80386, we handle X+REG by loading X into a register R and
1713 using R+REG. R will go in a general reg and indexing will be used.
1714 However, if REG is a broken-out memory address or multiplication,
1715 nothing needs to be done because REG can certainly go in a general reg.
1716
1717 When -fpic is used, special handling is needed for symbolic references.
1718 See comments by legitimize_pic_address in i386.c for details. */
1719
1720#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1721do { \
1722 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1723 if (memory_address_p ((MODE), (X))) \
1724 goto WIN; \
1725} while (0)
1726
1727#define REWRITE_ADDRESS(X) rewrite_address (X)
1728
1729/* Nonzero if the constant value X is a legitimate general operand
1730 when generating PIC code. It is given that flag_pic is on and
1731 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1732
1733#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1734
1735#define SYMBOLIC_CONST(X) \
1736 (GET_CODE (X) == SYMBOL_REF \
1737 || GET_CODE (X) == LABEL_REF \
1738 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1739
1740/* Go to LABEL if ADDR (a legitimate address expression)
1741 has an effect that depends on the machine mode it is used for.
1742 On the 80386, only postdecrement and postincrement address depend thus
1743 (the amount of decrement or increment being the length of the operand). */
1744#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1745do { \
1746 if (GET_CODE (ADDR) == POST_INC \
1747 || GET_CODE (ADDR) == POST_DEC) \
1748 goto LABEL; \
1749} while (0)
1750
1751/* Max number of args passed in registers. If this is more than 3, we will
1752 have problems with ebx (register #4), since it is a caller save register and
1753 is also used as the pic register in ELF. So for now, don't allow more than
1754 3 registers to be passed in registers. */
1755
1756#define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
1757
1758#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0))
1759
1760#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1761
1762
1763/* Specify the machine mode that this machine uses
1764 for the index in the tablejump instruction. */
1765#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
1766
1767/* Define this as 1 if `char' should by default be signed; else as 0. */
1768#define DEFAULT_SIGNED_CHAR 1
1769
1770/* Number of bytes moved into a data cache for a single prefetch operation. */
1771#define PREFETCH_BLOCK ix86_cost->prefetch_block
1772
1773/* Number of prefetch operations that can be done in parallel. */
1774#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
1775
1776/* Max number of bytes we can move from memory to memory
1777 in one reasonably fast instruction. */
1778#define MOVE_MAX 16
1779
1780/* MOVE_MAX_PIECES is the number of bytes at a time which we can
1781 move efficiently, as opposed to MOVE_MAX which is the maximum
1782 number of bytes we can move with a single instruction. */
1783#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1784
1785/* If a memory-to-memory move would take MOVE_RATIO or more simple
1786 move-instruction pairs, we will do a movmem or libcall instead.
1787 Increasing the value will always make code faster, but eventually
1788 incurs high cost in increased code size.
1789
1790 If you don't define this, a reasonable default is used. */
1791
1792#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
1793
1794/* If a clear memory operation would take CLEAR_RATIO or more simple
1795 move-instruction sequences, we will do a clrmem or libcall instead. */
1796
1797#define CLEAR_RATIO (optimize_size ? 2 \
1798 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio)
1799
1800/* Define if shifts truncate the shift count
1801 which implies one can omit a sign-extension or zero-extension
1802 of a shift count. */
1803/* On i386, shifts do truncate the count. But bit opcodes don't. */
1804
1805/* #define SHIFT_COUNT_TRUNCATED */
1806
1807/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1808 is done just by pretending it is already truncated. */
1809#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1810
1811/* A macro to update M and UNSIGNEDP when an object whose type is
1812 TYPE and which has the specified mode and signedness is to be
1813 stored in a register. This macro is only called when TYPE is a
1814 scalar type.
1815
1816 On i386 it is sometimes useful to promote HImode and QImode
1817 quantities to SImode. The choice depends on target type. */
1818
1819#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1820do { \
1821 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1822 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1823 (MODE) = SImode; \
1824} while (0)
1825
1826/* Specify the machine mode that pointers have.
1827 After generation of rtl, the compiler makes no further distinction
1828 between pointers and any other objects of this machine mode. */
1829#define Pmode (TARGET_64BIT ? DImode : SImode)
1830
1831/* A function address in a call instruction
1832 is a byte address (for indexing purposes)
1833 so give the MEM rtx a byte's mode. */
1834#define FUNCTION_MODE QImode
1835
1836/* A C expression for the cost of moving data from a register in class FROM to
1837 one in class TO. The classes are expressed using the enumeration values
1838 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1839 interpreted relative to that.
1840
1841 It is not required that the cost always equal 2 when FROM is the same as TO;
1842 on some machines it is expensive to move between registers if they are not
1843 general registers. */
1844
1845#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1846 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
1847
1848/* A C expression for the cost of moving data of mode M between a
1849 register and memory. A value of 2 is the default; this cost is
1850 relative to those in `REGISTER_MOVE_COST'.
1851
1852 If moving between registers and memory is more expensive than
1853 between two registers, you should define this macro to express the
1854 relative cost. */
1855
1856#define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1857 ix86_memory_move_cost ((MODE), (CLASS), (IN))
1858
1859/* A C expression for the cost of a branch instruction. A value of 1
1860 is the default; other values are interpreted relative to that. */
1861
1862#define BRANCH_COST ix86_branch_cost
1863
1864/* Define this macro as a C expression which is nonzero if accessing
1865 less than a word of memory (i.e. a `char' or a `short') is no
1866 faster than accessing a word of memory, i.e., if such access
1867 require more than one instruction or if there is no difference in
1868 cost between byte and (aligned) word loads.
1869
1870 When this macro is not defined, the compiler will access a field by
1871 finding the smallest containing object; when it is defined, a
1872 fullword load will be used if alignment permits. Unless bytes
1873 accesses are faster than word accesses, using word accesses is
1874 preferable since it may eliminate subsequent memory access if
1875 subsequent accesses occur to other fields in the same word of the
1876 structure, but to different bytes. */
1877
1878#define SLOW_BYTE_ACCESS 0
1879
1880/* Nonzero if access to memory by shorts is slow and undesirable. */
1881#define SLOW_SHORT_ACCESS 0
1882
1883/* Define this macro to be the value 1 if unaligned accesses have a
1884 cost many times greater than aligned accesses, for example if they
1885 are emulated in a trap handler.
1886
1887 When this macro is nonzero, the compiler will act as if
1888 `STRICT_ALIGNMENT' were nonzero when generating code for block
1889 moves. This can cause significantly more instructions to be
1890 produced. Therefore, do not set this macro nonzero if unaligned
1891 accesses only add a cycle or two to the time for a memory access.
1892
1893 If the value of this macro is always zero, it need not be defined. */
1894
1895/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1896
1897/* Define this macro if it is as good or better to call a constant
1898 function address than to call an address kept in a register.
1899
1900 Desirable on the 386 because a CALL with a constant address is
1901 faster than one with a register address. */
1902
1903#define NO_FUNCTION_CSE
1904
1905/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1906 return the mode to be used for the comparison.
1907
1908 For floating-point equality comparisons, CCFPEQmode should be used.
1909 VOIDmode should be used in all other cases.
1910
1911 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1912 possible, to allow for more combinations. */
1913
1914#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1915
1916/* Return nonzero if MODE implies a floating point inequality can be
1917 reversed. */
1918
1919#define REVERSIBLE_CC_MODE(MODE) 1
1920
1921/* A C expression whose value is reversed condition code of the CODE for
1922 comparison done in CC_MODE mode. */
1923#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1924
1925
1926/* Control the assembler format that we output, to the extent
1927 this does not vary between assemblers. */
1928
1929/* How to refer to registers in assembler output.
1930 This sequence is indexed by compiler's hard-register-number (see above). */
1931
1932/* In order to refer to the first 8 regs as 32 bit regs, prefix an "e".
1933 For non floating point regs, the following are the HImode names.
1934
1935 For float regs, the stack top is sometimes referred to as "%st(0)"
1936 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
1937
1938#define HI_REGISTER_NAMES \
1939{"ax","dx","cx","bx","si","di","bp","sp", \
1940 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
1941 "argp", "flags", "fpsr", "dirflag", "frame", \
1942 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
1943 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
1944 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1945 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
1946
1947#define REGISTER_NAMES HI_REGISTER_NAMES
1948
1949/* Table of additional register names to use in user input. */
1950
1951#define ADDITIONAL_REGISTER_NAMES \
1952{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
1953 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
1954 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
1955 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
1956 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
1957 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
1958
1959/* Note we are omitting these since currently I don't know how
1960to get gcc to use these, since they want the same but different
1961number as al, and ax.
1962*/
1963
1964#define QI_REGISTER_NAMES \
1965{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
1966
1967/* These parallel the array above, and can be used to access bits 8:15
1968 of regs 0 through 3. */
1969
1970#define QI_HIGH_REGISTER_NAMES \
1971{"ah", "dh", "ch", "bh", }
1972
1973/* How to renumber registers for dbx and gdb. */
1974
1975#define DBX_REGISTER_NUMBER(N) \
1976 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
1977
1978extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
1979extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
1980extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
1981
1982/* Before the prologue, RA is at 0(%esp). */
1983#define INCOMING_RETURN_ADDR_RTX \
1984 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1985
1986/* After the prologue, RA is at -4(AP) in the current frame. */
1987#define RETURN_ADDR_RTX(COUNT, FRAME) \
1988 ((COUNT) == 0 \
1989 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
1990 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
1991
1992/* PC is dbx register 8; let's use that column for RA. */
1993#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
1994
1995/* Before the prologue, the top of the frame is at 4(%esp). */
1996#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
1997
1998/* Describe how we implement __builtin_eh_return. */
1999#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2000#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2001
2002
2003/* Select a format to encode pointers in exception handling data. CODE
2004 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2005 true if the symbol may be affected by dynamic relocations.
2006
2007 ??? All x86 object file formats are capable of representing this.
2008 After all, the relocation needed is the same as for the call insn.
2009 Whether or not a particular assembler allows us to enter such, I
2010 guess we'll have to see. */
2011#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2012 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2013
2014/* This is how to output an insn to push a register on the stack.
2015 It need not be very fast code. */
2016
2017#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2018do { \
2019 if (TARGET_64BIT) \
2020 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2021 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2022 else \
2023 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2024} while (0)
2025
2026/* This is how to output an insn to pop a register from the stack.
2027 It need not be very fast code. */
2028
2029#define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2030do { \
2031 if (TARGET_64BIT) \
2032 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2033 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2034 else \
2035 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2036} while (0)
2037
2038/* This is how to output an element of a case-vector that is absolute. */
2039
2040#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2041 ix86_output_addr_vec_elt ((FILE), (VALUE))
2042
2043/* This is how to output an element of a case-vector that is relative. */
2044
2045#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2046 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2047
2048/* Under some conditions we need jump tables in the text section,
2049 because the assembler cannot handle label differences between
2050 sections. This is the case for x86_64 on Mach-O for example. */
2051
2052#define JUMP_TABLES_IN_TEXT_SECTION \
2053 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2054 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2055
2056/* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2057 and switch back. For x86 we do this only to save a few bytes that
2058 would otherwise be unused in the text section. */
2059#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2060 asm (SECTION_OP "\n\t" \
2061 "call " USER_LABEL_PREFIX #FUNC "\n" \
2062 TEXT_SECTION_ASM_OP);
2063
2064/* Print operand X (an rtx) in assembler syntax to file FILE.
2065 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2066 Effect of various CODE letters is described in i386.c near
2067 print_operand function. */
2068
2069#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2070 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
2071
2072#define PRINT_OPERAND(FILE, X, CODE) \
2073 print_operand ((FILE), (X), (CODE))
2074
2075#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2076 print_operand_address ((FILE), (ADDR))
2077
2078#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2079do { \
2080 if (! output_addr_const_extra (FILE, (X))) \
2081 goto FAIL; \
2082} while (0);
2083
2084/* a letter which is not needed by the normal asm syntax, which
2085 we can use for operand syntax in the extended asm */
2086
2087#define ASM_OPERAND_LETTER '#'
2088#define RET return ""
2089#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
2090
2091/* Which processor to schedule for. The cpu attribute defines a list that
2092 mirrors this list, so changes to i386.md must be made at the same time. */
2093
2094enum processor_type
2095{
2096 PROCESSOR_I386, /* 80386 */
2097 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2098 PROCESSOR_PENTIUM,
2099 PROCESSOR_PENTIUMPRO,
2100 PROCESSOR_GEODE,
2101 PROCESSOR_K6,
2102 PROCESSOR_ATHLON,
2103 PROCESSOR_PENTIUM4,
2104 PROCESSOR_K8,
2105 PROCESSOR_NOCONA,
2106 PROCESSOR_CORE2,
2107 PROCESSOR_GENERIC32,
2108 PROCESSOR_GENERIC64,
2109 PROCESSOR_max
2110};
2111
2112extern enum processor_type ix86_tune;
2113extern enum processor_type ix86_arch;
2114
2115enum fpmath_unit
2116{
2117 FPMATH_387 = 1,
2118 FPMATH_SSE = 2
2119};
2120
2121extern enum fpmath_unit ix86_fpmath;
2122
2123enum tls_dialect
2124{
2125 TLS_DIALECT_GNU,
2126 TLS_DIALECT_GNU2,
2127 TLS_DIALECT_SUN
2128};
2129
2130extern enum tls_dialect ix86_tls_dialect;
2131
2132enum cmodel {
2133 CM_32, /* The traditional 32-bit ABI. */
2134 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2135 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2136 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2137 CM_LARGE, /* No assumptions. */
2138 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2139 CM_MEDIUM_PIC /* Assumes code+got/plt fits in a 31 bit region. */
2140};
2141
2142extern enum cmodel ix86_cmodel;
2143
2144/* Size of the RED_ZONE area. */
2145#define RED_ZONE_SIZE 128
2146/* Reserved area of the red zone for temporaries. */
2147#define RED_ZONE_RESERVE 8
2148
2149enum asm_dialect {
2150 ASM_ATT,
2151 ASM_INTEL
2152};
2153
2154extern enum asm_dialect ix86_asm_dialect;
2155extern unsigned int ix86_preferred_stack_boundary;
2156extern int ix86_branch_cost, ix86_section_threshold;
2157
2158/* Smallest class containing REGNO. */
2159extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2160
2161extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2162extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2163extern rtx ix86_compare_emitted;
2164
2165/* To properly truncate FP values into integers, we need to set i387 control
2166 word. We can't emit proper mode switching code before reload, as spills
2167 generated by reload may truncate values incorrectly, but we still can avoid
2168 redundant computation of new control word by the mode switching pass.
2169 The fldcw instructions are still emitted redundantly, but this is probably
2170 not going to be noticeable problem, as most CPUs do have fast path for
2171 the sequence.
2172
2173 The machinery is to emit simple truncation instructions and split them
2174 before reload to instructions having USEs of two memory locations that
2175 are filled by this code to old and new control word.
2176
2177 Post-reload pass may be later used to eliminate the redundant fildcw if
2178 needed. */
2179
2180enum ix86_entity
2181{
2182 I387_TRUNC = 0,
2183 I387_FLOOR,
2184 I387_CEIL,
2185 I387_MASK_PM,
2186 MAX_386_ENTITIES
2187};
2188
2189enum ix86_stack_slot
2190{
2191 SLOT_VIRTUAL = 0,
2192 SLOT_TEMP,
2193 SLOT_CW_STORED,
2194 SLOT_CW_TRUNC,
2195 SLOT_CW_FLOOR,
2196 SLOT_CW_CEIL,
2197 SLOT_CW_MASK_PM,
2198 MAX_386_STACK_LOCALS
2199};
2200
2201/* Define this macro if the port needs extra instructions inserted
2202 for mode switching in an optimizing compilation. */
2203
2204#define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2205 ix86_optimize_mode_switching[(ENTITY)]
2206
2207/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2208 initializer for an array of integers. Each initializer element N
2209 refers to an entity that needs mode switching, and specifies the
2210 number of different modes that might need to be set for this
2211 entity. The position of the initializer in the initializer -
2212 starting counting at zero - determines the integer that is used to
2213 refer to the mode-switched entity in question. */
2214
2215#define NUM_MODES_FOR_MODE_SWITCHING \
2216 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2217
2218/* ENTITY is an integer specifying a mode-switched entity. If
2219 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2220 return an integer value not larger than the corresponding element
2221 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2222 must be switched into prior to the execution of INSN. */
2223
2224#define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2225
2226/* This macro specifies the order in which modes for ENTITY are
2227 processed. 0 is the highest priority. */
2228
2229#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2230
2231/* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2232 is the set of hard registers live at the point where the insn(s)
2233 are to be inserted. */
2234
2235#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2236 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2237 ? emit_i387_cw_initialization (MODE), 0 \
2238 : 0)
2239
2240
2241/* Avoid renaming of stack registers, as doing so in combination with
2242 scheduling just increases amount of live registers at time and in
2243 the turn amount of fxch instructions needed.
2244
2245 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2246
2247#define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2248 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
2249
2250
2251#define DLL_IMPORT_EXPORT_PREFIX '#'
2252
2253#define FASTCALL_PREFIX '@'
2254
2255struct machine_function GTY(())
2256{
2257 struct stack_local_entry *stack_locals;
2258 const char *some_ld_name;
2259 rtx force_align_arg_pointer;
2260 int save_varrargs_registers;
2261 int accesses_prev_frame;
2262 int optimize_mode_switching[MAX_386_ENTITIES];
2263 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
2264 determine the style used. */
2265 int use_fast_prologue_epilogue;
2266 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2267 for. */
2268 int use_fast_prologue_epilogue_nregs;
2269 /* If true, the current function needs the default PIC register, not
2270 an alternate register (on x86) and must not use the red zone (on
2271 x86_64), even if it's a leaf function. We don't want the
2272 function to be regarded as non-leaf because TLS calls need not
2273 affect register allocation. This flag is set when a TLS call
2274 instruction is expanded within a function, and never reset, even
2275 if all such instructions are optimized away. Use the
2276 ix86_current_function_calls_tls_descriptor macro for a better
2277 approximation. */
2278 int tls_descriptor_call_expanded_p;
2279};
2280
2281#define ix86_stack_locals (cfun->machine->stack_locals)
2282#define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2283#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2284#define ix86_tls_descriptor_calls_expanded_in_cfun \
2285 (cfun->machine->tls_descriptor_call_expanded_p)
2286/* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2287 calls are optimized away, we try to detect cases in which it was
2288 optimized away. Since such instructions (use (reg REG_SP)), we can
2289 verify whether there's any such instruction live by testing that
2290 REG_SP is live. */
2291#define ix86_current_function_calls_tls_descriptor \
2292 (ix86_tls_descriptor_calls_expanded_in_cfun && regs_ever_live[SP_REG])
2293
2294/* Control behavior of x86_file_start. */
2295#define X86_FILE_START_VERSION_DIRECTIVE false
2296#define X86_FILE_START_FLTUSED false
2297
2298/* Flag to mark data that is in the large address area. */
2299#define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2300#define SYMBOL_REF_FAR_ADDR_P(X) \
2301 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2302/*
2303Local variables:
2304version-control: t
2305End:
2306*/
| 423 if (TARGET_SSE_MATH && TARGET_SSE) \
424 builtin_define ("__SSE_MATH__"); \
425 if (TARGET_SSE_MATH && TARGET_SSE2) \
426 builtin_define ("__SSE2_MATH__"); \
427 \
428 /* Built-ins based on -march=. */ \
429 if (ix86_arch == PROCESSOR_I486) \
430 { \
431 builtin_define ("__i486"); \
432 builtin_define ("__i486__"); \
433 } \
434 else if (ix86_arch == PROCESSOR_PENTIUM) \
435 { \
436 builtin_define ("__i586"); \
437 builtin_define ("__i586__"); \
438 builtin_define ("__pentium"); \
439 builtin_define ("__pentium__"); \
440 if (last_arch_char == 'x') \
441 builtin_define ("__pentium_mmx__"); \
442 } \
443 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
444 { \
445 builtin_define ("__i686"); \
446 builtin_define ("__i686__"); \
447 builtin_define ("__pentiumpro"); \
448 builtin_define ("__pentiumpro__"); \
449 } \
450 else if (ix86_arch == PROCESSOR_GEODE) \
451 { \
452 builtin_define ("__geode"); \
453 builtin_define ("__geode__"); \
454 } \
455 else if (ix86_arch == PROCESSOR_K6) \
456 { \
457 \
458 builtin_define ("__k6"); \
459 builtin_define ("__k6__"); \
460 if (last_arch_char == '2') \
461 builtin_define ("__k6_2__"); \
462 else if (last_arch_char == '3') \
463 builtin_define ("__k6_3__"); \
464 } \
465 else if (ix86_arch == PROCESSOR_ATHLON) \
466 { \
467 builtin_define ("__athlon"); \
468 builtin_define ("__athlon__"); \
469 /* Plain "athlon" & "athlon-tbird" lacks SSE. */ \
470 if (last_tune_char != 'n' && last_tune_char != 'd') \
471 builtin_define ("__athlon_sse__"); \
472 } \
473 else if (ix86_arch == PROCESSOR_K8) \
474 { \
475 builtin_define ("__k8"); \
476 builtin_define ("__k8__"); \
477 } \
478 else if (ix86_arch == PROCESSOR_PENTIUM4) \
479 { \
480 builtin_define ("__pentium4"); \
481 builtin_define ("__pentium4__"); \
482 } \
483 else if (ix86_arch == PROCESSOR_NOCONA) \
484 { \
485 builtin_define ("__nocona"); \
486 builtin_define ("__nocona__"); \
487 } \
488 else if (ix86_arch == PROCESSOR_CORE2) \
489 { \
490 builtin_define ("__core2"); \
491 builtin_define ("__core2__"); \
492 } \
493 } \
494 while (0)
495
496#define TARGET_CPU_DEFAULT_i386 0
497#define TARGET_CPU_DEFAULT_i486 1
498#define TARGET_CPU_DEFAULT_pentium 2
499#define TARGET_CPU_DEFAULT_pentium_mmx 3
500#define TARGET_CPU_DEFAULT_pentiumpro 4
501#define TARGET_CPU_DEFAULT_pentium2 5
502#define TARGET_CPU_DEFAULT_pentium3 6
503#define TARGET_CPU_DEFAULT_pentium4 7
504#define TARGET_CPU_DEFAULT_geode 8
505#define TARGET_CPU_DEFAULT_k6 9
506#define TARGET_CPU_DEFAULT_k6_2 10
507#define TARGET_CPU_DEFAULT_k6_3 11
508#define TARGET_CPU_DEFAULT_athlon 12
509#define TARGET_CPU_DEFAULT_athlon_sse 13
510#define TARGET_CPU_DEFAULT_k8 14
511#define TARGET_CPU_DEFAULT_pentium_m 15
512#define TARGET_CPU_DEFAULT_prescott 16
513#define TARGET_CPU_DEFAULT_nocona 17
514#define TARGET_CPU_DEFAULT_core2 18
515#define TARGET_CPU_DEFAULT_generic 19
516
517#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
518 "pentiumpro", "pentium2", "pentium3", \
519 "pentium4", "geode", "k6", "k6-2", "k6-3", \
520 "athlon", "athlon-4", "k8", \
521 "pentium-m", "prescott", "nocona", \
522 "core2", "generic"}
523
524#ifndef CC1_SPEC
525#define CC1_SPEC "%(cc1_cpu) "
526#endif
527
528/* This macro defines names of additional specifications to put in the
529 specs that can be used in various specifications like CC1_SPEC. Its
530 definition is an initializer with a subgrouping for each command option.
531
532 Each subgrouping contains a string constant, that defines the
533 specification name, and a string constant that used by the GCC driver
534 program.
535
536 Do not define this macro if it does not need to do anything. */
537
538#ifndef SUBTARGET_EXTRA_SPECS
539#define SUBTARGET_EXTRA_SPECS
540#endif
541
542#define EXTRA_SPECS \
543 { "cc1_cpu", CC1_CPU_SPEC }, \
544 SUBTARGET_EXTRA_SPECS
545
546/* target machine storage layout */
547
548#define LONG_DOUBLE_TYPE_SIZE 80
549
550/* Set the value of FLT_EVAL_METHOD in float.h. When using only the
551 FPU, assume that the fpcw is set to extended precision; when using
552 only SSE, rounding is correct; when using both SSE and the FPU,
553 the rounding precision is indeterminate, since either may be chosen
554 apparently at random. */
555#define TARGET_FLT_EVAL_METHOD \
556 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
557
558#define SHORT_TYPE_SIZE 16
559#define INT_TYPE_SIZE 32
560#define FLOAT_TYPE_SIZE 32
561#ifndef LONG_TYPE_SIZE
562#define LONG_TYPE_SIZE BITS_PER_WORD
563#endif
564#define DOUBLE_TYPE_SIZE 64
565#define LONG_LONG_TYPE_SIZE 64
566
567#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
568#define MAX_BITS_PER_WORD 64
569#else
570#define MAX_BITS_PER_WORD 32
571#endif
572
573/* Define this if most significant byte of a word is the lowest numbered. */
574/* That is true on the 80386. */
575
576#define BITS_BIG_ENDIAN 0
577
578/* Define this if most significant byte of a word is the lowest numbered. */
579/* That is not true on the 80386. */
580#define BYTES_BIG_ENDIAN 0
581
582/* Define this if most significant word of a multiword number is the lowest
583 numbered. */
584/* Not true for 80386 */
585#define WORDS_BIG_ENDIAN 0
586
587/* Width of a word, in units (bytes). */
588#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
589#ifdef IN_LIBGCC2
590#define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
591#else
592#define MIN_UNITS_PER_WORD 4
593#endif
594
595/* Allocation boundary (in *bits*) for storing arguments in argument list. */
596#define PARM_BOUNDARY BITS_PER_WORD
597
598/* Boundary (in *bits*) on which stack pointer should be aligned. */
599#define STACK_BOUNDARY BITS_PER_WORD
600
601/* Boundary (in *bits*) on which the stack pointer prefers to be
602 aligned; the compiler cannot rely on having this alignment. */
603#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
604
605/* As of July 2001, many runtimes do not align the stack properly when
606 entering main. This causes expand_main_function to forcibly align
607 the stack, which results in aligned frames for functions called from
608 main, though it does nothing for the alignment of main itself. */
609#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
610 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
611
612/* Minimum allocation boundary for the code of a function. */
613#define FUNCTION_BOUNDARY 8
614
615/* C++ stores the virtual bit in the lowest bit of function pointers. */
616#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
617
618/* Alignment of field after `int : 0' in a structure. */
619
620#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
621
622/* Minimum size in bits of the largest boundary to which any
623 and all fundamental data types supported by the hardware
624 might need to be aligned. No data type wants to be aligned
625 rounder than this.
626
627 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
628 and Pentium Pro XFmode values at 128 bit boundaries. */
629
630#define BIGGEST_ALIGNMENT 128
631
632/* Decide whether a variable of mode MODE should be 128 bit aligned. */
633#define ALIGN_MODE_128(MODE) \
634 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
635
636/* The published ABIs say that doubles should be aligned on word
637 boundaries, so lower the alignment for structure fields unless
638 -malign-double is set. */
639
640/* ??? Blah -- this macro is used directly by libobjc. Since it
641 supports no vector modes, cut out the complexity and fall back
642 on BIGGEST_FIELD_ALIGNMENT. */
643#ifdef IN_TARGET_LIBS
644#ifdef __x86_64__
645#define BIGGEST_FIELD_ALIGNMENT 128
646#else
647#define BIGGEST_FIELD_ALIGNMENT 32
648#endif
649#else
650#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
651 x86_field_alignment (FIELD, COMPUTED)
652#endif
653
654/* If defined, a C expression to compute the alignment given to a
655 constant that is being placed in memory. EXP is the constant
656 and ALIGN is the alignment that the object would ordinarily have.
657 The value of this macro is used instead of that alignment to align
658 the object.
659
660 If this macro is not defined, then ALIGN is used.
661
662 The typical use of this macro is to increase alignment for string
663 constants to be word aligned so that `strcpy' calls that copy
664 constants can be done inline. */
665
666#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
667
668/* If defined, a C expression to compute the alignment for a static
669 variable. TYPE is the data type, and ALIGN is the alignment that
670 the object would ordinarily have. The value of this macro is used
671 instead of that alignment to align the object.
672
673 If this macro is not defined, then ALIGN is used.
674
675 One use of this macro is to increase alignment of medium-size
676 data to make it all fit in fewer cache lines. Another is to
677 cause character arrays to be word-aligned so that `strcpy' calls
678 that copy constants to character arrays can be done inline. */
679
680#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
681
682/* If defined, a C expression to compute the alignment for a local
683 variable. TYPE is the data type, and ALIGN is the alignment that
684 the object would ordinarily have. The value of this macro is used
685 instead of that alignment to align the object.
686
687 If this macro is not defined, then ALIGN is used.
688
689 One use of this macro is to increase alignment of medium-size
690 data to make it all fit in fewer cache lines. */
691
692#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
693
694/* If defined, a C expression that gives the alignment boundary, in
695 bits, of an argument with the specified mode and type. If it is
696 not defined, `PARM_BOUNDARY' is used for all arguments. */
697
698#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
699 ix86_function_arg_boundary ((MODE), (TYPE))
700
701/* Set this nonzero if move instructions will actually fail to work
702 when given unaligned data. */
703#define STRICT_ALIGNMENT 0
704
705/* If bit field type is int, don't let it cross an int,
706 and give entire struct the alignment of an int. */
707/* Required on the 386 since it doesn't have bit-field insns. */
708#define PCC_BITFIELD_TYPE_MATTERS 1
709
710/* Standard register usage. */
711
712/* This processor has special stack-like registers. See reg-stack.c
713 for details. */
714
715#define STACK_REGS
716#define IS_STACK_MODE(MODE) \
717 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
718 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
719 || (MODE) == XFmode)
720
721/* Number of actual hardware registers.
722 The hardware registers are assigned numbers for the compiler
723 from 0 to just below FIRST_PSEUDO_REGISTER.
724 All registers that the compiler knows about must be given numbers,
725 even those that are not normally considered general registers.
726
727 In the 80386 we give the 8 general purpose registers the numbers 0-7.
728 We number the floating point registers 8-15.
729 Note that registers 0-7 can be accessed as a short or int,
730 while only 0-3 may be used with byte `mov' instructions.
731
732 Reg 16 does not correspond to any hardware register, but instead
733 appears in the RTL as an argument pointer prior to reload, and is
734 eliminated during reloading in favor of either the stack or frame
735 pointer. */
736
737#define FIRST_PSEUDO_REGISTER 53
738
739/* Number of hardware registers that go into the DWARF-2 unwind info.
740 If not defined, equals FIRST_PSEUDO_REGISTER. */
741
742#define DWARF_FRAME_REGISTERS 17
743
744/* 1 for registers that have pervasive standard uses
745 and are not available for the register allocator.
746 On the 80386, the stack pointer is such, as is the arg pointer.
747
748 The value is zero if the register is not fixed on either 32 or
749 64 bit targets, one if the register if fixed on both 32 and 64
750 bit targets, two if it is only fixed on 32bit targets and three
751 if its only fixed on 64bit targets.
752 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
753 */
754#define FIXED_REGISTERS \
755/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
756{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
757/*arg,flags,fpsr,dir,frame*/ \
758 1, 1, 1, 1, 1, \
759/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
760 0, 0, 0, 0, 0, 0, 0, 0, \
761/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
762 0, 0, 0, 0, 0, 0, 0, 0, \
763/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
764 2, 2, 2, 2, 2, 2, 2, 2, \
765/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
766 2, 2, 2, 2, 2, 2, 2, 2}
767
768
769/* 1 for registers not available across function calls.
770 These must include the FIXED_REGISTERS and also any
771 registers that can be used without being saved.
772 The latter must include the registers where values are returned
773 and the register where structure-value addresses are passed.
774 Aside from that, you can include as many other registers as you like.
775
776 The value is zero if the register is not call used on either 32 or
777 64 bit targets, one if the register if call used on both 32 and 64
778 bit targets, two if it is only call used on 32bit targets and three
779 if its only call used on 64bit targets.
780 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
781*/
782#define CALL_USED_REGISTERS \
783/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
784{ 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
785/*arg,flags,fpsr,dir,frame*/ \
786 1, 1, 1, 1, 1, \
787/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
788 1, 1, 1, 1, 1, 1, 1, 1, \
789/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
790 1, 1, 1, 1, 1, 1, 1, 1, \
791/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
792 1, 1, 1, 1, 2, 2, 2, 2, \
793/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
794 1, 1, 1, 1, 1, 1, 1, 1} \
795
796/* Order in which to allocate registers. Each register must be
797 listed once, even those in FIXED_REGISTERS. List frame pointer
798 late and fixed registers last. Note that, in general, we prefer
799 registers listed in CALL_USED_REGISTERS, keeping the others
800 available for storage of persistent values.
801
802 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
803 so this is just empty initializer for array. */
804
805#define REG_ALLOC_ORDER \
806{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
807 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
808 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
809 48, 49, 50, 51, 52 }
810
811/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
812 to be rearranged based on a particular function. When using sse math,
813 we want to allocate SSE before x87 registers and vice vera. */
814
815#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
816
817
818/* Macro to conditionally modify fixed_regs/call_used_regs. */
819#define CONDITIONAL_REGISTER_USAGE \
820do { \
821 int i; \
822 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
823 { \
824 if (fixed_regs[i] > 1) \
825 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
826 if (call_used_regs[i] > 1) \
827 call_used_regs[i] = (call_used_regs[i] \
828 == (TARGET_64BIT ? 3 : 2)); \
829 } \
830 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
831 { \
832 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
833 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
834 } \
835 if (! TARGET_MMX) \
836 { \
837 int i; \
838 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
839 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
840 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
841 } \
842 if (! TARGET_SSE) \
843 { \
844 int i; \
845 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
846 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
847 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
848 } \
849 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
850 { \
851 int i; \
852 HARD_REG_SET x; \
853 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
854 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
855 if (TEST_HARD_REG_BIT (x, i)) \
856 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
857 } \
858 if (! TARGET_64BIT) \
859 { \
860 int i; \
861 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
862 reg_names[i] = ""; \
863 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
864 reg_names[i] = ""; \
865 } \
866 } while (0)
867
868/* Return number of consecutive hard regs needed starting at reg REGNO
869 to hold something of mode MODE.
870 This is ordinarily the length in words of a value of mode MODE
871 but can be less for certain modes in special long registers.
872
873 Actually there are no two word move instructions for consecutive
874 registers. And only registers 0-3 may have mov byte instructions
875 applied to them.
876 */
877
878#define HARD_REGNO_NREGS(REGNO, MODE) \
879 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
880 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
881 : ((MODE) == XFmode \
882 ? (TARGET_64BIT ? 2 : 3) \
883 : (MODE) == XCmode \
884 ? (TARGET_64BIT ? 4 : 6) \
885 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
886
887#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
888 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
889 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
890 ? 0 \
891 : ((MODE) == XFmode || (MODE) == XCmode)) \
892 : 0)
893
894#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
895
896#define VALID_SSE2_REG_MODE(MODE) \
897 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
898 || (MODE) == V2DImode || (MODE) == DFmode)
899
900#define VALID_SSE_REG_MODE(MODE) \
901 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
902 || (MODE) == SFmode || (MODE) == TFmode)
903
904#define VALID_MMX_REG_MODE_3DNOW(MODE) \
905 ((MODE) == V2SFmode || (MODE) == SFmode)
906
907#define VALID_MMX_REG_MODE(MODE) \
908 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
909 || (MODE) == V2SImode || (MODE) == SImode)
910
911/* ??? No autovectorization into MMX or 3DNOW until we can reliably
912 place emms and femms instructions. */
913#define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD)
914
915#define VALID_FP_MODE_P(MODE) \
916 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
917 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
918
919#define VALID_INT_MODE_P(MODE) \
920 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
921 || (MODE) == DImode \
922 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
923 || (MODE) == CDImode \
924 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
925 || (MODE) == TFmode || (MODE) == TCmode)))
926
927/* Return true for modes passed in SSE registers. */
928#define SSE_REG_MODE_P(MODE) \
929 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
930 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
931 || (MODE) == V4SFmode || (MODE) == V4SImode)
932
933/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
934
935#define HARD_REGNO_MODE_OK(REGNO, MODE) \
936 ix86_hard_regno_mode_ok ((REGNO), (MODE))
937
938/* Value is 1 if it is a good idea to tie two pseudo registers
939 when one has mode MODE1 and one has mode MODE2.
940 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
941 for any hard reg, then this must be 0 for correct output. */
942
943#define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
944
945/* It is possible to write patterns to move flags; but until someone
946 does it, */
947#define AVOID_CCMODE_COPIES
948
949/* Specify the modes required to caller save a given hard regno.
950 We do this on i386 to prevent flags from being saved at all.
951
952 Kill any attempts to combine saving of modes. */
953
954#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
955 (CC_REGNO_P (REGNO) ? VOIDmode \
956 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
957 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
958 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
959 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
960 : (MODE))
961/* Specify the registers used for certain standard purposes.
962 The values of these macros are register numbers. */
963
964/* on the 386 the pc register is %eip, and is not usable as a general
965 register. The ordinary mov instructions won't work */
966/* #define PC_REGNUM */
967
968/* Register to use for pushing function arguments. */
969#define STACK_POINTER_REGNUM 7
970
971/* Base register for access to local variables of the function. */
972#define HARD_FRAME_POINTER_REGNUM 6
973
974/* Base register for access to local variables of the function. */
975#define FRAME_POINTER_REGNUM 20
976
977/* First floating point reg */
978#define FIRST_FLOAT_REG 8
979
980/* First & last stack-like regs */
981#define FIRST_STACK_REG FIRST_FLOAT_REG
982#define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
983
984#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
985#define LAST_SSE_REG (FIRST_SSE_REG + 7)
986
987#define FIRST_MMX_REG (LAST_SSE_REG + 1)
988#define LAST_MMX_REG (FIRST_MMX_REG + 7)
989
990#define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
991#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
992
993#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
994#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
995
996/* Value should be nonzero if functions must have frame pointers.
997 Zero means the frame pointer need not be set up (and parms
998 may be accessed via the stack pointer) in functions that seem suitable.
999 This is computed in `reload', in reload1.c. */
1000#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1001
1002/* Override this in other tm.h files to cope with various OS lossage
1003 requiring a frame pointer. */
1004#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1005#define SUBTARGET_FRAME_POINTER_REQUIRED 0
1006#endif
1007
1008/* Make sure we can access arbitrary call frames. */
1009#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1010
1011/* Base register for access to arguments of the function. */
1012#define ARG_POINTER_REGNUM 16
1013
1014/* Register in which static-chain is passed to a function.
1015 We do use ECX as static chain register for 32 bit ABI. On the
1016 64bit ABI, ECX is an argument register, so we use R10 instead. */
1017#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1018
1019/* Register to hold the addressing base for position independent
1020 code access to data items. We don't use PIC pointer for 64bit
1021 mode. Define the regnum to dummy value to prevent gcc from
1022 pessimizing code dealing with EBX.
1023
1024 To avoid clobbering a call-saved register unnecessarily, we renumber
1025 the pic register when possible. The change is visible after the
1026 prologue has been emitted. */
1027
1028#define REAL_PIC_OFFSET_TABLE_REGNUM 3
1029
1030#define PIC_OFFSET_TABLE_REGNUM \
1031 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1032 || !flag_pic ? INVALID_REGNUM \
1033 : reload_completed ? REGNO (pic_offset_table_rtx) \
1034 : REAL_PIC_OFFSET_TABLE_REGNUM)
1035
1036#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1037
1038/* A C expression which can inhibit the returning of certain function
1039 values in registers, based on the type of value. A nonzero value
1040 says to return the function value in memory, just as large
1041 structures are always returned. Here TYPE will be a C expression
1042 of type `tree', representing the data type of the value.
1043
1044 Note that values of mode `BLKmode' must be explicitly handled by
1045 this macro. Also, the option `-fpcc-struct-return' takes effect
1046 regardless of this macro. On most systems, it is possible to
1047 leave the macro undefined; this causes a default definition to be
1048 used, whose value is the constant 1 for `BLKmode' values, and 0
1049 otherwise.
1050
1051 Do not use this macro to indicate that structures and unions
1052 should always be returned in memory. You should instead use
1053 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1054
1055#define RETURN_IN_MEMORY(TYPE) \
1056 ix86_return_in_memory (TYPE)
1057
1058/* This is overridden by <cygwin.h>. */
1059#define MS_AGGREGATE_RETURN 0
1060
1061/* This is overridden by <netware.h>. */
1062#define KEEP_AGGREGATE_RETURN_POINTER 0
1063
1064/* Define the classes of registers for register constraints in the
1065 machine description. Also define ranges of constants.
1066
1067 One of the classes must always be named ALL_REGS and include all hard regs.
1068 If there is more than one class, another class must be named NO_REGS
1069 and contain no registers.
1070
1071 The name GENERAL_REGS must be the name of a class (or an alias for
1072 another name such as ALL_REGS). This is the class of registers
1073 that is allowed by "g" or "r" in a register constraint.
1074 Also, registers outside this class are allocated only when
1075 instructions express preferences for them.
1076
1077 The classes must be numbered in nondecreasing order; that is,
1078 a larger-numbered class must never be contained completely
1079 in a smaller-numbered class.
1080
1081 For any two classes, it is very desirable that there be another
1082 class that represents their union.
1083
1084 It might seem that class BREG is unnecessary, since no useful 386
1085 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1086 and the "b" register constraint is useful in asms for syscalls.
1087
1088 The flags and fpsr registers are in no class. */
1089
1090enum reg_class
1091{
1092 NO_REGS,
1093 AREG, DREG, CREG, BREG, SIREG, DIREG,
1094 AD_REGS, /* %eax/%edx for DImode */
1095 Q_REGS, /* %eax %ebx %ecx %edx */
1096 NON_Q_REGS, /* %esi %edi %ebp %esp */
1097 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1098 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1099 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1100 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1101 FLOAT_REGS,
1102 SSE_REGS,
1103 MMX_REGS,
1104 FP_TOP_SSE_REGS,
1105 FP_SECOND_SSE_REGS,
1106 FLOAT_SSE_REGS,
1107 FLOAT_INT_REGS,
1108 INT_SSE_REGS,
1109 FLOAT_INT_SSE_REGS,
1110 ALL_REGS, LIM_REG_CLASSES
1111};
1112
1113#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1114
1115#define INTEGER_CLASS_P(CLASS) \
1116 reg_class_subset_p ((CLASS), GENERAL_REGS)
1117#define FLOAT_CLASS_P(CLASS) \
1118 reg_class_subset_p ((CLASS), FLOAT_REGS)
1119#define SSE_CLASS_P(CLASS) \
1120 ((CLASS) == SSE_REGS)
1121#define MMX_CLASS_P(CLASS) \
1122 ((CLASS) == MMX_REGS)
1123#define MAYBE_INTEGER_CLASS_P(CLASS) \
1124 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1125#define MAYBE_FLOAT_CLASS_P(CLASS) \
1126 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1127#define MAYBE_SSE_CLASS_P(CLASS) \
1128 reg_classes_intersect_p (SSE_REGS, (CLASS))
1129#define MAYBE_MMX_CLASS_P(CLASS) \
1130 reg_classes_intersect_p (MMX_REGS, (CLASS))
1131
1132#define Q_CLASS_P(CLASS) \
1133 reg_class_subset_p ((CLASS), Q_REGS)
1134
1135/* Give names of register classes as strings for dump file. */
1136
1137#define REG_CLASS_NAMES \
1138{ "NO_REGS", \
1139 "AREG", "DREG", "CREG", "BREG", \
1140 "SIREG", "DIREG", \
1141 "AD_REGS", \
1142 "Q_REGS", "NON_Q_REGS", \
1143 "INDEX_REGS", \
1144 "LEGACY_REGS", \
1145 "GENERAL_REGS", \
1146 "FP_TOP_REG", "FP_SECOND_REG", \
1147 "FLOAT_REGS", \
1148 "SSE_REGS", \
1149 "MMX_REGS", \
1150 "FP_TOP_SSE_REGS", \
1151 "FP_SECOND_SSE_REGS", \
1152 "FLOAT_SSE_REGS", \
1153 "FLOAT_INT_REGS", \
1154 "INT_SSE_REGS", \
1155 "FLOAT_INT_SSE_REGS", \
1156 "ALL_REGS" }
1157
1158/* Define which registers fit in which classes.
1159 This is an initializer for a vector of HARD_REG_SET
1160 of length N_REG_CLASSES. */
1161
1162#define REG_CLASS_CONTENTS \
1163{ { 0x00, 0x0 }, \
1164 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1165 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1166 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1167 { 0x03, 0x0 }, /* AD_REGS */ \
1168 { 0x0f, 0x0 }, /* Q_REGS */ \
1169 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1170 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1171 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1172 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1173 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1174 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1175{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1176{ 0xe0000000, 0x1f }, /* MMX_REGS */ \
1177{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1178{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1179{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1180 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1181{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1182{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1183{ 0xffffffff,0x1fffff } \
1184}
1185
1186/* The same information, inverted:
1187 Return the class number of the smallest class containing
1188 reg number REGNO. This could be a conditional expression
1189 or could index an array. */
1190
1191#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1192
1193/* When defined, the compiler allows registers explicitly used in the
1194 rtl to be used as spill registers but prevents the compiler from
1195 extending the lifetime of these registers. */
1196
1197#define SMALL_REGISTER_CLASSES 1
1198
1199#define QI_REG_P(X) \
1200 (REG_P (X) && REGNO (X) < 4)
1201
1202#define GENERAL_REGNO_P(N) \
1203 ((N) < 8 || REX_INT_REGNO_P (N))
1204
1205#define GENERAL_REG_P(X) \
1206 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1207
1208#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1209
1210#define NON_QI_REG_P(X) \
1211 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1212
1213#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1214#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1215
1216#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1217#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1218#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1219#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1220
1221#define SSE_REGNO_P(N) \
1222 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1223 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1224
1225#define REX_SSE_REGNO_P(N) \
1226 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)
1227
1228#define SSE_REGNO(N) \
1229 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1230#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1231
1232#define SSE_FLOAT_MODE_P(MODE) \
1233 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1234
1235#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1236#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1237
1238#define STACK_REG_P(XOP) \
1239 (REG_P (XOP) && \
1240 REGNO (XOP) >= FIRST_STACK_REG && \
1241 REGNO (XOP) <= LAST_STACK_REG)
1242
1243#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1244
1245#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1246
1247#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1248#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1249
1250/* The class value for index registers, and the one for base regs. */
1251
1252#define INDEX_REG_CLASS INDEX_REGS
1253#define BASE_REG_CLASS GENERAL_REGS
1254
1255/* Place additional restrictions on the register class to use when it
1256 is necessary to be able to hold a value of mode MODE in a reload
1257 register for which class CLASS would ordinarily be used. */
1258
1259#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1260 ((MODE) == QImode && !TARGET_64BIT \
1261 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1262 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1263 ? Q_REGS : (CLASS))
1264
1265/* Given an rtx X being reloaded into a reg required to be
1266 in class CLASS, return the class of reg to actually use.
1267 In general this is just CLASS; but on some machines
1268 in some cases it is preferable to use a more restrictive class.
1269 On the 80386 series, we prevent floating constants from being
1270 reloaded into floating registers (since no move-insn can do that)
1271 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1272
1273/* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1274 QImode must go into class Q_REGS.
1275 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1276 movdf to do mem-to-mem moves through integer regs. */
1277
1278#define PREFERRED_RELOAD_CLASS(X, CLASS) \
1279 ix86_preferred_reload_class ((X), (CLASS))
1280
1281/* Discourage putting floating-point values in SSE registers unless
1282 SSE math is being used, and likewise for the 387 registers. */
1283
1284#define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1285 ix86_preferred_output_reload_class ((X), (CLASS))
1286
1287/* If we are copying between general and FP registers, we need a memory
1288 location. The same is true for SSE and MMX registers. */
1289#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1290 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1291
1292/* QImode spills from non-QI registers need a scratch. This does not
1293 happen often -- the only example so far requires an uninitialized
1294 pseudo. */
1295
1296#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1297 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1298 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1299 ? Q_REGS : NO_REGS)
1300
1301/* Return the maximum number of consecutive registers
1302 needed to represent mode MODE in a register of class CLASS. */
1303/* On the 80386, this is the size of MODE in words,
1304 except in the FP regs, where a single reg is always enough. */
1305#define CLASS_MAX_NREGS(CLASS, MODE) \
1306 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1307 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1308 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1309 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1310
1311/* A C expression whose value is nonzero if pseudos that have been
1312 assigned to registers of class CLASS would likely be spilled
1313 because registers of CLASS are needed for spill registers.
1314
1315 The default value of this macro returns 1 if CLASS has exactly one
1316 register and zero otherwise. On most machines, this default
1317 should be used. Only define this macro to some other expression
1318 if pseudo allocated by `local-alloc.c' end up in memory because
1319 their hard registers were needed for spill registers. If this
1320 macro returns nonzero for those classes, those pseudos will only
1321 be allocated by `global.c', which knows how to reallocate the
1322 pseudo to another register. If there would not be another
1323 register available for reallocation, you should not change the
1324 definition of this macro since the only effect of such a
1325 definition would be to slow down register allocation. */
1326
1327#define CLASS_LIKELY_SPILLED_P(CLASS) \
1328 (((CLASS) == AREG) \
1329 || ((CLASS) == DREG) \
1330 || ((CLASS) == CREG) \
1331 || ((CLASS) == BREG) \
1332 || ((CLASS) == AD_REGS) \
1333 || ((CLASS) == SIREG) \
1334 || ((CLASS) == DIREG) \
1335 || ((CLASS) == FP_TOP_REG) \
1336 || ((CLASS) == FP_SECOND_REG))
1337
1338/* Return a class of registers that cannot change FROM mode to TO mode. */
1339
1340#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1341 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1342
1343/* Stack layout; function entry, exit and calling. */
1344
1345/* Define this if pushing a word on the stack
1346 makes the stack pointer a smaller address. */
1347#define STACK_GROWS_DOWNWARD
1348
1349/* Define this to nonzero if the nominal address of the stack frame
1350 is at the high-address end of the local variables;
1351 that is, each additional local variable allocated
1352 goes at a more negative offset in the frame. */
1353#define FRAME_GROWS_DOWNWARD 1
1354
1355/* Offset within stack frame to start allocating local variables at.
1356 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1357 first local allocated. Otherwise, it is the offset to the BEGINNING
1358 of the first local allocated. */
1359#define STARTING_FRAME_OFFSET 0
1360
1361/* If we generate an insn to push BYTES bytes,
1362 this says how many the stack pointer really advances by.
1363 On 386, we have pushw instruction that decrements by exactly 2 no
1364 matter what the position was, there is no pushb.
1365 But as CIE data alignment factor on this arch is -4, we need to make
1366 sure all stack pointer adjustments are in multiple of 4.
1367
1368 For 64bit ABI we round up to 8 bytes.
1369 */
1370
1371#define PUSH_ROUNDING(BYTES) \
1372 (TARGET_64BIT \
1373 ? (((BYTES) + 7) & (-8)) \
1374 : (((BYTES) + 3) & (-4)))
1375
1376/* If defined, the maximum amount of space required for outgoing arguments will
1377 be computed and placed into the variable
1378 `current_function_outgoing_args_size'. No space will be pushed onto the
1379 stack for each call; instead, the function prologue should increase the stack
1380 frame size by this amount. */
1381
1382#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1383
1384/* If defined, a C expression whose value is nonzero when we want to use PUSH
1385 instructions to pass outgoing arguments. */
1386
1387#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1388
1389/* We want the stack and args grow in opposite directions, even if
1390 PUSH_ARGS is 0. */
1391#define PUSH_ARGS_REVERSED 1
1392
1393/* Offset of first parameter from the argument pointer register value. */
1394#define FIRST_PARM_OFFSET(FNDECL) 0
1395
1396/* Define this macro if functions should assume that stack space has been
1397 allocated for arguments even when their values are passed in registers.
1398
1399 The value of this macro is the size, in bytes, of the area reserved for
1400 arguments passed in registers for the function represented by FNDECL.
1401
1402 This space can be allocated by the caller, or be a part of the
1403 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1404 which. */
1405#define REG_PARM_STACK_SPACE(FNDECL) 0
1406
1407/* Value is the number of bytes of arguments automatically
1408 popped when returning from a subroutine call.
1409 FUNDECL is the declaration node of the function (as a tree),
1410 FUNTYPE is the data type of the function (as a tree),
1411 or for a library call it is an identifier node for the subroutine name.
1412 SIZE is the number of bytes of arguments passed on the stack.
1413
1414 On the 80386, the RTD insn may be used to pop them if the number
1415 of args is fixed, but if the number is variable then the caller
1416 must pop them all. RTD can't be used for library calls now
1417 because the library is compiled with the Unix compiler.
1418 Use of RTD is a selectable option, since it is incompatible with
1419 standard Unix calling sequences. If the option is not selected,
1420 the caller must always pop the args.
1421
1422 The attribute stdcall is equivalent to RTD on a per module basis. */
1423
1424#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1425 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1426
1427#define FUNCTION_VALUE_REGNO_P(N) \
1428 ix86_function_value_regno_p (N)
1429
1430/* Define how to find the value returned by a library function
1431 assuming the value has mode MODE. */
1432
1433#define LIBCALL_VALUE(MODE) \
1434 ix86_libcall_value (MODE)
1435
1436/* Define the size of the result block used for communication between
1437 untyped_call and untyped_return. The block contains a DImode value
1438 followed by the block used by fnsave and frstor. */
1439
1440#define APPLY_RESULT_SIZE (8+108)
1441
1442/* 1 if N is a possible register number for function argument passing. */
1443#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1444
1445/* Define a data type for recording info about an argument list
1446 during the scan of that argument list. This data type should
1447 hold all necessary information about the function itself
1448 and about the args processed so far, enough to enable macros
1449 such as FUNCTION_ARG to determine where the next arg should go. */
1450
1451typedef struct ix86_args {
1452 int words; /* # words passed so far */
1453 int nregs; /* # registers available for passing */
1454 int regno; /* next available register number */
1455 int fastcall; /* fastcall calling convention is used */
1456 int sse_words; /* # sse words passed so far */
1457 int sse_nregs; /* # sse registers available for passing */
1458 int warn_sse; /* True when we want to warn about SSE ABI. */
1459 int warn_mmx; /* True when we want to warn about MMX ABI. */
1460 int sse_regno; /* next available sse register number */
1461 int mmx_words; /* # mmx words passed so far */
1462 int mmx_nregs; /* # mmx registers available for passing */
1463 int mmx_regno; /* next available mmx register number */
1464 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1465 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1466 be passed in SSE registers. Otherwise 0. */
1467} CUMULATIVE_ARGS;
1468
1469/* Initialize a variable CUM of type CUMULATIVE_ARGS
1470 for a call to a function whose data type is FNTYPE.
1471 For a library call, FNTYPE is 0. */
1472
1473#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1474 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1475
1476/* Update the data in CUM to advance over an argument
1477 of mode MODE and data type TYPE.
1478 (TYPE is null for libcalls where that information may not be available.) */
1479
1480#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1481 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1482
1483/* Define where to put the arguments to a function.
1484 Value is zero to push the argument on the stack,
1485 or a hard register in which to store the argument.
1486
1487 MODE is the argument's machine mode.
1488 TYPE is the data type of the argument (as a tree).
1489 This is null for libcalls where that information may
1490 not be available.
1491 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1492 the preceding args and about the function being called.
1493 NAMED is nonzero if this argument is a named parameter
1494 (otherwise it is an extra parameter matching an ellipsis). */
1495
1496#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1497 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1498
1499/* Implement `va_start' for varargs and stdarg. */
1500#define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1501 ix86_va_start (VALIST, NEXTARG)
1502
1503#define TARGET_ASM_FILE_END ix86_file_end
1504#define NEED_INDICATE_EXEC_STACK 0
1505
1506/* Output assembler code to FILE to increment profiler label # LABELNO
1507 for profiling a function entry. */
1508
1509#define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1510
1511#define MCOUNT_NAME "_mcount"
1512
1513#define PROFILE_COUNT_REGISTER "edx"
1514
1515/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1516 the stack pointer does not matter. The value is tested only in
1517 functions that have frame pointers.
1518 No definition is equivalent to always zero. */
1519/* Note on the 386 it might be more efficient not to define this since
1520 we have to restore it ourselves from the frame pointer, in order to
1521 use pop */
1522
1523#define EXIT_IGNORE_STACK 1
1524
1525/* Output assembler code for a block containing the constant parts
1526 of a trampoline, leaving space for the variable parts. */
1527
1528/* On the 386, the trampoline contains two instructions:
1529 mov #STATIC,ecx
1530 jmp FUNCTION
1531 The trampoline is generated entirely at runtime. The operand of JMP
1532 is the address of FUNCTION relative to the instruction following the
1533 JMP (which is 5 bytes long). */
1534
1535/* Length in units of the trampoline for entering a nested function. */
1536
1537#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1538
1539/* Emit RTL insns to initialize the variable parts of a trampoline.
1540 FNADDR is an RTX for the address of the function's pure code.
1541 CXT is an RTX for the static chain value for the function. */
1542
1543#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1544 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1545
1546/* Definitions for register eliminations.
1547
1548 This is an array of structures. Each structure initializes one pair
1549 of eliminable registers. The "from" register number is given first,
1550 followed by "to". Eliminations of the same "from" register are listed
1551 in order of preference.
1552
1553 There are two registers that can always be eliminated on the i386.
1554 The frame pointer and the arg pointer can be replaced by either the
1555 hard frame pointer or to the stack pointer, depending upon the
1556 circumstances. The hard frame pointer is not used before reload and
1557 so it is not eligible for elimination. */
1558
1559#define ELIMINABLE_REGS \
1560{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1561 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1562 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1563 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1564
1565/* Given FROM and TO register numbers, say whether this elimination is
1566 allowed. Frame pointer elimination is automatically handled.
1567
1568 All other eliminations are valid. */
1569
1570#define CAN_ELIMINATE(FROM, TO) \
1571 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1572
1573/* Define the offset between two registers, one to be eliminated, and the other
1574 its replacement, at the start of a routine. */
1575
1576#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1577 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1578
1579/* Addressing modes, and classification of registers for them. */
1580
1581/* Macros to check register numbers against specific register classes. */
1582
1583/* These assume that REGNO is a hard or pseudo reg number.
1584 They give nonzero only if REGNO is a hard reg of the suitable class
1585 or a pseudo reg currently allocated to a suitable hard reg.
1586 Since they use reg_renumber, they are safe only once reg_renumber
1587 has been allocated, which happens in local-alloc.c. */
1588
1589#define REGNO_OK_FOR_INDEX_P(REGNO) \
1590 ((REGNO) < STACK_POINTER_REGNUM \
1591 || (REGNO >= FIRST_REX_INT_REG \
1592 && (REGNO) <= LAST_REX_INT_REG) \
1593 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1594 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1595 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1596
1597#define REGNO_OK_FOR_BASE_P(REGNO) \
1598 ((REGNO) <= STACK_POINTER_REGNUM \
1599 || (REGNO) == ARG_POINTER_REGNUM \
1600 || (REGNO) == FRAME_POINTER_REGNUM \
1601 || (REGNO >= FIRST_REX_INT_REG \
1602 && (REGNO) <= LAST_REX_INT_REG) \
1603 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1604 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1605 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1606
1607#define REGNO_OK_FOR_SIREG_P(REGNO) \
1608 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1609#define REGNO_OK_FOR_DIREG_P(REGNO) \
1610 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1611
1612/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1613 and check its validity for a certain class.
1614 We have two alternate definitions for each of them.
1615 The usual definition accepts all pseudo regs; the other rejects
1616 them unless they have been allocated suitable hard regs.
1617 The symbol REG_OK_STRICT causes the latter definition to be used.
1618
1619 Most source files want to accept pseudo regs in the hope that
1620 they will get allocated to the class that the insn wants them to be in.
1621 Source files for reload pass need to be strict.
1622 After reload, it makes no difference, since pseudo regs have
1623 been eliminated by then. */
1624
1625
1626/* Non strict versions, pseudos are ok. */
1627#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1628 (REGNO (X) < STACK_POINTER_REGNUM \
1629 || (REGNO (X) >= FIRST_REX_INT_REG \
1630 && REGNO (X) <= LAST_REX_INT_REG) \
1631 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1632
1633#define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1634 (REGNO (X) <= STACK_POINTER_REGNUM \
1635 || REGNO (X) == ARG_POINTER_REGNUM \
1636 || REGNO (X) == FRAME_POINTER_REGNUM \
1637 || (REGNO (X) >= FIRST_REX_INT_REG \
1638 && REGNO (X) <= LAST_REX_INT_REG) \
1639 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1640
1641/* Strict versions, hard registers only */
1642#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1643#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1644
1645#ifndef REG_OK_STRICT
1646#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1647#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1648
1649#else
1650#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1651#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1652#endif
1653
1654/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1655 that is a valid memory address for an instruction.
1656 The MODE argument is the machine mode for the MEM expression
1657 that wants to use this address.
1658
1659 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1660 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1661
1662 See legitimize_pic_address in i386.c for details as to what
1663 constitutes a legitimate address when -fpic is used. */
1664
1665#define MAX_REGS_PER_ADDRESS 2
1666
1667#define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1668
1669/* Nonzero if the constant value X is a legitimate general operand.
1670 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1671
1672#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1673
1674#ifdef REG_OK_STRICT
1675#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1676do { \
1677 if (legitimate_address_p ((MODE), (X), 1)) \
1678 goto ADDR; \
1679} while (0)
1680
1681#else
1682#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1683do { \
1684 if (legitimate_address_p ((MODE), (X), 0)) \
1685 goto ADDR; \
1686} while (0)
1687
1688#endif
1689
1690/* If defined, a C expression to determine the base term of address X.
1691 This macro is used in only one place: `find_base_term' in alias.c.
1692
1693 It is always safe for this macro to not be defined. It exists so
1694 that alias analysis can understand machine-dependent addresses.
1695
1696 The typical use of this macro is to handle addresses containing
1697 a label_ref or symbol_ref within an UNSPEC. */
1698
1699#define FIND_BASE_TERM(X) ix86_find_base_term (X)
1700
1701/* Try machine-dependent ways of modifying an illegitimate address
1702 to be legitimate. If we find one, return the new, valid address.
1703 This macro is used in only one place: `memory_address' in explow.c.
1704
1705 OLDX is the address as it was before break_out_memory_refs was called.
1706 In some cases it is useful to look at this to decide what needs to be done.
1707
1708 MODE and WIN are passed so that this macro can use
1709 GO_IF_LEGITIMATE_ADDRESS.
1710
1711 It is always safe for this macro to do nothing. It exists to recognize
1712 opportunities to optimize the output.
1713
1714 For the 80386, we handle X+REG by loading X into a register R and
1715 using R+REG. R will go in a general reg and indexing will be used.
1716 However, if REG is a broken-out memory address or multiplication,
1717 nothing needs to be done because REG can certainly go in a general reg.
1718
1719 When -fpic is used, special handling is needed for symbolic references.
1720 See comments by legitimize_pic_address in i386.c for details. */
1721
1722#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1723do { \
1724 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1725 if (memory_address_p ((MODE), (X))) \
1726 goto WIN; \
1727} while (0)
1728
1729#define REWRITE_ADDRESS(X) rewrite_address (X)
1730
1731/* Nonzero if the constant value X is a legitimate general operand
1732 when generating PIC code. It is given that flag_pic is on and
1733 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1734
1735#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1736
1737#define SYMBOLIC_CONST(X) \
1738 (GET_CODE (X) == SYMBOL_REF \
1739 || GET_CODE (X) == LABEL_REF \
1740 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1741
1742/* Go to LABEL if ADDR (a legitimate address expression)
1743 has an effect that depends on the machine mode it is used for.
1744 On the 80386, only postdecrement and postincrement address depend thus
1745 (the amount of decrement or increment being the length of the operand). */
1746#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1747do { \
1748 if (GET_CODE (ADDR) == POST_INC \
1749 || GET_CODE (ADDR) == POST_DEC) \
1750 goto LABEL; \
1751} while (0)
1752
1753/* Max number of args passed in registers. If this is more than 3, we will
1754 have problems with ebx (register #4), since it is a caller save register and
1755 is also used as the pic register in ELF. So for now, don't allow more than
1756 3 registers to be passed in registers. */
1757
1758#define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
1759
1760#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0))
1761
1762#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1763
1764
1765/* Specify the machine mode that this machine uses
1766 for the index in the tablejump instruction. */
1767#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
1768
1769/* Define this as 1 if `char' should by default be signed; else as 0. */
1770#define DEFAULT_SIGNED_CHAR 1
1771
1772/* Number of bytes moved into a data cache for a single prefetch operation. */
1773#define PREFETCH_BLOCK ix86_cost->prefetch_block
1774
1775/* Number of prefetch operations that can be done in parallel. */
1776#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
1777
1778/* Max number of bytes we can move from memory to memory
1779 in one reasonably fast instruction. */
1780#define MOVE_MAX 16
1781
1782/* MOVE_MAX_PIECES is the number of bytes at a time which we can
1783 move efficiently, as opposed to MOVE_MAX which is the maximum
1784 number of bytes we can move with a single instruction. */
1785#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1786
1787/* If a memory-to-memory move would take MOVE_RATIO or more simple
1788 move-instruction pairs, we will do a movmem or libcall instead.
1789 Increasing the value will always make code faster, but eventually
1790 incurs high cost in increased code size.
1791
1792 If you don't define this, a reasonable default is used. */
1793
1794#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
1795
1796/* If a clear memory operation would take CLEAR_RATIO or more simple
1797 move-instruction sequences, we will do a clrmem or libcall instead. */
1798
1799#define CLEAR_RATIO (optimize_size ? 2 \
1800 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio)
1801
1802/* Define if shifts truncate the shift count
1803 which implies one can omit a sign-extension or zero-extension
1804 of a shift count. */
1805/* On i386, shifts do truncate the count. But bit opcodes don't. */
1806
1807/* #define SHIFT_COUNT_TRUNCATED */
1808
1809/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1810 is done just by pretending it is already truncated. */
1811#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1812
1813/* A macro to update M and UNSIGNEDP when an object whose type is
1814 TYPE and which has the specified mode and signedness is to be
1815 stored in a register. This macro is only called when TYPE is a
1816 scalar type.
1817
1818 On i386 it is sometimes useful to promote HImode and QImode
1819 quantities to SImode. The choice depends on target type. */
1820
1821#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1822do { \
1823 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1824 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1825 (MODE) = SImode; \
1826} while (0)
1827
1828/* Specify the machine mode that pointers have.
1829 After generation of rtl, the compiler makes no further distinction
1830 between pointers and any other objects of this machine mode. */
1831#define Pmode (TARGET_64BIT ? DImode : SImode)
1832
1833/* A function address in a call instruction
1834 is a byte address (for indexing purposes)
1835 so give the MEM rtx a byte's mode. */
1836#define FUNCTION_MODE QImode
1837
1838/* A C expression for the cost of moving data from a register in class FROM to
1839 one in class TO. The classes are expressed using the enumeration values
1840 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1841 interpreted relative to that.
1842
1843 It is not required that the cost always equal 2 when FROM is the same as TO;
1844 on some machines it is expensive to move between registers if they are not
1845 general registers. */
1846
1847#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1848 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
1849
1850/* A C expression for the cost of moving data of mode M between a
1851 register and memory. A value of 2 is the default; this cost is
1852 relative to those in `REGISTER_MOVE_COST'.
1853
1854 If moving between registers and memory is more expensive than
1855 between two registers, you should define this macro to express the
1856 relative cost. */
1857
1858#define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1859 ix86_memory_move_cost ((MODE), (CLASS), (IN))
1860
1861/* A C expression for the cost of a branch instruction. A value of 1
1862 is the default; other values are interpreted relative to that. */
1863
1864#define BRANCH_COST ix86_branch_cost
1865
1866/* Define this macro as a C expression which is nonzero if accessing
1867 less than a word of memory (i.e. a `char' or a `short') is no
1868 faster than accessing a word of memory, i.e., if such access
1869 require more than one instruction or if there is no difference in
1870 cost between byte and (aligned) word loads.
1871
1872 When this macro is not defined, the compiler will access a field by
1873 finding the smallest containing object; when it is defined, a
1874 fullword load will be used if alignment permits. Unless bytes
1875 accesses are faster than word accesses, using word accesses is
1876 preferable since it may eliminate subsequent memory access if
1877 subsequent accesses occur to other fields in the same word of the
1878 structure, but to different bytes. */
1879
1880#define SLOW_BYTE_ACCESS 0
1881
1882/* Nonzero if access to memory by shorts is slow and undesirable. */
1883#define SLOW_SHORT_ACCESS 0
1884
1885/* Define this macro to be the value 1 if unaligned accesses have a
1886 cost many times greater than aligned accesses, for example if they
1887 are emulated in a trap handler.
1888
1889 When this macro is nonzero, the compiler will act as if
1890 `STRICT_ALIGNMENT' were nonzero when generating code for block
1891 moves. This can cause significantly more instructions to be
1892 produced. Therefore, do not set this macro nonzero if unaligned
1893 accesses only add a cycle or two to the time for a memory access.
1894
1895 If the value of this macro is always zero, it need not be defined. */
1896
1897/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1898
1899/* Define this macro if it is as good or better to call a constant
1900 function address than to call an address kept in a register.
1901
1902 Desirable on the 386 because a CALL with a constant address is
1903 faster than one with a register address. */
1904
1905#define NO_FUNCTION_CSE
1906
1907/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1908 return the mode to be used for the comparison.
1909
1910 For floating-point equality comparisons, CCFPEQmode should be used.
1911 VOIDmode should be used in all other cases.
1912
1913 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1914 possible, to allow for more combinations. */
1915
1916#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1917
1918/* Return nonzero if MODE implies a floating point inequality can be
1919 reversed. */
1920
1921#define REVERSIBLE_CC_MODE(MODE) 1
1922
1923/* A C expression whose value is reversed condition code of the CODE for
1924 comparison done in CC_MODE mode. */
1925#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1926
1927
1928/* Control the assembler format that we output, to the extent
1929 this does not vary between assemblers. */
1930
1931/* How to refer to registers in assembler output.
1932 This sequence is indexed by compiler's hard-register-number (see above). */
1933
1934/* In order to refer to the first 8 regs as 32 bit regs, prefix an "e".
1935 For non floating point regs, the following are the HImode names.
1936
1937 For float regs, the stack top is sometimes referred to as "%st(0)"
1938 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
1939
1940#define HI_REGISTER_NAMES \
1941{"ax","dx","cx","bx","si","di","bp","sp", \
1942 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
1943 "argp", "flags", "fpsr", "dirflag", "frame", \
1944 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
1945 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
1946 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1947 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
1948
1949#define REGISTER_NAMES HI_REGISTER_NAMES
1950
1951/* Table of additional register names to use in user input. */
1952
1953#define ADDITIONAL_REGISTER_NAMES \
1954{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
1955 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
1956 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
1957 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
1958 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
1959 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
1960
1961/* Note we are omitting these since currently I don't know how
1962to get gcc to use these, since they want the same but different
1963number as al, and ax.
1964*/
1965
1966#define QI_REGISTER_NAMES \
1967{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
1968
1969/* These parallel the array above, and can be used to access bits 8:15
1970 of regs 0 through 3. */
1971
1972#define QI_HIGH_REGISTER_NAMES \
1973{"ah", "dh", "ch", "bh", }
1974
1975/* How to renumber registers for dbx and gdb. */
1976
1977#define DBX_REGISTER_NUMBER(N) \
1978 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
1979
1980extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
1981extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
1982extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
1983
1984/* Before the prologue, RA is at 0(%esp). */
1985#define INCOMING_RETURN_ADDR_RTX \
1986 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1987
1988/* After the prologue, RA is at -4(AP) in the current frame. */
1989#define RETURN_ADDR_RTX(COUNT, FRAME) \
1990 ((COUNT) == 0 \
1991 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
1992 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
1993
1994/* PC is dbx register 8; let's use that column for RA. */
1995#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
1996
1997/* Before the prologue, the top of the frame is at 4(%esp). */
1998#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
1999
2000/* Describe how we implement __builtin_eh_return. */
2001#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2002#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2003
2004
2005/* Select a format to encode pointers in exception handling data. CODE
2006 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2007 true if the symbol may be affected by dynamic relocations.
2008
2009 ??? All x86 object file formats are capable of representing this.
2010 After all, the relocation needed is the same as for the call insn.
2011 Whether or not a particular assembler allows us to enter such, I
2012 guess we'll have to see. */
2013#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2014 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2015
2016/* This is how to output an insn to push a register on the stack.
2017 It need not be very fast code. */
2018
2019#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2020do { \
2021 if (TARGET_64BIT) \
2022 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2023 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2024 else \
2025 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2026} while (0)
2027
2028/* This is how to output an insn to pop a register from the stack.
2029 It need not be very fast code. */
2030
2031#define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2032do { \
2033 if (TARGET_64BIT) \
2034 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2035 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2036 else \
2037 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2038} while (0)
2039
2040/* This is how to output an element of a case-vector that is absolute. */
2041
2042#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2043 ix86_output_addr_vec_elt ((FILE), (VALUE))
2044
2045/* This is how to output an element of a case-vector that is relative. */
2046
2047#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2048 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2049
2050/* Under some conditions we need jump tables in the text section,
2051 because the assembler cannot handle label differences between
2052 sections. This is the case for x86_64 on Mach-O for example. */
2053
2054#define JUMP_TABLES_IN_TEXT_SECTION \
2055 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2056 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2057
2058/* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2059 and switch back. For x86 we do this only to save a few bytes that
2060 would otherwise be unused in the text section. */
2061#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2062 asm (SECTION_OP "\n\t" \
2063 "call " USER_LABEL_PREFIX #FUNC "\n" \
2064 TEXT_SECTION_ASM_OP);
2065
2066/* Print operand X (an rtx) in assembler syntax to file FILE.
2067 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2068 Effect of various CODE letters is described in i386.c near
2069 print_operand function. */
2070
2071#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2072 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
2073
2074#define PRINT_OPERAND(FILE, X, CODE) \
2075 print_operand ((FILE), (X), (CODE))
2076
2077#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2078 print_operand_address ((FILE), (ADDR))
2079
2080#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2081do { \
2082 if (! output_addr_const_extra (FILE, (X))) \
2083 goto FAIL; \
2084} while (0);
2085
2086/* a letter which is not needed by the normal asm syntax, which
2087 we can use for operand syntax in the extended asm */
2088
2089#define ASM_OPERAND_LETTER '#'
2090#define RET return ""
2091#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
2092
2093/* Which processor to schedule for. The cpu attribute defines a list that
2094 mirrors this list, so changes to i386.md must be made at the same time. */
2095
2096enum processor_type
2097{
2098 PROCESSOR_I386, /* 80386 */
2099 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2100 PROCESSOR_PENTIUM,
2101 PROCESSOR_PENTIUMPRO,
2102 PROCESSOR_GEODE,
2103 PROCESSOR_K6,
2104 PROCESSOR_ATHLON,
2105 PROCESSOR_PENTIUM4,
2106 PROCESSOR_K8,
2107 PROCESSOR_NOCONA,
2108 PROCESSOR_CORE2,
2109 PROCESSOR_GENERIC32,
2110 PROCESSOR_GENERIC64,
2111 PROCESSOR_max
2112};
2113
2114extern enum processor_type ix86_tune;
2115extern enum processor_type ix86_arch;
2116
2117enum fpmath_unit
2118{
2119 FPMATH_387 = 1,
2120 FPMATH_SSE = 2
2121};
2122
2123extern enum fpmath_unit ix86_fpmath;
2124
2125enum tls_dialect
2126{
2127 TLS_DIALECT_GNU,
2128 TLS_DIALECT_GNU2,
2129 TLS_DIALECT_SUN
2130};
2131
2132extern enum tls_dialect ix86_tls_dialect;
2133
2134enum cmodel {
2135 CM_32, /* The traditional 32-bit ABI. */
2136 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2137 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2138 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2139 CM_LARGE, /* No assumptions. */
2140 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2141 CM_MEDIUM_PIC /* Assumes code+got/plt fits in a 31 bit region. */
2142};
2143
2144extern enum cmodel ix86_cmodel;
2145
2146/* Size of the RED_ZONE area. */
2147#define RED_ZONE_SIZE 128
2148/* Reserved area of the red zone for temporaries. */
2149#define RED_ZONE_RESERVE 8
2150
2151enum asm_dialect {
2152 ASM_ATT,
2153 ASM_INTEL
2154};
2155
2156extern enum asm_dialect ix86_asm_dialect;
2157extern unsigned int ix86_preferred_stack_boundary;
2158extern int ix86_branch_cost, ix86_section_threshold;
2159
2160/* Smallest class containing REGNO. */
2161extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2162
2163extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2164extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2165extern rtx ix86_compare_emitted;
2166
2167/* To properly truncate FP values into integers, we need to set i387 control
2168 word. We can't emit proper mode switching code before reload, as spills
2169 generated by reload may truncate values incorrectly, but we still can avoid
2170 redundant computation of new control word by the mode switching pass.
2171 The fldcw instructions are still emitted redundantly, but this is probably
2172 not going to be noticeable problem, as most CPUs do have fast path for
2173 the sequence.
2174
2175 The machinery is to emit simple truncation instructions and split them
2176 before reload to instructions having USEs of two memory locations that
2177 are filled by this code to old and new control word.
2178
2179 Post-reload pass may be later used to eliminate the redundant fildcw if
2180 needed. */
2181
2182enum ix86_entity
2183{
2184 I387_TRUNC = 0,
2185 I387_FLOOR,
2186 I387_CEIL,
2187 I387_MASK_PM,
2188 MAX_386_ENTITIES
2189};
2190
2191enum ix86_stack_slot
2192{
2193 SLOT_VIRTUAL = 0,
2194 SLOT_TEMP,
2195 SLOT_CW_STORED,
2196 SLOT_CW_TRUNC,
2197 SLOT_CW_FLOOR,
2198 SLOT_CW_CEIL,
2199 SLOT_CW_MASK_PM,
2200 MAX_386_STACK_LOCALS
2201};
2202
2203/* Define this macro if the port needs extra instructions inserted
2204 for mode switching in an optimizing compilation. */
2205
2206#define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2207 ix86_optimize_mode_switching[(ENTITY)]
2208
2209/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2210 initializer for an array of integers. Each initializer element N
2211 refers to an entity that needs mode switching, and specifies the
2212 number of different modes that might need to be set for this
2213 entity. The position of the initializer in the initializer -
2214 starting counting at zero - determines the integer that is used to
2215 refer to the mode-switched entity in question. */
2216
2217#define NUM_MODES_FOR_MODE_SWITCHING \
2218 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2219
2220/* ENTITY is an integer specifying a mode-switched entity. If
2221 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2222 return an integer value not larger than the corresponding element
2223 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2224 must be switched into prior to the execution of INSN. */
2225
2226#define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2227
2228/* This macro specifies the order in which modes for ENTITY are
2229 processed. 0 is the highest priority. */
2230
2231#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2232
2233/* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2234 is the set of hard registers live at the point where the insn(s)
2235 are to be inserted. */
2236
2237#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2238 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2239 ? emit_i387_cw_initialization (MODE), 0 \
2240 : 0)
2241
2242
2243/* Avoid renaming of stack registers, as doing so in combination with
2244 scheduling just increases amount of live registers at time and in
2245 the turn amount of fxch instructions needed.
2246
2247 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2248
2249#define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2250 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
2251
2252
2253#define DLL_IMPORT_EXPORT_PREFIX '#'
2254
2255#define FASTCALL_PREFIX '@'
2256
2257struct machine_function GTY(())
2258{
2259 struct stack_local_entry *stack_locals;
2260 const char *some_ld_name;
2261 rtx force_align_arg_pointer;
2262 int save_varrargs_registers;
2263 int accesses_prev_frame;
2264 int optimize_mode_switching[MAX_386_ENTITIES];
2265 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
2266 determine the style used. */
2267 int use_fast_prologue_epilogue;
2268 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2269 for. */
2270 int use_fast_prologue_epilogue_nregs;
2271 /* If true, the current function needs the default PIC register, not
2272 an alternate register (on x86) and must not use the red zone (on
2273 x86_64), even if it's a leaf function. We don't want the
2274 function to be regarded as non-leaf because TLS calls need not
2275 affect register allocation. This flag is set when a TLS call
2276 instruction is expanded within a function, and never reset, even
2277 if all such instructions are optimized away. Use the
2278 ix86_current_function_calls_tls_descriptor macro for a better
2279 approximation. */
2280 int tls_descriptor_call_expanded_p;
2281};
2282
2283#define ix86_stack_locals (cfun->machine->stack_locals)
2284#define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2285#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2286#define ix86_tls_descriptor_calls_expanded_in_cfun \
2287 (cfun->machine->tls_descriptor_call_expanded_p)
2288/* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2289 calls are optimized away, we try to detect cases in which it was
2290 optimized away. Since such instructions (use (reg REG_SP)), we can
2291 verify whether there's any such instruction live by testing that
2292 REG_SP is live. */
2293#define ix86_current_function_calls_tls_descriptor \
2294 (ix86_tls_descriptor_calls_expanded_in_cfun && regs_ever_live[SP_REG])
2295
2296/* Control behavior of x86_file_start. */
2297#define X86_FILE_START_VERSION_DIRECTIVE false
2298#define X86_FILE_START_FLTUSED false
2299
2300/* Flag to mark data that is in the large address area. */
2301#define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2302#define SYMBOL_REF_FAR_ADDR_P(X) \
2303 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2304/*
2305Local variables:
2306version-control: t
2307End:
2308*/
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