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busdma_machdep.c (203080) busdma_machdep.c (204689)
1/*-
2 * Copyright (c) 2006 Oleksandr Tymoshenko
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * From i386/busdma_machdep.c,v 1.26 2002/04/19 22:58:09 alfred
27 */
28
29#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2006 Oleksandr Tymoshenko
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 13 unchanged lines hidden (view full) ---

22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * From i386/busdma_machdep.c,v 1.26 2002/04/19 22:58:09 alfred
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD: head/sys/mips/mips/busdma_machdep.c 203080 2010-01-27 17:15:17Z kan $");
30__FBSDID("$FreeBSD: head/sys/mips/mips/busdma_machdep.c 204689 2010-03-04 05:23:08Z neel $");
31
32/*
33 * MIPS bus dma support routines
34 */
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/malloc.h>

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50#include <vm/vm.h>
51#include <vm/vm_page.h>
52#include <vm/vm_map.h>
53
54#include <machine/atomic.h>
55#include <machine/bus.h>
56#include <machine/cache.h>
57#include <machine/cpufunc.h>
31
32/*
33 * MIPS bus dma support routines
34 */
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/malloc.h>

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50#include <vm/vm.h>
51#include <vm/vm_page.h>
52#include <vm/vm_map.h>
53
54#include <machine/atomic.h>
55#include <machine/bus.h>
56#include <machine/cache.h>
57#include <machine/cpufunc.h>
58#include <machine/cpuinfo.h>
58#include <machine/md_var.h>
59
60#define MAX_BPAGES 64
61#define BUS_DMA_COULD_BOUNCE BUS_DMA_BUS3
62#define BUS_DMA_MIN_ALLOC_COMP BUS_DMA_BUS4
63
64struct bounce_zone;
65

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119SYSCTL_NODE(_hw, OID_AUTO, busdma, CTLFLAG_RD, 0, "Busdma parameters");
120SYSCTL_INT(_hw_busdma, OID_AUTO, total_bpages, CTLFLAG_RD, &total_bpages, 0,
121 "Total bounce pages");
122
123#define DMAMAP_LINEAR 0x1
124#define DMAMAP_MBUF 0x2
125#define DMAMAP_UIO 0x4
126#define DMAMAP_TYPE_MASK (DMAMAP_LINEAR|DMAMAP_MBUF|DMAMAP_UIO)
59#include <machine/md_var.h>
60
61#define MAX_BPAGES 64
62#define BUS_DMA_COULD_BOUNCE BUS_DMA_BUS3
63#define BUS_DMA_MIN_ALLOC_COMP BUS_DMA_BUS4
64
65struct bounce_zone;
66

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120SYSCTL_NODE(_hw, OID_AUTO, busdma, CTLFLAG_RD, 0, "Busdma parameters");
121SYSCTL_INT(_hw_busdma, OID_AUTO, total_bpages, CTLFLAG_RD, &total_bpages, 0,
122 "Total bounce pages");
123
124#define DMAMAP_LINEAR 0x1
125#define DMAMAP_MBUF 0x2
126#define DMAMAP_UIO 0x4
127#define DMAMAP_TYPE_MASK (DMAMAP_LINEAR|DMAMAP_MBUF|DMAMAP_UIO)
127#define DMAMAP_COHERENT 0x8
128#define DMAMAP_UNCACHEABLE 0x8
128#define DMAMAP_ALLOCATED 0x10
129#define DMAMAP_MALLOCUSED 0x20
130
131struct bus_dmamap {
132 struct bp_list bpages;
133 int pagesneeded;
134 int pagesreserved;
135 bus_dma_tag_t dmat;

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335 newtag->lowaddr = trunc_page((vm_offset_t)lowaddr) + (PAGE_SIZE - 1);
336 newtag->highaddr = trunc_page((vm_offset_t)highaddr) + (PAGE_SIZE - 1);
337 newtag->filter = filter;
338 newtag->filterarg = filterarg;
339 newtag->maxsize = maxsize;
340 newtag->nsegments = nsegments;
341 newtag->maxsegsz = maxsegsz;
342 newtag->flags = flags;
129#define DMAMAP_ALLOCATED 0x10
130#define DMAMAP_MALLOCUSED 0x20
131
132struct bus_dmamap {
133 struct bp_list bpages;
134 int pagesneeded;
135 int pagesreserved;
136 bus_dma_tag_t dmat;

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336 newtag->lowaddr = trunc_page((vm_offset_t)lowaddr) + (PAGE_SIZE - 1);
337 newtag->highaddr = trunc_page((vm_offset_t)highaddr) + (PAGE_SIZE - 1);
338 newtag->filter = filter;
339 newtag->filterarg = filterarg;
340 newtag->maxsize = maxsize;
341 newtag->nsegments = nsegments;
342 newtag->maxsegsz = maxsegsz;
343 newtag->flags = flags;
344 if (cpuinfo.cache_coherent_dma)
345 newtag->flags |= BUS_DMA_COHERENT;
343 newtag->ref_count = 1; /* Count ourself */
344 newtag->map_count = 0;
345 if (lockfunc != NULL) {
346 newtag->lockfunc = lockfunc;
347 newtag->lockfuncarg = lockfuncarg;
348 } else {
349 newtag->lockfunc = dflt_lock;
350 newtag->lockfuncarg = NULL;

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512 dmat->flags |= BUS_DMA_MIN_ALLOC_COMP;
513 } else {
514 error = 0;
515 }
516 }
517 bz->map_count++;
518 }
519
346 newtag->ref_count = 1; /* Count ourself */
347 newtag->map_count = 0;
348 if (lockfunc != NULL) {
349 newtag->lockfunc = lockfunc;
350 newtag->lockfuncarg = lockfuncarg;
351 } else {
352 newtag->lockfunc = dflt_lock;
353 newtag->lockfuncarg = NULL;

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515 dmat->flags |= BUS_DMA_MIN_ALLOC_COMP;
516 } else {
517 error = 0;
518 }
519 }
520 bz->map_count++;
521 }
522
520 if (flags & BUS_DMA_COHERENT)
521 newmap->flags |= DMAMAP_COHERENT;
522
523 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
524 __func__, dmat, dmat->flags, error);
525
526 return (0);
527}
528
529/*
530 * Destroy a handle for mapping from kva/uva/physical

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572 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
573 __func__, dmat, dmat->flags, ENOMEM);
574 return (ENOMEM);
575 }
576 dmat->map_count++;
577 *mapp = newmap;
578 newmap->dmat = dmat;
579
523 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
524 __func__, dmat, dmat->flags, error);
525
526 return (0);
527}
528
529/*
530 * Destroy a handle for mapping from kva/uva/physical

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572 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
573 __func__, dmat, dmat->flags, ENOMEM);
574 return (ENOMEM);
575 }
576 dmat->map_count++;
577 *mapp = newmap;
578 newmap->dmat = dmat;
579
580 /*
581 * If all the memory is coherent with DMA then we don't need to
582 * do anything special for a coherent mapping request.
583 */
584 if (dmat->flags & BUS_DMA_COHERENT)
585 flags &= ~BUS_DMA_COHERENT;
586
587 /*
588 * Allocate uncacheable memory if all else fails.
589 */
580 if (flags & BUS_DMA_COHERENT)
590 if (flags & BUS_DMA_COHERENT)
581 newmap->flags |= DMAMAP_COHERENT;
582
591 newmap->flags |= DMAMAP_UNCACHEABLE;
592
583 if (dmat->maxsize <= PAGE_SIZE &&
584 (dmat->alignment < dmat->maxsize) &&
585 !_bus_dma_can_bounce(dmat->lowaddr, dmat->highaddr) &&
593 if (dmat->maxsize <= PAGE_SIZE &&
594 (dmat->alignment < dmat->maxsize) &&
595 !_bus_dma_can_bounce(dmat->lowaddr, dmat->highaddr) &&
586 !(flags & BUS_DMA_COHERENT)) {
596 !(newmap->flags & DMAMAP_UNCACHEABLE)) {
587 *vaddr = malloc(dmat->maxsize, M_DEVBUF, mflags);
588 newmap->flags |= DMAMAP_MALLOCUSED;
589 } else {
590 /*
591 * XXX Use Contigmalloc until it is merged into this facility
592 * and handles multi-seg allocations. Nobody is doing
593 * multi-seg allocations yet though.
594 */

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614 if (newmap != NULL) {
615 _busdma_free_dmamap(newmap);
616 dmat->map_count--;
617 }
618 *mapp = NULL;
619 return (ENOMEM);
620 }
621
597 *vaddr = malloc(dmat->maxsize, M_DEVBUF, mflags);
598 newmap->flags |= DMAMAP_MALLOCUSED;
599 } else {
600 /*
601 * XXX Use Contigmalloc until it is merged into this facility
602 * and handles multi-seg allocations. Nobody is doing
603 * multi-seg allocations yet though.
604 */

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624 if (newmap != NULL) {
625 _busdma_free_dmamap(newmap);
626 dmat->map_count--;
627 }
628 *mapp = NULL;
629 return (ENOMEM);
630 }
631
622 if (flags & BUS_DMA_COHERENT) {
632 if (newmap->flags & DMAMAP_UNCACHEABLE) {
623 void *tmpaddr = (void *)*vaddr;
624
625 if (tmpaddr) {
626 tmpaddr = (void *)MIPS_PHYS_TO_KSEG1(vtophys(tmpaddr));
627 newmap->origbuffer = *vaddr;
628 newmap->allocbuffer = tmpaddr;
629 mips_dcache_wbinv_range((vm_offset_t)*vaddr,
630 dmat->maxsize);

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1172 struct uio *uio;
1173 int resid;
1174 struct iovec *iov;
1175
1176 if (op == BUS_DMASYNC_POSTWRITE)
1177 return;
1178 if (STAILQ_FIRST(&map->bpages))
1179 _bus_dmamap_sync_bp(dmat, map, op);
633 void *tmpaddr = (void *)*vaddr;
634
635 if (tmpaddr) {
636 tmpaddr = (void *)MIPS_PHYS_TO_KSEG1(vtophys(tmpaddr));
637 newmap->origbuffer = *vaddr;
638 newmap->allocbuffer = tmpaddr;
639 mips_dcache_wbinv_range((vm_offset_t)*vaddr,
640 dmat->maxsize);

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1182 struct uio *uio;
1183 int resid;
1184 struct iovec *iov;
1185
1186 if (op == BUS_DMASYNC_POSTWRITE)
1187 return;
1188 if (STAILQ_FIRST(&map->bpages))
1189 _bus_dmamap_sync_bp(dmat, map, op);
1180 if (map->flags & DMAMAP_COHERENT)
1190
1191 if (dmat->flags & BUS_DMA_COHERENT)
1181 return;
1192 return;
1193
1194 if (map->flags & DMAMAP_UNCACHEABLE)
1195 return;
1196
1182 CTR3(KTR_BUSDMA, "%s: op %x flags %x", __func__, op, map->flags);
1183 switch(map->flags & DMAMAP_TYPE_MASK) {
1184 case DMAMAP_LINEAR:
1185 if (!(_bus_dma_buf_is_in_bp(map, map->buffer, map->len)))
1186 bus_dmamap_sync_buf(map->buffer, map->len, op);
1187 break;
1188 case DMAMAP_MBUF:
1189 m = map->buffer;

--- 280 unchanged lines hidden --- 		1197 CTR3(KTR_BUSDMA, "%s: op %x flags %x", __func__, op, map->flags);
1198 switch(map->flags & DMAMAP_TYPE_MASK) {
1199 case DMAMAP_LINEAR:
1200 if (!(_bus_dma_buf_is_in_bp(map, map->buffer, map->len)))
1201 bus_dmamap_sync_buf(map->buffer, map->len, op);
1202 break;
1203 case DMAMAP_MBUF:
1204 m = map->buffer;

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