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if_run.c (259546) if_run.c (259547)
1/*-
2 * Copyright (c) 2008,2010 Damien Bergamini <damien.bergamini@free.fr>
3 * ported to FreeBSD by Akinori Furukoshi <moonlightakkiy@yahoo.ca>
4 * USB Consulting, Hans Petter Selasky <hselasky@freebsd.org>
5 * Copyright (c) 2013 Kevin Lo
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above

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13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2008,2010 Damien Bergamini <damien.bergamini@free.fr>
3 * ported to FreeBSD by Akinori Furukoshi <moonlightakkiy@yahoo.ca>
4 * USB Consulting, Hans Petter Selasky <hselasky@freebsd.org>
5 * Copyright (c) 2013 Kevin Lo
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above

--- 4 unchanged lines hidden (view full) ---

13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#include <sys/cdefs.h>
21__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_run.c 259546 2013-12-18 08:39:12Z kevlo $");
21__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_run.c 259547 2013-12-18 08:53:40Z kevlo $");
22
23/*-
24 * Ralink Technology RT2700U/RT2800U/RT3000U/RT3900E chipset driver.
25 * http://www.ralinktech.com/
26 */
27
28#include <sys/param.h>
29#include <sys/sockio.h>

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3654 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ,
3655 &val, 1);
3656 } else if (chan <= 165) {
3657 run_efuse_read(sc,
3658 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ,
3659 &val, 1);
3660 } else
3661 val = 0;
22
23/*-
24 * Ralink Technology RT2700U/RT2800U/RT3000U/RT3900E chipset driver.
25 * http://www.ralinktech.com/
26 */
27
28#include <sys/param.h>
29#include <sys/sockio.h>

--- 3624 unchanged lines hidden (view full) ---

3654 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ,
3655 &val, 1);
3656 } else if (chan <= 165) {
3657 run_efuse_read(sc,
3658 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ,
3659 &val, 1);
3660 } else
3661 val = 0;
3662 run_bbp_write(sc, 159, val & 0xff);
3662 run_bbp_write(sc, 159, val);
3663
3664 /* Tx0 IQ phase. */
3665 run_bbp_write(sc, 158, 0x2d);
3666 if (chan <= 14) {
3667 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ,
3668 &val, 1);
3669 } else if (chan <= 64) {
3670 run_efuse_read(sc,

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3675 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ,
3676 &val, 1);
3677 } else if (chan <= 165) {
3678 run_efuse_read(sc,
3679 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ,
3680 &val, 1);
3681 } else
3682 val = 0;
3663
3664 /* Tx0 IQ phase. */
3665 run_bbp_write(sc, 158, 0x2d);
3666 if (chan <= 14) {
3667 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ,
3668 &val, 1);
3669 } else if (chan <= 64) {
3670 run_efuse_read(sc,

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3675 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ,
3676 &val, 1);
3677 } else if (chan <= 165) {
3678 run_efuse_read(sc,
3679 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ,
3680 &val, 1);
3681 } else
3682 val = 0;
3683 run_bbp_write(sc, 159, val & 0xff);
3683 run_bbp_write(sc, 159, val);
3684
3685 /* Tx1 IQ gain. */
3686 run_bbp_write(sc, 158, 0x4a);
3687 if (chan <= 14) {
3688 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ,
3689 &val, 1);
3690 } else if (chan <= 64) {
3691 run_efuse_read(sc,

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3696 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ,
3697 &val, 1);
3698 } else if (chan <= 165) {
3699 run_efuse_read(sc,
3700 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ,
3701 &val, 1);
3702 } else
3703 val = 0;
3684
3685 /* Tx1 IQ gain. */
3686 run_bbp_write(sc, 158, 0x4a);
3687 if (chan <= 14) {
3688 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ,
3689 &val, 1);
3690 } else if (chan <= 64) {
3691 run_efuse_read(sc,

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3696 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ,
3697 &val, 1);
3698 } else if (chan <= 165) {
3699 run_efuse_read(sc,
3700 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ,
3701 &val, 1);
3702 } else
3703 val = 0;
3704 run_bbp_write(sc, 159, val & 0xff);
3704 run_bbp_write(sc, 159, val);
3705
3706 /* Tx1 IQ phase. */
3707 run_bbp_write(sc, 158, 0x4b);
3708 if (chan <= 14) {
3709 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ,
3710 &val, 1);
3711 } else if (chan <= 64) {
3712 run_efuse_read(sc,

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3717 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ,
3718 &val, 1);
3719 } else if (chan <= 165) {
3720 run_efuse_read(sc,
3721 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ,
3722 &val, 1);
3723 } else
3724 val = 0;
3705
3706 /* Tx1 IQ phase. */
3707 run_bbp_write(sc, 158, 0x4b);
3708 if (chan <= 14) {
3709 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ,
3710 &val, 1);
3711 } else if (chan <= 64) {
3712 run_efuse_read(sc,

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3717 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ,
3718 &val, 1);
3719 } else if (chan <= 165) {
3720 run_efuse_read(sc,
3721 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ,
3722 &val, 1);
3723 } else
3724 val = 0;
3725 run_bbp_write(sc, 159, val & 0xff);
3725 run_bbp_write(sc, 159, val);
3726
3727 /* RF IQ compensation control. */
3728 run_bbp_write(sc, 158, 0x04);
3729 run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL,
3730 &val, 1);
3726
3727 /* RF IQ compensation control. */
3728 run_bbp_write(sc, 158, 0x04);
3729 run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL,
3730 &val, 1);
3731 run_bbp_write(sc, 159, val & 0xff);
3731 run_bbp_write(sc, 159, val);
3732
3733 /* RF IQ imbalance compensation control. */
3734 run_bbp_write(sc, 158, 0x03);
3735 run_efuse_read(sc,
3736 RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val, 1);
3732
3733 /* RF IQ imbalance compensation control. */
3734 run_bbp_write(sc, 158, 0x03);
3735 run_efuse_read(sc,
3736 RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val, 1);
3737 run_bbp_write(sc, 159, val & 0xff);
3737 run_bbp_write(sc, 159, val);
3738}
3739
3740static void
3741run_set_agc(struct run_softc *sc, uint8_t agc)
3742{
3743 uint8_t bbp;
3744
3745 if (sc->mac_ver == 0x3572) {

--- 2055 unchanged lines hidden --- 		3738}
3739
3740static void
3741run_set_agc(struct run_softc *sc, uint8_t agc)
3742{
3743 uint8_t bbp;
3744
3745 if (sc->mac_ver == 0x3572) {

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