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if_sf.c (72012) if_sf.c (72084)
1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/dev/sf/if_sf.c 72012 2001-02-04 16:08:18Z phk $
32 * $FreeBSD: head/sys/dev/sf/if_sf.c 72084 2001-02-06 10:12:15Z phk $
33 */
34
35/*
36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
37 * Programming manual is available from:
38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf.
39 *
40 * Written by Bill Paul <wpaul@ctr.columbia.edu>
41 * Department of Electical Engineering
42 * Columbia University, New York City
43 */
44
45/*
46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
47 * controller designed with flexibility and reducing CPU load in mind.
48 * The Starfire offers high and low priority buffer queues, a
49 * producer/consumer index mechanism and several different buffer
50 * queue and completion queue descriptor types. Any one of a number
51 * of different driver designs can be used, depending on system and
52 * OS requirements. This driver makes use of type0 transmit frame
53 * descriptors (since BSD fragments packets across an mbuf chain)
54 * and two RX buffer queues prioritized on size (one queue for small
55 * frames that will fit into a single mbuf, another with full size
56 * mbuf clusters for everything else). The producer/consumer indexes
57 * and completion queues are also used.
58 *
59 * One downside to the Starfire has to do with alignment: buffer
60 * queues must be aligned on 256-byte boundaries, and receive buffers
61 * must be aligned on longword boundaries. The receive buffer alignment
62 * causes problems on the Alpha platform, where the packet payload
63 * should be longword aligned. There is no simple way around this.
64 *
65 * For receive filtering, the Starfire offers 16 perfect filter slots
66 * and a 512-bit hash table.
67 *
68 * The Starfire has no internal transceiver, relying instead on an
69 * external MII-based transceiver. Accessing registers on external
70 * PHYs is done through a special register map rather than with the
71 * usual bitbang MDIO method.
72 *
73 * Acesssing the registers on the Starfire is a little tricky. The
74 * Starfire has a 512K internal register space. When programmed for
75 * PCI memory mapped mode, the entire register space can be accessed
76 * directly. However in I/O space mode, only 256 bytes are directly
77 * mapped into PCI I/O space. The other registers can be accessed
78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
79 * registers inside the 256-byte I/O window.
80 */
81
82#include <sys/param.h>
83#include <sys/systm.h>
84#include <sys/sockio.h>
85#include <sys/mbuf.h>
86#include <sys/malloc.h>
87#include <sys/kernel.h>
88#include <sys/socket.h>
89
90#include <net/if.h>
91#include <net/if_arp.h>
92#include <net/ethernet.h>
93#include <net/if_dl.h>
94#include <net/if_media.h>
95
96#include <net/bpf.h>
97
98#include <vm/vm.h> /* for vtophys */
99#include <vm/pmap.h> /* for vtophys */
100#include <machine/bus_pio.h>
101#include <machine/bus_memio.h>
102#include <machine/bus.h>
103#include <machine/resource.h>
104#include <sys/bus.h>
105#include <sys/rman.h>
106
107#include <dev/mii/mii.h>
108#include <dev/mii/miivar.h>
109
110/* "controller miibus0" required. See GENERIC if you get errors here. */
111#include "miibus_if.h"
112
113#include <pci/pcireg.h>
114#include <pci/pcivar.h>
115
116#define SF_USEIOSPACE
117
118#include <pci/if_sfreg.h>
119
120MODULE_DEPEND(sf, miibus, 1, 1, 1);
121
122#ifndef lint
123static const char rcsid[] =
33 */
34
35/*
36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
37 * Programming manual is available from:
38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf.
39 *
40 * Written by Bill Paul <wpaul@ctr.columbia.edu>
41 * Department of Electical Engineering
42 * Columbia University, New York City
43 */
44
45/*
46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
47 * controller designed with flexibility and reducing CPU load in mind.
48 * The Starfire offers high and low priority buffer queues, a
49 * producer/consumer index mechanism and several different buffer
50 * queue and completion queue descriptor types. Any one of a number
51 * of different driver designs can be used, depending on system and
52 * OS requirements. This driver makes use of type0 transmit frame
53 * descriptors (since BSD fragments packets across an mbuf chain)
54 * and two RX buffer queues prioritized on size (one queue for small
55 * frames that will fit into a single mbuf, another with full size
56 * mbuf clusters for everything else). The producer/consumer indexes
57 * and completion queues are also used.
58 *
59 * One downside to the Starfire has to do with alignment: buffer
60 * queues must be aligned on 256-byte boundaries, and receive buffers
61 * must be aligned on longword boundaries. The receive buffer alignment
62 * causes problems on the Alpha platform, where the packet payload
63 * should be longword aligned. There is no simple way around this.
64 *
65 * For receive filtering, the Starfire offers 16 perfect filter slots
66 * and a 512-bit hash table.
67 *
68 * The Starfire has no internal transceiver, relying instead on an
69 * external MII-based transceiver. Accessing registers on external
70 * PHYs is done through a special register map rather than with the
71 * usual bitbang MDIO method.
72 *
73 * Acesssing the registers on the Starfire is a little tricky. The
74 * Starfire has a 512K internal register space. When programmed for
75 * PCI memory mapped mode, the entire register space can be accessed
76 * directly. However in I/O space mode, only 256 bytes are directly
77 * mapped into PCI I/O space. The other registers can be accessed
78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
79 * registers inside the 256-byte I/O window.
80 */
81
82#include <sys/param.h>
83#include <sys/systm.h>
84#include <sys/sockio.h>
85#include <sys/mbuf.h>
86#include <sys/malloc.h>
87#include <sys/kernel.h>
88#include <sys/socket.h>
89
90#include <net/if.h>
91#include <net/if_arp.h>
92#include <net/ethernet.h>
93#include <net/if_dl.h>
94#include <net/if_media.h>
95
96#include <net/bpf.h>
97
98#include <vm/vm.h> /* for vtophys */
99#include <vm/pmap.h> /* for vtophys */
100#include <machine/bus_pio.h>
101#include <machine/bus_memio.h>
102#include <machine/bus.h>
103#include <machine/resource.h>
104#include <sys/bus.h>
105#include <sys/rman.h>
106
107#include <dev/mii/mii.h>
108#include <dev/mii/miivar.h>
109
110/* "controller miibus0" required. See GENERIC if you get errors here. */
111#include "miibus_if.h"
112
113#include <pci/pcireg.h>
114#include <pci/pcivar.h>
115
116#define SF_USEIOSPACE
117
118#include <pci/if_sfreg.h>
119
120MODULE_DEPEND(sf, miibus, 1, 1, 1);
121
122#ifndef lint
123static const char rcsid[] =
124 "$FreeBSD: head/sys/dev/sf/if_sf.c 72012 2001-02-04 16:08:18Z phk $";
124 "$FreeBSD: head/sys/dev/sf/if_sf.c 72084 2001-02-06 10:12:15Z phk $";
125#endif
126
127static struct sf_type sf_devs[] = {
128 { AD_VENDORID, AD_DEVICEID_STARFIRE,
129 "Adaptec AIC-6915 10/100BaseTX" },
130 { 0, 0, NULL }
131};
132
133static int sf_probe __P((device_t));
134static int sf_attach __P((device_t));
135static int sf_detach __P((device_t));
136static void sf_intr __P((void *));
137static void sf_stats_update __P((void *));
138static void sf_rxeof __P((struct sf_softc *));
139static void sf_txeof __P((struct sf_softc *));
140static int sf_encap __P((struct sf_softc *,
141 struct sf_tx_bufdesc_type0 *,
142 struct mbuf *));
143static void sf_start __P((struct ifnet *));
144static int sf_ioctl __P((struct ifnet *, u_long, caddr_t));
145static void sf_init __P((void *));
146static void sf_stop __P((struct sf_softc *));
147static void sf_watchdog __P((struct ifnet *));
148static void sf_shutdown __P((device_t));
149static int sf_ifmedia_upd __P((struct ifnet *));
150static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
151static void sf_reset __P((struct sf_softc *));
152static int sf_init_rx_ring __P((struct sf_softc *));
153static void sf_init_tx_ring __P((struct sf_softc *));
154static int sf_newbuf __P((struct sf_softc *,
155 struct sf_rx_bufdesc_type0 *,
156 struct mbuf *));
157static void sf_setmulti __P((struct sf_softc *));
158static int sf_setperf __P((struct sf_softc *, int, caddr_t));
159static int sf_sethash __P((struct sf_softc *, caddr_t, int));
160#ifdef notdef
161static int sf_setvlan __P((struct sf_softc *, int, u_int32_t));
162#endif
163
164static u_int8_t sf_read_eeprom __P((struct sf_softc *, int));
165static u_int32_t sf_calchash __P((caddr_t));
166
167static int sf_miibus_readreg __P((device_t, int, int));
168static int sf_miibus_writereg __P((device_t, int, int, int));
169static void sf_miibus_statchg __P((device_t));
170
171static u_int32_t csr_read_4 __P((struct sf_softc *, int));
172static void csr_write_4 __P((struct sf_softc *, int, u_int32_t));
173
174#ifdef SF_USEIOSPACE
175#define SF_RES SYS_RES_IOPORT
176#define SF_RID SF_PCI_LOIO
177#else
178#define SF_RES SYS_RES_MEMORY
179#define SF_RID SF_PCI_LOMEM
180#endif
181
182static device_method_t sf_methods[] = {
183 /* Device interface */
184 DEVMETHOD(device_probe, sf_probe),
185 DEVMETHOD(device_attach, sf_attach),
186 DEVMETHOD(device_detach, sf_detach),
187 DEVMETHOD(device_shutdown, sf_shutdown),
188
189 /* bus interface */
190 DEVMETHOD(bus_print_child, bus_generic_print_child),
191 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
192
193 /* MII interface */
194 DEVMETHOD(miibus_readreg, sf_miibus_readreg),
195 DEVMETHOD(miibus_writereg, sf_miibus_writereg),
196 DEVMETHOD(miibus_statchg, sf_miibus_statchg),
197
198 { 0, 0 }
199};
200
201static driver_t sf_driver = {
202 "sf",
203 sf_methods,
204 sizeof(struct sf_softc),
205};
206
207static devclass_t sf_devclass;
208
209DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0);
210DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
211
212#define SF_SETBIT(sc, reg, x) \
213 csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
214
215#define SF_CLRBIT(sc, reg, x) \
216 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
217
218static u_int32_t csr_read_4(sc, reg)
219 struct sf_softc *sc;
220 int reg;
221{
222 u_int32_t val;
223
224#ifdef SF_USEIOSPACE
225 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
226 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
227#else
228 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
229#endif
230
231 return(val);
232}
233
234static u_int8_t sf_read_eeprom(sc, reg)
235 struct sf_softc *sc;
236 int reg;
237{
238 u_int8_t val;
239
240 val = (csr_read_4(sc, SF_EEADDR_BASE +
241 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
242
243 return(val);
244}
245
246static void csr_write_4(sc, reg, val)
247 struct sf_softc *sc;
248 int reg;
249 u_int32_t val;
250{
251#ifdef SF_USEIOSPACE
252 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
253 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
254#else
255 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
256#endif
257 return;
258}
259
260static u_int32_t sf_calchash(addr)
261 caddr_t addr;
262{
263 u_int32_t crc, carry;
264 int i, j;
265 u_int8_t c;
266
267 /* Compute CRC for the address value. */
268 crc = 0xFFFFFFFF; /* initial value */
269
270 for (i = 0; i < 6; i++) {
271 c = *(addr + i);
272 for (j = 0; j < 8; j++) {
273 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
274 crc <<= 1;
275 c >>= 1;
276 if (carry)
277 crc = (crc ^ 0x04c11db6) | carry;
278 }
279 }
280
281 /* return the filter bit position */
282 return(crc >> 23 & 0x1FF);
283}
284
285/*
286 * Copy the address 'mac' into the perfect RX filter entry at
287 * offset 'idx.' The perfect filter only has 16 entries so do
288 * some sanity tests.
289 */
290static int sf_setperf(sc, idx, mac)
291 struct sf_softc *sc;
292 int idx;
293 caddr_t mac;
294{
295 u_int16_t *p;
296
297 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
298 return(EINVAL);
299
300 if (mac == NULL)
301 return(EINVAL);
302
303 p = (u_int16_t *)mac;
304
305 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
306 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2]));
307 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
308 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1]));
309 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
310 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0]));
311
312 return(0);
313}
314
315/*
316 * Set the bit in the 512-bit hash table that corresponds to the
317 * specified mac address 'mac.' If 'prio' is nonzero, update the
318 * priority hash table instead of the filter hash table.
319 */
320static int sf_sethash(sc, mac, prio)
321 struct sf_softc *sc;
322 caddr_t mac;
323 int prio;
324{
325 u_int32_t h = 0;
326
327 if (mac == NULL)
328 return(EINVAL);
329
330 h = sf_calchash(mac);
331
332 if (prio) {
333 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
334 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
335 } else {
336 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
337 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
338 }
339
340 return(0);
341}
342
343#ifdef notdef
344/*
345 * Set a VLAN tag in the receive filter.
346 */
347static int sf_setvlan(sc, idx, vlan)
348 struct sf_softc *sc;
349 int idx;
350 u_int32_t vlan;
351{
352 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
353 return(EINVAL);
354
355 csr_write_4(sc, SF_RXFILT_HASH_BASE +
356 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
357
358 return(0);
359}
360#endif
361
362static int sf_miibus_readreg(dev, phy, reg)
363 device_t dev;
364 int phy, reg;
365{
366 struct sf_softc *sc;
367 int i;
368 u_int32_t val = 0;
369
370 sc = device_get_softc(dev);
371
372 for (i = 0; i < SF_TIMEOUT; i++) {
373 val = csr_read_4(sc, SF_PHY_REG(phy, reg));
374 if (val & SF_MII_DATAVALID)
375 break;
376 }
377
378 if (i == SF_TIMEOUT)
379 return(0);
380
381 if ((val & 0x0000FFFF) == 0xFFFF)
382 return(0);
383
384 return(val & 0x0000FFFF);
385}
386
387static int sf_miibus_writereg(dev, phy, reg, val)
388 device_t dev;
389 int phy, reg, val;
390{
391 struct sf_softc *sc;
392 int i;
393 int busy;
394
395 sc = device_get_softc(dev);
396
397 csr_write_4(sc, SF_PHY_REG(phy, reg), val);
398
399 for (i = 0; i < SF_TIMEOUT; i++) {
400 busy = csr_read_4(sc, SF_PHY_REG(phy, reg));
401 if (!(busy & SF_MII_BUSY))
402 break;
403 }
404
405 return(0);
406}
407
408static void sf_miibus_statchg(dev)
409 device_t dev;
410{
411 struct sf_softc *sc;
412 struct mii_data *mii;
413
414 sc = device_get_softc(dev);
415 mii = device_get_softc(sc->sf_miibus);
416
417 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
418 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
419 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX);
420 } else {
421 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
422 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX);
423 }
424
425 return;
426}
427
428static void sf_setmulti(sc)
429 struct sf_softc *sc;
430{
431 struct ifnet *ifp;
432 int i;
433 struct ifmultiaddr *ifma;
434 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 };
435
436 ifp = &sc->arpcom.ac_if;
437
438 /* First zot all the existing filters. */
439 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
440 sf_setperf(sc, i, (char *)&dummy);
441 for (i = SF_RXFILT_HASH_BASE;
442 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
443 csr_write_4(sc, i, 0);
444 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
445
446 /* Now program new ones. */
447 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
448 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
449 } else {
450 i = 1;
125#endif
126
127static struct sf_type sf_devs[] = {
128 { AD_VENDORID, AD_DEVICEID_STARFIRE,
129 "Adaptec AIC-6915 10/100BaseTX" },
130 { 0, 0, NULL }
131};
132
133static int sf_probe __P((device_t));
134static int sf_attach __P((device_t));
135static int sf_detach __P((device_t));
136static void sf_intr __P((void *));
137static void sf_stats_update __P((void *));
138static void sf_rxeof __P((struct sf_softc *));
139static void sf_txeof __P((struct sf_softc *));
140static int sf_encap __P((struct sf_softc *,
141 struct sf_tx_bufdesc_type0 *,
142 struct mbuf *));
143static void sf_start __P((struct ifnet *));
144static int sf_ioctl __P((struct ifnet *, u_long, caddr_t));
145static void sf_init __P((void *));
146static void sf_stop __P((struct sf_softc *));
147static void sf_watchdog __P((struct ifnet *));
148static void sf_shutdown __P((device_t));
149static int sf_ifmedia_upd __P((struct ifnet *));
150static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
151static void sf_reset __P((struct sf_softc *));
152static int sf_init_rx_ring __P((struct sf_softc *));
153static void sf_init_tx_ring __P((struct sf_softc *));
154static int sf_newbuf __P((struct sf_softc *,
155 struct sf_rx_bufdesc_type0 *,
156 struct mbuf *));
157static void sf_setmulti __P((struct sf_softc *));
158static int sf_setperf __P((struct sf_softc *, int, caddr_t));
159static int sf_sethash __P((struct sf_softc *, caddr_t, int));
160#ifdef notdef
161static int sf_setvlan __P((struct sf_softc *, int, u_int32_t));
162#endif
163
164static u_int8_t sf_read_eeprom __P((struct sf_softc *, int));
165static u_int32_t sf_calchash __P((caddr_t));
166
167static int sf_miibus_readreg __P((device_t, int, int));
168static int sf_miibus_writereg __P((device_t, int, int, int));
169static void sf_miibus_statchg __P((device_t));
170
171static u_int32_t csr_read_4 __P((struct sf_softc *, int));
172static void csr_write_4 __P((struct sf_softc *, int, u_int32_t));
173
174#ifdef SF_USEIOSPACE
175#define SF_RES SYS_RES_IOPORT
176#define SF_RID SF_PCI_LOIO
177#else
178#define SF_RES SYS_RES_MEMORY
179#define SF_RID SF_PCI_LOMEM
180#endif
181
182static device_method_t sf_methods[] = {
183 /* Device interface */
184 DEVMETHOD(device_probe, sf_probe),
185 DEVMETHOD(device_attach, sf_attach),
186 DEVMETHOD(device_detach, sf_detach),
187 DEVMETHOD(device_shutdown, sf_shutdown),
188
189 /* bus interface */
190 DEVMETHOD(bus_print_child, bus_generic_print_child),
191 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
192
193 /* MII interface */
194 DEVMETHOD(miibus_readreg, sf_miibus_readreg),
195 DEVMETHOD(miibus_writereg, sf_miibus_writereg),
196 DEVMETHOD(miibus_statchg, sf_miibus_statchg),
197
198 { 0, 0 }
199};
200
201static driver_t sf_driver = {
202 "sf",
203 sf_methods,
204 sizeof(struct sf_softc),
205};
206
207static devclass_t sf_devclass;
208
209DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0);
210DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
211
212#define SF_SETBIT(sc, reg, x) \
213 csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
214
215#define SF_CLRBIT(sc, reg, x) \
216 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
217
218static u_int32_t csr_read_4(sc, reg)
219 struct sf_softc *sc;
220 int reg;
221{
222 u_int32_t val;
223
224#ifdef SF_USEIOSPACE
225 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
226 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
227#else
228 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
229#endif
230
231 return(val);
232}
233
234static u_int8_t sf_read_eeprom(sc, reg)
235 struct sf_softc *sc;
236 int reg;
237{
238 u_int8_t val;
239
240 val = (csr_read_4(sc, SF_EEADDR_BASE +
241 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
242
243 return(val);
244}
245
246static void csr_write_4(sc, reg, val)
247 struct sf_softc *sc;
248 int reg;
249 u_int32_t val;
250{
251#ifdef SF_USEIOSPACE
252 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
253 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
254#else
255 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
256#endif
257 return;
258}
259
260static u_int32_t sf_calchash(addr)
261 caddr_t addr;
262{
263 u_int32_t crc, carry;
264 int i, j;
265 u_int8_t c;
266
267 /* Compute CRC for the address value. */
268 crc = 0xFFFFFFFF; /* initial value */
269
270 for (i = 0; i < 6; i++) {
271 c = *(addr + i);
272 for (j = 0; j < 8; j++) {
273 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
274 crc <<= 1;
275 c >>= 1;
276 if (carry)
277 crc = (crc ^ 0x04c11db6) | carry;
278 }
279 }
280
281 /* return the filter bit position */
282 return(crc >> 23 & 0x1FF);
283}
284
285/*
286 * Copy the address 'mac' into the perfect RX filter entry at
287 * offset 'idx.' The perfect filter only has 16 entries so do
288 * some sanity tests.
289 */
290static int sf_setperf(sc, idx, mac)
291 struct sf_softc *sc;
292 int idx;
293 caddr_t mac;
294{
295 u_int16_t *p;
296
297 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
298 return(EINVAL);
299
300 if (mac == NULL)
301 return(EINVAL);
302
303 p = (u_int16_t *)mac;
304
305 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
306 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2]));
307 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
308 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1]));
309 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
310 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0]));
311
312 return(0);
313}
314
315/*
316 * Set the bit in the 512-bit hash table that corresponds to the
317 * specified mac address 'mac.' If 'prio' is nonzero, update the
318 * priority hash table instead of the filter hash table.
319 */
320static int sf_sethash(sc, mac, prio)
321 struct sf_softc *sc;
322 caddr_t mac;
323 int prio;
324{
325 u_int32_t h = 0;
326
327 if (mac == NULL)
328 return(EINVAL);
329
330 h = sf_calchash(mac);
331
332 if (prio) {
333 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
334 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
335 } else {
336 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
337 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
338 }
339
340 return(0);
341}
342
343#ifdef notdef
344/*
345 * Set a VLAN tag in the receive filter.
346 */
347static int sf_setvlan(sc, idx, vlan)
348 struct sf_softc *sc;
349 int idx;
350 u_int32_t vlan;
351{
352 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
353 return(EINVAL);
354
355 csr_write_4(sc, SF_RXFILT_HASH_BASE +
356 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
357
358 return(0);
359}
360#endif
361
362static int sf_miibus_readreg(dev, phy, reg)
363 device_t dev;
364 int phy, reg;
365{
366 struct sf_softc *sc;
367 int i;
368 u_int32_t val = 0;
369
370 sc = device_get_softc(dev);
371
372 for (i = 0; i < SF_TIMEOUT; i++) {
373 val = csr_read_4(sc, SF_PHY_REG(phy, reg));
374 if (val & SF_MII_DATAVALID)
375 break;
376 }
377
378 if (i == SF_TIMEOUT)
379 return(0);
380
381 if ((val & 0x0000FFFF) == 0xFFFF)
382 return(0);
383
384 return(val & 0x0000FFFF);
385}
386
387static int sf_miibus_writereg(dev, phy, reg, val)
388 device_t dev;
389 int phy, reg, val;
390{
391 struct sf_softc *sc;
392 int i;
393 int busy;
394
395 sc = device_get_softc(dev);
396
397 csr_write_4(sc, SF_PHY_REG(phy, reg), val);
398
399 for (i = 0; i < SF_TIMEOUT; i++) {
400 busy = csr_read_4(sc, SF_PHY_REG(phy, reg));
401 if (!(busy & SF_MII_BUSY))
402 break;
403 }
404
405 return(0);
406}
407
408static void sf_miibus_statchg(dev)
409 device_t dev;
410{
411 struct sf_softc *sc;
412 struct mii_data *mii;
413
414 sc = device_get_softc(dev);
415 mii = device_get_softc(sc->sf_miibus);
416
417 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
418 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
419 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX);
420 } else {
421 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
422 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX);
423 }
424
425 return;
426}
427
428static void sf_setmulti(sc)
429 struct sf_softc *sc;
430{
431 struct ifnet *ifp;
432 int i;
433 struct ifmultiaddr *ifma;
434 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 };
435
436 ifp = &sc->arpcom.ac_if;
437
438 /* First zot all the existing filters. */
439 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
440 sf_setperf(sc, i, (char *)&dummy);
441 for (i = SF_RXFILT_HASH_BASE;
442 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
443 csr_write_4(sc, i, 0);
444 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
445
446 /* Now program new ones. */
447 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
448 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
449 } else {
450 i = 1;
451 /* First find the tail of the list. */
452 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
453 if (LIST_NEXT(ifma, ifma_link) == NULL)
454 break;
455 }
456 /* Now traverse the list backwards. */
457 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
458 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
451 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
459 if (ifma->ifma_addr->sa_family != AF_LINK)
460 continue;
461 /*
462 * Program the first 15 multicast groups
463 * into the perfect filter. For all others,
464 * use the hash table.
465 */
466 if (i < SF_RXFILT_PERFECT_CNT) {
467 sf_setperf(sc, i,
468 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
469 i++;
470 continue;
471 }
472
473 sf_sethash(sc,
474 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
475 }
476 }
477
478 return;
479}
480
481/*
482 * Set media options.
483 */
484static int sf_ifmedia_upd(ifp)
485 struct ifnet *ifp;
486{
487 struct sf_softc *sc;
488 struct mii_data *mii;
489
490 sc = ifp->if_softc;
491 mii = device_get_softc(sc->sf_miibus);
492 sc->sf_link = 0;
493 if (mii->mii_instance) {
494 struct mii_softc *miisc;
495 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
496 mii_phy_reset(miisc);
497 }
498 mii_mediachg(mii);
499
500 return(0);
501}
502
503/*
504 * Report current media status.
505 */
506static void sf_ifmedia_sts(ifp, ifmr)
507 struct ifnet *ifp;
508 struct ifmediareq *ifmr;
509{
510 struct sf_softc *sc;
511 struct mii_data *mii;
512
513 sc = ifp->if_softc;
514 mii = device_get_softc(sc->sf_miibus);
515
516 mii_pollstat(mii);
517 ifmr->ifm_active = mii->mii_media_active;
518 ifmr->ifm_status = mii->mii_media_status;
519
520 return;
521}
522
523static int sf_ioctl(ifp, command, data)
524 struct ifnet *ifp;
525 u_long command;
526 caddr_t data;
527{
528 struct sf_softc *sc = ifp->if_softc;
529 struct ifreq *ifr = (struct ifreq *) data;
530 struct mii_data *mii;
531 int error = 0;
532
533 SF_LOCK(sc);
534
535 switch(command) {
536 case SIOCSIFADDR:
537 case SIOCGIFADDR:
538 case SIOCSIFMTU:
539 error = ether_ioctl(ifp, command, data);
540 break;
541 case SIOCSIFFLAGS:
542 if (ifp->if_flags & IFF_UP) {
543 if (ifp->if_flags & IFF_RUNNING &&
544 ifp->if_flags & IFF_PROMISC &&
545 !(sc->sf_if_flags & IFF_PROMISC)) {
546 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
547 } else if (ifp->if_flags & IFF_RUNNING &&
548 !(ifp->if_flags & IFF_PROMISC) &&
549 sc->sf_if_flags & IFF_PROMISC) {
550 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
551 } else if (!(ifp->if_flags & IFF_RUNNING))
552 sf_init(sc);
553 } else {
554 if (ifp->if_flags & IFF_RUNNING)
555 sf_stop(sc);
556 }
557 sc->sf_if_flags = ifp->if_flags;
558 error = 0;
559 break;
560 case SIOCADDMULTI:
561 case SIOCDELMULTI:
562 sf_setmulti(sc);
563 error = 0;
564 break;
565 case SIOCGIFMEDIA:
566 case SIOCSIFMEDIA:
567 mii = device_get_softc(sc->sf_miibus);
568 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
569 break;
570 default:
571 error = EINVAL;
572 break;
573 }
574
575 SF_UNLOCK(sc);
576
577 return(error);
578}
579
580static void sf_reset(sc)
581 struct sf_softc *sc;
582{
583 register int i;
584
585 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
586 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
587 DELAY(1000);
588 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
589
590 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
591
592 for (i = 0; i < SF_TIMEOUT; i++) {
593 DELAY(10);
594 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
595 break;
596 }
597
598 if (i == SF_TIMEOUT)
599 printf("sf%d: reset never completed!\n", sc->sf_unit);
600
601 /* Wait a little while for the chip to get its brains in order. */
602 DELAY(1000);
603 return;
604}
605
606/*
607 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
608 * IDs against our list and return a device name if we find a match.
609 * We also check the subsystem ID so that we can identify exactly which
610 * NIC has been found, if possible.
611 */
612static int sf_probe(dev)
613 device_t dev;
614{
615 struct sf_type *t;
616
617 t = sf_devs;
618
619 while(t->sf_name != NULL) {
620 if ((pci_get_vendor(dev) == t->sf_vid) &&
621 (pci_get_device(dev) == t->sf_did)) {
622 switch((pci_read_config(dev,
623 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) {
624 case AD_SUBSYSID_62011_REV0:
625 case AD_SUBSYSID_62011_REV1:
626 device_set_desc(dev,
627 "Adaptec ANA-62011 10/100BaseTX");
628 return(0);
629 break;
630 case AD_SUBSYSID_62022:
631 device_set_desc(dev,
632 "Adaptec ANA-62022 10/100BaseTX");
633 return(0);
634 break;
635 case AD_SUBSYSID_62044_REV0:
636 case AD_SUBSYSID_62044_REV1:
637 device_set_desc(dev,
638 "Adaptec ANA-62044 10/100BaseTX");
639 return(0);
640 break;
641 case AD_SUBSYSID_62020:
642 device_set_desc(dev,
643 "Adaptec ANA-62020 10/100BaseFX");
644 return(0);
645 break;
646 case AD_SUBSYSID_69011:
647 device_set_desc(dev,
648 "Adaptec ANA-69011 10/100BaseTX");
649 return(0);
650 break;
651 default:
652 device_set_desc(dev, t->sf_name);
653 return(0);
654 break;
655 }
656 }
657 t++;
658 }
659
660 return(ENXIO);
661}
662
663/*
664 * Attach the interface. Allocate softc structures, do ifmedia
665 * setup and ethernet/BPF attach.
666 */
667static int sf_attach(dev)
668 device_t dev;
669{
670 int i;
671 u_int32_t command;
672 struct sf_softc *sc;
673 struct ifnet *ifp;
674 int unit, rid, error = 0;
675
676 sc = device_get_softc(dev);
677 unit = device_get_unit(dev);
678 bzero(sc, sizeof(struct sf_softc));
679
680 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
681 SF_LOCK(sc);
682 /*
683 * Handle power management nonsense.
684 */
685 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF;
686 if (command == 0x01) {
687
688 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4);
689 if (command & SF_PSTATE_MASK) {
690 u_int32_t iobase, membase, irq;
691
692 /* Save important PCI config data. */
693 iobase = pci_read_config(dev, SF_PCI_LOIO, 4);
694 membase = pci_read_config(dev, SF_PCI_LOMEM, 4);
695 irq = pci_read_config(dev, SF_PCI_INTLINE, 4);
696
697 /* Reset the power state. */
698 printf("sf%d: chip is in D%d power mode "
699 "-- setting to D0\n", unit, command & SF_PSTATE_MASK);
700 command &= 0xFFFFFFFC;
701 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4);
702
703 /* Restore PCI config data. */
704 pci_write_config(dev, SF_PCI_LOIO, iobase, 4);
705 pci_write_config(dev, SF_PCI_LOMEM, membase, 4);
706 pci_write_config(dev, SF_PCI_INTLINE, irq, 4);
707 }
708 }
709
710 /*
711 * Map control/status registers.
712 */
713 command = pci_read_config(dev, PCIR_COMMAND, 4);
714 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
715 pci_write_config(dev, PCIR_COMMAND, command, 4);
716 command = pci_read_config(dev, PCIR_COMMAND, 4);
717
718#ifdef SF_USEIOSPACE
719 if (!(command & PCIM_CMD_PORTEN)) {
720 printf("sf%d: failed to enable I/O ports!\n", unit);
721 error = ENXIO;
722 goto fail;
723 }
724#else
725 if (!(command & PCIM_CMD_MEMEN)) {
726 printf("sf%d: failed to enable memory mapping!\n", unit);
727 error = ENXIO;
728 goto fail;
729 }
730#endif
731
732 rid = SF_RID;
733 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid,
734 0, ~0, 1, RF_ACTIVE);
735
736 if (sc->sf_res == NULL) {
737 printf ("sf%d: couldn't map ports\n", unit);
738 error = ENXIO;
739 goto fail;
740 }
741
742 sc->sf_btag = rman_get_bustag(sc->sf_res);
743 sc->sf_bhandle = rman_get_bushandle(sc->sf_res);
744
745 /* Allocate interrupt */
746 rid = 0;
747 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
748 RF_SHAREABLE | RF_ACTIVE);
749
750 if (sc->sf_irq == NULL) {
751 printf("sf%d: couldn't map interrupt\n", unit);
752 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
753 error = ENXIO;
754 goto fail;
755 }
756
757 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET,
758 sf_intr, sc, &sc->sf_intrhand);
759
760 if (error) {
761 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res);
762 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
763 printf("sf%d: couldn't set up irq\n", unit);
764 goto fail;
765 }
766
767 callout_handle_init(&sc->sf_stat_ch);
768 /* Reset the adapter. */
769 sf_reset(sc);
770
771 /*
772 * Get station address from the EEPROM.
773 */
774 for (i = 0; i < ETHER_ADDR_LEN; i++)
775 sc->arpcom.ac_enaddr[i] =
776 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
777
778 /*
779 * An Adaptec chip was detected. Inform the world.
780 */
781 printf("sf%d: Ethernet address: %6D\n", unit,
782 sc->arpcom.ac_enaddr, ":");
783
784 sc->sf_unit = unit;
785
786 /* Allocate the descriptor queues. */
787 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF,
788 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
789
790 if (sc->sf_ldata == NULL) {
791 printf("sf%d: no memory for list buffers!\n", unit);
792 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
793 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
794 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
795 error = ENXIO;
796 goto fail;
797 }
798
799 bzero(sc->sf_ldata, sizeof(struct sf_list_data));
800
801 /* Do MII setup. */
802 if (mii_phy_probe(dev, &sc->sf_miibus,
803 sf_ifmedia_upd, sf_ifmedia_sts)) {
804 printf("sf%d: MII without any phy!\n", sc->sf_unit);
805 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF);
806 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
807 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
808 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
809 error = ENXIO;
810 goto fail;
811 }
812
813 ifp = &sc->arpcom.ac_if;
814 ifp->if_softc = sc;
815 ifp->if_unit = unit;
816 ifp->if_name = "sf";
817 ifp->if_mtu = ETHERMTU;
818 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
819 ifp->if_ioctl = sf_ioctl;
820 ifp->if_output = ether_output;
821 ifp->if_start = sf_start;
822 ifp->if_watchdog = sf_watchdog;
823 ifp->if_init = sf_init;
824 ifp->if_baudrate = 10000000;
825 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1;
826
827 /*
828 * Call MI attach routine.
829 */
830 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
831 SF_UNLOCK(sc);
832 return(0);
833
834fail:
835 SF_UNLOCK(sc);
836 mtx_destroy(&sc->sf_mtx);
837 return(error);
838}
839
840static int sf_detach(dev)
841 device_t dev;
842{
843 struct sf_softc *sc;
844 struct ifnet *ifp;
845
846 sc = device_get_softc(dev);
847 SF_LOCK(sc);
848 ifp = &sc->arpcom.ac_if;
849
850 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
851 sf_stop(sc);
852
853 bus_generic_detach(dev);
854 device_delete_child(dev, sc->sf_miibus);
855
856 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
857 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
858 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
859
860 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF);
861
862 SF_UNLOCK(sc);
863 mtx_destroy(&sc->sf_mtx);
864
865 return(0);
866}
867
868static int sf_init_rx_ring(sc)
869 struct sf_softc *sc;
870{
871 struct sf_list_data *ld;
872 int i;
873
874 ld = sc->sf_ldata;
875
876 bzero((char *)ld->sf_rx_dlist_big,
877 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT);
878 bzero((char *)ld->sf_rx_clist,
879 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT);
880
881 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
882 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS)
883 return(ENOBUFS);
884 }
885
886 return(0);
887}
888
889static void sf_init_tx_ring(sc)
890 struct sf_softc *sc;
891{
892 struct sf_list_data *ld;
893 int i;
894
895 ld = sc->sf_ldata;
896
897 bzero((char *)ld->sf_tx_dlist,
898 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT);
899 bzero((char *)ld->sf_tx_clist,
900 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT);
901
902 for (i = 0; i < SF_TX_DLIST_CNT; i++)
903 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID;
904 for (i = 0; i < SF_TX_CLIST_CNT; i++)
905 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX;
906
907 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1;
908 sc->sf_tx_cnt = 0;
909
910 return;
911}
912
913static int sf_newbuf(sc, c, m)
914 struct sf_softc *sc;
915 struct sf_rx_bufdesc_type0 *c;
916 struct mbuf *m;
917{
918 struct mbuf *m_new = NULL;
919
920 if (m == NULL) {
921 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
922 if (m_new == NULL) {
923 printf("sf%d: no memory for rx list -- "
924 "packet dropped!\n", sc->sf_unit);
925 return(ENOBUFS);
926 }
927
928 MCLGET(m_new, M_DONTWAIT);
929 if (!(m_new->m_flags & M_EXT)) {
930 printf("sf%d: no memory for rx list -- "
931 "packet dropped!\n", sc->sf_unit);
932 m_freem(m_new);
933 return(ENOBUFS);
934 }
935 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
936 } else {
937 m_new = m;
938 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
939 m_new->m_data = m_new->m_ext.ext_buf;
940 }
941
942 m_adj(m_new, sizeof(u_int64_t));
943
944 c->sf_mbuf = m_new;
945 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t)));
946 c->sf_valid = 1;
947
948 return(0);
949}
950
951/*
952 * The starfire is programmed to use 'normal' mode for packet reception,
953 * which means we use the consumer/producer model for both the buffer
954 * descriptor queue and the completion descriptor queue. The only problem
955 * with this is that it involves a lot of register accesses: we have to
956 * read the RX completion consumer and producer indexes and the RX buffer
957 * producer index, plus the RX completion consumer and RX buffer producer
958 * indexes have to be updated. It would have been easier if Adaptec had
959 * put each index in a separate register, especially given that the damn
960 * NIC has a 512K register space.
961 *
962 * In spite of all the lovely features that Adaptec crammed into the 6915,
963 * it is marred by one truly stupid design flaw, which is that receive
964 * buffer addresses must be aligned on a longword boundary. This forces
965 * the packet payload to be unaligned, which is suboptimal on the x86 and
966 * completely unuseable on the Alpha. Our only recourse is to copy received
967 * packets into properly aligned buffers before handing them off.
968 */
969
970static void sf_rxeof(sc)
971 struct sf_softc *sc;
972{
973 struct ether_header *eh;
974 struct mbuf *m;
975 struct ifnet *ifp;
976 struct sf_rx_bufdesc_type0 *desc;
977 struct sf_rx_cmpdesc_type3 *cur_rx;
978 u_int32_t rxcons, rxprod;
979 int cmpprodidx, cmpconsidx, bufprodidx;
980
981 ifp = &sc->arpcom.ac_if;
982
983 rxcons = csr_read_4(sc, SF_CQ_CONSIDX);
984 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1);
985 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX));
986 cmpconsidx = SF_IDX_LO(rxcons);
987 bufprodidx = SF_IDX_LO(rxprod);
988
989 while (cmpconsidx != cmpprodidx) {
990 struct mbuf *m0;
991
992 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx];
993 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx];
994 m = desc->sf_mbuf;
995 SF_INC(cmpconsidx, SF_RX_CLIST_CNT);
996 SF_INC(bufprodidx, SF_RX_DLIST_CNT);
997
998 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) {
999 ifp->if_ierrors++;
1000 sf_newbuf(sc, desc, m);
1001 continue;
1002 }
1003
1004 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1005 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL);
1006 sf_newbuf(sc, desc, m);
1007 if (m0 == NULL) {
1008 ifp->if_ierrors++;
1009 continue;
1010 }
1011 m_adj(m0, ETHER_ALIGN);
1012 m = m0;
1013
1014 eh = mtod(m, struct ether_header *);
1015 ifp->if_ipackets++;
1016
1017 /* Remove header from mbuf and pass it on. */
1018 m_adj(m, sizeof(struct ether_header));
1019 ether_input(ifp, eh, m);
1020 }
1021
1022 csr_write_4(sc, SF_CQ_CONSIDX,
1023 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx);
1024 csr_write_4(sc, SF_RXDQ_PTR_Q1,
1025 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx);
1026
1027 return;
1028}
1029
1030/*
1031 * Read the transmit status from the completion queue and release
1032 * mbufs. Note that the buffer descriptor index in the completion
1033 * descriptor is an offset from the start of the transmit buffer
1034 * descriptor list in bytes. This is important because the manual
1035 * gives the impression that it should match the producer/consumer
1036 * index, which is the offset in 8 byte blocks.
1037 */
1038static void sf_txeof(sc)
1039 struct sf_softc *sc;
1040{
1041 int txcons, cmpprodidx, cmpconsidx;
1042 struct sf_tx_cmpdesc_type1 *cur_cmp;
1043 struct sf_tx_bufdesc_type0 *cur_tx;
1044 struct ifnet *ifp;
1045
1046 ifp = &sc->arpcom.ac_if;
1047
1048 txcons = csr_read_4(sc, SF_CQ_CONSIDX);
1049 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX));
1050 cmpconsidx = SF_IDX_HI(txcons);
1051
1052 while (cmpconsidx != cmpprodidx) {
1053 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx];
1054 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7];
1055 SF_INC(cmpconsidx, SF_TX_CLIST_CNT);
1056
1057 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK)
1058 ifp->if_opackets++;
1059 else
1060 ifp->if_oerrors++;
1061
1062 sc->sf_tx_cnt--;
1063 if (cur_tx->sf_mbuf != NULL) {
1064 m_freem(cur_tx->sf_mbuf);
1065 cur_tx->sf_mbuf = NULL;
1066 }
1067 }
1068
1069 ifp->if_timer = 0;
1070 ifp->if_flags &= ~IFF_OACTIVE;
1071
1072 csr_write_4(sc, SF_CQ_CONSIDX,
1073 (txcons & ~SF_CQ_CONSIDX_TXQ) |
1074 ((cmpconsidx << 16) & 0xFFFF0000));
1075
1076 return;
1077}
1078
1079static void sf_intr(arg)
1080 void *arg;
1081{
1082 struct sf_softc *sc;
1083 struct ifnet *ifp;
1084 u_int32_t status;
1085
1086 sc = arg;
1087 SF_LOCK(sc);
1088
1089 ifp = &sc->arpcom.ac_if;
1090
1091 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) {
1092 SF_UNLOCK(sc);
1093 return;
1094 }
1095
1096 /* Disable interrupts. */
1097 csr_write_4(sc, SF_IMR, 0x00000000);
1098
1099 for (;;) {
1100 status = csr_read_4(sc, SF_ISR);
1101 if (status)
1102 csr_write_4(sc, SF_ISR, status);
1103
1104 if (!(status & SF_INTRS))
1105 break;
1106
1107 if (status & SF_ISR_RXDQ1_DMADONE)
1108 sf_rxeof(sc);
1109
1110 if (status & SF_ISR_TX_TXDONE)
1111 sf_txeof(sc);
1112
1113 if (status & SF_ISR_ABNORMALINTR) {
1114 if (status & SF_ISR_STATSOFLOW) {
1115 untimeout(sf_stats_update, sc,
1116 sc->sf_stat_ch);
1117 sf_stats_update(sc);
1118 } else
1119 sf_init(sc);
1120 }
1121 }
1122
1123 /* Re-enable interrupts. */
1124 csr_write_4(sc, SF_IMR, SF_INTRS);
1125
1126 if (ifp->if_snd.ifq_head != NULL)
1127 sf_start(ifp);
1128
1129 SF_UNLOCK(sc);
1130 return;
1131}
1132
1133static void sf_init(xsc)
1134 void *xsc;
1135{
1136 struct sf_softc *sc;
1137 struct ifnet *ifp;
1138 struct mii_data *mii;
1139 int i;
1140
1141 sc = xsc;
1142 SF_LOCK(sc);
1143 ifp = &sc->arpcom.ac_if;
1144 mii = device_get_softc(sc->sf_miibus);
1145
1146 sf_stop(sc);
1147 sf_reset(sc);
1148
1149 /* Init all the receive filter registers */
1150 for (i = SF_RXFILT_PERFECT_BASE;
1151 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
1152 csr_write_4(sc, i, 0);
1153
1154 /* Empty stats counter registers. */
1155 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++)
1156 csr_write_4(sc, SF_STATS_BASE +
1157 (i + sizeof(u_int32_t)), 0);
1158
1159 /* Init our MAC address */
1160 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1161 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1162 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr);
1163
1164 if (sf_init_rx_ring(sc) == ENOBUFS) {
1165 printf("sf%d: initialization failed: no "
1166 "memory for rx buffers\n", sc->sf_unit);
1167 SF_UNLOCK(sc);
1168 return;
1169 }
1170
1171 sf_init_tx_ring(sc);
1172
1173 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
1174
1175 /* If we want promiscuous mode, set the allframes bit. */
1176 if (ifp->if_flags & IFF_PROMISC) {
1177 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1178 } else {
1179 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1180 }
1181
1182 if (ifp->if_flags & IFF_BROADCAST) {
1183 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1184 } else {
1185 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1186 }
1187
1188 /*
1189 * Load the multicast filter.
1190 */
1191 sf_setmulti(sc);
1192
1193 /* Init the completion queue indexes */
1194 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1195 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1196
1197 /* Init the RX completion queue */
1198 csr_write_4(sc, SF_RXCQ_CTL_1,
1199 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR);
1200 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3);
1201
1202 /* Init RX DMA control. */
1203 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS);
1204
1205 /* Init the RX buffer descriptor queue. */
1206 csr_write_4(sc, SF_RXDQ_ADDR_Q1,
1207 vtophys(sc->sf_ldata->sf_rx_dlist_big));
1208 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
1209 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
1210
1211 /* Init the TX completion queue */
1212 csr_write_4(sc, SF_TXCQ_CTL,
1213 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR);
1214
1215 /* Init the TX buffer descriptor queue. */
1216 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
1217 vtophys(sc->sf_ldata->sf_tx_dlist));
1218 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX);
1219 csr_write_4(sc, SF_TXDQ_CTL,
1220 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES);
1221 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP);
1222
1223 /* Enable autopadding of short TX frames. */
1224 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
1225
1226 /* Enable interrupts. */
1227 csr_write_4(sc, SF_IMR, SF_INTRS);
1228 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
1229
1230 /* Enable the RX and TX engines. */
1231 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB);
1232 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB);
1233
1234 /*mii_mediachg(mii);*/
1235 sf_ifmedia_upd(ifp);
1236
1237 ifp->if_flags |= IFF_RUNNING;
1238 ifp->if_flags &= ~IFF_OACTIVE;
1239
1240 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
1241
1242 SF_UNLOCK(sc);
1243
1244 return;
1245}
1246
1247static int sf_encap(sc, c, m_head)
1248 struct sf_softc *sc;
1249 struct sf_tx_bufdesc_type0 *c;
1250 struct mbuf *m_head;
1251{
1252 int frag = 0;
1253 struct sf_frag *f = NULL;
1254 struct mbuf *m;
1255
1256 m = m_head;
1257
1258 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1259 if (m->m_len != 0) {
1260 if (frag == SF_MAXFRAGS)
1261 break;
1262 f = &c->sf_frags[frag];
1263 if (frag == 0)
1264 f->sf_pktlen = m_head->m_pkthdr.len;
1265 f->sf_fraglen = m->m_len;
1266 f->sf_addr = vtophys(mtod(m, vm_offset_t));
1267 frag++;
1268 }
1269 }
1270
1271 if (m != NULL) {
1272 struct mbuf *m_new = NULL;
1273
1274 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1275 if (m_new == NULL) {
1276 printf("sf%d: no memory for tx list", sc->sf_unit);
1277 return(1);
1278 }
1279
1280 if (m_head->m_pkthdr.len > MHLEN) {
1281 MCLGET(m_new, M_DONTWAIT);
1282 if (!(m_new->m_flags & M_EXT)) {
1283 m_freem(m_new);
1284 printf("sf%d: no memory for tx list",
1285 sc->sf_unit);
1286 return(1);
1287 }
1288 }
1289 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1290 mtod(m_new, caddr_t));
1291 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1292 m_freem(m_head);
1293 m_head = m_new;
1294 f = &c->sf_frags[0];
1295 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len;
1296 f->sf_addr = vtophys(mtod(m_head, caddr_t));
1297 frag = 1;
1298 }
1299
1300 c->sf_mbuf = m_head;
1301 c->sf_id = SF_TX_BUFDESC_ID;
1302 c->sf_fragcnt = frag;
1303 c->sf_intr = 1;
1304 c->sf_caltcp = 0;
1305 c->sf_crcen = 1;
1306
1307 return(0);
1308}
1309
1310static void sf_start(ifp)
1311 struct ifnet *ifp;
1312{
1313 struct sf_softc *sc;
1314 struct sf_tx_bufdesc_type0 *cur_tx = NULL;
1315 struct mbuf *m_head = NULL;
1316 int i, txprod;
1317
1318 sc = ifp->if_softc;
1319 SF_LOCK(sc);
1320
1321 if (!sc->sf_link) {
1322 SF_UNLOCK(sc);
1323 return;
1324 }
1325
1326 if (ifp->if_flags & IFF_OACTIVE) {
1327 SF_UNLOCK(sc);
1328 return;
1329 }
1330
1331 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1332 i = SF_IDX_HI(txprod) >> 4;
1333
1334 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) {
1335 if (sc->sf_tx_cnt == (SF_TX_DLIST_CNT - 2)) {
1336 ifp->if_flags |= IFF_OACTIVE;
1337 cur_tx = NULL;
1338 break;
1339 }
1340 IF_DEQUEUE(&ifp->if_snd, m_head);
1341 if (m_head == NULL)
1342 break;
1343
1344 cur_tx = &sc->sf_ldata->sf_tx_dlist[i];
1345 if (sf_encap(sc, cur_tx, m_head)) {
1346 IF_PREPEND(&ifp->if_snd, m_head);
1347 ifp->if_flags |= IFF_OACTIVE;
1348 cur_tx = NULL;
1349 break;
1350 }
1351
1352 /*
1353 * If there's a BPF listener, bounce a copy of this frame
1354 * to him.
1355 */
1356 if (ifp->if_bpf)
1357 bpf_mtap(ifp, m_head);
1358
1359 SF_INC(i, SF_TX_DLIST_CNT);
1360 sc->sf_tx_cnt++;
1361 }
1362
1363 if (cur_tx == NULL) {
1364 SF_UNLOCK(sc);
1365 return;
1366 }
1367
1368 /* Transmit */
1369 csr_write_4(sc, SF_TXDQ_PRODIDX,
1370 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) |
1371 ((i << 20) & 0xFFFF0000));
1372
1373 ifp->if_timer = 5;
1374
1375 SF_UNLOCK(sc);
1376
1377 return;
1378}
1379
1380static void sf_stop(sc)
1381 struct sf_softc *sc;
1382{
1383 int i;
1384 struct ifnet *ifp;
1385
1386 SF_LOCK(sc);
1387
1388 ifp = &sc->arpcom.ac_if;
1389
1390 untimeout(sf_stats_update, sc, sc->sf_stat_ch);
1391
1392 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
1393 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1394 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1395 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
1396 csr_write_4(sc, SF_RXDQ_CTL_1, 0);
1397 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
1398 csr_write_4(sc, SF_TXCQ_CTL, 0);
1399 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
1400 csr_write_4(sc, SF_TXDQ_CTL, 0);
1401 sf_reset(sc);
1402
1403 sc->sf_link = 0;
1404
1405 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1406 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) {
1407 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf);
1408 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL;
1409 }
1410 }
1411
1412 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1413 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1414 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf);
1415 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL;
1416 }
1417 }
1418
1419 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1420 SF_UNLOCK(sc);
1421
1422 return;
1423}
1424
1425/*
1426 * Note: it is important that this function not be interrupted. We
1427 * use a two-stage register access scheme: if we are interrupted in
1428 * between setting the indirect address register and reading from the
1429 * indirect data register, the contents of the address register could
1430 * be changed out from under us.
1431 */
1432static void sf_stats_update(xsc)
1433 void *xsc;
1434{
1435 struct sf_softc *sc;
1436 struct ifnet *ifp;
1437 struct mii_data *mii;
1438 struct sf_stats stats;
1439 u_int32_t *ptr;
1440 int i;
1441
1442 sc = xsc;
1443 SF_LOCK(sc);
1444 ifp = &sc->arpcom.ac_if;
1445 mii = device_get_softc(sc->sf_miibus);
1446
1447 ptr = (u_int32_t *)&stats;
1448 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1449 ptr[i] = csr_read_4(sc, SF_STATS_BASE +
1450 (i + sizeof(u_int32_t)));
1451
1452 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1453 csr_write_4(sc, SF_STATS_BASE +
1454 (i + sizeof(u_int32_t)), 0);
1455
1456 ifp->if_collisions += stats.sf_tx_single_colls +
1457 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls;
1458
1459 mii_tick(mii);
1460 if (!sc->sf_link) {
1461 mii_pollstat(mii);
1462 if (mii->mii_media_status & IFM_ACTIVE &&
1463 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1464 sc->sf_link++;
1465 if (ifp->if_snd.ifq_head != NULL)
1466 sf_start(ifp);
1467 }
1468
1469 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
1470
1471 SF_UNLOCK(sc);
1472
1473 return;
1474}
1475
1476static void sf_watchdog(ifp)
1477 struct ifnet *ifp;
1478{
1479 struct sf_softc *sc;
1480
1481 sc = ifp->if_softc;
1482
1483 SF_LOCK(sc);
1484
1485 ifp->if_oerrors++;
1486 printf("sf%d: watchdog timeout\n", sc->sf_unit);
1487
1488 sf_stop(sc);
1489 sf_reset(sc);
1490 sf_init(sc);
1491
1492 if (ifp->if_snd.ifq_head != NULL)
1493 sf_start(ifp);
1494
1495 SF_UNLOCK(sc);
1496
1497 return;
1498}
1499
1500static void sf_shutdown(dev)
1501 device_t dev;
1502{
1503 struct sf_softc *sc;
1504
1505 sc = device_get_softc(dev);
1506
1507 sf_stop(sc);
1508
1509 return;
1510}
452 if (ifma->ifma_addr->sa_family != AF_LINK)
453 continue;
454 /*
455 * Program the first 15 multicast groups
456 * into the perfect filter. For all others,
457 * use the hash table.
458 */
459 if (i < SF_RXFILT_PERFECT_CNT) {
460 sf_setperf(sc, i,
461 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
462 i++;
463 continue;
464 }
465
466 sf_sethash(sc,
467 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
468 }
469 }
470
471 return;
472}
473
474/*
475 * Set media options.
476 */
477static int sf_ifmedia_upd(ifp)
478 struct ifnet *ifp;
479{
480 struct sf_softc *sc;
481 struct mii_data *mii;
482
483 sc = ifp->if_softc;
484 mii = device_get_softc(sc->sf_miibus);
485 sc->sf_link = 0;
486 if (mii->mii_instance) {
487 struct mii_softc *miisc;
488 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
489 mii_phy_reset(miisc);
490 }
491 mii_mediachg(mii);
492
493 return(0);
494}
495
496/*
497 * Report current media status.
498 */
499static void sf_ifmedia_sts(ifp, ifmr)
500 struct ifnet *ifp;
501 struct ifmediareq *ifmr;
502{
503 struct sf_softc *sc;
504 struct mii_data *mii;
505
506 sc = ifp->if_softc;
507 mii = device_get_softc(sc->sf_miibus);
508
509 mii_pollstat(mii);
510 ifmr->ifm_active = mii->mii_media_active;
511 ifmr->ifm_status = mii->mii_media_status;
512
513 return;
514}
515
516static int sf_ioctl(ifp, command, data)
517 struct ifnet *ifp;
518 u_long command;
519 caddr_t data;
520{
521 struct sf_softc *sc = ifp->if_softc;
522 struct ifreq *ifr = (struct ifreq *) data;
523 struct mii_data *mii;
524 int error = 0;
525
526 SF_LOCK(sc);
527
528 switch(command) {
529 case SIOCSIFADDR:
530 case SIOCGIFADDR:
531 case SIOCSIFMTU:
532 error = ether_ioctl(ifp, command, data);
533 break;
534 case SIOCSIFFLAGS:
535 if (ifp->if_flags & IFF_UP) {
536 if (ifp->if_flags & IFF_RUNNING &&
537 ifp->if_flags & IFF_PROMISC &&
538 !(sc->sf_if_flags & IFF_PROMISC)) {
539 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
540 } else if (ifp->if_flags & IFF_RUNNING &&
541 !(ifp->if_flags & IFF_PROMISC) &&
542 sc->sf_if_flags & IFF_PROMISC) {
543 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
544 } else if (!(ifp->if_flags & IFF_RUNNING))
545 sf_init(sc);
546 } else {
547 if (ifp->if_flags & IFF_RUNNING)
548 sf_stop(sc);
549 }
550 sc->sf_if_flags = ifp->if_flags;
551 error = 0;
552 break;
553 case SIOCADDMULTI:
554 case SIOCDELMULTI:
555 sf_setmulti(sc);
556 error = 0;
557 break;
558 case SIOCGIFMEDIA:
559 case SIOCSIFMEDIA:
560 mii = device_get_softc(sc->sf_miibus);
561 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
562 break;
563 default:
564 error = EINVAL;
565 break;
566 }
567
568 SF_UNLOCK(sc);
569
570 return(error);
571}
572
573static void sf_reset(sc)
574 struct sf_softc *sc;
575{
576 register int i;
577
578 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
579 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
580 DELAY(1000);
581 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
582
583 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
584
585 for (i = 0; i < SF_TIMEOUT; i++) {
586 DELAY(10);
587 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
588 break;
589 }
590
591 if (i == SF_TIMEOUT)
592 printf("sf%d: reset never completed!\n", sc->sf_unit);
593
594 /* Wait a little while for the chip to get its brains in order. */
595 DELAY(1000);
596 return;
597}
598
599/*
600 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
601 * IDs against our list and return a device name if we find a match.
602 * We also check the subsystem ID so that we can identify exactly which
603 * NIC has been found, if possible.
604 */
605static int sf_probe(dev)
606 device_t dev;
607{
608 struct sf_type *t;
609
610 t = sf_devs;
611
612 while(t->sf_name != NULL) {
613 if ((pci_get_vendor(dev) == t->sf_vid) &&
614 (pci_get_device(dev) == t->sf_did)) {
615 switch((pci_read_config(dev,
616 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) {
617 case AD_SUBSYSID_62011_REV0:
618 case AD_SUBSYSID_62011_REV1:
619 device_set_desc(dev,
620 "Adaptec ANA-62011 10/100BaseTX");
621 return(0);
622 break;
623 case AD_SUBSYSID_62022:
624 device_set_desc(dev,
625 "Adaptec ANA-62022 10/100BaseTX");
626 return(0);
627 break;
628 case AD_SUBSYSID_62044_REV0:
629 case AD_SUBSYSID_62044_REV1:
630 device_set_desc(dev,
631 "Adaptec ANA-62044 10/100BaseTX");
632 return(0);
633 break;
634 case AD_SUBSYSID_62020:
635 device_set_desc(dev,
636 "Adaptec ANA-62020 10/100BaseFX");
637 return(0);
638 break;
639 case AD_SUBSYSID_69011:
640 device_set_desc(dev,
641 "Adaptec ANA-69011 10/100BaseTX");
642 return(0);
643 break;
644 default:
645 device_set_desc(dev, t->sf_name);
646 return(0);
647 break;
648 }
649 }
650 t++;
651 }
652
653 return(ENXIO);
654}
655
656/*
657 * Attach the interface. Allocate softc structures, do ifmedia
658 * setup and ethernet/BPF attach.
659 */
660static int sf_attach(dev)
661 device_t dev;
662{
663 int i;
664 u_int32_t command;
665 struct sf_softc *sc;
666 struct ifnet *ifp;
667 int unit, rid, error = 0;
668
669 sc = device_get_softc(dev);
670 unit = device_get_unit(dev);
671 bzero(sc, sizeof(struct sf_softc));
672
673 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
674 SF_LOCK(sc);
675 /*
676 * Handle power management nonsense.
677 */
678 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF;
679 if (command == 0x01) {
680
681 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4);
682 if (command & SF_PSTATE_MASK) {
683 u_int32_t iobase, membase, irq;
684
685 /* Save important PCI config data. */
686 iobase = pci_read_config(dev, SF_PCI_LOIO, 4);
687 membase = pci_read_config(dev, SF_PCI_LOMEM, 4);
688 irq = pci_read_config(dev, SF_PCI_INTLINE, 4);
689
690 /* Reset the power state. */
691 printf("sf%d: chip is in D%d power mode "
692 "-- setting to D0\n", unit, command & SF_PSTATE_MASK);
693 command &= 0xFFFFFFFC;
694 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4);
695
696 /* Restore PCI config data. */
697 pci_write_config(dev, SF_PCI_LOIO, iobase, 4);
698 pci_write_config(dev, SF_PCI_LOMEM, membase, 4);
699 pci_write_config(dev, SF_PCI_INTLINE, irq, 4);
700 }
701 }
702
703 /*
704 * Map control/status registers.
705 */
706 command = pci_read_config(dev, PCIR_COMMAND, 4);
707 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
708 pci_write_config(dev, PCIR_COMMAND, command, 4);
709 command = pci_read_config(dev, PCIR_COMMAND, 4);
710
711#ifdef SF_USEIOSPACE
712 if (!(command & PCIM_CMD_PORTEN)) {
713 printf("sf%d: failed to enable I/O ports!\n", unit);
714 error = ENXIO;
715 goto fail;
716 }
717#else
718 if (!(command & PCIM_CMD_MEMEN)) {
719 printf("sf%d: failed to enable memory mapping!\n", unit);
720 error = ENXIO;
721 goto fail;
722 }
723#endif
724
725 rid = SF_RID;
726 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid,
727 0, ~0, 1, RF_ACTIVE);
728
729 if (sc->sf_res == NULL) {
730 printf ("sf%d: couldn't map ports\n", unit);
731 error = ENXIO;
732 goto fail;
733 }
734
735 sc->sf_btag = rman_get_bustag(sc->sf_res);
736 sc->sf_bhandle = rman_get_bushandle(sc->sf_res);
737
738 /* Allocate interrupt */
739 rid = 0;
740 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
741 RF_SHAREABLE | RF_ACTIVE);
742
743 if (sc->sf_irq == NULL) {
744 printf("sf%d: couldn't map interrupt\n", unit);
745 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
746 error = ENXIO;
747 goto fail;
748 }
749
750 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET,
751 sf_intr, sc, &sc->sf_intrhand);
752
753 if (error) {
754 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res);
755 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
756 printf("sf%d: couldn't set up irq\n", unit);
757 goto fail;
758 }
759
760 callout_handle_init(&sc->sf_stat_ch);
761 /* Reset the adapter. */
762 sf_reset(sc);
763
764 /*
765 * Get station address from the EEPROM.
766 */
767 for (i = 0; i < ETHER_ADDR_LEN; i++)
768 sc->arpcom.ac_enaddr[i] =
769 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
770
771 /*
772 * An Adaptec chip was detected. Inform the world.
773 */
774 printf("sf%d: Ethernet address: %6D\n", unit,
775 sc->arpcom.ac_enaddr, ":");
776
777 sc->sf_unit = unit;
778
779 /* Allocate the descriptor queues. */
780 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF,
781 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
782
783 if (sc->sf_ldata == NULL) {
784 printf("sf%d: no memory for list buffers!\n", unit);
785 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
786 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
787 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
788 error = ENXIO;
789 goto fail;
790 }
791
792 bzero(sc->sf_ldata, sizeof(struct sf_list_data));
793
794 /* Do MII setup. */
795 if (mii_phy_probe(dev, &sc->sf_miibus,
796 sf_ifmedia_upd, sf_ifmedia_sts)) {
797 printf("sf%d: MII without any phy!\n", sc->sf_unit);
798 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF);
799 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
800 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
801 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
802 error = ENXIO;
803 goto fail;
804 }
805
806 ifp = &sc->arpcom.ac_if;
807 ifp->if_softc = sc;
808 ifp->if_unit = unit;
809 ifp->if_name = "sf";
810 ifp->if_mtu = ETHERMTU;
811 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
812 ifp->if_ioctl = sf_ioctl;
813 ifp->if_output = ether_output;
814 ifp->if_start = sf_start;
815 ifp->if_watchdog = sf_watchdog;
816 ifp->if_init = sf_init;
817 ifp->if_baudrate = 10000000;
818 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1;
819
820 /*
821 * Call MI attach routine.
822 */
823 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
824 SF_UNLOCK(sc);
825 return(0);
826
827fail:
828 SF_UNLOCK(sc);
829 mtx_destroy(&sc->sf_mtx);
830 return(error);
831}
832
833static int sf_detach(dev)
834 device_t dev;
835{
836 struct sf_softc *sc;
837 struct ifnet *ifp;
838
839 sc = device_get_softc(dev);
840 SF_LOCK(sc);
841 ifp = &sc->arpcom.ac_if;
842
843 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
844 sf_stop(sc);
845
846 bus_generic_detach(dev);
847 device_delete_child(dev, sc->sf_miibus);
848
849 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
850 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
851 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
852
853 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF);
854
855 SF_UNLOCK(sc);
856 mtx_destroy(&sc->sf_mtx);
857
858 return(0);
859}
860
861static int sf_init_rx_ring(sc)
862 struct sf_softc *sc;
863{
864 struct sf_list_data *ld;
865 int i;
866
867 ld = sc->sf_ldata;
868
869 bzero((char *)ld->sf_rx_dlist_big,
870 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT);
871 bzero((char *)ld->sf_rx_clist,
872 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT);
873
874 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
875 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS)
876 return(ENOBUFS);
877 }
878
879 return(0);
880}
881
882static void sf_init_tx_ring(sc)
883 struct sf_softc *sc;
884{
885 struct sf_list_data *ld;
886 int i;
887
888 ld = sc->sf_ldata;
889
890 bzero((char *)ld->sf_tx_dlist,
891 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT);
892 bzero((char *)ld->sf_tx_clist,
893 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT);
894
895 for (i = 0; i < SF_TX_DLIST_CNT; i++)
896 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID;
897 for (i = 0; i < SF_TX_CLIST_CNT; i++)
898 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX;
899
900 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1;
901 sc->sf_tx_cnt = 0;
902
903 return;
904}
905
906static int sf_newbuf(sc, c, m)
907 struct sf_softc *sc;
908 struct sf_rx_bufdesc_type0 *c;
909 struct mbuf *m;
910{
911 struct mbuf *m_new = NULL;
912
913 if (m == NULL) {
914 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
915 if (m_new == NULL) {
916 printf("sf%d: no memory for rx list -- "
917 "packet dropped!\n", sc->sf_unit);
918 return(ENOBUFS);
919 }
920
921 MCLGET(m_new, M_DONTWAIT);
922 if (!(m_new->m_flags & M_EXT)) {
923 printf("sf%d: no memory for rx list -- "
924 "packet dropped!\n", sc->sf_unit);
925 m_freem(m_new);
926 return(ENOBUFS);
927 }
928 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
929 } else {
930 m_new = m;
931 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
932 m_new->m_data = m_new->m_ext.ext_buf;
933 }
934
935 m_adj(m_new, sizeof(u_int64_t));
936
937 c->sf_mbuf = m_new;
938 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t)));
939 c->sf_valid = 1;
940
941 return(0);
942}
943
944/*
945 * The starfire is programmed to use 'normal' mode for packet reception,
946 * which means we use the consumer/producer model for both the buffer
947 * descriptor queue and the completion descriptor queue. The only problem
948 * with this is that it involves a lot of register accesses: we have to
949 * read the RX completion consumer and producer indexes and the RX buffer
950 * producer index, plus the RX completion consumer and RX buffer producer
951 * indexes have to be updated. It would have been easier if Adaptec had
952 * put each index in a separate register, especially given that the damn
953 * NIC has a 512K register space.
954 *
955 * In spite of all the lovely features that Adaptec crammed into the 6915,
956 * it is marred by one truly stupid design flaw, which is that receive
957 * buffer addresses must be aligned on a longword boundary. This forces
958 * the packet payload to be unaligned, which is suboptimal on the x86 and
959 * completely unuseable on the Alpha. Our only recourse is to copy received
960 * packets into properly aligned buffers before handing them off.
961 */
962
963static void sf_rxeof(sc)
964 struct sf_softc *sc;
965{
966 struct ether_header *eh;
967 struct mbuf *m;
968 struct ifnet *ifp;
969 struct sf_rx_bufdesc_type0 *desc;
970 struct sf_rx_cmpdesc_type3 *cur_rx;
971 u_int32_t rxcons, rxprod;
972 int cmpprodidx, cmpconsidx, bufprodidx;
973
974 ifp = &sc->arpcom.ac_if;
975
976 rxcons = csr_read_4(sc, SF_CQ_CONSIDX);
977 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1);
978 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX));
979 cmpconsidx = SF_IDX_LO(rxcons);
980 bufprodidx = SF_IDX_LO(rxprod);
981
982 while (cmpconsidx != cmpprodidx) {
983 struct mbuf *m0;
984
985 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx];
986 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx];
987 m = desc->sf_mbuf;
988 SF_INC(cmpconsidx, SF_RX_CLIST_CNT);
989 SF_INC(bufprodidx, SF_RX_DLIST_CNT);
990
991 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) {
992 ifp->if_ierrors++;
993 sf_newbuf(sc, desc, m);
994 continue;
995 }
996
997 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
998 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL);
999 sf_newbuf(sc, desc, m);
1000 if (m0 == NULL) {
1001 ifp->if_ierrors++;
1002 continue;
1003 }
1004 m_adj(m0, ETHER_ALIGN);
1005 m = m0;
1006
1007 eh = mtod(m, struct ether_header *);
1008 ifp->if_ipackets++;
1009
1010 /* Remove header from mbuf and pass it on. */
1011 m_adj(m, sizeof(struct ether_header));
1012 ether_input(ifp, eh, m);
1013 }
1014
1015 csr_write_4(sc, SF_CQ_CONSIDX,
1016 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx);
1017 csr_write_4(sc, SF_RXDQ_PTR_Q1,
1018 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx);
1019
1020 return;
1021}
1022
1023/*
1024 * Read the transmit status from the completion queue and release
1025 * mbufs. Note that the buffer descriptor index in the completion
1026 * descriptor is an offset from the start of the transmit buffer
1027 * descriptor list in bytes. This is important because the manual
1028 * gives the impression that it should match the producer/consumer
1029 * index, which is the offset in 8 byte blocks.
1030 */
1031static void sf_txeof(sc)
1032 struct sf_softc *sc;
1033{
1034 int txcons, cmpprodidx, cmpconsidx;
1035 struct sf_tx_cmpdesc_type1 *cur_cmp;
1036 struct sf_tx_bufdesc_type0 *cur_tx;
1037 struct ifnet *ifp;
1038
1039 ifp = &sc->arpcom.ac_if;
1040
1041 txcons = csr_read_4(sc, SF_CQ_CONSIDX);
1042 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX));
1043 cmpconsidx = SF_IDX_HI(txcons);
1044
1045 while (cmpconsidx != cmpprodidx) {
1046 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx];
1047 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7];
1048 SF_INC(cmpconsidx, SF_TX_CLIST_CNT);
1049
1050 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK)
1051 ifp->if_opackets++;
1052 else
1053 ifp->if_oerrors++;
1054
1055 sc->sf_tx_cnt--;
1056 if (cur_tx->sf_mbuf != NULL) {
1057 m_freem(cur_tx->sf_mbuf);
1058 cur_tx->sf_mbuf = NULL;
1059 }
1060 }
1061
1062 ifp->if_timer = 0;
1063 ifp->if_flags &= ~IFF_OACTIVE;
1064
1065 csr_write_4(sc, SF_CQ_CONSIDX,
1066 (txcons & ~SF_CQ_CONSIDX_TXQ) |
1067 ((cmpconsidx << 16) & 0xFFFF0000));
1068
1069 return;
1070}
1071
1072static void sf_intr(arg)
1073 void *arg;
1074{
1075 struct sf_softc *sc;
1076 struct ifnet *ifp;
1077 u_int32_t status;
1078
1079 sc = arg;
1080 SF_LOCK(sc);
1081
1082 ifp = &sc->arpcom.ac_if;
1083
1084 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) {
1085 SF_UNLOCK(sc);
1086 return;
1087 }
1088
1089 /* Disable interrupts. */
1090 csr_write_4(sc, SF_IMR, 0x00000000);
1091
1092 for (;;) {
1093 status = csr_read_4(sc, SF_ISR);
1094 if (status)
1095 csr_write_4(sc, SF_ISR, status);
1096
1097 if (!(status & SF_INTRS))
1098 break;
1099
1100 if (status & SF_ISR_RXDQ1_DMADONE)
1101 sf_rxeof(sc);
1102
1103 if (status & SF_ISR_TX_TXDONE)
1104 sf_txeof(sc);
1105
1106 if (status & SF_ISR_ABNORMALINTR) {
1107 if (status & SF_ISR_STATSOFLOW) {
1108 untimeout(sf_stats_update, sc,
1109 sc->sf_stat_ch);
1110 sf_stats_update(sc);
1111 } else
1112 sf_init(sc);
1113 }
1114 }
1115
1116 /* Re-enable interrupts. */
1117 csr_write_4(sc, SF_IMR, SF_INTRS);
1118
1119 if (ifp->if_snd.ifq_head != NULL)
1120 sf_start(ifp);
1121
1122 SF_UNLOCK(sc);
1123 return;
1124}
1125
1126static void sf_init(xsc)
1127 void *xsc;
1128{
1129 struct sf_softc *sc;
1130 struct ifnet *ifp;
1131 struct mii_data *mii;
1132 int i;
1133
1134 sc = xsc;
1135 SF_LOCK(sc);
1136 ifp = &sc->arpcom.ac_if;
1137 mii = device_get_softc(sc->sf_miibus);
1138
1139 sf_stop(sc);
1140 sf_reset(sc);
1141
1142 /* Init all the receive filter registers */
1143 for (i = SF_RXFILT_PERFECT_BASE;
1144 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
1145 csr_write_4(sc, i, 0);
1146
1147 /* Empty stats counter registers. */
1148 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++)
1149 csr_write_4(sc, SF_STATS_BASE +
1150 (i + sizeof(u_int32_t)), 0);
1151
1152 /* Init our MAC address */
1153 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1154 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1155 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr);
1156
1157 if (sf_init_rx_ring(sc) == ENOBUFS) {
1158 printf("sf%d: initialization failed: no "
1159 "memory for rx buffers\n", sc->sf_unit);
1160 SF_UNLOCK(sc);
1161 return;
1162 }
1163
1164 sf_init_tx_ring(sc);
1165
1166 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
1167
1168 /* If we want promiscuous mode, set the allframes bit. */
1169 if (ifp->if_flags & IFF_PROMISC) {
1170 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1171 } else {
1172 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1173 }
1174
1175 if (ifp->if_flags & IFF_BROADCAST) {
1176 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1177 } else {
1178 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1179 }
1180
1181 /*
1182 * Load the multicast filter.
1183 */
1184 sf_setmulti(sc);
1185
1186 /* Init the completion queue indexes */
1187 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1188 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1189
1190 /* Init the RX completion queue */
1191 csr_write_4(sc, SF_RXCQ_CTL_1,
1192 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR);
1193 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3);
1194
1195 /* Init RX DMA control. */
1196 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS);
1197
1198 /* Init the RX buffer descriptor queue. */
1199 csr_write_4(sc, SF_RXDQ_ADDR_Q1,
1200 vtophys(sc->sf_ldata->sf_rx_dlist_big));
1201 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
1202 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
1203
1204 /* Init the TX completion queue */
1205 csr_write_4(sc, SF_TXCQ_CTL,
1206 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR);
1207
1208 /* Init the TX buffer descriptor queue. */
1209 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
1210 vtophys(sc->sf_ldata->sf_tx_dlist));
1211 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX);
1212 csr_write_4(sc, SF_TXDQ_CTL,
1213 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES);
1214 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP);
1215
1216 /* Enable autopadding of short TX frames. */
1217 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
1218
1219 /* Enable interrupts. */
1220 csr_write_4(sc, SF_IMR, SF_INTRS);
1221 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
1222
1223 /* Enable the RX and TX engines. */
1224 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB);
1225 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB);
1226
1227 /*mii_mediachg(mii);*/
1228 sf_ifmedia_upd(ifp);
1229
1230 ifp->if_flags |= IFF_RUNNING;
1231 ifp->if_flags &= ~IFF_OACTIVE;
1232
1233 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
1234
1235 SF_UNLOCK(sc);
1236
1237 return;
1238}
1239
1240static int sf_encap(sc, c, m_head)
1241 struct sf_softc *sc;
1242 struct sf_tx_bufdesc_type0 *c;
1243 struct mbuf *m_head;
1244{
1245 int frag = 0;
1246 struct sf_frag *f = NULL;
1247 struct mbuf *m;
1248
1249 m = m_head;
1250
1251 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1252 if (m->m_len != 0) {
1253 if (frag == SF_MAXFRAGS)
1254 break;
1255 f = &c->sf_frags[frag];
1256 if (frag == 0)
1257 f->sf_pktlen = m_head->m_pkthdr.len;
1258 f->sf_fraglen = m->m_len;
1259 f->sf_addr = vtophys(mtod(m, vm_offset_t));
1260 frag++;
1261 }
1262 }
1263
1264 if (m != NULL) {
1265 struct mbuf *m_new = NULL;
1266
1267 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1268 if (m_new == NULL) {
1269 printf("sf%d: no memory for tx list", sc->sf_unit);
1270 return(1);
1271 }
1272
1273 if (m_head->m_pkthdr.len > MHLEN) {
1274 MCLGET(m_new, M_DONTWAIT);
1275 if (!(m_new->m_flags & M_EXT)) {
1276 m_freem(m_new);
1277 printf("sf%d: no memory for tx list",
1278 sc->sf_unit);
1279 return(1);
1280 }
1281 }
1282 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1283 mtod(m_new, caddr_t));
1284 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1285 m_freem(m_head);
1286 m_head = m_new;
1287 f = &c->sf_frags[0];
1288 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len;
1289 f->sf_addr = vtophys(mtod(m_head, caddr_t));
1290 frag = 1;
1291 }
1292
1293 c->sf_mbuf = m_head;
1294 c->sf_id = SF_TX_BUFDESC_ID;
1295 c->sf_fragcnt = frag;
1296 c->sf_intr = 1;
1297 c->sf_caltcp = 0;
1298 c->sf_crcen = 1;
1299
1300 return(0);
1301}
1302
1303static void sf_start(ifp)
1304 struct ifnet *ifp;
1305{
1306 struct sf_softc *sc;
1307 struct sf_tx_bufdesc_type0 *cur_tx = NULL;
1308 struct mbuf *m_head = NULL;
1309 int i, txprod;
1310
1311 sc = ifp->if_softc;
1312 SF_LOCK(sc);
1313
1314 if (!sc->sf_link) {
1315 SF_UNLOCK(sc);
1316 return;
1317 }
1318
1319 if (ifp->if_flags & IFF_OACTIVE) {
1320 SF_UNLOCK(sc);
1321 return;
1322 }
1323
1324 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1325 i = SF_IDX_HI(txprod) >> 4;
1326
1327 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) {
1328 if (sc->sf_tx_cnt == (SF_TX_DLIST_CNT - 2)) {
1329 ifp->if_flags |= IFF_OACTIVE;
1330 cur_tx = NULL;
1331 break;
1332 }
1333 IF_DEQUEUE(&ifp->if_snd, m_head);
1334 if (m_head == NULL)
1335 break;
1336
1337 cur_tx = &sc->sf_ldata->sf_tx_dlist[i];
1338 if (sf_encap(sc, cur_tx, m_head)) {
1339 IF_PREPEND(&ifp->if_snd, m_head);
1340 ifp->if_flags |= IFF_OACTIVE;
1341 cur_tx = NULL;
1342 break;
1343 }
1344
1345 /*
1346 * If there's a BPF listener, bounce a copy of this frame
1347 * to him.
1348 */
1349 if (ifp->if_bpf)
1350 bpf_mtap(ifp, m_head);
1351
1352 SF_INC(i, SF_TX_DLIST_CNT);
1353 sc->sf_tx_cnt++;
1354 }
1355
1356 if (cur_tx == NULL) {
1357 SF_UNLOCK(sc);
1358 return;
1359 }
1360
1361 /* Transmit */
1362 csr_write_4(sc, SF_TXDQ_PRODIDX,
1363 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) |
1364 ((i << 20) & 0xFFFF0000));
1365
1366 ifp->if_timer = 5;
1367
1368 SF_UNLOCK(sc);
1369
1370 return;
1371}
1372
1373static void sf_stop(sc)
1374 struct sf_softc *sc;
1375{
1376 int i;
1377 struct ifnet *ifp;
1378
1379 SF_LOCK(sc);
1380
1381 ifp = &sc->arpcom.ac_if;
1382
1383 untimeout(sf_stats_update, sc, sc->sf_stat_ch);
1384
1385 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
1386 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1387 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1388 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
1389 csr_write_4(sc, SF_RXDQ_CTL_1, 0);
1390 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
1391 csr_write_4(sc, SF_TXCQ_CTL, 0);
1392 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
1393 csr_write_4(sc, SF_TXDQ_CTL, 0);
1394 sf_reset(sc);
1395
1396 sc->sf_link = 0;
1397
1398 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1399 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) {
1400 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf);
1401 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL;
1402 }
1403 }
1404
1405 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1406 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1407 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf);
1408 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL;
1409 }
1410 }
1411
1412 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1413 SF_UNLOCK(sc);
1414
1415 return;
1416}
1417
1418/*
1419 * Note: it is important that this function not be interrupted. We
1420 * use a two-stage register access scheme: if we are interrupted in
1421 * between setting the indirect address register and reading from the
1422 * indirect data register, the contents of the address register could
1423 * be changed out from under us.
1424 */
1425static void sf_stats_update(xsc)
1426 void *xsc;
1427{
1428 struct sf_softc *sc;
1429 struct ifnet *ifp;
1430 struct mii_data *mii;
1431 struct sf_stats stats;
1432 u_int32_t *ptr;
1433 int i;
1434
1435 sc = xsc;
1436 SF_LOCK(sc);
1437 ifp = &sc->arpcom.ac_if;
1438 mii = device_get_softc(sc->sf_miibus);
1439
1440 ptr = (u_int32_t *)&stats;
1441 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1442 ptr[i] = csr_read_4(sc, SF_STATS_BASE +
1443 (i + sizeof(u_int32_t)));
1444
1445 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1446 csr_write_4(sc, SF_STATS_BASE +
1447 (i + sizeof(u_int32_t)), 0);
1448
1449 ifp->if_collisions += stats.sf_tx_single_colls +
1450 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls;
1451
1452 mii_tick(mii);
1453 if (!sc->sf_link) {
1454 mii_pollstat(mii);
1455 if (mii->mii_media_status & IFM_ACTIVE &&
1456 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1457 sc->sf_link++;
1458 if (ifp->if_snd.ifq_head != NULL)
1459 sf_start(ifp);
1460 }
1461
1462 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
1463
1464 SF_UNLOCK(sc);
1465
1466 return;
1467}
1468
1469static void sf_watchdog(ifp)
1470 struct ifnet *ifp;
1471{
1472 struct sf_softc *sc;
1473
1474 sc = ifp->if_softc;
1475
1476 SF_LOCK(sc);
1477
1478 ifp->if_oerrors++;
1479 printf("sf%d: watchdog timeout\n", sc->sf_unit);
1480
1481 sf_stop(sc);
1482 sf_reset(sc);
1483 sf_init(sc);
1484
1485 if (ifp->if_snd.ifq_head != NULL)
1486 sf_start(ifp);
1487
1488 SF_UNLOCK(sc);
1489
1490 return;
1491}
1492
1493static void sf_shutdown(dev)
1494 device_t dev;
1495{
1496 struct sf_softc *sc;
1497
1498 sc = device_get_softc(dev);
1499
1500 sf_stop(sc);
1501
1502 return;
1503}