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if_rl.c (117208) if_rl.c (117388)
1/*
1/*
2 * Copyright (c) 1997, 1998
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

--- 15 unchanged lines hidden (view full) ---

26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

--- 15 unchanged lines hidden (view full) ---

26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*
34 * RealTek 8129/8139 PCI NIC driver
34 * RealTek 8129/8139/8139C+/8169 PCI NIC driver
35 *
35 *
36 * Supports several extremely cheap PCI 10/100 adapters based on
37 * the RealTek chipset. Datasheets can be obtained from
36 * Supports several extremely cheap PCI 10/100 and 10/100/1000 adapters
37 * based on RealTek chipsets. Datasheets can be obtained from
38 * www.realtek.com.tw.
39 *
38 * www.realtek.com.tw.
39 *
40 * Written by Bill Paul <wpaul@ctr.columbia.edu>
41 * Electrical Engineering Department
42 * Columbia University, New York City
40 * Written by Bill Paul <wpaul@windriver.com>
41 * Senior Networking Software Engineer
42 * Wind River Systems
43 */
44
45/*
46 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
47 * probably the worst PCI ethernet controller ever made, with the possible
48 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
49 * DMA, but it has a terrible interface that nullifies any performance
50 * gains that bus-master DMA usually offers.

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74 * PHY registers are directly accessible through the 8139's register
75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
76 * filter.
77 *
78 * The 8129 chip is an older version of the 8139 that uses an external PHY
79 * chip. The 8129 has a serial MDIO interface for accessing the MII where
80 * the 8139 lets you directly access the on-board PHY registers. We need
81 * to select which interface to use depending on the chip type.
43 */
44
45/*
46 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
47 * probably the worst PCI ethernet controller ever made, with the possible
48 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
49 * DMA, but it has a terrible interface that nullifies any performance
50 * gains that bus-master DMA usually offers.

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74 * PHY registers are directly accessible through the 8139's register
75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
76 * filter.
77 *
78 * The 8129 chip is an older version of the 8139 that uses an external PHY
79 * chip. The 8129 has a serial MDIO interface for accessing the MII where
80 * the 8139 lets you directly access the on-board PHY registers. We need
81 * to select which interface to use depending on the chip type.
82 *
83 * Fast forward a few years. RealTek how has a new chip called the
84 * 8139C+ which at long last implements descriptor-based DMA. Not
85 * only that, in supports RX and TX TCP/IP checksum offload, VLAN
86 * tagging and insertion, TCP large send and 64-bit addressing.
87 * Better still, it allows arbitrary byte alignments for RX and
88 * TX buffers, meaning no copying is necessary on any architecture.
89 * There are a few limitations however: the RX and TX descriptor
90 * rings must be aligned on 256 byte boundaries, they must be in
91 * contiguous RAM, and each ring can have a maximum of 64 descriptors.
92 * There are two TX descriptor queues: one normal priority and one
93 * high. Descriptor ring addresses and DMA buffer addresses are
94 * 64 bits wide. The 8139C+ is also backwards compatible with the
95 * 8139, so the chip will still function with older drivers: C+
96 * mode has to be enabled by setting the appropriate bits in the C+
97 * command register. The PHY access mechanism appears to be unchanged.
98 *
99 * The 8169 is a 10/100/1000 ethernet MAC with built-in tri-speed
100 * copper PHY. It has almost the same programming API as the C+ mode
101 * of the 8139C+, with a couple of minor changes and additions: the
102 * TX start register is located at a different offset, and there are
103 * additional registers for GMII PHY status and control, as well as
104 * TBI-mode status and control. There is also a maximum RX packet
105 * size register to allow the chip to receive jumbo frames. The
106 * 8169 can only be programmed in C+ mode: the old 8139 programming
107 * method isn't supported with this chip. Also, RealTek has a LOM
108 * (LAN On Motherboard) gigabit MAC chip called the RTL8110S which
109 * I believe to be register compatible with the 8169.
110 *
111 * Unfortunately, RealTek has not released a programming manual for
112 * the 8169 or 8110 yet. The datasheet for the 8139C+ provides most
113 * of the information, but you must refer to RealTek's 8169 Linux
114 * driver to fill in the gaps.
115 *
116 * This driver now supports both the old 8139 and new 8139C+
117 * programming models. We detect the 8139C+ by looking for a PCI
118 * revision ID of 0x20 or higher, and we detect the 8169 by its
119 * PCI ID. Two new NIC type codes, RL_8139CPLUS and RL_8169 have
120 * been added to distinguish the chips at runtime. Separate RX and
121 * TX handling routines have been added to handle C+ mode, which
122 * are selected via function pointers that are initialized during
123 * the driver attach phase.
82 */
83
84#include <sys/cdefs.h>
124 */
125
126#include <sys/cdefs.h>
85__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 117208 2003-07-03 21:39:53Z imp $");
127__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 117388 2003-07-10 20:38:48Z wpaul $");
86
87#include <sys/param.h>
88#include <sys/endian.h>
89#include <sys/systm.h>
90#include <sys/sockio.h>
91#include <sys/mbuf.h>
92#include <sys/malloc.h>
93#include <sys/kernel.h>
94#include <sys/socket.h>
95
96#include <net/if.h>
97#include <net/if_arp.h>
98#include <net/ethernet.h>
99#include <net/if_dl.h>
100#include <net/if_media.h>
128
129#include <sys/param.h>
130#include <sys/endian.h>
131#include <sys/systm.h>
132#include <sys/sockio.h>
133#include <sys/mbuf.h>
134#include <sys/malloc.h>
135#include <sys/kernel.h>
136#include <sys/socket.h>
137
138#include <net/if.h>
139#include <net/if_arp.h>
140#include <net/ethernet.h>
141#include <net/if_dl.h>
142#include <net/if_media.h>
143#include <net/if_vlan_var.h>
101
102#include <net/bpf.h>
103
104#include <machine/bus_pio.h>
105#include <machine/bus_memio.h>
106#include <machine/bus.h>
107#include <machine/resource.h>
108#include <sys/bus.h>

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128 * can hang the bus. I'm inclined to blame this on crummy design/construction
129 * on the part of RealTek. Memory mapped mode does appear to work on
130 * uniprocessor systems though.
131 */
132#define RL_USEIOSPACE
133
134#include <pci/if_rlreg.h>
135
144
145#include <net/bpf.h>
146
147#include <machine/bus_pio.h>
148#include <machine/bus_memio.h>
149#include <machine/bus.h>
150#include <machine/resource.h>
151#include <sys/bus.h>

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171 * can hang the bus. I'm inclined to blame this on crummy design/construction
172 * on the part of RealTek. Memory mapped mode does appear to work on
173 * uniprocessor systems though.
174 */
175#define RL_USEIOSPACE
176
177#include <pci/if_rlreg.h>
178
136__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 117208 2003-07-03 21:39:53Z imp $");
179__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 117388 2003-07-10 20:38:48Z wpaul $");
137
180
181#define RL_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
182
138/*
139 * Various supported device vendors/types and their names.
140 */
141static struct rl_type rl_devs[] = {
183/*
184 * Various supported device vendors/types and their names.
185 */
186static struct rl_type rl_devs[] = {
142 { RT_VENDORID, RT_DEVICEID_8129,
187 { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
143 "RealTek 8129 10/100BaseTX" },
188 "RealTek 8129 10/100BaseTX" },
144 { RT_VENDORID, RT_DEVICEID_8139,
189 { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
145 "RealTek 8139 10/100BaseTX" },
190 "RealTek 8139 10/100BaseTX" },
146 { RT_VENDORID, RT_DEVICEID_8138,
191 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
147 "RealTek 8139 10/100BaseTX CardBus" },
192 "RealTek 8139 10/100BaseTX CardBus" },
148 { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
193 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
149 "Accton MPX 5030/5038 10/100BaseTX" },
194 "Accton MPX 5030/5038 10/100BaseTX" },
150 { DELTA_VENDORID, DELTA_DEVICEID_8139,
195 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
151 "Delta Electronics 8139 10/100BaseTX" },
196 "Delta Electronics 8139 10/100BaseTX" },
152 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
197 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
153 "Addtron Technolgy 8139 10/100BaseTX" },
198 "Addtron Technolgy 8139 10/100BaseTX" },
154 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS,
199 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
155 "D-Link DFE-530TX+ 10/100BaseTX" },
200 "D-Link DFE-530TX+ 10/100BaseTX" },
156 { DLINK_VENDORID, DLINK_DEVICEID_690TXD,
201 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
157 "D-Link DFE-690TXD 10/100BaseTX" },
202 "D-Link DFE-690TXD 10/100BaseTX" },
158 { NORTEL_VENDORID, ACCTON_DEVICEID_5030,
203 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
159 "Nortel Networks 10/100BaseTX" },
204 "Nortel Networks 10/100BaseTX" },
160 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD,
205 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
161 "Corega FEther CB-TXD" },
206 "Corega FEther CB-TXD" },
162 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD,
207 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
163 "Corega FEtherII CB-TXD" },
208 "Corega FEtherII CB-TXD" },
164 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF,
209 /* XXX what type of realtek is PEPPERCON_DEVICEID_ROLF ? */
210 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
165 "Peppercon AG ROL-F" },
211 "Peppercon AG ROL-F" },
166 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX,
212 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
167 "Planex FNW-3800-TX" },
213 "Planex FNW-3800-TX" },
214 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
215 "Compaq HNE-300" },
216 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
217 "LevelOne FPC-0106TX" },
218 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
219 "Edimax EP-4103DL CardBus" },
220 { 0, 0, 0, NULL }
221};
222
223static struct rl_hwrev rl_hwrevs[] = {
224 { RL_HWREV_8139, RL_8139, "" },
225 { RL_HWREV_8139A, RL_8139, "A" },
226 { RL_HWREV_8139AG, RL_8139, "A-G" },
227 { RL_HWREV_8139B, RL_8139, "B" },
228 { RL_HWREV_8130, RL_8139, "8130" },
229 { RL_HWREV_8139C, RL_8139, "C" },
230 { RL_HWREV_8139D, RL_8139, "D" },
231 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
168 { 0, 0, NULL }
169};
170
171static int rl_probe (device_t);
172static int rl_attach (device_t);
173static int rl_detach (device_t);
174
232 { 0, 0, NULL }
233};
234
235static int rl_probe (device_t);
236static int rl_attach (device_t);
237static int rl_detach (device_t);
238
175static int rl_encap (struct rl_softc *, struct mbuf * );
239static int rl_encap (struct rl_softc *, struct mbuf *);
240static int rl_encapcplus (struct rl_softc *, struct mbuf *, int *);
176
241
242static void rl_dma_map_addr (void *, bus_dma_segment_t *, int, int);
243static void rl_dma_map_desc (void *, bus_dma_segment_t *, int,
244 bus_size_t, int);
245static int rl_allocmem (device_t, struct rl_softc *);
246static int rl_allocmemcplus (device_t, struct rl_softc *);
247static int rl_newbuf (struct rl_softc *, int, struct mbuf *);
248static int rl_rx_list_init (struct rl_softc *);
249static int rl_tx_list_init (struct rl_softc *);
177static void rl_rxeof (struct rl_softc *);
250static void rl_rxeof (struct rl_softc *);
251static void rl_rxeofcplus (struct rl_softc *);
178static void rl_txeof (struct rl_softc *);
252static void rl_txeof (struct rl_softc *);
253static void rl_txeofcplus (struct rl_softc *);
179static void rl_intr (void *);
254static void rl_intr (void *);
255static void rl_intrcplus (void *);
180static void rl_tick (void *);
181static void rl_start (struct ifnet *);
256static void rl_tick (void *);
257static void rl_start (struct ifnet *);
258static void rl_startcplus (struct ifnet *);
182static int rl_ioctl (struct ifnet *, u_long, caddr_t);
183static void rl_init (void *);
184static void rl_stop (struct rl_softc *);
185static void rl_watchdog (struct ifnet *);
186static int rl_suspend (device_t);
187static int rl_resume (device_t);
188static void rl_shutdown (device_t);
189static int rl_ifmedia_upd (struct ifnet *);

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598 struct rl_softc *sc;
599 struct rl_mii_frame frame;
600 u_int16_t rval = 0;
601 u_int16_t rl8139_reg = 0;
602
603 sc = device_get_softc(dev);
604 RL_LOCK(sc);
605
259static int rl_ioctl (struct ifnet *, u_long, caddr_t);
260static void rl_init (void *);
261static void rl_stop (struct rl_softc *);
262static void rl_watchdog (struct ifnet *);
263static int rl_suspend (device_t);
264static int rl_resume (device_t);
265static void rl_shutdown (device_t);
266static int rl_ifmedia_upd (struct ifnet *);

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675 struct rl_softc *sc;
676 struct rl_mii_frame frame;
677 u_int16_t rval = 0;
678 u_int16_t rl8139_reg = 0;
679
680 sc = device_get_softc(dev);
681 RL_LOCK(sc);
682
606 if (sc->rl_type == RL_8139) {
683 if (sc->rl_type == RL_8139 || sc->rl_type == RL_8139CPLUS) {
607 /* Pretend the internal PHY is only at address 0 */
608 if (phy) {
609 RL_UNLOCK(sc);
610 return(0);
611 }
612 switch(reg) {
613 case MII_BMCR:
614 rl8139_reg = RL_BMCR;

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666{
667 struct rl_softc *sc;
668 struct rl_mii_frame frame;
669 u_int16_t rl8139_reg = 0;
670
671 sc = device_get_softc(dev);
672 RL_LOCK(sc);
673
684 /* Pretend the internal PHY is only at address 0 */
685 if (phy) {
686 RL_UNLOCK(sc);
687 return(0);
688 }
689 switch(reg) {
690 case MII_BMCR:
691 rl8139_reg = RL_BMCR;

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743{
744 struct rl_softc *sc;
745 struct rl_mii_frame frame;
746 u_int16_t rl8139_reg = 0;
747
748 sc = device_get_softc(dev);
749 RL_LOCK(sc);
750
674 if (sc->rl_type == RL_8139) {
751 if (sc->rl_type == RL_8139 || sc->rl_type == RL_8139CPLUS) {
675 /* Pretend the internal PHY is only at address 0 */
676 if (phy) {
677 RL_UNLOCK(sc);
678 return(0);
679 }
680 switch(reg) {
681 case MII_BMCR:
682 rl8139_reg = RL_BMCR;

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833 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
834 * IDs against our list and return a device name if we find a match.
835 */
836static int
837rl_probe(dev)
838 device_t dev;
839{
840 struct rl_type *t;
752 /* Pretend the internal PHY is only at address 0 */
753 if (phy) {
754 RL_UNLOCK(sc);
755 return(0);
756 }
757 switch(reg) {
758 case MII_BMCR:
759 rl8139_reg = RL_BMCR;

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910 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
911 * IDs against our list and return a device name if we find a match.
912 */
913static int
914rl_probe(dev)
915 device_t dev;
916{
917 struct rl_type *t;
918 struct rl_softc *sc;
919 struct rl_hwrev *hw_rev;
920 int rid;
921 u_int32_t hwrev;
922 char desc[64];
841
842 t = rl_devs;
923
924 t = rl_devs;
925 sc = device_get_softc(dev);
843
844 while(t->rl_name != NULL) {
845 if ((pci_get_vendor(dev) == t->rl_vid) &&
846 (pci_get_device(dev) == t->rl_did)) {
926
927 while(t->rl_name != NULL) {
928 if ((pci_get_vendor(dev) == t->rl_vid) &&
929 (pci_get_device(dev) == t->rl_did)) {
847 device_set_desc(dev, t->rl_name);
930
931 /*
932 * Temporarily map the I/O space
933 * so we can read the chip ID register.
934 */
935 rid = RL_RID;
936 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid,
937 0, ~0, 1, RF_ACTIVE);
938 if (sc->rl_res == NULL) {
939 device_printf(dev,
940 "couldn't map ports/memory\n");
941 return(ENXIO);
942 }
943 sc->rl_btag = rman_get_bustag(sc->rl_res);
944 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
945 mtx_init(&sc->rl_mtx,
946 device_get_nameunit(dev),
947 MTX_NETWORK_LOCK, MTX_DEF);
948 RL_LOCK(sc);
949 if (t->rl_basetype == RL_8139) {
950 hwrev = CSR_READ_4(sc, RL_TXCFG) &
951 RL_TXCFG_HWREV;
952 hw_rev = rl_hwrevs;
953 while (hw_rev->rl_desc != NULL) {
954 if (hw_rev->rl_rev == hwrev) {
955 sprintf(desc, "%s, rev. %s",
956 t->rl_name,
957 hw_rev->rl_desc);
958 sc->rl_type = hw_rev->rl_type;
959 break;
960 }
961 hw_rev++;
962 }
963 if (hw_rev->rl_desc == NULL)
964 sprintf(desc, "%s, rev. %s",
965 t->rl_name, "unknown");
966 }
967 bus_release_resource(dev, RL_RES,
968 RL_RID, sc->rl_res);
969 RL_UNLOCK(sc);
970 mtx_destroy(&sc->rl_mtx);
971 device_set_desc_copy(dev, desc);
848 return(0);
849 }
850 t++;
851 }
852
853 return(ENXIO);
854}
855
856/*
972 return(0);
973 }
974 t++;
975 }
976
977 return(ENXIO);
978}
979
980/*
981 * This routine takes the segment list provided as the result of
982 * a bus_dma_map_load() operation and assigns the addresses/lengths
983 * to RealTek DMA descriptors. This can be called either by the RX
984 * code or the TX code. In the RX case, we'll probably wind up mapping
985 * at most one segment. For the TX case, there could be any number of
986 * segments since TX packets may span multiple mbufs. In either case,
987 * if the number of segments is larger than the rl_maxsegs limit
988 * specified by the caller, we abort the mapping operation. Sadly,
989 * whoever designed the buffer mapping API did not provide a way to
990 * return an error from here, so we have to fake it a bit.
991 */
992
993static void
994rl_dma_map_desc(arg, segs, nseg, mapsize, error)
995 void *arg;
996 bus_dma_segment_t *segs;
997 int nseg;
998 bus_size_t mapsize;
999 int error;
1000{
1001 struct rl_dmaload_arg *ctx;
1002 struct rl_desc *d = NULL;
1003 int i = 0, idx;
1004
1005 if (error)
1006 return;
1007
1008 ctx = arg;
1009
1010 /* Signal error to caller if there's too many segments */
1011 if (nseg > ctx->rl_maxsegs) {
1012 ctx->rl_maxsegs = 0;
1013 return;
1014 }
1015
1016 /*
1017 * Map the segment array into descriptors. Note that we set the
1018 * start-of-frame and end-of-frame markers for either TX or RX, but
1019 * they really only have meaning in the TX case. (In the RX case,
1020 * it's the chip that tells us where packets begin and end.)
1021 * We also keep track of the end of the ring and set the
1022 * end-of-ring bits as needed, and we set the ownership bits
1023 * in all except the very first descriptor. (The caller will
1024 * set this descriptor later when it start transmission or
1025 * reception.)
1026 */
1027 idx = ctx->rl_idx;
1028 while(1) {
1029 u_int32_t cmdstat;
1030 d = &ctx->rl_ring[idx];
1031 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) {
1032 ctx->rl_maxsegs = 0;
1033 return;
1034 }
1035 cmdstat = segs[i].ds_len;
1036 d->rl_bufaddr_lo = htole32(segs[i].ds_addr);
1037 d->rl_bufaddr_hi = 0;
1038 if (i == 0)
1039 cmdstat |= RL_TDESC_CMD_SOF;
1040 else
1041 cmdstat |= RL_TDESC_CMD_OWN;
1042 if (idx == RL_RX_DESC_CNT)
1043 cmdstat |= RL_TDESC_CMD_EOR;
1044 d->rl_cmdstat = htole32(cmdstat);
1045 i++;
1046 if (i == nseg)
1047 break;
1048 RL_DESC_INC(idx);
1049 }
1050
1051 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
1052 ctx->rl_maxsegs = nseg;
1053 ctx->rl_idx = idx;
1054
1055 return;
1056}
1057
1058/*
1059 * Map a single buffer address.
1060 */
1061
1062static void
1063rl_dma_map_addr(arg, segs, nseg, error)
1064 void *arg;
1065 bus_dma_segment_t *segs;
1066 int nseg;
1067 int error;
1068{
1069 u_int32_t *addr;
1070
1071 if (error)
1072 return;
1073
1074 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
1075 addr = arg;
1076 *addr = segs->ds_addr;
1077
1078 return;
1079}
1080
1081static int
1082rl_allocmem(dev, sc)
1083 device_t dev;
1084 struct rl_softc *sc;
1085{
1086 int error;
1087
1088 /*
1089 * Now allocate a tag for the DMA descriptor lists.
1090 * All of our lists are allocated as a contiguous block
1091 * of memory.
1092 */
1093 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
1094 1, 0, /* alignment, boundary */
1095 BUS_SPACE_MAXADDR, /* lowaddr */
1096 BUS_SPACE_MAXADDR, /* highaddr */
1097 NULL, NULL, /* filter, filterarg */
1098 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */
1099 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1100 0, /* flags */
1101 NULL, NULL, /* lockfunc, lockarg */
1102 &sc->rl_tag);
1103 if (error)
1104 return(error);
1105
1106 /*
1107 * Now allocate a chunk of DMA-able memory based on the
1108 * tag we just created.
1109 */
1110 error = bus_dmamem_alloc(sc->rl_tag,
1111 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT,
1112 &sc->rl_cdata.rl_rx_dmamap);
1113
1114 if (error) {
1115 printf("rl%d: no memory for list buffers!\n", sc->rl_unit);
1116 bus_dma_tag_destroy(sc->rl_tag);
1117 sc->rl_tag = NULL;
1118 return(error);
1119 }
1120
1121 /* Leave a few bytes before the start of the RX ring buffer. */
1122 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1123 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
1124
1125 return(0);
1126}
1127
1128static int
1129rl_allocmemcplus(dev, sc)
1130 device_t dev;
1131 struct rl_softc *sc;
1132{
1133 int error;
1134 int nseg;
1135 int i;
1136
1137 /*
1138 * Allocate map for RX mbufs.
1139 */
1140 nseg = 32;
1141 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0,
1142 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1143 NULL, MCLBYTES * nseg, nseg, MCLBYTES, 0, NULL, NULL,
1144 &sc->rl_ldata.rl_mtag);
1145 if (error) {
1146 device_printf(dev, "could not allocate dma tag\n");
1147 return (ENOMEM);
1148 }
1149
1150 /*
1151 * Allocate map for TX descriptor list.
1152 */
1153 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1154 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1155 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, 0, NULL, NULL,
1156 &sc->rl_ldata.rl_tx_list_tag);
1157 if (error) {
1158 device_printf(dev, "could not allocate dma tag\n");
1159 return (ENOMEM);
1160 }
1161
1162 /* Allocate DMA'able memory for the TX ring */
1163
1164 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1165 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT,
1166 &sc->rl_ldata.rl_tx_list_map);
1167 if (error)
1168 return (ENOMEM);
1169
1170 bzero((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ);
1171
1172 /* Load the map for the TX ring. */
1173
1174 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1175 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1176 RL_TX_LIST_SZ, rl_dma_map_addr,
1177 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1178
1179 /* Create DMA maps for TX buffers */
1180
1181 for (i = 0; i < RL_TX_DESC_CNT; i++) {
1182 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1183 &sc->rl_ldata.rl_tx_dmamap[i]);
1184 if (error) {
1185 device_printf(dev, "can't create DMA map for TX\n");
1186 return(ENOMEM);
1187 }
1188 }
1189
1190 /*
1191 * Allocate map for RX descriptor list.
1192 */
1193 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1194 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1195 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, 0, NULL, NULL,
1196 &sc->rl_ldata.rl_rx_list_tag);
1197 if (error) {
1198 device_printf(dev, "could not allocate dma tag\n");
1199 return (ENOMEM);
1200 }
1201
1202 /* Allocate DMA'able memory for the RX ring */
1203
1204 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1205 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT,
1206 &sc->rl_ldata.rl_rx_list_map);
1207 if (error)
1208 return (ENOMEM);
1209
1210 bzero((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ);
1211
1212 /* Load the map for the RX ring. */
1213
1214 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1215 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1216 RL_TX_LIST_SZ, rl_dma_map_addr,
1217 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1218
1219 /* Create DMA maps for RX buffers */
1220
1221 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1222 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1223 &sc->rl_ldata.rl_rx_dmamap[i]);
1224 if (error) {
1225 device_printf(dev, "can't create DMA map for RX\n");
1226 return(ENOMEM);
1227 }
1228 }
1229
1230 return(0);
1231}
1232
1233/*
857 * Attach the interface. Allocate softc structures, do ifmedia
858 * setup and ethernet/BPF attach.
859 */
860static int
861rl_attach(dev)
862 device_t dev;
863{
864 u_char eaddr[ETHER_ADDR_LEN];
865 u_int16_t as[3];
866 struct rl_softc *sc;
867 struct ifnet *ifp;
1234 * Attach the interface. Allocate softc structures, do ifmedia
1235 * setup and ethernet/BPF attach.
1236 */
1237static int
1238rl_attach(dev)
1239 device_t dev;
1240{
1241 u_char eaddr[ETHER_ADDR_LEN];
1242 u_int16_t as[3];
1243 struct rl_softc *sc;
1244 struct ifnet *ifp;
1245 struct rl_type *t;
1246 struct rl_hwrev *hw_rev;
1247 int hwrev;
868 u_int16_t rl_did = 0;
869 int unit, error = 0, rid, i;
870
871 sc = device_get_softc(dev);
872 unit = device_get_unit(dev);
873
874 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
875 MTX_DEF | MTX_RECURSE);

--- 33 unchanged lines hidden (view full) ---

909 0, ~0, 1, RF_ACTIVE);
910
911 if (sc->rl_res == NULL) {
912 printf ("rl%d: couldn't map ports/memory\n", unit);
913 error = ENXIO;
914 goto fail;
915 }
916
1248 u_int16_t rl_did = 0;
1249 int unit, error = 0, rid, i;
1250
1251 sc = device_get_softc(dev);
1252 unit = device_get_unit(dev);
1253
1254 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1255 MTX_DEF | MTX_RECURSE);

--- 33 unchanged lines hidden (view full) ---

1289 0, ~0, 1, RF_ACTIVE);
1290
1291 if (sc->rl_res == NULL) {
1292 printf ("rl%d: couldn't map ports/memory\n", unit);
1293 error = ENXIO;
1294 goto fail;
1295 }
1296
1297#ifdef notdef
917 /* Detect the Realtek 8139B. For some reason, this chip is very
918 * unstable when left to autoselect the media
919 * The best workaround is to set the device to the required
920 * media type or to set it to the 10 Meg speed.
921 */
922
923 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) {
1298 /* Detect the Realtek 8139B. For some reason, this chip is very
1299 * unstable when left to autoselect the media
1300 * The best workaround is to set the device to the required
1301 * media type or to set it to the 10 Meg speed.
1302 */
1303
1304 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) {
924 printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit);
1305 printf("rl%d: Realtek 8139B detected. Warning,"
1306 " this may be unstable in autoselect mode\n", unit);
925 }
1307 }
1308#endif
926
927 sc->rl_btag = rman_get_bustag(sc->rl_res);
928 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
929
930 /* Allocate interrupt */
931 rid = 0;
932 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
933 RF_SHAREABLE | RF_ACTIVE);

--- 29 unchanged lines hidden (view full) ---

963 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
964
965 /*
966 * Now read the exact device type from the EEPROM to find
967 * out if it's an 8129 or 8139.
968 */
969 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
970
1309
1310 sc->rl_btag = rman_get_bustag(sc->rl_res);
1311 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1312
1313 /* Allocate interrupt */
1314 rid = 0;
1315 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1316 RF_SHAREABLE | RF_ACTIVE);

--- 29 unchanged lines hidden (view full) ---

1346 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1347
1348 /*
1349 * Now read the exact device type from the EEPROM to find
1350 * out if it's an 8129 or 8139.
1351 */
1352 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
1353
971 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
972 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 ||
973 rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS ||
974 rl_did == DLINK_DEVICEID_690TXD ||
975 rl_did == COREGA_DEVICEID_FETHERCBTXD ||
976 rl_did == COREGA_DEVICEID_FETHERIICBTXD ||
977 rl_did == PLANEX_DEVICEID_FNW3800TX)
978 sc->rl_type = RL_8139;
979 else if (rl_did == RT_DEVICEID_8129)
980 sc->rl_type = RL_8129;
981 else {
1354 t = rl_devs;
1355 while(t->rl_name != NULL) {
1356 if (rl_did == t->rl_did) {
1357 sc->rl_type = t->rl_basetype;
1358 break;
1359 }
1360 t++;
1361 }
1362 if (t->rl_name == NULL) {
982 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
983 error = ENXIO;
984 goto fail;
985 }
1363 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
1364 error = ENXIO;
1365 goto fail;
1366 }
1367 if (sc->rl_type == RL_8139) {
1368 hw_rev = rl_hwrevs;
1369 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
1370 while (hw_rev->rl_desc != NULL) {
1371 if (hw_rev->rl_rev == hwrev) {
1372 sc->rl_type = hw_rev->rl_type;
1373 break;
1374 }
1375 hw_rev++;
1376 }
1377 if (hw_rev->rl_desc == NULL) {
1378 printf("rl%d: unknown hwrev: %x\n", unit, hwrev);
1379 }
1380 } else if (rl_did == RT_DEVICEID_8129) {
1381 sc->rl_type = RL_8129;
1382 } else if (rl_did == RT_DEVICEID_8169) {
1383 sc->rl_type = RL_8169;
1384 }
986
987 /*
988 * Allocate the parent bus DMA tag appropriate for PCI.
989 */
990#define RL_NSEG_NEW 32
991 error = bus_dma_tag_create(NULL, /* parent */
992 1, 0, /* alignment, boundary */
993 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
994 BUS_SPACE_MAXADDR, /* highaddr */
995 NULL, NULL, /* filter, filterarg */
996 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
997 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
998 BUS_DMA_ALLOCNOW, /* flags */
999 NULL, NULL, /* lockfunc, lockarg */
1000 &sc->rl_parent_tag);
1001 if (error)
1002 goto fail;
1003
1004 /*
1385
1386 /*
1387 * Allocate the parent bus DMA tag appropriate for PCI.
1388 */
1389#define RL_NSEG_NEW 32
1390 error = bus_dma_tag_create(NULL, /* parent */
1391 1, 0, /* alignment, boundary */
1392 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1393 BUS_SPACE_MAXADDR, /* highaddr */
1394 NULL, NULL, /* filter, filterarg */
1395 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
1396 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1397 BUS_DMA_ALLOCNOW, /* flags */
1398 NULL, NULL, /* lockfunc, lockarg */
1399 &sc->rl_parent_tag);
1400 if (error)
1401 goto fail;
1402
1403 /*
1005 * Now allocate a tag for the DMA descriptor lists.
1006 * All of our lists are allocated as a contiguous block
1007 * of memory.
1404 * If this is an 8139C+ or 8169 chip, we have to allocate
1405 * our busdma tags/memory differently. We need to allocate
1406 * a chunk of DMA'able memory for the RX and TX descriptor
1407 * lists.
1008 */
1408 */
1009 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
1010 1, 0, /* alignment, boundary */
1011 BUS_SPACE_MAXADDR, /* lowaddr */
1012 BUS_SPACE_MAXADDR, /* highaddr */
1013 NULL, NULL, /* filter, filterarg */
1014 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */
1015 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1016 0, /* flags */
1017 busdma_lock_mutex, /* lockfunc */
1018 &Giant, /* lockarg */
1019 &sc->rl_tag);
1409 if (sc->rl_type == RL_8139CPLUS || sc->rl_type == RL_8169)
1410 error = rl_allocmemcplus(dev, sc);
1411 else
1412 error = rl_allocmem(dev, sc);
1413
1020 if (error)
1021 goto fail;
1022
1414 if (error)
1415 goto fail;
1416
1023 /*
1024 * Now allocate a chunk of DMA-able memory based on the
1025 * tag we just created.
1026 */
1027 error = bus_dmamem_alloc(sc->rl_tag,
1028 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT,
1029 &sc->rl_cdata.rl_rx_dmamap);
1030
1031 if (error) {
1032 printf("rl%d: no memory for list buffers!\n", unit);
1033 bus_dma_tag_destroy(sc->rl_tag);
1034 sc->rl_tag = NULL;
1035 goto fail;
1036 }
1037
1038 /* Leave a few bytes before the start of the RX ring buffer. */
1039 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1040 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
1041
1042 /* Do MII setup */
1043 if (mii_phy_probe(dev, &sc->rl_miibus,
1044 rl_ifmedia_upd, rl_ifmedia_sts)) {
1045 printf("rl%d: MII without any phy!\n", sc->rl_unit);
1046 error = ENXIO;
1047 goto fail;
1048 }
1049
1050 ifp = &sc->arpcom.ac_if;
1051 ifp->if_softc = sc;
1052 ifp->if_unit = unit;
1053 ifp->if_name = "rl";
1054 ifp->if_mtu = ETHERMTU;
1055 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1056 ifp->if_ioctl = rl_ioctl;
1057 ifp->if_output = ether_output;
1417 /* Do MII setup */
1418 if (mii_phy_probe(dev, &sc->rl_miibus,
1419 rl_ifmedia_upd, rl_ifmedia_sts)) {
1420 printf("rl%d: MII without any phy!\n", sc->rl_unit);
1421 error = ENXIO;
1422 goto fail;
1423 }
1424
1425 ifp = &sc->arpcom.ac_if;
1426 ifp->if_softc = sc;
1427 ifp->if_unit = unit;
1428 ifp->if_name = "rl";
1429 ifp->if_mtu = ETHERMTU;
1430 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1431 ifp->if_ioctl = rl_ioctl;
1432 ifp->if_output = ether_output;
1058 ifp->if_start = rl_start;
1433 ifp->if_capabilities = IFCAP_VLAN_MTU;
1434 if (RL_ISCPLUS(sc)) {
1435 ifp->if_start = rl_startcplus;
1436 ifp->if_hwassist = RL_CSUM_FEATURES;
1437 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1438 } else
1439 ifp->if_start = rl_start;
1059 ifp->if_watchdog = rl_watchdog;
1060 ifp->if_init = rl_init;
1061 ifp->if_baudrate = 10000000;
1440 ifp->if_watchdog = rl_watchdog;
1441 ifp->if_init = rl_init;
1442 ifp->if_baudrate = 10000000;
1062 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1443 ifp->if_snd.ifq_maxlen = RL_IFQ_MAXLEN;
1444 ifp->if_capenable = ifp->if_capabilities;
1063
1064 callout_handle_init(&sc->rl_stat_ch);
1065
1066 /*
1067 * Call MI attach routine.
1068 */
1069 ether_ifattach(ifp, eaddr);
1070
1071 /* Hook interrupt last to avoid having to lock softc */
1072 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
1445
1446 callout_handle_init(&sc->rl_stat_ch);
1447
1448 /*
1449 * Call MI attach routine.
1450 */
1451 ether_ifattach(ifp, eaddr);
1452
1453 /* Hook interrupt last to avoid having to lock softc */
1454 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
1073 rl_intr, sc, &sc->rl_intrhand);
1455 RL_ISCPLUS(sc) ? rl_intrcplus : rl_intr, sc, &sc->rl_intrhand);
1074
1075 if (error) {
1076 printf("rl%d: couldn't set up irq\n", unit);
1077 ether_ifdetach(ifp);
1078 goto fail;
1079 }
1080
1081fail:

--- 11 unchanged lines hidden (view full) ---

1093 * allocated.
1094 */
1095static int
1096rl_detach(dev)
1097 device_t dev;
1098{
1099 struct rl_softc *sc;
1100 struct ifnet *ifp;
1456
1457 if (error) {
1458 printf("rl%d: couldn't set up irq\n", unit);
1459 ether_ifdetach(ifp);
1460 goto fail;
1461 }
1462
1463fail:

--- 11 unchanged lines hidden (view full) ---

1475 * allocated.
1476 */
1477static int
1478rl_detach(dev)
1479 device_t dev;
1480{
1481 struct rl_softc *sc;
1482 struct ifnet *ifp;
1483 int i;
1101
1102 sc = device_get_softc(dev);
1103 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
1104 RL_LOCK(sc);
1105 ifp = &sc->arpcom.ac_if;
1106
1107 /* These should only be active if attach succeeded */
1108 if (device_is_attached(dev)) {

--- 6 unchanged lines hidden (view full) ---

1115
1116 if (sc->rl_intrhand)
1117 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1118 if (sc->rl_irq)
1119 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1120 if (sc->rl_res)
1121 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1122
1484
1485 sc = device_get_softc(dev);
1486 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
1487 RL_LOCK(sc);
1488 ifp = &sc->arpcom.ac_if;
1489
1490 /* These should only be active if attach succeeded */
1491 if (device_is_attached(dev)) {

--- 6 unchanged lines hidden (view full) ---

1498
1499 if (sc->rl_intrhand)
1500 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1501 if (sc->rl_irq)
1502 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1503 if (sc->rl_res)
1504 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1505
1123 if (sc->rl_tag) {
1124 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1125 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
1126 sc->rl_cdata.rl_rx_dmamap);
1127 bus_dma_tag_destroy(sc->rl_tag);
1506 if (RL_ISCPLUS(sc)) {
1507
1508 /* Unload and free the RX DMA ring memory and map */
1509
1510 if (sc->rl_ldata.rl_rx_list_tag) {
1511 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1512 sc->rl_ldata.rl_rx_list_map);
1513 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1514 sc->rl_ldata.rl_rx_list,
1515 sc->rl_ldata.rl_rx_list_map);
1516 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1517 }
1518
1519 /* Unload and free the TX DMA ring memory and map */
1520
1521 if (sc->rl_ldata.rl_tx_list_tag) {
1522 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1523 sc->rl_ldata.rl_tx_list_map);
1524 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1525 sc->rl_ldata.rl_tx_list,
1526 sc->rl_ldata.rl_tx_list_map);
1527 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1528 }
1529
1530 /* Destroy all the RX and TX buffer maps */
1531
1532 if (sc->rl_ldata.rl_mtag) {
1533 for (i = 0; i < RL_TX_DESC_CNT; i++)
1534 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1535 sc->rl_ldata.rl_tx_dmamap[i]);
1536 for (i = 0; i < RL_RX_DESC_CNT; i++)
1537 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1538 sc->rl_ldata.rl_rx_dmamap[i]);
1539 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag);
1540 }
1541
1542 /* Unload and free the stats buffer and map */
1543
1544 if (sc->rl_ldata.rl_stag) {
1545 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1546 sc->rl_ldata.rl_rx_list_map);
1547 bus_dmamem_free(sc->rl_ldata.rl_stag,
1548 sc->rl_ldata.rl_stats,
1549 sc->rl_ldata.rl_smap);
1550 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1551 }
1552
1553 } else {
1554 if (sc->rl_tag) {
1555 bus_dmamap_unload(sc->rl_tag,
1556 sc->rl_cdata.rl_rx_dmamap);
1557 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
1558 sc->rl_cdata.rl_rx_dmamap);
1559 bus_dma_tag_destroy(sc->rl_tag);
1560 }
1128 }
1561 }
1562
1129 if (sc->rl_parent_tag)
1130 bus_dma_tag_destroy(sc->rl_parent_tag);
1131
1132 RL_UNLOCK(sc);
1133 mtx_destroy(&sc->rl_mtx);
1134
1135 return(0);
1136}

--- 16 unchanged lines hidden (view full) ---

1153 }
1154
1155 sc->rl_cdata.cur_tx = 0;
1156 sc->rl_cdata.last_tx = 0;
1157
1158 return(0);
1159}
1160
1563 if (sc->rl_parent_tag)
1564 bus_dma_tag_destroy(sc->rl_parent_tag);
1565
1566 RL_UNLOCK(sc);
1567 mtx_destroy(&sc->rl_mtx);
1568
1569 return(0);
1570}

--- 16 unchanged lines hidden (view full) ---

1587 }
1588
1589 sc->rl_cdata.cur_tx = 0;
1590 sc->rl_cdata.last_tx = 0;
1591
1592 return(0);
1593}
1594
1595static int
1596rl_newbuf (sc, idx, m)
1597 struct rl_softc *sc;
1598 int idx;
1599 struct mbuf *m;
1600{
1601 struct rl_dmaload_arg arg;
1602 struct mbuf *n = NULL;
1603 int error;
1604
1605 if (m == NULL) {
1606 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1607 if (n == NULL)
1608 return(ENOBUFS);
1609 m = n;
1610 } else
1611 m->m_data = m->m_ext.ext_buf;
1612
1613 /*
1614 * Initialize mbuf length fields and fixup
1615 * alignment so that the frame payload is
1616 * longword aligned.
1617 */
1618 m->m_len = m->m_pkthdr.len = 1536;
1619 m_adj(m, ETHER_ALIGN);
1620
1621 arg.sc = sc;
1622 arg.rl_idx = idx;
1623 arg.rl_maxsegs = 1;
1624 arg.rl_ring = sc->rl_ldata.rl_rx_list;
1625
1626 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag,
1627 sc->rl_ldata.rl_rx_dmamap[idx], m, rl_dma_map_desc,
1628 &arg, BUS_DMA_NOWAIT);
1629 if (error || arg.rl_maxsegs != 1) {
1630 if (n != NULL)
1631 m_freem(n);
1632 return (ENOMEM);
1633 }
1634
1635 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN);
1636 sc->rl_ldata.rl_rx_mbuf[idx] = m;
1637
1638 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1639 sc->rl_ldata.rl_rx_dmamap[idx],
1640 BUS_DMASYNC_PREREAD);
1641
1642 return(0);
1643}
1644
1645static int
1646rl_tx_list_init(sc)
1647 struct rl_softc *sc;
1648{
1649 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ);
1650 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf,
1651 (RL_TX_DESC_CNT * sizeof(struct mbuf *)));
1652
1653 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1654 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE);
1655 sc->rl_ldata.rl_tx_prodidx = 0;
1656 sc->rl_ldata.rl_tx_considx = 0;
1657 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT;
1658
1659 return(0);
1660}
1661
1662static int
1663rl_rx_list_init(sc)
1664 struct rl_softc *sc;
1665{
1666 int i;
1667
1668 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ);
1669 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf,
1670 (RL_RX_DESC_CNT * sizeof(struct mbuf *)));
1671
1672 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1673 if (rl_newbuf(sc, i, NULL) == ENOBUFS)
1674 return(ENOBUFS);
1675 }
1676
1677 /* Flush the RX descriptors */
1678
1679 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1680 sc->rl_ldata.rl_rx_list_map,
1681 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1682
1683 sc->rl_ldata.rl_rx_prodidx = 0;
1684
1685 return(0);
1686}
1687
1161/*
1688/*
1689 * RX handler for C+. This is pretty much like any other
1690 * descriptor-based RX handler.
1691 */
1692static void
1693rl_rxeofcplus(sc)
1694 struct rl_softc *sc;
1695{
1696 struct mbuf *m;
1697 struct ifnet *ifp;
1698 int i, total_len;
1699 struct rl_desc *cur_rx;
1700 u_int32_t rxstat, rxvlan;
1701
1702 ifp = &sc->arpcom.ac_if;
1703 i = sc->rl_ldata.rl_rx_prodidx;
1704
1705 /* Invalidate the descriptor memory */
1706
1707 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1708 sc->rl_ldata.rl_rx_list_map,
1709 BUS_DMASYNC_POSTREAD);
1710
1711 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) {
1712
1713 cur_rx = &sc->rl_ldata.rl_rx_list[i];
1714 m = sc->rl_ldata.rl_rx_mbuf[i];
1715 total_len = RL_RXBYTES(cur_rx) - ETHER_CRC_LEN;
1716 rxstat = le32toh(cur_rx->rl_cmdstat);
1717 rxvlan = le32toh(cur_rx->rl_vlanctl);
1718
1719 /* Invalidate the RX mbuf and unload its map */
1720
1721 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1722 sc->rl_ldata.rl_rx_dmamap[i],
1723 BUS_DMASYNC_POSTREAD);
1724 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1725 sc->rl_ldata.rl_rx_dmamap[i]);
1726
1727 if (rxstat & RL_RDESC_STAT_RXERRSUM) {
1728 ifp->if_ierrors++;
1729 rl_newbuf(sc, i, m);
1730 RL_DESC_INC(i);
1731 continue;
1732 }
1733
1734 /*
1735 * If allocating a replacement mbuf fails,
1736 * reload the current one.
1737 */
1738
1739 if (rl_newbuf(sc, i, NULL)) {
1740 ifp->if_ierrors++;
1741 rl_newbuf(sc, i, m);
1742 RL_DESC_INC(i);
1743 continue;
1744 }
1745
1746 RL_DESC_INC(i);
1747
1748 ifp->if_ipackets++;
1749 m->m_pkthdr.len = m->m_len = total_len;
1750 m->m_pkthdr.rcvif = ifp;
1751
1752 /* Check IP header checksum */
1753 if (rxstat & RL_RDESC_STAT_PROTOID)
1754 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1755 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
1756 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1757
1758 /* Check TCP/UDP checksum */
1759 if ((RL_TCPPKT(rxstat) &&
1760 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
1761 (RL_UDPPKT(rxstat) &&
1762 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
1763 m->m_pkthdr.csum_flags |=
1764 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1765 m->m_pkthdr.csum_data = 0xffff;
1766 }
1767
1768 if (rxvlan & RL_RDESC_VLANCTL_TAG)
1769 VLAN_INPUT_TAG(ifp, m,
1770 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue);
1771 (*ifp->if_input)(ifp, m);
1772 }
1773
1774 /* Flush the RX DMA ring */
1775
1776 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1777 sc->rl_ldata.rl_rx_list_map,
1778 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1779
1780 sc->rl_ldata.rl_rx_prodidx = i;
1781
1782 return;
1783}
1784
1785/*
1162 * A frame has been uploaded: pass the resulting mbuf chain up to
1163 * the higher level protocols.
1164 *
1165 * You know there's something wrong with a PCI bus-master chip design
1166 * when you have to use m_devget().
1167 *
1168 * The receive operation is badly documented in the datasheet, so I'll
1169 * attempt to document it here. The driver provides a buffer area and

--- 124 unchanged lines hidden (view full) ---

1294
1295 ifp->if_ipackets++;
1296 (*ifp->if_input)(ifp, m);
1297 }
1298
1299 return;
1300}
1301
1786 * A frame has been uploaded: pass the resulting mbuf chain up to
1787 * the higher level protocols.
1788 *
1789 * You know there's something wrong with a PCI bus-master chip design
1790 * when you have to use m_devget().
1791 *
1792 * The receive operation is badly documented in the datasheet, so I'll
1793 * attempt to document it here. The driver provides a buffer area and

--- 124 unchanged lines hidden (view full) ---

1918
1919 ifp->if_ipackets++;
1920 (*ifp->if_input)(ifp, m);
1921 }
1922
1923 return;
1924}
1925
1926static void
1927rl_txeofcplus(sc)
1928 struct rl_softc *sc;
1929{
1930 struct ifnet *ifp;
1931 u_int32_t txstat;
1932 int idx;
1933
1934 ifp = &sc->arpcom.ac_if;
1935 idx = sc->rl_ldata.rl_tx_considx;
1936
1937 /* Invalidate the TX descriptor list */
1938
1939 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1940 sc->rl_ldata.rl_tx_list_map,
1941 BUS_DMASYNC_POSTREAD);
1942
1943 while (idx != sc->rl_ldata.rl_tx_prodidx) {
1944
1945 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat);
1946 if (txstat & RL_TDESC_CMD_OWN)
1947 break;
1948
1949 /*
1950 * We only stash mbufs in the last descriptor
1951 * in a fragment chain, which also happens to
1952 * be the only place where the TX status bits
1953 * are valid.
1954 */
1955
1956 if (txstat & RL_TDESC_CMD_EOF) {
1957 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]);
1958 sc->rl_ldata.rl_tx_mbuf[idx] = NULL;
1959 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1960 sc->rl_ldata.rl_tx_dmamap[idx]);
1961 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
1962 RL_TDESC_STAT_COLCNT))
1963 ifp->if_collisions++;
1964 if (txstat & RL_TDESC_STAT_TXERRSUM)
1965 ifp->if_oerrors++;
1966 else
1967 ifp->if_opackets++;
1968 }
1969 sc->rl_ldata.rl_tx_free++;
1970 RL_DESC_INC(idx);
1971 }
1972
1973 /* No changes made to the TX ring, so no flush needed */
1974
1975 if (idx != sc->rl_ldata.rl_tx_considx) {
1976 sc->rl_ldata.rl_tx_considx = idx;
1977 ifp->if_flags &= ~IFF_OACTIVE;
1978 ifp->if_timer = 0;
1979 }
1980
1981 return;
1982}
1983
1302/*
1303 * A frame was downloaded to the chip. It's safe for us to clean up
1304 * the list buffers.
1305 */
1306static void
1307rl_txeof(sc)
1308 struct rl_softc *sc;
1309{

--- 72 unchanged lines hidden (view full) ---

1382#ifdef DEVICE_POLLING
1383static void
1384rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
1385{
1386 struct rl_softc *sc = ifp->if_softc;
1387
1388 RL_LOCK(sc);
1389 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1984/*
1985 * A frame was downloaded to the chip. It's safe for us to clean up
1986 * the list buffers.
1987 */
1988static void
1989rl_txeof(sc)
1990 struct rl_softc *sc;
1991{

--- 72 unchanged lines hidden (view full) ---

2064#ifdef DEVICE_POLLING
2065static void
2066rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
2067{
2068 struct rl_softc *sc = ifp->if_softc;
2069
2070 RL_LOCK(sc);
2071 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1390 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
2072 if (RL_ISCPLUS(sc))
2073 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2074 else
2075 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1391 goto done;
1392 }
1393
1394 sc->rxcycles = count;
2076 goto done;
2077 }
2078
2079 sc->rxcycles = count;
1395 rl_rxeof(sc);
1396 rl_txeof(sc);
2080 if (RL_ISCPLUS(sc)) {
2081 rl_rxeofcplus(sc);
2082 rl_txeofcplus(sc);
2083 } else {
2084 rl_rxeof(sc);
2085 rl_txeof(sc);
2086 }
2087
1397 if (ifp->if_snd.ifq_head != NULL)
2088 if (ifp->if_snd.ifq_head != NULL)
1398 rl_start(ifp);
2089 (*ifp->if_start)(ifp);
1399
1400 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1401 u_int16_t status;
1402
1403 status = CSR_READ_2(sc, RL_ISR);
1404 if (status == 0xffff)
1405 goto done;
1406 if (status)

--- 9 unchanged lines hidden (view full) ---

1416 }
1417 }
1418done:
1419 RL_UNLOCK(sc);
1420}
1421#endif /* DEVICE_POLLING */
1422
1423static void
2090
2091 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2092 u_int16_t status;
2093
2094 status = CSR_READ_2(sc, RL_ISR);
2095 if (status == 0xffff)
2096 goto done;
2097 if (status)

--- 9 unchanged lines hidden (view full) ---

2107 }
2108 }
2109done:
2110 RL_UNLOCK(sc);
2111}
2112#endif /* DEVICE_POLLING */
2113
2114static void
2115rl_intrcplus(arg)
2116 void *arg;
2117{
2118 struct rl_softc *sc;
2119 struct ifnet *ifp;
2120 u_int16_t status;
2121
2122 sc = arg;
2123
2124 if (sc->suspended) {
2125 return;
2126 }
2127
2128 RL_LOCK(sc);
2129 ifp = &sc->arpcom.ac_if;
2130
2131#ifdef DEVICE_POLLING
2132 if (ifp->if_flags & IFF_POLLING)
2133 goto done;
2134 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */
2135 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2136 rl_poll(ifp, 0, 1);
2137 goto done;
2138 }
2139#endif /* DEVICE_POLLING */
2140
2141 for (;;) {
2142
2143 status = CSR_READ_2(sc, RL_ISR);
2144 /* If the card has gone away the read returns 0xffff. */
2145 if (status == 0xffff)
2146 break;
2147 if (status)
2148 CSR_WRITE_2(sc, RL_ISR, status);
2149
2150 if ((status & RL_INTRS_CPLUS) == 0)
2151 break;
2152
2153 if (status & RL_ISR_RX_OK)
2154 rl_rxeofcplus(sc);
2155
2156 if (status & RL_ISR_RX_ERR)
2157 rl_rxeofcplus(sc);
2158
2159 if ((status & RL_ISR_TIMEOUT_EXPIRED) ||
2160 (status & RL_ISR_TX_ERR) ||
2161 (status & RL_ISR_TX_DESC_UNAVAIL))
2162 rl_txeofcplus(sc);
2163
2164 if (status & RL_ISR_SYSTEM_ERR) {
2165 rl_reset(sc);
2166 rl_init(sc);
2167 }
2168
2169 }
2170
2171 if (ifp->if_snd.ifq_head != NULL)
2172 (*ifp->if_start)(ifp);
2173
2174#ifdef DEVICE_POLLING
2175done:
2176#endif
2177 RL_UNLOCK(sc);
2178
2179 return;
2180}
2181
2182static void
1424rl_intr(arg)
1425 void *arg;
1426{
1427 struct rl_softc *sc;
1428 struct ifnet *ifp;
1429 u_int16_t status;
1430
1431 sc = arg;

--- 39 unchanged lines hidden (view full) ---

1471 if (status & RL_ISR_SYSTEM_ERR) {
1472 rl_reset(sc);
1473 rl_init(sc);
1474 }
1475
1476 }
1477
1478 if (ifp->if_snd.ifq_head != NULL)
2183rl_intr(arg)
2184 void *arg;
2185{
2186 struct rl_softc *sc;
2187 struct ifnet *ifp;
2188 u_int16_t status;
2189
2190 sc = arg;

--- 39 unchanged lines hidden (view full) ---

2230 if (status & RL_ISR_SYSTEM_ERR) {
2231 rl_reset(sc);
2232 rl_init(sc);
2233 }
2234
2235 }
2236
2237 if (ifp->if_snd.ifq_head != NULL)
1479 rl_start(ifp);
2238 (*ifp->if_start)(ifp);
1480
1481#ifdef DEVICE_POLLING
1482done:
1483#endif
1484 RL_UNLOCK(sc);
1485
1486 return;
1487}
1488
2239
2240#ifdef DEVICE_POLLING
2241done:
2242#endif
2243 RL_UNLOCK(sc);
2244
2245 return;
2246}
2247
2248static int
2249rl_encapcplus(sc, m_head, idx)
2250 struct rl_softc *sc;
2251 struct mbuf *m_head;
2252 int *idx;
2253{
2254 struct mbuf *m_new = NULL;
2255 struct rl_dmaload_arg arg;
2256 bus_dmamap_t map;
2257 int error;
2258 u_int32_t csumcmd = RL_TDESC_CMD_OWN;
2259 struct m_tag *mtag;
2260
2261 if (sc->rl_ldata.rl_tx_free < 4)
2262 return(EFBIG);
2263
2264 arg.sc = sc;
2265 arg.rl_idx = *idx;
2266 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
2267 arg.rl_ring = sc->rl_ldata.rl_tx_list;
2268
2269 map = sc->rl_ldata.rl_tx_dmamap[*idx];
2270 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
2271 m_head, rl_dma_map_desc, &arg, BUS_DMA_NOWAIT);
2272
2273 if (error && error != EFBIG) {
2274 printf("rl%d: can't map mbuf (error %d)\n", sc->rl_unit, error);
2275 return(ENOBUFS);
2276 }
2277
2278 /* Too many segments to map, coalesce into a single mbuf */
2279
2280 if (error || arg.rl_maxsegs == 0) {
2281 m_new = m_defrag(m_head, M_DONTWAIT);
2282 if (m_new == NULL)
2283 return(1);
2284 else
2285 m_head = m_new;
2286
2287 arg.sc = sc;
2288 arg.rl_idx = *idx;
2289 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
2290 arg.rl_ring = sc->rl_ldata.rl_tx_list;
2291
2292 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
2293 m_head, rl_dma_map_desc, &arg, BUS_DMA_NOWAIT);
2294 if (error) {
2295 printf("rl%d: can't map mbuf (error %d)\n",
2296 sc->rl_unit, error);
2297 return(EFBIG);
2298 }
2299 }
2300
2301 /*
2302 * Insure that the map for this transmission
2303 * is placed at the array index of the last descriptor
2304 * in this chain.
2305 */
2306 sc->rl_ldata.rl_tx_dmamap[*idx] =
2307 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx];
2308 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map;
2309
2310 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = m_head;
2311 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs;
2312
2313 /*
2314 * Set up hardware VLAN tagging. Note: vlan tag info must
2315 * appear in the first descriptor of a multi-descriptor
2316 * transmission attempt.
2317 */
2318
2319 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head);
2320 if (mtag != NULL)
2321 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl =
2322 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG);
2323
2324 /*
2325 * Set up checksum offload. Note: checksum offload bits must
2326 * appear in the first descriptor of a multi-descriptor
2327 * transmission attempt.
2328 */
2329
2330 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2331 csumcmd |= RL_TDESC_CMD_IPCSUM;
2332 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2333 csumcmd |= RL_TDESC_CMD_TCPCSUM;
2334 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2335 csumcmd |= RL_TDESC_CMD_UDPCSUM;
2336
2337 /* Transfer ownership of packet to the chip. */
2338
2339 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= htole32(csumcmd);
2340 if (*idx != arg.rl_idx)
2341 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= htole32(csumcmd);
2342
2343 RL_DESC_INC(arg.rl_idx);
2344 *idx = arg.rl_idx;
2345
2346 return(0);
2347}
2348
1489/*
2349/*
2350 * Main transmit routine for C+ and gigE NICs.
2351 */
2352
2353static void
2354rl_startcplus(ifp)
2355 struct ifnet *ifp;
2356{
2357 struct rl_softc *sc;
2358 struct mbuf *m_head = NULL;
2359 int idx;
2360
2361 sc = ifp->if_softc;
2362 RL_LOCK(sc);
2363
2364 idx = sc->rl_ldata.rl_tx_prodidx;
2365
2366 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) {
2367 IF_DEQUEUE(&ifp->if_snd, m_head);
2368 if (m_head == NULL)
2369 break;
2370
2371 if (rl_encapcplus(sc, m_head, &idx)) {
2372 IF_PREPEND(&ifp->if_snd, m_head);
2373 ifp->if_flags |= IFF_OACTIVE;
2374 break;
2375 }
2376
2377 /*
2378 * If there's a BPF listener, bounce a copy of this frame
2379 * to him.
2380 */
2381 BPF_MTAP(ifp, m_head);
2382 }
2383
2384 /* Flush the TX descriptors */
2385
2386 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
2387 sc->rl_ldata.rl_tx_list_map,
2388 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2389
2390 sc->rl_ldata.rl_tx_prodidx = idx;
2391
2392 /*
2393 * RealTek put the TX poll request register in a different
2394 * location on the 8169 gigE chip. I don't know why.
2395 */
2396
2397 if (sc->rl_type == RL_8169)
2398 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START);
2399 else
2400 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START);
2401
2402 /*
2403 * Use the countdown timer for interrupt moderation.
2404 * 'TX done' interrupts are disabled. Instead, we reset the
2405 * countdown timer, which will begin counting until it hits
2406 * the value in the TIMERINT register, and then trigger an
2407 * interrupt. Each time we write to the TIMERCNT register,
2408 * the timer count is reset to 0.
2409 */
2410 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2411
2412 RL_UNLOCK(sc);
2413
2414 /*
2415 * Set a timeout in case the chip goes out to lunch.
2416 */
2417 ifp->if_timer = 5;
2418
2419 return;
2420}
2421
2422/*
1490 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1491 * pointers to the fragment pointers.
1492 */
1493static int
1494rl_encap(sc, m_head)
1495 struct rl_softc *sc;
1496 struct mbuf *m_head;
1497{

--- 62 unchanged lines hidden (view full) ---

1560 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1561
1562 /*
1563 * Transmit the frame.
1564 */
1565 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1566 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1567 mtod(RL_CUR_TXMBUF(sc), void *),
2423 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2424 * pointers to the fragment pointers.
2425 */
2426static int
2427rl_encap(sc, m_head)
2428 struct rl_softc *sc;
2429 struct mbuf *m_head;
2430{

--- 62 unchanged lines hidden (view full) ---

2493 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
2494
2495 /*
2496 * Transmit the frame.
2497 */
2498 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
2499 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
2500 mtod(RL_CUR_TXMBUF(sc), void *),
1568 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
2501 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf,
2502 sc, BUS_DMA_NOWAIT);
1569 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1570 BUS_DMASYNC_PREREAD);
1571 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1572 RL_TXTHRESH(sc->rl_txthresh) |
1573 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1574
1575 RL_INC(sc->rl_cdata.cur_tx);
1576

--- 38 unchanged lines hidden (view full) ---

1615 * documentation doesn't mention it, we need to enter "Config
1616 * register write enable" mode to modify the ID registers.
1617 */
1618 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1619 CSR_WRITE_4(sc, RL_IDR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1620 CSR_WRITE_4(sc, RL_IDR4, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1621 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1622
2503 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
2504 BUS_DMASYNC_PREREAD);
2505 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
2506 RL_TXTHRESH(sc->rl_txthresh) |
2507 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
2508
2509 RL_INC(sc->rl_cdata.cur_tx);
2510

--- 38 unchanged lines hidden (view full) ---

2549 * documentation doesn't mention it, we need to enter "Config
2550 * register write enable" mode to modify the ID registers.
2551 */
2552 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2553 CSR_WRITE_4(sc, RL_IDR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
2554 CSR_WRITE_4(sc, RL_IDR4, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
2555 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2556
1623 /* Init the RX buffer pointer register. */
1624 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1625 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
1626 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1627 BUS_DMASYNC_PREWRITE);
2557 /*
2558 * For C+ mode, initialize the RX descriptors and mbufs.
2559 */
2560 if (RL_ISCPLUS(sc)) {
2561 rl_rx_list_init(sc);
2562 rl_tx_list_init(sc);
2563 } else {
1628
2564
1629 /* Init TX descriptors. */
1630 rl_list_tx_init(sc);
2565 /* Init the RX buffer pointer register. */
2566 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
2567 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN,
2568 rl_dma_map_rxbuf, sc, BUS_DMA_NOWAIT);
2569 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
2570 BUS_DMASYNC_PREWRITE);
1631
2571
2572 /* Init TX descriptors. */
2573 rl_list_tx_init(sc);
2574 }
2575
1632 /*
1633 * Enable transmit and receive.
1634 */
1635 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1636
1637 /*
1638 * Set the initial TX and RX configuration.
1639 */

--- 35 unchanged lines hidden (view full) ---

1675 */
1676 if (ifp->if_flags & IFF_POLLING)
1677 CSR_WRITE_2(sc, RL_IMR, 0);
1678 else /* otherwise ... */
1679#endif /* DEVICE_POLLING */
1680 /*
1681 * Enable interrupts.
1682 */
2576 /*
2577 * Enable transmit and receive.
2578 */
2579 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2580
2581 /*
2582 * Set the initial TX and RX configuration.
2583 */

--- 35 unchanged lines hidden (view full) ---

2619 */
2620 if (ifp->if_flags & IFF_POLLING)
2621 CSR_WRITE_2(sc, RL_IMR, 0);
2622 else /* otherwise ... */
2623#endif /* DEVICE_POLLING */
2624 /*
2625 * Enable interrupts.
2626 */
1683 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
2627 if (RL_ISCPLUS(sc))
2628 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2629 else
2630 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1684
1685 /* Set initial TX threshold */
1686 sc->rl_txthresh = RL_TX_THRESH_INIT;
1687
1688 /* Start RX/TX process. */
1689 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
2631
2632 /* Set initial TX threshold */
2633 sc->rl_txthresh = RL_TX_THRESH_INIT;
2634
2635 /* Start RX/TX process. */
2636 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1690
2637#ifdef notdef
1691 /* Enable receiver and transmitter. */
1692 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2638 /* Enable receiver and transmitter. */
2639 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2640#endif
2641 /*
2642 * If this is a C+ capable chip, enable C+ RX and TX mode,
2643 * and load the addresses of the RX and TX lists into the chip.
2644 */
2645 if (RL_ISCPLUS(sc)) {
2646 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
2647 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
2648 RL_CPLUSCMD_VLANSTRIP|
2649 (ifp->if_capenable & IFCAP_RXCSUM ?
2650 RL_CPLUSCMD_RXCSUM_ENB : 0));
1693
2651
2652 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 0);
2653 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
2654 sc->rl_ldata.rl_rx_list_addr);
2655
2656 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 0);
2657 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
2658 sc->rl_ldata.rl_tx_list_addr);
2659
2660 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, RL_EARLYTXTHRESH_CNT);
2661
2662 /*
2663 * Initialize the timer interrupt register so that
2664 * a timer interrupt will be generated once the timer
2665 * reaches a certain number of ticks. The timer is
2666 * reloaded on each transmit. This gives us TX interrupt
2667 * moderation, which dramatically improves TX frame rate.
2668 */
2669
2670 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
2671
2672 /*
2673 * For 8169 gigE NICs, set the max allowed RX packet
2674 * size so we can receive jumbo frames.
2675 */
2676 if (sc->rl_type == RL_8169)
2677 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RL_PKTSZ(16384));
2678
2679 }
2680
1694 mii_mediachg(mii);
1695
1696 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1697
1698 ifp->if_flags |= IFF_RUNNING;
1699 ifp->if_flags &= ~IFF_OACTIVE;
1700
1701 sc->rl_stat_ch = timeout(rl_tick, sc, hz);

--- 68 unchanged lines hidden (view full) ---

1770 rl_setmulti(sc);
1771 error = 0;
1772 break;
1773 case SIOCGIFMEDIA:
1774 case SIOCSIFMEDIA:
1775 mii = device_get_softc(sc->rl_miibus);
1776 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1777 break;
2681 mii_mediachg(mii);
2682
2683 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
2684
2685 ifp->if_flags |= IFF_RUNNING;
2686 ifp->if_flags &= ~IFF_OACTIVE;
2687
2688 sc->rl_stat_ch = timeout(rl_tick, sc, hz);

--- 68 unchanged lines hidden (view full) ---

2757 rl_setmulti(sc);
2758 error = 0;
2759 break;
2760 case SIOCGIFMEDIA:
2761 case SIOCSIFMEDIA:
2762 mii = device_get_softc(sc->rl_miibus);
2763 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2764 break;
2765 case SIOCSIFCAP:
2766 ifp->if_capenable = ifr->ifr_reqcap;
2767 if (ifp->if_capenable & IFCAP_TXCSUM)
2768 ifp->if_hwassist = RL_CSUM_FEATURES;
2769 else
2770 ifp->if_hwassist = 0;
2771 if (ifp->if_flags & IFF_RUNNING)
2772 rl_init(sc);
2773 break;
1778 default:
1779 error = ether_ioctl(ifp, command, data);
1780 break;
1781 }
1782
1783 RL_UNLOCK(sc);
1784
1785 return(error);

--- 5 unchanged lines hidden (view full) ---

1791{
1792 struct rl_softc *sc;
1793
1794 sc = ifp->if_softc;
1795 RL_LOCK(sc);
1796 printf("rl%d: watchdog timeout\n", sc->rl_unit);
1797 ifp->if_oerrors++;
1798
2774 default:
2775 error = ether_ioctl(ifp, command, data);
2776 break;
2777 }
2778
2779 RL_UNLOCK(sc);
2780
2781 return(error);

--- 5 unchanged lines hidden (view full) ---

2787{
2788 struct rl_softc *sc;
2789
2790 sc = ifp->if_softc;
2791 RL_LOCK(sc);
2792 printf("rl%d: watchdog timeout\n", sc->rl_unit);
2793 ifp->if_oerrors++;
2794
1799 rl_txeof(sc);
1800 rl_rxeof(sc);
2795 if (RL_ISCPLUS(sc)) {
2796 rl_txeofcplus(sc);
2797 rl_rxeofcplus(sc);
2798 } else {
2799 rl_txeof(sc);
2800 rl_rxeof(sc);
2801 }
2802
1801 rl_init(sc);
2803 rl_init(sc);
2804
1802 RL_UNLOCK(sc);
1803
1804 return;
1805}
1806
1807/*
1808 * Stop the adapter and free any mbufs allocated to the
1809 * RX and TX lists.

--- 12 unchanged lines hidden (view full) ---

1822 untimeout(rl_tick, sc, sc->rl_stat_ch);
1823 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1824#ifdef DEVICE_POLLING
1825 ether_poll_deregister(ifp);
1826#endif /* DEVICE_POLLING */
1827
1828 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1829 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2805 RL_UNLOCK(sc);
2806
2807 return;
2808}
2809
2810/*
2811 * Stop the adapter and free any mbufs allocated to the
2812 * RX and TX lists.

--- 12 unchanged lines hidden (view full) ---

2825 untimeout(rl_tick, sc, sc->rl_stat_ch);
2826 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2827#ifdef DEVICE_POLLING
2828 ether_poll_deregister(ifp);
2829#endif /* DEVICE_POLLING */
2830
2831 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2832 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1830 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1831
2833
1832 /*
1833 * Free the TX list buffers.
1834 */
1835 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1836 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1837 bus_dmamap_unload(sc->rl_tag,
1838 sc->rl_cdata.rl_tx_dmamap[i]);
1839 bus_dmamap_destroy(sc->rl_tag,
1840 sc->rl_cdata.rl_tx_dmamap[i]);
1841 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1842 sc->rl_cdata.rl_tx_chain[i] = NULL;
1843 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
2834 if (RL_ISCPLUS(sc)) {
2835
2836 /* Free the TX list buffers. */
2837
2838 for (i = 0; i < RL_TX_DESC_CNT; i++) {
2839 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) {
2840 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2841 sc->rl_ldata.rl_tx_dmamap[i]);
2842 m_freem(sc->rl_ldata.rl_tx_mbuf[i]);
2843 sc->rl_ldata.rl_tx_mbuf[i] = NULL;
2844 }
1844 }
2845 }
2846
2847 /* Free the RX list buffers. */
2848
2849 for (i = 0; i < RL_RX_DESC_CNT; i++) {
2850 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) {
2851 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2852 sc->rl_ldata.rl_rx_dmamap[i]);
2853 m_freem(sc->rl_ldata.rl_rx_mbuf[i]);
2854 sc->rl_ldata.rl_rx_mbuf[i] = NULL;
2855 }
2856 }
2857
2858 } else {
2859
2860 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
2861
2862 /*
2863 * Free the TX list buffers.
2864 */
2865 for (i = 0; i < RL_TX_LIST_CNT; i++) {
2866 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
2867 bus_dmamap_unload(sc->rl_tag,
2868 sc->rl_cdata.rl_tx_dmamap[i]);
2869 bus_dmamap_destroy(sc->rl_tag,
2870 sc->rl_cdata.rl_tx_dmamap[i]);
2871 m_freem(sc->rl_cdata.rl_tx_chain[i]);
2872 sc->rl_cdata.rl_tx_chain[i] = NULL;
2873 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
2874 }
2875 }
1845 }
1846
1847 RL_UNLOCK(sc);
1848 return;
1849}
1850
1851/*
1852 * Device suspend routine. Stop the interface and save some PCI

--- 79 unchanged lines hidden --- 		2876 }
2877
2878 RL_UNLOCK(sc);
2879 return;
2880}
2881
2882/*
2883 * Device suspend routine. Stop the interface and save some PCI

--- 79 unchanged lines hidden ---