1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
|
32 * $Id: if_rl.c,v 1.2 1998/11/18 21:03:57 wpaul Exp $
|
| 32 * $Id: if_rl.c,v 1.16 1998/12/07 00:16:44 wpaul Exp $ |
33 */
34
35/*
36 * RealTek 8129/8139 PCI NIC driver
37 *
38 * Supports several extremely cheap PCI 10/100 adapters based on
39 * the RealTek chipset. Datasheets can be obtained from
40 * www.realtek.com.tw.
41 *
42 * Written by Bill Paul <wpaul@ctr.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
45 */
46
47/*
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
53 *
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
|
56 * on a doubleword (32-bit) boundary. This means we almost always have to
|
| 56 * on a longword (32-bit) boundary. This means we almost always have to |
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
62 *
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
68 * levels.
69 *
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
73 *
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
78 * filter.
79 *
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
|
84 *
85 * Note: beware of trying to use the Linux RealTek driver as a reference
86 * for information about the RealTek chip. It contains several bogosities.
87 * It contains definitions for several undocumented registers which it
88 * claims are 'required for proper operation' yet it does not use these
89 * registers anywhere in the code. It also refers to some undocumented
90 * 'Twister tuning codes' which it doesn't use anywhere. It also contains
91 * bit definitions for several registers which are totally ignored: magic
92 * numbers are used instead, making the code hard to read.
|
84 */
85
86#include "bpfilter.h"
87
88#include <sys/param.h>
89#include <sys/systm.h>
90#include <sys/sockio.h>
91#include <sys/mbuf.h>
92#include <sys/malloc.h>
93#include <sys/kernel.h>
94#include <sys/socket.h>
95
96#include <net/if.h>
97#include <net/if_arp.h>
98#include <net/ethernet.h>
99#include <net/if_dl.h>
100#include <net/if_media.h>
101
102#if NBPFILTER > 0
103#include <net/bpf.h>
104#endif
105
106#include <vm/vm.h> /* for vtophys */
107#include <vm/pmap.h> /* for vtophys */
108#include <machine/clock.h> /* for DELAY */
|
109#include <machine/bus_pio.h>
110#include <machine/bus_memio.h>
111#include <machine/bus.h> |
112
113#include <pci/pcireg.h>
114#include <pci/pcivar.h>
115
116/*
117 * Default to using PIO access for this driver. On SMP systems,
118 * there appear to be problems with memory mapped mode: it looks like
119 * doing too many memory mapped access back to back in rapid succession
120 * can hang the bus. I'm inclined to blame this on crummy design/construction
121 * on the part of RealTek. Memory mapped mode does appear to work on
122 * uniprocessor systems though.
123 */
124#define RL_USEIOSPACE
125
126#include <pci/if_rlreg.h>
127
128#ifndef lint
129static char rcsid[] =
|
136 "$Id: if_rl.c,v 1.2 1998/11/18 21:03:57 wpaul Exp $";
|
| 130 "$Id: if_rl.c,v 1.16 1998/12/07 00:16:44 wpaul Exp $"; |
131#endif
132
133/*
134 * Various supported device vendors/types and their names.
135 */
136static struct rl_type rl_devs[] = {
137 { RT_VENDORID, RT_DEVICEID_8129,
138 "RealTek 8129 10/100BaseTX" },
139 { RT_VENDORID, RT_DEVICEID_8139,
140 "RealTek 8139 10/100BaseTX" },
141 { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
142 "Accton MPX 5030/5038 10/100BaseTX" },
143 { 0, 0, NULL }
144};
145
146/*
147 * Various supported PHY vendors/types and their names. Note that
148 * this driver will work with pretty much any MII-compliant PHY,
149 * so failure to positively identify the chip is not a fatal error.
150 */
151
152static struct rl_type rl_phys[] = {
153 { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" },
154 { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" },
155 { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"},
156 { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" },
157 { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" },
158 { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" },
159 { 0, 0, "<MII-compliant physical interface>" }
160};
161
162static unsigned long rl_count = 0;
163static char *rl_probe __P((pcici_t, pcidi_t));
164static void rl_attach __P((pcici_t, int));
165
166static int rl_encap __P((struct rl_softc *, struct rl_chain *,
167 struct mbuf * ));
168
169static void rl_rxeof __P((struct rl_softc *));
170static void rl_txeof __P((struct rl_softc *));
171static void rl_txeoc __P((struct rl_softc *));
172static void rl_intr __P((void *));
173static void rl_start __P((struct ifnet *));
174static int rl_ioctl __P((struct ifnet *, u_long, caddr_t));
175static void rl_init __P((void *));
176static void rl_stop __P((struct rl_softc *));
177static void rl_watchdog __P((struct ifnet *));
178static void rl_shutdown __P((int, void *));
179static int rl_ifmedia_upd __P((struct ifnet *));
180static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
181
182static void rl_eeprom_putbyte __P((struct rl_softc *, u_int8_t));
183static void rl_eeprom_getword __P((struct rl_softc *, u_int8_t, u_int16_t *));
184static void rl_read_eeprom __P((struct rl_softc *, caddr_t,
185 int, int, int));
186static void rl_mii_sync __P((struct rl_softc *));
187static void rl_mii_send __P((struct rl_softc *, u_int32_t, int));
188static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *));
189static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *));
190
191static u_int16_t rl_phy_readreg __P((struct rl_softc *, int));
192static void rl_phy_writereg __P((struct rl_softc *, u_int16_t, u_int16_t));
193
194static void rl_autoneg_xmit __P((struct rl_softc *));
195static void rl_autoneg_mii __P((struct rl_softc *, int, int));
196static void rl_setmode_mii __P((struct rl_softc *, int));
197static void rl_getmode_mii __P((struct rl_softc *));
198static u_int8_t rl_calchash __P((u_int8_t *));
199static void rl_setmulti __P((struct rl_softc *));
200static void rl_reset __P((struct rl_softc *));
201static int rl_list_tx_init __P((struct rl_softc *));
202
203#define EE_SET(x) \
204 CSR_WRITE_1(sc, RL_EECMD, \
205 CSR_READ_1(sc, RL_EECMD) | x)
206
207#define EE_CLR(x) \
208 CSR_WRITE_1(sc, RL_EECMD, \
209 CSR_READ_1(sc, RL_EECMD) & ~x)
210
211/*
212 * Send a read command and address to the EEPROM, check for ACK.
213 */
214static void rl_eeprom_putbyte(sc, addr)
215 struct rl_softc *sc;
216 u_int8_t addr;
217{
218 register int d, i;
219
220 d = addr | RL_EECMD_READ;
221
222 /*
223 * Feed in each bit and stobe the clock.
224 */
225 for (i = 0x400; i; i >>= 1) {
226 if (d & i) {
227 EE_SET(RL_EE_DATAIN);
228 } else {
229 EE_CLR(RL_EE_DATAIN);
230 }
231 DELAY(100);
232 EE_SET(RL_EE_CLK);
233 DELAY(150);
234 EE_CLR(RL_EE_CLK);
235 DELAY(100);
236 }
237
238 return;
239}
240
241/*
242 * Read a word of data stored in the EEPROM at address 'addr.'
243 */
244static void rl_eeprom_getword(sc, addr, dest)
245 struct rl_softc *sc;
246 u_int8_t addr;
247 u_int16_t *dest;
248{
249 register int i;
250 u_int16_t word = 0;
251
252 /* Enter EEPROM access mode. */
253 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
254
255 /*
256 * Send address of word we want to read.
257 */
258 rl_eeprom_putbyte(sc, addr);
259
260 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
261
262 /*
263 * Start reading bits from EEPROM.
264 */
265 for (i = 0x8000; i; i >>= 1) {
266 EE_SET(RL_EE_CLK);
267 DELAY(100);
268 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
269 word |= i;
270 EE_CLR(RL_EE_CLK);
271 DELAY(100);
272 }
273
274 /* Turn off EEPROM access mode. */
275 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
276
277 *dest = word;
278
279 return;
280}
281
282/*
283 * Read a sequence of words from the EEPROM.
284 */
285static void rl_read_eeprom(sc, dest, off, cnt, swap)
286 struct rl_softc *sc;
287 caddr_t dest;
288 int off;
289 int cnt;
290 int swap;
291{
292 int i;
293 u_int16_t word = 0, *ptr;
294
295 for (i = 0; i < cnt; i++) {
296 rl_eeprom_getword(sc, off + i, &word);
297 ptr = (u_int16_t *)(dest + (i * 2));
298 if (swap)
299 *ptr = ntohs(word);
300 else
301 *ptr = word;
302 }
303
304 return;
305}
306
307
308/*
309 * MII access routines are provided for the 8129, which
310 * doesn't have a built-in PHY. For the 8139, we fake things
311 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
312 * direct access PHY registers.
313 */
314#define MII_SET(x) \
315 CSR_WRITE_1(sc, RL_MII, \
316 CSR_READ_1(sc, RL_MII) | x)
317
318#define MII_CLR(x) \
319 CSR_WRITE_1(sc, RL_MII, \
320 CSR_READ_1(sc, RL_MII) & ~x)
321
322/*
323 * Sync the PHYs by setting data bit and strobing the clock 32 times.
324 */
325static void rl_mii_sync(sc)
326 struct rl_softc *sc;
327{
328 register int i;
329
330 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
331
332 for (i = 0; i < 32; i++) {
333 MII_SET(RL_MII_CLK);
334 DELAY(1);
335 MII_CLR(RL_MII_CLK);
336 DELAY(1);
337 }
338
339 return;
340}
341
342/*
343 * Clock a series of bits through the MII.
344 */
345static void rl_mii_send(sc, bits, cnt)
346 struct rl_softc *sc;
347 u_int32_t bits;
348 int cnt;
349{
350 int i;
351
352 MII_CLR(RL_MII_CLK);
353
354 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
355 if (bits & i) {
356 MII_SET(RL_MII_DATAOUT);
357 } else {
358 MII_CLR(RL_MII_DATAOUT);
359 }
360 DELAY(1);
361 MII_CLR(RL_MII_CLK);
362 DELAY(1);
363 MII_SET(RL_MII_CLK);
364 }
365}
366
367/*
368 * Read an PHY register through the MII.
369 */
370static int rl_mii_readreg(sc, frame)
371 struct rl_softc *sc;
372 struct rl_mii_frame *frame;
373
374{
375 int i, ack, s;
376
377 s = splimp();
378
379 /*
380 * Set up frame for RX.
381 */
382 frame->mii_stdelim = RL_MII_STARTDELIM;
383 frame->mii_opcode = RL_MII_READOP;
384 frame->mii_turnaround = 0;
385 frame->mii_data = 0;
386
387 CSR_WRITE_2(sc, RL_MII, 0);
388
389 /*
390 * Turn on data xmit.
391 */
392 MII_SET(RL_MII_DIR);
393
394 rl_mii_sync(sc);
395
396 /*
397 * Send command/address info.
398 */
399 rl_mii_send(sc, frame->mii_stdelim, 2);
400 rl_mii_send(sc, frame->mii_opcode, 2);
401 rl_mii_send(sc, frame->mii_phyaddr, 5);
402 rl_mii_send(sc, frame->mii_regaddr, 5);
403
404 /* Idle bit */
405 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
406 DELAY(1);
407 MII_SET(RL_MII_CLK);
408 DELAY(1);
409
410 /* Turn off xmit. */
411 MII_CLR(RL_MII_DIR);
412
413 /* Check for ack */
414 MII_CLR(RL_MII_CLK);
415 DELAY(1);
416 MII_SET(RL_MII_CLK);
417 DELAY(1);
418 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
419
420 /*
421 * Now try reading data bits. If the ack failed, we still
422 * need to clock through 16 cycles to keep the PHY(s) in sync.
423 */
424 if (ack) {
425 for(i = 0; i < 16; i++) {
426 MII_CLR(RL_MII_CLK);
427 DELAY(1);
428 MII_SET(RL_MII_CLK);
429 DELAY(1);
430 }
431 goto fail;
432 }
433
434 for (i = 0x8000; i; i >>= 1) {
435 MII_CLR(RL_MII_CLK);
436 DELAY(1);
437 if (!ack) {
438 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
439 frame->mii_data |= i;
440 DELAY(1);
441 }
442 MII_SET(RL_MII_CLK);
443 DELAY(1);
444 }
445
446fail:
447
448 MII_CLR(RL_MII_CLK);
449 DELAY(1);
450 MII_SET(RL_MII_CLK);
451 DELAY(1);
452
453 splx(s);
454
455 if (ack)
456 return(1);
457 return(0);
458}
459
460/*
461 * Write to a PHY register through the MII.
462 */
463static int rl_mii_writereg(sc, frame)
464 struct rl_softc *sc;
465 struct rl_mii_frame *frame;
466
467{
468 int s;
469
470 s = splimp();
471 /*
472 * Set up frame for TX.
473 */
474
475 frame->mii_stdelim = RL_MII_STARTDELIM;
476 frame->mii_opcode = RL_MII_WRITEOP;
477 frame->mii_turnaround = RL_MII_TURNAROUND;
478
479 /*
480 * Turn on data output.
481 */
482 MII_SET(RL_MII_DIR);
483
484 rl_mii_sync(sc);
485
486 rl_mii_send(sc, frame->mii_stdelim, 2);
487 rl_mii_send(sc, frame->mii_opcode, 2);
488 rl_mii_send(sc, frame->mii_phyaddr, 5);
489 rl_mii_send(sc, frame->mii_regaddr, 5);
490 rl_mii_send(sc, frame->mii_turnaround, 2);
491 rl_mii_send(sc, frame->mii_data, 16);
492
493 /* Idle bit. */
494 MII_SET(RL_MII_CLK);
495 DELAY(1);
496 MII_CLR(RL_MII_CLK);
497 DELAY(1);
498
499 /*
500 * Turn off xmit.
501 */
502 MII_CLR(RL_MII_DIR);
503
504 splx(s);
505
506 return(0);
507}
508
509static u_int16_t rl_phy_readreg(sc, reg)
510 struct rl_softc *sc;
511 int reg;
512{
513 struct rl_mii_frame frame;
514 u_int16_t rval = 0;
515 u_int16_t rl8139_reg = 0;
516
517 if (sc->rl_type == RL_8139) {
518 switch(reg) {
519 case PHY_BMCR:
520 rl8139_reg = RL_BMCR;
521 break;
522 case PHY_BMSR:
523 rl8139_reg = RL_BMSR;
524 break;
525 case PHY_ANAR:
526 rl8139_reg = RL_ANAR;
527 break;
528 case PHY_LPAR:
529 rl8139_reg = RL_LPAR;
530 break;
531 default:
532 printf("rl%d: bad phy register\n", sc->rl_unit);
533 return(0);
534 }
535 rval = CSR_READ_2(sc, rl8139_reg);
536 return(rval);
537 }
538
539 bzero((char *)&frame, sizeof(frame));
540
541 frame.mii_phyaddr = sc->rl_phy_addr;
542 frame.mii_regaddr = reg;
543 rl_mii_readreg(sc, &frame);
544
545 return(frame.mii_data);
546}
547
548static void rl_phy_writereg(sc, reg, data)
549 struct rl_softc *sc;
550 u_int16_t reg;
551 u_int16_t data;
552{
553 struct rl_mii_frame frame;
554 u_int16_t rl8139_reg = 0;
555
556 if (sc->rl_type == RL_8139) {
557 switch(reg) {
558 case PHY_BMCR:
559 rl8139_reg = RL_BMCR;
560 break;
561 case PHY_BMSR:
562 rl8139_reg = RL_BMSR;
563 break;
564 case PHY_ANAR:
565 rl8139_reg = RL_ANAR;
566 break;
567 case PHY_LPAR:
568 rl8139_reg = RL_LPAR;
569 break;
570 default:
571 printf("rl%d: bad phy register\n", sc->rl_unit);
572 return;
573 }
574 CSR_WRITE_2(sc, rl8139_reg, data);
575 return;
576 }
577
578 bzero((char *)&frame, sizeof(frame));
579
580 frame.mii_phyaddr = sc->rl_phy_addr;
581 frame.mii_regaddr = reg;
582 frame.mii_data = data;
583
584 rl_mii_writereg(sc, &frame);
585
586 return;
587}
588
589/*
590 * Calculate CRC of a multicast group address, return the lower 6 bits.
591 */
592static u_int8_t rl_calchash(addr)
593 u_int8_t *addr;
594{
595 u_int32_t crc, carry;
596 int i, j;
597 u_int8_t c;
598
599 /* Compute CRC for the address value. */
600 crc = 0xFFFFFFFF; /* initial value */
601
602 for (i = 0; i < 6; i++) {
603 c = *(addr + i);
604 for (j = 0; j < 8; j++) {
605 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
606 crc <<= 1;
607 c >>= 1;
608 if (carry)
609 crc = (crc ^ 0x04c11db6) | carry;
610 }
611 }
612
613 /* return the filter bit position */
614 return(crc & 0x0000003F);
615}
616
617/*
618 * Program the 64-bit multicast hash filter.
619 */
620static void rl_setmulti(sc)
621 struct rl_softc *sc;
622{
623 struct ifnet *ifp;
624 int h = 0;
625 u_int32_t hashes[2] = { 0, 0 };
626 struct ifmultiaddr *ifma;
627 u_int32_t rxfilt;
628 int mcnt = 0;
629
630 ifp = &sc->arpcom.ac_if;
631
632 rxfilt = CSR_READ_4(sc, RL_RXCFG);
633
634 if (ifp->if_flags & IFF_ALLMULTI) {
635 rxfilt |= RL_RXCFG_RX_MULTI;
636 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
637 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
638 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
639 return;
640 }
641
642 /* first, zot all the existing hash bits */
643 CSR_WRITE_4(sc, RL_MAR0, 0);
644 CSR_WRITE_4(sc, RL_MAR4, 0);
645
646 /* now program new ones */
647 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
648 ifma = ifma->ifma_link.le_next) {
649 if (ifma->ifma_addr->sa_family != AF_LINK)
650 continue;
651 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
652 if (h < 32)
653 hashes[0] |= (1 << h);
654 else
655 hashes[1] |= (1 << (h - 32));
656 mcnt++;
657 }
658
659 if (mcnt)
660 rxfilt |= RL_RXCFG_RX_MULTI;
661 else
662 rxfilt &= ~RL_RXCFG_RX_MULTI;
663
664 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
665 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
666 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
667
668 return;
669}
670
671/*
672 * Initiate an autonegotiation session.
673 */
674static void rl_autoneg_xmit(sc)
675 struct rl_softc *sc;
676{
677 u_int16_t phy_sts;
678
679 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
680 DELAY(500);
681 while(rl_phy_readreg(sc, PHY_BMCR)
682 & PHY_BMCR_RESET);
683
684 phy_sts = rl_phy_readreg(sc, PHY_BMCR);
685 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
686 rl_phy_writereg(sc, PHY_BMCR, phy_sts);
687
688 return;
689}
690
691/*
692 * Invoke autonegotiation on a PHY. Also used with the 8139 internal
693 * transceiver.
694 */
695static void rl_autoneg_mii(sc, flag, verbose)
696 struct rl_softc *sc;
697 int flag;
698 int verbose;
699{
700 u_int16_t phy_sts = 0, media, advert, ability;
701 struct ifnet *ifp;
702 struct ifmedia *ifm;
703
704 ifm = &sc->ifmedia;
705 ifp = &sc->arpcom.ac_if;
706
707 /*
708 * The 100baseT4 PHY sometimes has the 'autoneg supported'
709 * bit cleared in the status register, but has the 'autoneg enabled'
710 * bit set in the control register. This is a contradiction, and
711 * I'm not sure how to handle it. If you want to force an attempt
712 * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR
713 * and see what happens.
714 */
715#ifndef FORCE_AUTONEG_TFOUR
716 /*
717 * First, see if autoneg is supported. If not, there's
718 * no point in continuing.
719 */
720 phy_sts = rl_phy_readreg(sc, PHY_BMSR);
721 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
722 if (verbose)
723 printf("rl%d: autonegotiation not supported\n",
724 sc->rl_unit);
725 return;
726 }
727#endif
728
729 switch (flag) {
730 case RL_FLAG_FORCEDELAY:
731 /*
732 * XXX Never use this option anywhere but in the probe
733 * routine: making the kernel stop dead in its tracks
734 * for three whole seconds after we've gone multi-user
735 * is really bad manners.
736 */
737 rl_autoneg_xmit(sc);
738 DELAY(5000000);
739 break;
740 case RL_FLAG_SCHEDDELAY:
741 /*
742 * Wait for the transmitter to go idle before starting
743 * an autoneg session, otherwise rl_start() may clobber
744 * our timeout, and we don't want to allow transmission
745 * during an autoneg session since that can screw it up.
746 */
747 if (sc->rl_cdata.rl_tx_cnt) {
748 sc->rl_want_auto = 1;
749 return;
750 }
751 rl_autoneg_xmit(sc);
752 ifp->if_timer = 5;
753 sc->rl_autoneg = 1;
754 sc->rl_want_auto = 0;
755 return;
756 break;
757 case RL_FLAG_DELAYTIMEO:
758 ifp->if_timer = 0;
759 sc->rl_autoneg = 0;
760 break;
761 default:
762 printf("rl%d: invalid autoneg flag: %d\n", sc->rl_unit, flag);
763 return;
764 }
765
766 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
767 if (verbose)
768 printf("rl%d: autoneg complete, ", sc->rl_unit);
769 phy_sts = rl_phy_readreg(sc, PHY_BMSR);
770 } else {
771 if (verbose)
772 printf("rl%d: autoneg not complete, ", sc->rl_unit);
773 }
774
775 media = rl_phy_readreg(sc, PHY_BMCR);
776
777 /* Link is good. Report modes and set duplex mode. */
778 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
779 if (verbose)
780 printf("link status good ");
781 advert = rl_phy_readreg(sc, PHY_ANAR);
782 ability = rl_phy_readreg(sc, PHY_LPAR);
783
784 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
785 ifm->ifm_media = IFM_ETHER|IFM_100_T4;
786 media |= PHY_BMCR_SPEEDSEL;
787 media &= ~PHY_BMCR_DUPLEX;
788 printf("(100baseT4)\n");
789 } else if (advert & PHY_ANAR_100BTXFULL &&
790 ability & PHY_ANAR_100BTXFULL) {
791 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
792 media |= PHY_BMCR_SPEEDSEL;
793 media |= PHY_BMCR_DUPLEX;
794 printf("(full-duplex, 100Mbps)\n");
795 } else if (advert & PHY_ANAR_100BTXHALF &&
796 ability & PHY_ANAR_100BTXHALF) {
797 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
798 media |= PHY_BMCR_SPEEDSEL;
799 media &= ~PHY_BMCR_DUPLEX;
800 printf("(half-duplex, 100Mbps)\n");
801 } else if (advert & PHY_ANAR_10BTFULL &&
802 ability & PHY_ANAR_10BTFULL) {
803 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
804 media &= ~PHY_BMCR_SPEEDSEL;
805 media |= PHY_BMCR_DUPLEX;
806 printf("(full-duplex, 10Mbps)\n");
807 } else if (advert & PHY_ANAR_10BTHALF &&
808 ability & PHY_ANAR_10BTHALF) {
809 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
810 media &= ~PHY_BMCR_SPEEDSEL;
811 media &= ~PHY_BMCR_DUPLEX;
812 printf("(half-duplex, 10Mbps)\n");
813 } else {
814 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
815 media &= ~PHY_BMCR_SPEEDSEL;
816 media &= ~PHY_BMCR_DUPLEX;
817 printf("(unknown mode! forcing half-duplex, 10Mbps)\n");
818 }
819
820 /* Set ASIC's duplex mode to match the PHY. */
821 rl_phy_writereg(sc, PHY_BMCR, media);
822 } else {
823 if (verbose)
824 printf("no carrier\n");
825 }
826
827 rl_init(sc);
828
829 if (sc->rl_tx_pend) {
830 sc->rl_autoneg = 0;
831 sc->rl_tx_pend = 0;
832 rl_start(ifp);
833 }
834
835 return;
836}
837
838static void rl_getmode_mii(sc)
839 struct rl_softc *sc;
840{
841 u_int16_t bmsr;
842 struct ifnet *ifp;
843
844 ifp = &sc->arpcom.ac_if;
845
846 bmsr = rl_phy_readreg(sc, PHY_BMSR);
847 if (bootverbose)
848 printf("rl%d: PHY status word: %x\n", sc->rl_unit, bmsr);
849
850 /* fallback */
851 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
852
853 if (bmsr & PHY_BMSR_10BTHALF) {
854 if (bootverbose)
855 printf("rl%d: 10Mbps half-duplex mode supported\n",
856 sc->rl_unit);
857 ifmedia_add(&sc->ifmedia,
858 IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
859 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
860 }
861
862 if (bmsr & PHY_BMSR_10BTFULL) {
863 if (bootverbose)
864 printf("rl%d: 10Mbps full-duplex mode supported\n",
865 sc->rl_unit);
866 ifmedia_add(&sc->ifmedia,
867 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
868 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
869 }
870
871 if (bmsr & PHY_BMSR_100BTXHALF) {
872 if (bootverbose)
873 printf("rl%d: 100Mbps half-duplex mode supported\n",
874 sc->rl_unit);
875 ifp->if_baudrate = 100000000;
876 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
877 ifmedia_add(&sc->ifmedia,
878 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
879 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
880 }
881
882 if (bmsr & PHY_BMSR_100BTXFULL) {
883 if (bootverbose)
884 printf("rl%d: 100Mbps full-duplex mode supported\n",
885 sc->rl_unit);
886 ifp->if_baudrate = 100000000;
887 ifmedia_add(&sc->ifmedia,
888 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
889 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
890 }
891
892 /* Some also support 100BaseT4. */
893 if (bmsr & PHY_BMSR_100BT4) {
894 if (bootverbose)
895 printf("rl%d: 100baseT4 mode supported\n", sc->rl_unit);
896 ifp->if_baudrate = 100000000;
897 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL);
898 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4;
899#ifdef FORCE_AUTONEG_TFOUR
900 if (bootverbose)
901 printf("rl%d: forcing on autoneg support for BT4\n",
902 sc->rl_unit);
903 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL):
904 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
905#endif
906 }
907
908 if (bmsr & PHY_BMSR_CANAUTONEG) {
909 if (bootverbose)
910 printf("rl%d: autoneg supported\n", sc->rl_unit);
911 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
912 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
913 }
914
915 return;
916}
917
918/*
919 * Set speed and duplex mode.
920 */
921static void rl_setmode_mii(sc, media)
922 struct rl_softc *sc;
923 int media;
924{
925 u_int16_t bmcr;
926
927 printf("rl%d: selecting MII, ", sc->rl_unit);
928
929 bmcr = rl_phy_readreg(sc, PHY_BMCR);
930
931 bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL|
932 PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK);
933
934 if (IFM_SUBTYPE(media) == IFM_100_T4) {
935 printf("100Mbps/T4, half-duplex\n");
936 bmcr |= PHY_BMCR_SPEEDSEL;
937 bmcr &= ~PHY_BMCR_DUPLEX;
938 }
939
940 if (IFM_SUBTYPE(media) == IFM_100_TX) {
941 printf("100Mbps, ");
942 bmcr |= PHY_BMCR_SPEEDSEL;
943 }
944
945 if (IFM_SUBTYPE(media) == IFM_10_T) {
946 printf("10Mbps, ");
947 bmcr &= ~PHY_BMCR_SPEEDSEL;
948 }
949
950 if ((media & IFM_GMASK) == IFM_FDX) {
951 printf("full duplex\n");
952 bmcr |= PHY_BMCR_DUPLEX;
953 } else {
954 printf("half duplex\n");
955 bmcr &= ~PHY_BMCR_DUPLEX;
956 }
957
958 rl_phy_writereg(sc, PHY_BMCR, bmcr);
959
960 return;
961}
962
963static void rl_reset(sc)
964 struct rl_softc *sc;
965{
966 register int i;
967
968 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
969
970 for (i = 0; i < RL_TIMEOUT; i++) {
971 DELAY(10);
972 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
973 break;
974 }
975 if (i == RL_TIMEOUT)
976 printf("rl%d: reset never completed!\n", sc->rl_unit);
977
978 return;
979}
980
981/*
982 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
983 * IDs against our list and return a device name if we find a match.
984 */
985static char *
986rl_probe(config_id, device_id)
987 pcici_t config_id;
988 pcidi_t device_id;
989{
990 struct rl_type *t;
991
992 t = rl_devs;
993
994 while(t->rl_name != NULL) {
995 if ((device_id & 0xFFFF) == t->rl_vid &&
996 ((device_id >> 16) & 0xFFFF) == t->rl_did) {
997 return(t->rl_name);
998 }
999 t++;
1000 }
1001
1002 return(NULL);
1003}
1004
1005/*
1006 * Attach the interface. Allocate softc structures, do ifmedia
1007 * setup and ethernet/BPF attach.
1008 */
1009static void
1010rl_attach(config_id, unit)
1011 pcici_t config_id;
1012 int unit;
1013{
1014 int s, i;
1015#ifndef RL_USEIOSPACE
1016 vm_offset_t pbase, vbase;
1017#endif
1018 u_char eaddr[ETHER_ADDR_LEN];
1019 u_int32_t command;
1020 struct rl_softc *sc;
1021 struct ifnet *ifp;
1022 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1023 struct rl_type *p;
1024 u_int16_t phy_vid, phy_did, phy_sts;
1025 u_int16_t rl_did = 0;
1026
1027 s = splimp();
1028
1029 sc = malloc(sizeof(struct rl_softc), M_DEVBUF, M_NOWAIT);
1030 if (sc == NULL) {
1031 printf("rl%d: no memory for softc struct!\n", unit);
1032 return;
1033 }
1034 bzero(sc, sizeof(struct rl_softc));
1035
1036 /*
1037 * Handle power management nonsense.
1038 */
1039
1040 command = pci_conf_read(config_id, RL_PCI_CAPID) & 0x000000FF;
1041 if (command == 0x01) {
1042
1043 command = pci_conf_read(config_id, RL_PCI_PWRMGMTCTRL);
1044 if (command & RL_PSTATE_MASK) {
1045 u_int32_t iobase, membase, irq;
1046
1047 /* Save important PCI config data. */
1048 iobase = pci_conf_read(config_id, RL_PCI_LOIO);
1049 membase = pci_conf_read(config_id, RL_PCI_LOMEM);
1050 irq = pci_conf_read(config_id, RL_PCI_INTLINE);
1051
1052 /* Reset the power state. */
1053 printf("rl%d: chip is is in D%d power mode "
1054 "-- setting to D0\n", unit, command & RL_PSTATE_MASK);
1055 command &= 0xFFFFFFFC;
1056 pci_conf_write(config_id, RL_PCI_PWRMGMTCTRL, command);
1057
1058 /* Restore PCI config data. */
1059 pci_conf_write(config_id, RL_PCI_LOIO, iobase);
1060 pci_conf_write(config_id, RL_PCI_LOMEM, membase);
1061 pci_conf_write(config_id, RL_PCI_INTLINE, irq);
1062 }
1063 }
1064
1065 /*
1066 * Map control/status registers.
1067 */
1068 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1069 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1070 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command);
1071 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1072
1073#ifdef RL_USEIOSPACE
1074 if (!(command & PCIM_CMD_PORTEN)) {
1075 printf("rl%d: failed to enable I/O ports!\n", unit);
1076 free(sc, M_DEVBUF);
1077 goto fail;
1078 }
1079
|
1086 sc->iobase = pci_conf_read(config_id, RL_PCI_LOIO) & 0xFFFFFFFC;
|
1080 if (!pci_map_port(config_id, RL_PCI_LOIO,
1081 (u_int16_t *)&(sc->rl_bhandle))) {
1082 printf ("rl%d: couldn't map ports\n", unit);
1083 goto fail;
1084 }
1085 sc->rl_btag = I386_BUS_SPACE_IO; |
1086#else
1087 if (!(command & PCIM_CMD_MEMEN)) {
1088 printf("rl%d: failed to enable memory mapping!\n", unit);
1089 goto fail;
1090 }
1091
1092 if (!pci_map_mem(config_id, RL_PCI_LOMEM, &vbase, &pbase)) {
1093 printf ("rl%d: couldn't map memory\n", unit);
1094 goto fail;
1095 }
|
1097 sc->csr = (volatile caddr_t)vbase;
|
1096 sc->rl_btag = I386_BUS_SPACE_MEM;
1097 sc->rl_bhandle = vbase; |
1098#endif
1099
1100 /* Allocate interrupt */
1101 if (!pci_map_int(config_id, rl_intr, sc, &net_imask)) {
1102 printf("rl%d: couldn't map interrupt\n", unit);
1103 goto fail;
1104 }
1105
1106 /* Reset the adapter. */
1107 rl_reset(sc);
1108
1109 /*
1110 * Get station address from the EEPROM.
1111 */
1112 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
1113
1114 /*
1115 * A RealTek chip was detected. Inform the world.
1116 */
1117 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
1118
1119 sc->rl_unit = unit;
1120 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1121
1122 /*
1123 * Now read the exact device type from the EEPROM to find
1124 * out if it's an 8129 or 8139.
1125 */
1126 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
1127
|
1128 if (rl_did == RT_DEVICEID_8139)
|
| 1128 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030) |
1129 sc->rl_type = RL_8139;
1130 else if (rl_did == RT_DEVICEID_8129)
1131 sc->rl_type = RL_8129;
1132 else {
1133 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
1134 free(sc, M_DEVBUF);
1135 goto fail;
1136 }
1137
1138 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 16, M_DEVBUF,
1139 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0);
1140
1141 if (sc->rl_cdata.rl_rx_buf == NULL) {
1142 free(sc, M_DEVBUF);
1143 printf("rl%d: no memory for list buffers!\n", unit);
1144 goto fail;
1145 }
1146
1147 ifp = &sc->arpcom.ac_if;
1148 ifp->if_softc = sc;
1149 ifp->if_unit = unit;
1150 ifp->if_name = "rl";
1151 ifp->if_mtu = ETHERMTU;
1152 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1153 ifp->if_ioctl = rl_ioctl;
1154 ifp->if_output = ether_output;
1155 ifp->if_start = rl_start;
1156 ifp->if_watchdog = rl_watchdog;
1157 ifp->if_init = rl_init;
1158 ifp->if_baudrate = 10000000;
1159
1160 if (sc->rl_type == RL_8129) {
1161 if (bootverbose)
1162 printf("rl%d: probing for a PHY\n", sc->rl_unit);
1163 for (i = RL_PHYADDR_MIN; i < RL_PHYADDR_MAX + 1; i++) {
1164 if (bootverbose)
1165 printf("rl%d: checking address: %d\n",
1166 sc->rl_unit, i);
1167 sc->rl_phy_addr = i;
1168 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
1169 DELAY(500);
1170 while(rl_phy_readreg(sc, PHY_BMCR)
1171 & PHY_BMCR_RESET);
1172 if ((phy_sts = rl_phy_readreg(sc, PHY_BMSR)))
1173 break;
1174 }
1175 if (phy_sts) {
1176 phy_vid = rl_phy_readreg(sc, PHY_VENID);
1177 phy_did = rl_phy_readreg(sc, PHY_DEVID);
1178 if (bootverbose)
1179 printf("rl%d: found PHY at address %d, ",
1180 sc->rl_unit, sc->rl_phy_addr);
1181 if (bootverbose)
1182 printf("vendor id: %x device id: %x\n",
1183 phy_vid, phy_did);
1184 p = rl_phys;
1185 while(p->rl_vid) {
1186 if (phy_vid == p->rl_vid &&
1187 (phy_did | 0x000F) == p->rl_did) {
1188 sc->rl_pinfo = p;
1189 break;
1190 }
1191 p++;
1192 }
1193 if (sc->rl_pinfo == NULL)
1194 sc->rl_pinfo = &rl_phys[PHY_UNKNOWN];
1195 if (bootverbose)
1196 printf("rl%d: PHY type: %s\n",
1197 sc->rl_unit, sc->rl_pinfo->rl_name);
1198 } else {
1199 printf("rl%d: MII without any phy!\n", sc->rl_unit);
1200 }
1201 }
1202
1203 /*
1204 * Do ifmedia setup.
1205 */
1206 ifmedia_init(&sc->ifmedia, 0, rl_ifmedia_upd, rl_ifmedia_sts);
1207
1208 rl_getmode_mii(sc);
1209
1210 /* Choose a default media. */
1211 media = IFM_ETHER|IFM_AUTO;
1212 ifmedia_set(&sc->ifmedia, media);
1213
1214 rl_autoneg_mii(sc, RL_FLAG_FORCEDELAY, 1);
1215
1216 /*
1217 * Call MI attach routines.
1218 */
1219 if_attach(ifp);
1220 ether_ifattach(ifp);
1221
1222#if NBPFILTER > 0
1223 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1224#endif
1225 at_shutdown(rl_shutdown, sc, SHUTDOWN_POST_SYNC);
1226
1227fail:
1228 splx(s);
1229 return;
1230}
1231
1232/*
1233 * Initialize the transmit descriptors.
1234 */
1235static int rl_list_tx_init(sc)
1236 struct rl_softc *sc;
1237{
1238 struct rl_chain_data *cd;
1239 int i;
1240
1241 cd = &sc->rl_cdata;
1242 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1243 cd->rl_tx_chain[i].rl_desc = i * 4;
1244 CSR_WRITE_4(sc, RL_TXADDR0 + cd->rl_tx_chain[i].rl_desc, 0);
1245 CSR_WRITE_4(sc, RL_TXSTAT0 + cd->rl_tx_chain[i].rl_desc, 0);
1246 if (i == (RL_TX_LIST_CNT - 1))
1247 cd->rl_tx_chain[i].rl_next = &cd->rl_tx_chain[0];
1248 else
1249 cd->rl_tx_chain[i].rl_next = &cd->rl_tx_chain[i + 1];
1250 }
1251
1252 sc->rl_cdata.rl_tx_cnt = 0;
1253 cd->rl_tx_cur = cd->rl_tx_free = &cd->rl_tx_chain[0];
1254
1255 return(0);
1256}
1257
1258/*
1259 * A frame has been uploaded: pass the resulting mbuf chain up to
1260 * the higher level protocols.
1261 *
1262 * You know there's something wrong with a PCI bus-master chip design
1263 * when you have to use m_devget().
1264 *
1265 * The receive operation is badly documented in the datasheet, so I'll
1266 * attempt to document it here. The driver provides a buffer area and
1267 * places its base address in the RX buffer start address register.
1268 * The chip then begins copying frames into the RX buffer. Each frame
1269 * is preceeded by a 32-bit RX status word which specifies the length
1270 * of the frame and certain other status bits. Each frame (starting with
1271 * the status word) is also 32-bit aligned. The frame length is in the
1272 * first 16 bits of the status word; the lower 15 bits correspond with
1273 * the 'rx status register' mentioned in the datasheet.
1274 */
1275static void rl_rxeof(sc)
1276 struct rl_softc *sc;
1277{
1278 struct ether_header *eh;
1279 struct mbuf *m;
1280 struct ifnet *ifp;
1281 int total_len = 0;
1282 u_int32_t rxstat;
1283 caddr_t rxbufpos;
1284 int wrap = 0;
1285 u_int16_t cur_rx;
1286 u_int16_t limit;
1287 u_int16_t rx_bytes = 0, max_bytes;
1288
1289 ifp = &sc->arpcom.ac_if;
1290
1291 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1292
1293 /* Do not try to read past this point. */
1294 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1295
1296 if (limit < cur_rx)
1297 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1298 else
1299 max_bytes = limit - cur_rx;
1300
1301 while((CSR_READ_1(sc, RL_COMMAND) & 1) == 0) {
1302 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1303 rxstat = *(u_int32_t *)rxbufpos;
1304
1305 /*
1306 * Here's a totally undocumented fact for you. When the
1307 * RealTek chip is in the process of copying a packet into
1308 * RAM for you, the length will be 0xfff0. If you spot a
1309 * packet header with this value, you need to stop. The
1310 * datasheet makes absolutely no mention of this and
1311 * RealTek should be shot for this.
1312 */
1313 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1314 break;
1315
1316 if (!(rxstat & RL_RXSTAT_RXOK)) {
1317 ifp->if_ierrors++;
1318 if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT|
1319 RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR|
1320 RL_RXSTAT_ALIGNERR)) {
1321 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB);
1322 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB|
1323 RL_CMD_RX_ENB);
1324 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1325 CSR_WRITE_4(sc, RL_RXADDR,
1326 vtophys(sc->rl_cdata.rl_rx_buf));
1327 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1328 cur_rx = 0;
1329 }
1330 break;
1331 }
1332
1333 /* No errors; receive the packet. */
1334 total_len = rxstat >> 16;
1335 rx_bytes += total_len + 4;
1336
1337 /*
1338 * Avoid trying to read more bytes than we know
1339 * the chip has prepared for us.
1340 */
1341 if (rx_bytes > max_bytes)
1342 break;
1343
1344 rxbufpos = sc->rl_cdata.rl_rx_buf +
1345 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1346
1347 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1348 rxbufpos = sc->rl_cdata.rl_rx_buf;
1349
1350 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1351
1352 if (total_len > wrap) {
1353 m = m_devget(rxbufpos, wrap, 0, ifp, NULL);
1354 if (m == NULL) {
1355 ifp->if_ierrors++;
1356 printf("rl%d: out of mbufs, tried to "
1357 "copy %d bytes\n", sc->rl_unit, wrap);
1358 }
1359 else
1360 m_copyback(m, wrap, total_len - wrap,
1361 sc->rl_cdata.rl_rx_buf);
1362 cur_rx = (total_len - wrap);
1363 } else {
1364 m = m_devget(rxbufpos, total_len, 0, ifp, NULL);
1365 if (m == NULL) {
1366 ifp->if_ierrors++;
1367 printf("rl%d: out of mbufs, tried to "
1368 "copy %d bytes\n", sc->rl_unit, total_len);
1369 }
1370 cur_rx += total_len + 4;
1371 }
1372
1373 /*
1374 * Round up to 32-bit boundary.
1375 */
1376 cur_rx = (cur_rx + 3) & ~3;
1377 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1378
1379 if (m == NULL)
1380 continue;
1381
1382 eh = mtod(m, struct ether_header *);
1383 ifp->if_ipackets++;
1384
1385#if NBPFILTER > 0
1386 /*
1387 * Handle BPF listeners. Let the BPF user see the packet, but
1388 * don't pass it up to the ether_input() layer unless it's
1389 * a broadcast packet, multicast packet, matches our ethernet
1390 * address or the interface is in promiscuous mode.
1391 */
1392 if (ifp->if_bpf) {
1393 bpf_mtap(ifp, m);
1394 if (ifp->if_flags & IFF_PROMISC &&
1395 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1396 ETHER_ADDR_LEN) &&
1397 (eh->ether_dhost[0] & 1) == 0)) {
1398 m_freem(m);
1399 continue;
1400 }
1401 }
1402#endif
1403 /* Remove header from mbuf and pass it on. */
1404 m_adj(m, sizeof(struct ether_header));
1405 ether_input(ifp, eh, m);
1406 }
1407
1408 return;
1409}
1410
1411/*
1412 * A frame was downloaded to the chip. It's safe for us to clean up
1413 * the list buffers.
1414 */
1415static void rl_txeof(sc)
1416 struct rl_softc *sc;
1417{
1418 struct rl_chain *cur_tx;
1419 struct ifnet *ifp;
1420 u_int32_t txstat;
1421
1422 ifp = &sc->arpcom.ac_if;
1423
1424 /* Clear the timeout timer. */
1425 ifp->if_timer = 0;
1426
1427 /*
1428 * Go through our tx list and free mbufs for those
1429 * frames that have been uploaded.
1430 */
1431 if (sc->rl_cdata.rl_tx_free == NULL)
1432 return;
1433
1434 while(sc->rl_cdata.rl_tx_free->rl_mbuf != NULL) {
1435 cur_tx = sc->rl_cdata.rl_tx_free;
1436 txstat = CSR_READ_4(sc, RL_TXSTAT0 + cur_tx->rl_desc);
1437
1438 if (!(txstat & RL_TXSTAT_TX_OK))
1439 break;
1440
1441 if (txstat & RL_TXSTAT_COLLCNT)
1442 ifp->if_collisions +=
1443 (txstat & RL_TXSTAT_COLLCNT) >> 24;
1444
1445 sc->rl_cdata.rl_tx_free = cur_tx->rl_next;
1446
1447 sc->rl_cdata.rl_tx_cnt--;
1448 m_freem(cur_tx->rl_mbuf);
1449 cur_tx->rl_mbuf = NULL;
1450 ifp->if_opackets++;
1451 }
1452
1453 if (!sc->rl_cdata.rl_tx_cnt) {
1454 ifp->if_flags &= ~IFF_OACTIVE;
1455 if (sc->rl_want_auto)
1456 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1);
1457 } else {
1458 if (ifp->if_snd.ifq_head != NULL)
1459 rl_start(ifp);
1460 }
1461
1462 return;
1463}
1464
1465/*
1466 * TX error handler.
1467 */
1468static void rl_txeoc(sc)
1469 struct rl_softc *sc;
1470{
1471 u_int32_t txstat;
1472 struct rl_chain *cur_tx;
1473 struct ifnet *ifp;
1474
1475 ifp = &sc->arpcom.ac_if;
1476
1477 if (sc->rl_cdata.rl_tx_free == NULL)
1478 return;
1479
1480 while(sc->rl_cdata.rl_tx_free->rl_mbuf != NULL) {
1481 cur_tx = sc->rl_cdata.rl_tx_free;
1482 txstat = CSR_READ_4(sc, RL_TXSTAT0 + cur_tx->rl_desc);
1483
1484 if (!(txstat & RL_TXSTAT_OWN))
1485 break;
1486
1487 if (!(txstat & RL_TXSTAT_TX_OK)) {
1488 ifp->if_oerrors++;
1489 if (txstat & RL_TXSTAT_COLLCNT)
1490 ifp->if_collisions +=
1491 (txstat & RL_TXSTAT_COLLCNT) >> 24;
1492 CSR_WRITE_4(sc, RL_TXADDR0 + cur_tx->rl_desc,
1493 vtophys(mtod(cur_tx->rl_mbuf, caddr_t)));
1494 CSR_WRITE_4(sc, RL_TXSTAT0 + cur_tx->rl_desc,
1495 RL_TX_EARLYTHRESH |
1496 cur_tx->rl_mbuf->m_pkthdr.len);
1497 break;
1498 } else {
1499 if (txstat & RL_TXSTAT_COLLCNT)
1500 ifp->if_collisions +=
1501 (txstat & RL_TXSTAT_COLLCNT) >> 24;
1502 sc->rl_cdata.rl_tx_free = cur_tx->rl_next;
1503
1504 sc->rl_cdata.rl_tx_cnt--;
1505 m_freem(cur_tx->rl_mbuf);
1506 cur_tx->rl_mbuf = NULL;
1507 ifp->if_opackets++;
1508 }
1509 }
1510
1511 return;
1512}
1513
1514static void rl_intr(arg)
1515 void *arg;
1516{
1517 struct rl_softc *sc;
1518 struct ifnet *ifp;
1519 u_int16_t status;
1520
1521 sc = arg;
1522 ifp = &sc->arpcom.ac_if;
1523
1524 /* Disable interrupts. */
1525 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1526
1527 for (;;) {
1528
1529 status = CSR_READ_2(sc, RL_ISR);
1530 if (status)
1531 CSR_WRITE_2(sc, RL_ISR, status);
1532
1533 if ((status & RL_INTRS) == 0)
1534 break;
1535
1536 if (status & RL_ISR_RX_OK)
1537 rl_rxeof(sc);
1538
1539 if (status & RL_ISR_RX_ERR)
1540 rl_rxeof(sc);
1541
1542 if (status & RL_ISR_TX_OK)
1543 rl_txeof(sc);
1544
1545 if (status & RL_ISR_TX_ERR)
1546 rl_txeoc(sc);
1547
1548 if (status & RL_ISR_SYSTEM_ERR) {
1549 rl_reset(sc);
1550 rl_init(sc);
1551 }
1552
1553 }
1554
1555 /* Re-enable interrupts. */
1556 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1557
1558 if (ifp->if_snd.ifq_head != NULL) {
1559 rl_start(ifp);
1560 }
1561
1562 return;
1563}
1564
1565/*
1566 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1567 * pointers to the fragment pointers.
1568 */
1569static int rl_encap(sc, c, m_head)
1570 struct rl_softc *sc;
1571 struct rl_chain *c;
1572 struct mbuf *m_head;
1573{
1574 struct mbuf *m;
1575 struct mbuf *m_new = NULL;
1576
1577 /*
1578 * There are two possible encapsulation mechanisms
1579 * that we can use: an efficient one, and a very lossy
1580 * one. The efficient one only happens very rarely,
1581 * whereas the lossy one can and most likely will happen
1582 * all the time.
1583 * The efficient case happens if:
1584 * - the packet fits in a single mbuf
1585 * - the packet is 32-bit aligned within the mbuf data area
1586 * In this case, we can DMA from the mbuf directly.
1587 * The lossy case covers everything else. Bah.
1588 */
1589
1590 m = m_head;
1591
1592 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1593 if (m_new == NULL) {
1594 printf("rl%d: no memory for tx list", sc->rl_unit);
1595 return(1);
1596 }
1597 if (m_head->m_pkthdr.len > MHLEN) {
1598 MCLGET(m_new, M_DONTWAIT);
1599 if (!(m_new->m_flags & M_EXT)) {
1600 m_freem(m_new);
1601 printf("rl%d: no memory for tx list",
1602 sc->rl_unit);
1603 return(1);
1604 }
1605 }
1606 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1607 mtod(m_new, caddr_t));
1608 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1609 m_freem(m_head);
1610 m_head = m_new;
1611
1612 /* Pad frames to at least 60 bytes. */
1613 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1614 m_head->m_pkthdr.len +=
1615 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1616 m_head->m_len = m_head->m_pkthdr.len;
1617 }
1618
1619 c->rl_mbuf = m_head;
1620
1621 return(0);
1622}
1623
1624/*
1625 * Main transmit routine.
1626 */
1627
1628static void rl_start(ifp)
1629 struct ifnet *ifp;
1630{
1631 struct rl_softc *sc;
1632 struct mbuf *m_head = NULL;
1633 struct rl_chain *cur_tx = NULL;
1634
1635 sc = ifp->if_softc;
1636
1637 if (sc->rl_autoneg) {
1638 sc->rl_tx_pend = 1;
1639 return;
1640 }
1641
1642 /*
1643 * Check for an available queue slot. If there are none,
1644 * punt.
1645 */
1646 if (sc->rl_cdata.rl_tx_cur->rl_mbuf != NULL) {
1647 ifp->if_flags |= IFF_OACTIVE;
1648 return;
1649 }
1650
1651 while(sc->rl_cdata.rl_tx_cur->rl_mbuf == NULL) {
1652 IF_DEQUEUE(&ifp->if_snd, m_head);
1653 if (m_head == NULL)
1654 break;
1655
1656
1657 /* Pick a descriptor off the free list. */
1658 cur_tx = sc->rl_cdata.rl_tx_cur;
1659 sc->rl_cdata.rl_tx_cur = cur_tx->rl_next;
1660 sc->rl_cdata.rl_tx_cnt++;
1661
1662 /* Pack the data into the descriptor. */
1663 rl_encap(sc, cur_tx, m_head);
1664
1665#if NBPFILTER > 0
1666 /*
1667 * If there's a BPF listener, bounce a copy of this frame
1668 * to him.
1669 */
1670 if (ifp->if_bpf)
1671 bpf_mtap(ifp, cur_tx->rl_mbuf);
1672#endif
1673 /*
1674 * Transmit the frame.
1675 */
1676 CSR_WRITE_4(sc, RL_TXADDR0 + cur_tx->rl_desc,
1677 vtophys(mtod(cur_tx->rl_mbuf, caddr_t)));
1678 CSR_WRITE_4(sc, RL_TXSTAT0 + cur_tx->rl_desc,
1679 RL_TX_EARLYTHRESH | cur_tx->rl_mbuf->m_pkthdr.len);
1680 }
1681
1682 /*
1683 * Set a timeout in case the chip goes out to lunch.
1684 */
1685 ifp->if_timer = 5;
1686
1687 return;
1688}
1689
1690static void rl_init(xsc)
1691 void *xsc;
1692{
1693 struct rl_softc *sc = xsc;
1694 struct ifnet *ifp = &sc->arpcom.ac_if;
1695 int s, i;
1696 u_int32_t rxcfg = 0;
1697 u_int16_t phy_bmcr = 0;
1698
1699 if (sc->rl_autoneg)
1700 return;
1701
1702 s = splimp();
1703
1704 /*
1705 * XXX Hack for the 8139: the built-in autoneg logic's state
1706 * gets reset by rl_init() when we don't want it to. Try
1707 * to preserve it. (For 8129 cards with real external PHYs,
1708 * the BMCR register doesn't change, but this doesn't hurt.)
1709 */
1710 if (sc->rl_type == RL_8139)
1711 phy_bmcr = rl_phy_readreg(sc, PHY_BMCR);
1712
1713 /*
1714 * Cancel pending I/O and free all RX/TX buffers.
1715 */
1716 rl_stop(sc);
1717
1718 /* Init our MAC address */
1719 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1720 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
1721 }
1722
1723 /* Init the RX buffer pointer register. */
1724 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf));
1725
1726 /* Init TX descriptors. */
1727 rl_list_tx_init(sc);
1728
1729 /*
1730 * Enable transmit and receive.
1731 */
1732 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1733
1734 /*
1735 * Set the buffer size values.
1736 */
1737 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1738
1739 /* Set the individual bit to receive frames for this host only. */
1740 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1741 rxcfg |= RL_RXCFG_RX_INDIV;
1742
1743 /* If we want promiscuous mode, set the allframes bit. */
1744 if (ifp->if_flags & IFF_PROMISC) {
1745 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1746 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1747 } else {
1748 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1749 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1750 }
1751
1752 /*
1753 * Set capture broadcast bit to capture broadcast frames.
1754 */
1755 if (ifp->if_flags & IFF_BROADCAST) {
1756 rxcfg |= RL_RXCFG_RX_BROAD;
1757 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1758 } else {
1759 rxcfg &= ~RL_RXCFG_RX_BROAD;
1760 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1761 }
1762
1763 /*
1764 * Program the multicast filter, if necessary.
1765 */
1766 rl_setmulti(sc);
1767
1768 /*
1769 * Enable interrupts.
1770 */
1771 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1772
1773 /* Start RX/TX process. */
1774 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1775
1776 /* Enable receiver and transmitter. */
1777 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1778
1779 /* Restore state of BMCR */
1780 if (sc->rl_pinfo != NULL)
1781 rl_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1782
1783 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1784
1785 ifp->if_flags |= IFF_RUNNING;
1786 ifp->if_flags &= ~IFF_OACTIVE;
1787
1788 (void)splx(s);
1789
1790 return;
1791}
1792
1793/*
1794 * Set media options.
1795 */
1796static int rl_ifmedia_upd(ifp)
1797 struct ifnet *ifp;
1798{
1799 struct rl_softc *sc;
1800 struct ifmedia *ifm;
1801
1802 sc = ifp->if_softc;
1803 ifm = &sc->ifmedia;
1804
1805 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1806 return(EINVAL);
1807
1808 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1809 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1);
1810 else
1811 rl_setmode_mii(sc, ifm->ifm_media);
1812
1813 return(0);
1814}
1815
1816/*
1817 * Report current media status.
1818 */
1819static void rl_ifmedia_sts(ifp, ifmr)
1820 struct ifnet *ifp;
1821 struct ifmediareq *ifmr;
1822{
1823 struct rl_softc *sc;
1824 u_int16_t advert = 0, ability = 0;
1825
1826 sc = ifp->if_softc;
1827
1828 if (!(rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1829 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1830 ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
1831 else
1832 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
1833
1834 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1835 ifmr->ifm_active |= IFM_FDX;
1836 else
1837 ifmr->ifm_active |= IFM_HDX;
1838 return;
1839 }
1840
1841 ability = rl_phy_readreg(sc, PHY_LPAR);
1842 advert = rl_phy_readreg(sc, PHY_ANAR);
1843 if (advert & PHY_ANAR_100BT4 &&
1844 ability & PHY_ANAR_100BT4) {
1845 ifmr->ifm_active = IFM_ETHER|IFM_100_T4;
1846 } else if (advert & PHY_ANAR_100BTXFULL &&
1847 ability & PHY_ANAR_100BTXFULL) {
1848 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX;
1849 } else if (advert & PHY_ANAR_100BTXHALF &&
1850 ability & PHY_ANAR_100BTXHALF) {
1851 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX;
1852 } else if (advert & PHY_ANAR_10BTFULL &&
1853 ability & PHY_ANAR_10BTFULL) {
1854 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX;
1855 } else if (advert & PHY_ANAR_10BTHALF &&
1856 ability & PHY_ANAR_10BTHALF) {
1857 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX;
1858 }
1859
1860 return;
1861}
1862
1863static int rl_ioctl(ifp, command, data)
1864 struct ifnet *ifp;
1865 u_long command;
1866 caddr_t data;
1867{
1868 struct rl_softc *sc = ifp->if_softc;
1869 struct ifreq *ifr = (struct ifreq *) data;
1870 int s, error = 0;
1871
1872 s = splimp();
1873
1874 switch(command) {
1875 case SIOCSIFADDR:
1876 case SIOCGIFADDR:
1877 case SIOCSIFMTU:
1878 error = ether_ioctl(ifp, command, data);
1879 break;
1880 case SIOCSIFFLAGS:
1881 if (ifp->if_flags & IFF_UP) {
1882 rl_init(sc);
1883 } else {
1884 if (ifp->if_flags & IFF_RUNNING)
1885 rl_stop(sc);
1886 }
1887 error = 0;
1888 break;
1889 case SIOCADDMULTI:
1890 case SIOCDELMULTI:
1891 rl_setmulti(sc);
1892 error = 0;
1893 break;
1894 case SIOCGIFMEDIA:
1895 case SIOCSIFMEDIA:
1896 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1897 break;
1898 default:
1899 error = EINVAL;
1900 break;
1901 }
1902
1903 (void)splx(s);
1904
1905 return(error);
1906}
1907
1908static void rl_watchdog(ifp)
1909 struct ifnet *ifp;
1910{
1911 struct rl_softc *sc;
1912
1913 sc = ifp->if_softc;
1914
1915 if (sc->rl_autoneg) {
1916 rl_autoneg_mii(sc, RL_FLAG_DELAYTIMEO, 1);
1917 return;
1918 }
1919
1920 printf("rl%d: watchdog timeout\n", sc->rl_unit);
1921 ifp->if_oerrors++;
1922 if (!(rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1923 printf("rl%d: no carrier - transceiver cable problem?\n",
1924 sc->rl_unit);
1925 rl_txeoc(sc);
1926 rl_txeof(sc);
1927 rl_rxeof(sc);
1928 rl_init(sc);
1929
1930 return;
1931}
1932
1933/*
1934 * Stop the adapter and free any mbufs allocated to the
1935 * RX and TX lists.
1936 */
1937static void rl_stop(sc)
1938 struct rl_softc *sc;
1939{
1940 register int i;
1941 struct ifnet *ifp;
1942
1943 ifp = &sc->arpcom.ac_if;
1944 ifp->if_timer = 0;
1945
1946 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1947 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1948
1949 /*
1950 * Free the TX list buffers.
1951 */
1952 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1953 if (sc->rl_cdata.rl_tx_chain[i].rl_mbuf != NULL) {
1954 m_freem(sc->rl_cdata.rl_tx_chain[i].rl_mbuf);
1955 sc->rl_cdata.rl_tx_chain[i].rl_mbuf = NULL;
1956 CSR_WRITE_4(sc, RL_TXADDR0 +
1957 sc->rl_cdata.rl_tx_chain[i].rl_desc, 0x00000000);
1958 }
1959 }
1960
1961 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1962
1963 return;
1964}
1965
1966/*
1967 * Stop all chip I/O so that the kernel's probe routines don't
1968 * get confused by errant DMAs when rebooting.
1969 */
1970static void rl_shutdown(howto, arg)
1971 int howto;
1972 void *arg;
1973{
1974 struct rl_softc *sc = (struct rl_softc *)arg;
1975
1976 rl_stop(sc);
1977
1978 return;
1979}
1980
1981
1982static struct pci_device rl_device = {
1983 "rl",
1984 rl_probe,
1985 rl_attach,
1986 &rl_count,
1987 NULL
1988};
1989DATA_SET(pcidevice_set, rl_device);
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