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if_rl.c (61041) if_rl.c (63090)
1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/pci/if_rl.c 61041 2000-05-28 16:13:43Z peter $
32 * $FreeBSD: head/sys/pci/if_rl.c 63090 2000-07-13 22:54:34Z archie $
33 */
34
35/*
36 * RealTek 8129/8139 PCI NIC driver
37 *
38 * Supports several extremely cheap PCI 10/100 adapters based on
39 * the RealTek chipset. Datasheets can be obtained from
40 * www.realtek.com.tw.
41 *
42 * Written by Bill Paul <wpaul@ctr.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
45 */
46
47/*
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
53 *
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
62 *
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
68 * levels.
69 *
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
73 *
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
78 * filter.
79 *
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
84 */
85
86#include <sys/param.h>
87#include <sys/systm.h>
88#include <sys/sockio.h>
89#include <sys/mbuf.h>
90#include <sys/malloc.h>
91#include <sys/kernel.h>
92#include <sys/socket.h>
93
94#include <net/if.h>
95#include <net/if_arp.h>
96#include <net/ethernet.h>
97#include <net/if_dl.h>
98#include <net/if_media.h>
99
100#include <net/bpf.h>
101
102#include <vm/vm.h> /* for vtophys */
103#include <vm/pmap.h> /* for vtophys */
104#include <machine/clock.h> /* for DELAY */
105#include <machine/bus_pio.h>
106#include <machine/bus_memio.h>
107#include <machine/bus.h>
108#include <machine/resource.h>
109#include <sys/bus.h>
110#include <sys/rman.h>
111
112#include <dev/mii/mii.h>
113#include <dev/mii/miivar.h>
114
115#include <pci/pcireg.h>
116#include <pci/pcivar.h>
117
118MODULE_DEPEND(rl, miibus, 1, 1, 1);
119
120/* "controller miibus0" required. See GENERIC if you get errors here. */
121#include "miibus_if.h"
122
123/*
124 * Default to using PIO access for this driver. On SMP systems,
125 * there appear to be problems with memory mapped mode: it looks like
126 * doing too many memory mapped access back to back in rapid succession
127 * can hang the bus. I'm inclined to blame this on crummy design/construction
128 * on the part of RealTek. Memory mapped mode does appear to work on
129 * uniprocessor systems though.
130 */
131#define RL_USEIOSPACE
132
133#include <pci/if_rlreg.h>
134
135#ifndef lint
136static const char rcsid[] =
33 */
34
35/*
36 * RealTek 8129/8139 PCI NIC driver
37 *
38 * Supports several extremely cheap PCI 10/100 adapters based on
39 * the RealTek chipset. Datasheets can be obtained from
40 * www.realtek.com.tw.
41 *
42 * Written by Bill Paul <wpaul@ctr.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
45 */
46
47/*
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
53 *
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
62 *
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
68 * levels.
69 *
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
73 *
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
78 * filter.
79 *
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
84 */
85
86#include <sys/param.h>
87#include <sys/systm.h>
88#include <sys/sockio.h>
89#include <sys/mbuf.h>
90#include <sys/malloc.h>
91#include <sys/kernel.h>
92#include <sys/socket.h>
93
94#include <net/if.h>
95#include <net/if_arp.h>
96#include <net/ethernet.h>
97#include <net/if_dl.h>
98#include <net/if_media.h>
99
100#include <net/bpf.h>
101
102#include <vm/vm.h> /* for vtophys */
103#include <vm/pmap.h> /* for vtophys */
104#include <machine/clock.h> /* for DELAY */
105#include <machine/bus_pio.h>
106#include <machine/bus_memio.h>
107#include <machine/bus.h>
108#include <machine/resource.h>
109#include <sys/bus.h>
110#include <sys/rman.h>
111
112#include <dev/mii/mii.h>
113#include <dev/mii/miivar.h>
114
115#include <pci/pcireg.h>
116#include <pci/pcivar.h>
117
118MODULE_DEPEND(rl, miibus, 1, 1, 1);
119
120/* "controller miibus0" required. See GENERIC if you get errors here. */
121#include "miibus_if.h"
122
123/*
124 * Default to using PIO access for this driver. On SMP systems,
125 * there appear to be problems with memory mapped mode: it looks like
126 * doing too many memory mapped access back to back in rapid succession
127 * can hang the bus. I'm inclined to blame this on crummy design/construction
128 * on the part of RealTek. Memory mapped mode does appear to work on
129 * uniprocessor systems though.
130 */
131#define RL_USEIOSPACE
132
133#include <pci/if_rlreg.h>
134
135#ifndef lint
136static const char rcsid[] =
137 "$FreeBSD: head/sys/pci/if_rl.c 61041 2000-05-28 16:13:43Z peter $";
137 "$FreeBSD: head/sys/pci/if_rl.c 63090 2000-07-13 22:54:34Z archie $";
138#endif
139
140/*
141 * Various supported device vendors/types and their names.
142 */
143static struct rl_type rl_devs[] = {
144 { RT_VENDORID, RT_DEVICEID_8129,
145 "RealTek 8129 10/100BaseTX" },
146 { RT_VENDORID, RT_DEVICEID_8139,
147 "RealTek 8139 10/100BaseTX" },
148 { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
149 "Accton MPX 5030/5038 10/100BaseTX" },
150 { DELTA_VENDORID, DELTA_DEVICEID_8139,
151 "Delta Electronics 8139 10/100BaseTX" },
152 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
153 "Addtron Technolgy 8139 10/100BaseTX" },
154 { 0, 0, NULL }
155};
156
157static int rl_probe __P((device_t));
158static int rl_attach __P((device_t));
159static int rl_detach __P((device_t));
160
161static int rl_encap __P((struct rl_softc *, struct mbuf * ));
162
163static void rl_rxeof __P((struct rl_softc *));
164static void rl_txeof __P((struct rl_softc *));
165static void rl_intr __P((void *));
166static void rl_tick __P((void *));
167static void rl_start __P((struct ifnet *));
168static int rl_ioctl __P((struct ifnet *, u_long, caddr_t));
169static void rl_init __P((void *));
170static void rl_stop __P((struct rl_softc *));
171static void rl_watchdog __P((struct ifnet *));
172static void rl_shutdown __P((device_t));
173static int rl_ifmedia_upd __P((struct ifnet *));
174static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
175
176static void rl_eeprom_putbyte __P((struct rl_softc *, int));
177static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *));
178static void rl_read_eeprom __P((struct rl_softc *, caddr_t,
179 int, int, int));
180static void rl_mii_sync __P((struct rl_softc *));
181static void rl_mii_send __P((struct rl_softc *, u_int32_t, int));
182static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *));
183static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *));
184
185static int rl_miibus_readreg __P((device_t, int, int));
186static int rl_miibus_writereg __P((device_t, int, int, int));
187static void rl_miibus_statchg __P((device_t));
188
189static u_int8_t rl_calchash __P((caddr_t));
190static void rl_setmulti __P((struct rl_softc *));
191static void rl_reset __P((struct rl_softc *));
192static int rl_list_tx_init __P((struct rl_softc *));
193
194#ifdef RL_USEIOSPACE
195#define RL_RES SYS_RES_IOPORT
196#define RL_RID RL_PCI_LOIO
197#else
198#define RL_RES SYS_RES_MEMORY
199#define RL_RID RL_PCI_LOMEM
200#endif
201
202static device_method_t rl_methods[] = {
203 /* Device interface */
204 DEVMETHOD(device_probe, rl_probe),
205 DEVMETHOD(device_attach, rl_attach),
206 DEVMETHOD(device_detach, rl_detach),
207 DEVMETHOD(device_shutdown, rl_shutdown),
208
209 /* bus interface */
210 DEVMETHOD(bus_print_child, bus_generic_print_child),
211 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
212
213 /* MII interface */
214 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
215 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
216 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
217
218 { 0, 0 }
219};
220
221static driver_t rl_driver = {
222 "rl",
223 rl_methods,
224 sizeof(struct rl_softc)
225};
226
227static devclass_t rl_devclass;
228
229DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
230DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
231
232#define EE_SET(x) \
233 CSR_WRITE_1(sc, RL_EECMD, \
234 CSR_READ_1(sc, RL_EECMD) | x)
235
236#define EE_CLR(x) \
237 CSR_WRITE_1(sc, RL_EECMD, \
238 CSR_READ_1(sc, RL_EECMD) & ~x)
239
240/*
241 * Send a read command and address to the EEPROM, check for ACK.
242 */
243static void rl_eeprom_putbyte(sc, addr)
244 struct rl_softc *sc;
245 int addr;
246{
247 register int d, i;
248
249 d = addr | RL_EECMD_READ;
250
251 /*
252 * Feed in each bit and strobe the clock.
253 */
254 for (i = 0x400; i; i >>= 1) {
255 if (d & i) {
256 EE_SET(RL_EE_DATAIN);
257 } else {
258 EE_CLR(RL_EE_DATAIN);
259 }
260 DELAY(100);
261 EE_SET(RL_EE_CLK);
262 DELAY(150);
263 EE_CLR(RL_EE_CLK);
264 DELAY(100);
265 }
266
267 return;
268}
269
270/*
271 * Read a word of data stored in the EEPROM at address 'addr.'
272 */
273static void rl_eeprom_getword(sc, addr, dest)
274 struct rl_softc *sc;
275 int addr;
276 u_int16_t *dest;
277{
278 register int i;
279 u_int16_t word = 0;
280
281 /* Enter EEPROM access mode. */
282 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
283
284 /*
285 * Send address of word we want to read.
286 */
287 rl_eeprom_putbyte(sc, addr);
288
289 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
290
291 /*
292 * Start reading bits from EEPROM.
293 */
294 for (i = 0x8000; i; i >>= 1) {
295 EE_SET(RL_EE_CLK);
296 DELAY(100);
297 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
298 word |= i;
299 EE_CLR(RL_EE_CLK);
300 DELAY(100);
301 }
302
303 /* Turn off EEPROM access mode. */
304 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
305
306 *dest = word;
307
308 return;
309}
310
311/*
312 * Read a sequence of words from the EEPROM.
313 */
314static void rl_read_eeprom(sc, dest, off, cnt, swap)
315 struct rl_softc *sc;
316 caddr_t dest;
317 int off;
318 int cnt;
319 int swap;
320{
321 int i;
322 u_int16_t word = 0, *ptr;
323
324 for (i = 0; i < cnt; i++) {
325 rl_eeprom_getword(sc, off + i, &word);
326 ptr = (u_int16_t *)(dest + (i * 2));
327 if (swap)
328 *ptr = ntohs(word);
329 else
330 *ptr = word;
331 }
332
333 return;
334}
335
336
337/*
338 * MII access routines are provided for the 8129, which
339 * doesn't have a built-in PHY. For the 8139, we fake things
340 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
341 * direct access PHY registers.
342 */
343#define MII_SET(x) \
344 CSR_WRITE_1(sc, RL_MII, \
345 CSR_READ_1(sc, RL_MII) | x)
346
347#define MII_CLR(x) \
348 CSR_WRITE_1(sc, RL_MII, \
349 CSR_READ_1(sc, RL_MII) & ~x)
350
351/*
352 * Sync the PHYs by setting data bit and strobing the clock 32 times.
353 */
354static void rl_mii_sync(sc)
355 struct rl_softc *sc;
356{
357 register int i;
358
359 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
360
361 for (i = 0; i < 32; i++) {
362 MII_SET(RL_MII_CLK);
363 DELAY(1);
364 MII_CLR(RL_MII_CLK);
365 DELAY(1);
366 }
367
368 return;
369}
370
371/*
372 * Clock a series of bits through the MII.
373 */
374static void rl_mii_send(sc, bits, cnt)
375 struct rl_softc *sc;
376 u_int32_t bits;
377 int cnt;
378{
379 int i;
380
381 MII_CLR(RL_MII_CLK);
382
383 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
384 if (bits & i) {
385 MII_SET(RL_MII_DATAOUT);
386 } else {
387 MII_CLR(RL_MII_DATAOUT);
388 }
389 DELAY(1);
390 MII_CLR(RL_MII_CLK);
391 DELAY(1);
392 MII_SET(RL_MII_CLK);
393 }
394}
395
396/*
397 * Read an PHY register through the MII.
398 */
399static int rl_mii_readreg(sc, frame)
400 struct rl_softc *sc;
401 struct rl_mii_frame *frame;
402
403{
404 int i, ack, s;
405
406 s = splimp();
407
408 /*
409 * Set up frame for RX.
410 */
411 frame->mii_stdelim = RL_MII_STARTDELIM;
412 frame->mii_opcode = RL_MII_READOP;
413 frame->mii_turnaround = 0;
414 frame->mii_data = 0;
415
416 CSR_WRITE_2(sc, RL_MII, 0);
417
418 /*
419 * Turn on data xmit.
420 */
421 MII_SET(RL_MII_DIR);
422
423 rl_mii_sync(sc);
424
425 /*
426 * Send command/address info.
427 */
428 rl_mii_send(sc, frame->mii_stdelim, 2);
429 rl_mii_send(sc, frame->mii_opcode, 2);
430 rl_mii_send(sc, frame->mii_phyaddr, 5);
431 rl_mii_send(sc, frame->mii_regaddr, 5);
432
433 /* Idle bit */
434 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
435 DELAY(1);
436 MII_SET(RL_MII_CLK);
437 DELAY(1);
438
439 /* Turn off xmit. */
440 MII_CLR(RL_MII_DIR);
441
442 /* Check for ack */
443 MII_CLR(RL_MII_CLK);
444 DELAY(1);
445 MII_SET(RL_MII_CLK);
446 DELAY(1);
447 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
448
449 /*
450 * Now try reading data bits. If the ack failed, we still
451 * need to clock through 16 cycles to keep the PHY(s) in sync.
452 */
453 if (ack) {
454 for(i = 0; i < 16; i++) {
455 MII_CLR(RL_MII_CLK);
456 DELAY(1);
457 MII_SET(RL_MII_CLK);
458 DELAY(1);
459 }
460 goto fail;
461 }
462
463 for (i = 0x8000; i; i >>= 1) {
464 MII_CLR(RL_MII_CLK);
465 DELAY(1);
466 if (!ack) {
467 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
468 frame->mii_data |= i;
469 DELAY(1);
470 }
471 MII_SET(RL_MII_CLK);
472 DELAY(1);
473 }
474
475fail:
476
477 MII_CLR(RL_MII_CLK);
478 DELAY(1);
479 MII_SET(RL_MII_CLK);
480 DELAY(1);
481
482 splx(s);
483
484 if (ack)
485 return(1);
486 return(0);
487}
488
489/*
490 * Write to a PHY register through the MII.
491 */
492static int rl_mii_writereg(sc, frame)
493 struct rl_softc *sc;
494 struct rl_mii_frame *frame;
495
496{
497 int s;
498
499 s = splimp();
500 /*
501 * Set up frame for TX.
502 */
503
504 frame->mii_stdelim = RL_MII_STARTDELIM;
505 frame->mii_opcode = RL_MII_WRITEOP;
506 frame->mii_turnaround = RL_MII_TURNAROUND;
507
508 /*
509 * Turn on data output.
510 */
511 MII_SET(RL_MII_DIR);
512
513 rl_mii_sync(sc);
514
515 rl_mii_send(sc, frame->mii_stdelim, 2);
516 rl_mii_send(sc, frame->mii_opcode, 2);
517 rl_mii_send(sc, frame->mii_phyaddr, 5);
518 rl_mii_send(sc, frame->mii_regaddr, 5);
519 rl_mii_send(sc, frame->mii_turnaround, 2);
520 rl_mii_send(sc, frame->mii_data, 16);
521
522 /* Idle bit. */
523 MII_SET(RL_MII_CLK);
524 DELAY(1);
525 MII_CLR(RL_MII_CLK);
526 DELAY(1);
527
528 /*
529 * Turn off xmit.
530 */
531 MII_CLR(RL_MII_DIR);
532
533 splx(s);
534
535 return(0);
536}
537
538static int rl_miibus_readreg(dev, phy, reg)
539 device_t dev;
540 int phy, reg;
541{
542 struct rl_softc *sc;
543 struct rl_mii_frame frame;
544 u_int16_t rval = 0;
545 u_int16_t rl8139_reg = 0;
546
547 sc = device_get_softc(dev);
548
549 if (sc->rl_type == RL_8139) {
550 /* Pretend the internal PHY is only at address 0 */
551 if (phy)
552 return(0);
553 switch(reg) {
554 case MII_BMCR:
555 rl8139_reg = RL_BMCR;
556 break;
557 case MII_BMSR:
558 rl8139_reg = RL_BMSR;
559 break;
560 case MII_ANAR:
561 rl8139_reg = RL_ANAR;
562 break;
563 case MII_ANER:
564 rl8139_reg = RL_ANER;
565 break;
566 case MII_ANLPAR:
567 rl8139_reg = RL_LPAR;
568 break;
569 case MII_PHYIDR1:
570 case MII_PHYIDR2:
571 return(0);
572 break;
573 default:
574 printf("rl%d: bad phy register\n", sc->rl_unit);
575 return(0);
576 }
577 rval = CSR_READ_2(sc, rl8139_reg);
578 return(rval);
579 }
580
581 bzero((char *)&frame, sizeof(frame));
582
583 frame.mii_phyaddr = phy;
584 frame.mii_regaddr = reg;
585 rl_mii_readreg(sc, &frame);
586
587 return(frame.mii_data);
588}
589
590static int rl_miibus_writereg(dev, phy, reg, data)
591 device_t dev;
592 int phy, reg, data;
593{
594 struct rl_softc *sc;
595 struct rl_mii_frame frame;
596 u_int16_t rl8139_reg = 0;
597
598 sc = device_get_softc(dev);
599
600 if (sc->rl_type == RL_8139) {
601 /* Pretend the internal PHY is only at address 0 */
602 if (phy)
603 return(0);
604 switch(reg) {
605 case MII_BMCR:
606 rl8139_reg = RL_BMCR;
607 break;
608 case MII_BMSR:
609 rl8139_reg = RL_BMSR;
610 break;
611 case MII_ANAR:
612 rl8139_reg = RL_ANAR;
613 break;
614 case MII_ANER:
615 rl8139_reg = RL_ANER;
616 break;
617 case MII_ANLPAR:
618 rl8139_reg = RL_LPAR;
619 break;
620 case MII_PHYIDR1:
621 case MII_PHYIDR2:
622 return(0);
623 break;
624 default:
625 printf("rl%d: bad phy register\n", sc->rl_unit);
626 return(0);
627 }
628 CSR_WRITE_2(sc, rl8139_reg, data);
629 return(0);
630 }
631
632 bzero((char *)&frame, sizeof(frame));
633
634 frame.mii_phyaddr = phy;
635 frame.mii_regaddr = reg;
636 frame.mii_data = data;
637
638 rl_mii_writereg(sc, &frame);
639
640 return(0);
641}
642
643static void rl_miibus_statchg(dev)
644 device_t dev;
645{
646 return;
647}
648
649/*
650 * Calculate CRC of a multicast group address, return the upper 6 bits.
651 */
652static u_int8_t rl_calchash(addr)
653 caddr_t addr;
654{
655 u_int32_t crc, carry;
656 int i, j;
657 u_int8_t c;
658
659 /* Compute CRC for the address value. */
660 crc = 0xFFFFFFFF; /* initial value */
661
662 for (i = 0; i < 6; i++) {
663 c = *(addr + i);
664 for (j = 0; j < 8; j++) {
665 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
666 crc <<= 1;
667 c >>= 1;
668 if (carry)
669 crc = (crc ^ 0x04c11db6) | carry;
670 }
671 }
672
673 /* return the filter bit position */
674 return(crc >> 26);
675}
676
677/*
678 * Program the 64-bit multicast hash filter.
679 */
680static void rl_setmulti(sc)
681 struct rl_softc *sc;
682{
683 struct ifnet *ifp;
684 int h = 0;
685 u_int32_t hashes[2] = { 0, 0 };
686 struct ifmultiaddr *ifma;
687 u_int32_t rxfilt;
688 int mcnt = 0;
689
690 ifp = &sc->arpcom.ac_if;
691
692 rxfilt = CSR_READ_4(sc, RL_RXCFG);
693
694 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
695 rxfilt |= RL_RXCFG_RX_MULTI;
696 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
697 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
698 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
699 return;
700 }
701
702 /* first, zot all the existing hash bits */
703 CSR_WRITE_4(sc, RL_MAR0, 0);
704 CSR_WRITE_4(sc, RL_MAR4, 0);
705
706 /* now program new ones */
707 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
708 ifma = ifma->ifma_link.le_next) {
709 if (ifma->ifma_addr->sa_family != AF_LINK)
710 continue;
711 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
712 if (h < 32)
713 hashes[0] |= (1 << h);
714 else
715 hashes[1] |= (1 << (h - 32));
716 mcnt++;
717 }
718
719 if (mcnt)
720 rxfilt |= RL_RXCFG_RX_MULTI;
721 else
722 rxfilt &= ~RL_RXCFG_RX_MULTI;
723
724 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
725 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
726 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
727
728 return;
729}
730
731static void rl_reset(sc)
732 struct rl_softc *sc;
733{
734 register int i;
735
736 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
737
738 for (i = 0; i < RL_TIMEOUT; i++) {
739 DELAY(10);
740 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
741 break;
742 }
743 if (i == RL_TIMEOUT)
744 printf("rl%d: reset never completed!\n", sc->rl_unit);
745
746 return;
747}
748
749/*
750 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
751 * IDs against our list and return a device name if we find a match.
752 */
753static int rl_probe(dev)
754 device_t dev;
755{
756 struct rl_type *t;
757
758 t = rl_devs;
759
760 while(t->rl_name != NULL) {
761 if ((pci_get_vendor(dev) == t->rl_vid) &&
762 (pci_get_device(dev) == t->rl_did)) {
763 device_set_desc(dev, t->rl_name);
764 return(0);
765 }
766 t++;
767 }
768
769 return(ENXIO);
770}
771
772/*
773 * Attach the interface. Allocate softc structures, do ifmedia
774 * setup and ethernet/BPF attach.
775 */
776static int rl_attach(dev)
777 device_t dev;
778{
779 int s;
780 u_char eaddr[ETHER_ADDR_LEN];
781 u_int32_t command;
782 struct rl_softc *sc;
783 struct ifnet *ifp;
784 u_int16_t rl_did = 0;
785 int unit, error = 0, rid;
786
787 s = splimp();
788
789 sc = device_get_softc(dev);
790 unit = device_get_unit(dev);
791 bzero(sc, sizeof(struct rl_softc));
792
793 /*
794 * Handle power management nonsense.
795 */
796
797 command = pci_read_config(dev, RL_PCI_CAPID, 4) & 0x000000FF;
798 if (command == 0x01) {
799
800 command = pci_read_config(dev, RL_PCI_PWRMGMTCTRL, 4);
801 if (command & RL_PSTATE_MASK) {
802 u_int32_t iobase, membase, irq;
803
804 /* Save important PCI config data. */
805 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
806 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
807 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
808
809 /* Reset the power state. */
810 printf("rl%d: chip is is in D%d power mode "
811 "-- setting to D0\n", unit, command & RL_PSTATE_MASK);
812 command &= 0xFFFFFFFC;
813 pci_write_config(dev, RL_PCI_PWRMGMTCTRL, command, 4);
814
815 /* Restore PCI config data. */
816 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
817 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
818 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
819 }
820 }
821
822 /*
823 * Map control/status registers.
824 */
825 command = pci_read_config(dev, PCIR_COMMAND, 4);
826 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
827 pci_write_config(dev, PCIR_COMMAND, command, 4);
828 command = pci_read_config(dev, PCIR_COMMAND, 4);
829
830#ifdef RL_USEIOSPACE
831 if (!(command & PCIM_CMD_PORTEN)) {
832 printf("rl%d: failed to enable I/O ports!\n", unit);
833 error = ENXIO;
834 goto fail;
835 }
836#else
837 if (!(command & PCIM_CMD_MEMEN)) {
838 printf("rl%d: failed to enable memory mapping!\n", unit);
839 error = ENXIO;
840 goto fail;
841 }
842#endif
843
844 rid = RL_RID;
845 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid,
846 0, ~0, 1, RF_ACTIVE);
847
848 if (sc->rl_res == NULL) {
849 printf ("rl%d: couldn't map ports/memory\n", unit);
850 error = ENXIO;
851 goto fail;
852 }
853
854 sc->rl_btag = rman_get_bustag(sc->rl_res);
855 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
856
857 rid = 0;
858 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
859 RF_SHAREABLE | RF_ACTIVE);
860
861 if (sc->rl_irq == NULL) {
862 printf("rl%d: couldn't map interrupt\n", unit);
863 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
864 error = ENXIO;
865 goto fail;
866 }
867
868 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
869 rl_intr, sc, &sc->rl_intrhand);
870
871 if (error) {
872 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res);
873 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
874 printf("rl%d: couldn't set up irq\n", unit);
875 goto fail;
876 }
877
878 callout_handle_init(&sc->rl_stat_ch);
879
880 /* Reset the adapter. */
881 rl_reset(sc);
882
883 /*
884 * Get station address from the EEPROM.
885 */
886 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
887
888 /*
889 * A RealTek chip was detected. Inform the world.
890 */
891 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
892
893 sc->rl_unit = unit;
894 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
895
896 /*
897 * Now read the exact device type from the EEPROM to find
898 * out if it's an 8129 or 8139.
899 */
900 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
901
902 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
903 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139)
904 sc->rl_type = RL_8139;
905 else if (rl_did == RT_DEVICEID_8129)
906 sc->rl_type = RL_8129;
907 else {
908 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
909 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
910 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res);
911 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
912 error = ENXIO;
913 goto fail;
914 }
915
916 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 1518, M_DEVBUF,
917 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
918
919 if (sc->rl_cdata.rl_rx_buf == NULL) {
920 printf("rl%d: no memory for list buffers!\n", unit);
921 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
922 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res);
923 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
924 error = ENXIO;
925 goto fail;
926 }
927
928 /* Leave a few bytes before the start of the RX ring buffer. */
929 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
930 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
931
932 /* Do MII setup */
933 if (mii_phy_probe(dev, &sc->rl_miibus,
934 rl_ifmedia_upd, rl_ifmedia_sts)) {
935 printf("rl%d: MII without any phy!\n", sc->rl_unit);
936 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
937 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res);
938 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
939 free(sc->rl_cdata.rl_rx_buf, M_DEVBUF);
940 error = ENXIO;
941 goto fail;
942 }
943
944 ifp = &sc->arpcom.ac_if;
945 ifp->if_softc = sc;
946 ifp->if_unit = unit;
947 ifp->if_name = "rl";
948 ifp->if_mtu = ETHERMTU;
949 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
950 ifp->if_ioctl = rl_ioctl;
951 ifp->if_output = ether_output;
952 ifp->if_start = rl_start;
953 ifp->if_watchdog = rl_watchdog;
954 ifp->if_init = rl_init;
955 ifp->if_baudrate = 10000000;
956 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
957
958 /*
138#endif
139
140/*
141 * Various supported device vendors/types and their names.
142 */
143static struct rl_type rl_devs[] = {
144 { RT_VENDORID, RT_DEVICEID_8129,
145 "RealTek 8129 10/100BaseTX" },
146 { RT_VENDORID, RT_DEVICEID_8139,
147 "RealTek 8139 10/100BaseTX" },
148 { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
149 "Accton MPX 5030/5038 10/100BaseTX" },
150 { DELTA_VENDORID, DELTA_DEVICEID_8139,
151 "Delta Electronics 8139 10/100BaseTX" },
152 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
153 "Addtron Technolgy 8139 10/100BaseTX" },
154 { 0, 0, NULL }
155};
156
157static int rl_probe __P((device_t));
158static int rl_attach __P((device_t));
159static int rl_detach __P((device_t));
160
161static int rl_encap __P((struct rl_softc *, struct mbuf * ));
162
163static void rl_rxeof __P((struct rl_softc *));
164static void rl_txeof __P((struct rl_softc *));
165static void rl_intr __P((void *));
166static void rl_tick __P((void *));
167static void rl_start __P((struct ifnet *));
168static int rl_ioctl __P((struct ifnet *, u_long, caddr_t));
169static void rl_init __P((void *));
170static void rl_stop __P((struct rl_softc *));
171static void rl_watchdog __P((struct ifnet *));
172static void rl_shutdown __P((device_t));
173static int rl_ifmedia_upd __P((struct ifnet *));
174static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
175
176static void rl_eeprom_putbyte __P((struct rl_softc *, int));
177static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *));
178static void rl_read_eeprom __P((struct rl_softc *, caddr_t,
179 int, int, int));
180static void rl_mii_sync __P((struct rl_softc *));
181static void rl_mii_send __P((struct rl_softc *, u_int32_t, int));
182static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *));
183static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *));
184
185static int rl_miibus_readreg __P((device_t, int, int));
186static int rl_miibus_writereg __P((device_t, int, int, int));
187static void rl_miibus_statchg __P((device_t));
188
189static u_int8_t rl_calchash __P((caddr_t));
190static void rl_setmulti __P((struct rl_softc *));
191static void rl_reset __P((struct rl_softc *));
192static int rl_list_tx_init __P((struct rl_softc *));
193
194#ifdef RL_USEIOSPACE
195#define RL_RES SYS_RES_IOPORT
196#define RL_RID RL_PCI_LOIO
197#else
198#define RL_RES SYS_RES_MEMORY
199#define RL_RID RL_PCI_LOMEM
200#endif
201
202static device_method_t rl_methods[] = {
203 /* Device interface */
204 DEVMETHOD(device_probe, rl_probe),
205 DEVMETHOD(device_attach, rl_attach),
206 DEVMETHOD(device_detach, rl_detach),
207 DEVMETHOD(device_shutdown, rl_shutdown),
208
209 /* bus interface */
210 DEVMETHOD(bus_print_child, bus_generic_print_child),
211 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
212
213 /* MII interface */
214 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
215 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
216 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
217
218 { 0, 0 }
219};
220
221static driver_t rl_driver = {
222 "rl",
223 rl_methods,
224 sizeof(struct rl_softc)
225};
226
227static devclass_t rl_devclass;
228
229DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
230DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
231
232#define EE_SET(x) \
233 CSR_WRITE_1(sc, RL_EECMD, \
234 CSR_READ_1(sc, RL_EECMD) | x)
235
236#define EE_CLR(x) \
237 CSR_WRITE_1(sc, RL_EECMD, \
238 CSR_READ_1(sc, RL_EECMD) & ~x)
239
240/*
241 * Send a read command and address to the EEPROM, check for ACK.
242 */
243static void rl_eeprom_putbyte(sc, addr)
244 struct rl_softc *sc;
245 int addr;
246{
247 register int d, i;
248
249 d = addr | RL_EECMD_READ;
250
251 /*
252 * Feed in each bit and strobe the clock.
253 */
254 for (i = 0x400; i; i >>= 1) {
255 if (d & i) {
256 EE_SET(RL_EE_DATAIN);
257 } else {
258 EE_CLR(RL_EE_DATAIN);
259 }
260 DELAY(100);
261 EE_SET(RL_EE_CLK);
262 DELAY(150);
263 EE_CLR(RL_EE_CLK);
264 DELAY(100);
265 }
266
267 return;
268}
269
270/*
271 * Read a word of data stored in the EEPROM at address 'addr.'
272 */
273static void rl_eeprom_getword(sc, addr, dest)
274 struct rl_softc *sc;
275 int addr;
276 u_int16_t *dest;
277{
278 register int i;
279 u_int16_t word = 0;
280
281 /* Enter EEPROM access mode. */
282 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
283
284 /*
285 * Send address of word we want to read.
286 */
287 rl_eeprom_putbyte(sc, addr);
288
289 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
290
291 /*
292 * Start reading bits from EEPROM.
293 */
294 for (i = 0x8000; i; i >>= 1) {
295 EE_SET(RL_EE_CLK);
296 DELAY(100);
297 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
298 word |= i;
299 EE_CLR(RL_EE_CLK);
300 DELAY(100);
301 }
302
303 /* Turn off EEPROM access mode. */
304 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
305
306 *dest = word;
307
308 return;
309}
310
311/*
312 * Read a sequence of words from the EEPROM.
313 */
314static void rl_read_eeprom(sc, dest, off, cnt, swap)
315 struct rl_softc *sc;
316 caddr_t dest;
317 int off;
318 int cnt;
319 int swap;
320{
321 int i;
322 u_int16_t word = 0, *ptr;
323
324 for (i = 0; i < cnt; i++) {
325 rl_eeprom_getword(sc, off + i, &word);
326 ptr = (u_int16_t *)(dest + (i * 2));
327 if (swap)
328 *ptr = ntohs(word);
329 else
330 *ptr = word;
331 }
332
333 return;
334}
335
336
337/*
338 * MII access routines are provided for the 8129, which
339 * doesn't have a built-in PHY. For the 8139, we fake things
340 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
341 * direct access PHY registers.
342 */
343#define MII_SET(x) \
344 CSR_WRITE_1(sc, RL_MII, \
345 CSR_READ_1(sc, RL_MII) | x)
346
347#define MII_CLR(x) \
348 CSR_WRITE_1(sc, RL_MII, \
349 CSR_READ_1(sc, RL_MII) & ~x)
350
351/*
352 * Sync the PHYs by setting data bit and strobing the clock 32 times.
353 */
354static void rl_mii_sync(sc)
355 struct rl_softc *sc;
356{
357 register int i;
358
359 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
360
361 for (i = 0; i < 32; i++) {
362 MII_SET(RL_MII_CLK);
363 DELAY(1);
364 MII_CLR(RL_MII_CLK);
365 DELAY(1);
366 }
367
368 return;
369}
370
371/*
372 * Clock a series of bits through the MII.
373 */
374static void rl_mii_send(sc, bits, cnt)
375 struct rl_softc *sc;
376 u_int32_t bits;
377 int cnt;
378{
379 int i;
380
381 MII_CLR(RL_MII_CLK);
382
383 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
384 if (bits & i) {
385 MII_SET(RL_MII_DATAOUT);
386 } else {
387 MII_CLR(RL_MII_DATAOUT);
388 }
389 DELAY(1);
390 MII_CLR(RL_MII_CLK);
391 DELAY(1);
392 MII_SET(RL_MII_CLK);
393 }
394}
395
396/*
397 * Read an PHY register through the MII.
398 */
399static int rl_mii_readreg(sc, frame)
400 struct rl_softc *sc;
401 struct rl_mii_frame *frame;
402
403{
404 int i, ack, s;
405
406 s = splimp();
407
408 /*
409 * Set up frame for RX.
410 */
411 frame->mii_stdelim = RL_MII_STARTDELIM;
412 frame->mii_opcode = RL_MII_READOP;
413 frame->mii_turnaround = 0;
414 frame->mii_data = 0;
415
416 CSR_WRITE_2(sc, RL_MII, 0);
417
418 /*
419 * Turn on data xmit.
420 */
421 MII_SET(RL_MII_DIR);
422
423 rl_mii_sync(sc);
424
425 /*
426 * Send command/address info.
427 */
428 rl_mii_send(sc, frame->mii_stdelim, 2);
429 rl_mii_send(sc, frame->mii_opcode, 2);
430 rl_mii_send(sc, frame->mii_phyaddr, 5);
431 rl_mii_send(sc, frame->mii_regaddr, 5);
432
433 /* Idle bit */
434 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
435 DELAY(1);
436 MII_SET(RL_MII_CLK);
437 DELAY(1);
438
439 /* Turn off xmit. */
440 MII_CLR(RL_MII_DIR);
441
442 /* Check for ack */
443 MII_CLR(RL_MII_CLK);
444 DELAY(1);
445 MII_SET(RL_MII_CLK);
446 DELAY(1);
447 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
448
449 /*
450 * Now try reading data bits. If the ack failed, we still
451 * need to clock through 16 cycles to keep the PHY(s) in sync.
452 */
453 if (ack) {
454 for(i = 0; i < 16; i++) {
455 MII_CLR(RL_MII_CLK);
456 DELAY(1);
457 MII_SET(RL_MII_CLK);
458 DELAY(1);
459 }
460 goto fail;
461 }
462
463 for (i = 0x8000; i; i >>= 1) {
464 MII_CLR(RL_MII_CLK);
465 DELAY(1);
466 if (!ack) {
467 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
468 frame->mii_data |= i;
469 DELAY(1);
470 }
471 MII_SET(RL_MII_CLK);
472 DELAY(1);
473 }
474
475fail:
476
477 MII_CLR(RL_MII_CLK);
478 DELAY(1);
479 MII_SET(RL_MII_CLK);
480 DELAY(1);
481
482 splx(s);
483
484 if (ack)
485 return(1);
486 return(0);
487}
488
489/*
490 * Write to a PHY register through the MII.
491 */
492static int rl_mii_writereg(sc, frame)
493 struct rl_softc *sc;
494 struct rl_mii_frame *frame;
495
496{
497 int s;
498
499 s = splimp();
500 /*
501 * Set up frame for TX.
502 */
503
504 frame->mii_stdelim = RL_MII_STARTDELIM;
505 frame->mii_opcode = RL_MII_WRITEOP;
506 frame->mii_turnaround = RL_MII_TURNAROUND;
507
508 /*
509 * Turn on data output.
510 */
511 MII_SET(RL_MII_DIR);
512
513 rl_mii_sync(sc);
514
515 rl_mii_send(sc, frame->mii_stdelim, 2);
516 rl_mii_send(sc, frame->mii_opcode, 2);
517 rl_mii_send(sc, frame->mii_phyaddr, 5);
518 rl_mii_send(sc, frame->mii_regaddr, 5);
519 rl_mii_send(sc, frame->mii_turnaround, 2);
520 rl_mii_send(sc, frame->mii_data, 16);
521
522 /* Idle bit. */
523 MII_SET(RL_MII_CLK);
524 DELAY(1);
525 MII_CLR(RL_MII_CLK);
526 DELAY(1);
527
528 /*
529 * Turn off xmit.
530 */
531 MII_CLR(RL_MII_DIR);
532
533 splx(s);
534
535 return(0);
536}
537
538static int rl_miibus_readreg(dev, phy, reg)
539 device_t dev;
540 int phy, reg;
541{
542 struct rl_softc *sc;
543 struct rl_mii_frame frame;
544 u_int16_t rval = 0;
545 u_int16_t rl8139_reg = 0;
546
547 sc = device_get_softc(dev);
548
549 if (sc->rl_type == RL_8139) {
550 /* Pretend the internal PHY is only at address 0 */
551 if (phy)
552 return(0);
553 switch(reg) {
554 case MII_BMCR:
555 rl8139_reg = RL_BMCR;
556 break;
557 case MII_BMSR:
558 rl8139_reg = RL_BMSR;
559 break;
560 case MII_ANAR:
561 rl8139_reg = RL_ANAR;
562 break;
563 case MII_ANER:
564 rl8139_reg = RL_ANER;
565 break;
566 case MII_ANLPAR:
567 rl8139_reg = RL_LPAR;
568 break;
569 case MII_PHYIDR1:
570 case MII_PHYIDR2:
571 return(0);
572 break;
573 default:
574 printf("rl%d: bad phy register\n", sc->rl_unit);
575 return(0);
576 }
577 rval = CSR_READ_2(sc, rl8139_reg);
578 return(rval);
579 }
580
581 bzero((char *)&frame, sizeof(frame));
582
583 frame.mii_phyaddr = phy;
584 frame.mii_regaddr = reg;
585 rl_mii_readreg(sc, &frame);
586
587 return(frame.mii_data);
588}
589
590static int rl_miibus_writereg(dev, phy, reg, data)
591 device_t dev;
592 int phy, reg, data;
593{
594 struct rl_softc *sc;
595 struct rl_mii_frame frame;
596 u_int16_t rl8139_reg = 0;
597
598 sc = device_get_softc(dev);
599
600 if (sc->rl_type == RL_8139) {
601 /* Pretend the internal PHY is only at address 0 */
602 if (phy)
603 return(0);
604 switch(reg) {
605 case MII_BMCR:
606 rl8139_reg = RL_BMCR;
607 break;
608 case MII_BMSR:
609 rl8139_reg = RL_BMSR;
610 break;
611 case MII_ANAR:
612 rl8139_reg = RL_ANAR;
613 break;
614 case MII_ANER:
615 rl8139_reg = RL_ANER;
616 break;
617 case MII_ANLPAR:
618 rl8139_reg = RL_LPAR;
619 break;
620 case MII_PHYIDR1:
621 case MII_PHYIDR2:
622 return(0);
623 break;
624 default:
625 printf("rl%d: bad phy register\n", sc->rl_unit);
626 return(0);
627 }
628 CSR_WRITE_2(sc, rl8139_reg, data);
629 return(0);
630 }
631
632 bzero((char *)&frame, sizeof(frame));
633
634 frame.mii_phyaddr = phy;
635 frame.mii_regaddr = reg;
636 frame.mii_data = data;
637
638 rl_mii_writereg(sc, &frame);
639
640 return(0);
641}
642
643static void rl_miibus_statchg(dev)
644 device_t dev;
645{
646 return;
647}
648
649/*
650 * Calculate CRC of a multicast group address, return the upper 6 bits.
651 */
652static u_int8_t rl_calchash(addr)
653 caddr_t addr;
654{
655 u_int32_t crc, carry;
656 int i, j;
657 u_int8_t c;
658
659 /* Compute CRC for the address value. */
660 crc = 0xFFFFFFFF; /* initial value */
661
662 for (i = 0; i < 6; i++) {
663 c = *(addr + i);
664 for (j = 0; j < 8; j++) {
665 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
666 crc <<= 1;
667 c >>= 1;
668 if (carry)
669 crc = (crc ^ 0x04c11db6) | carry;
670 }
671 }
672
673 /* return the filter bit position */
674 return(crc >> 26);
675}
676
677/*
678 * Program the 64-bit multicast hash filter.
679 */
680static void rl_setmulti(sc)
681 struct rl_softc *sc;
682{
683 struct ifnet *ifp;
684 int h = 0;
685 u_int32_t hashes[2] = { 0, 0 };
686 struct ifmultiaddr *ifma;
687 u_int32_t rxfilt;
688 int mcnt = 0;
689
690 ifp = &sc->arpcom.ac_if;
691
692 rxfilt = CSR_READ_4(sc, RL_RXCFG);
693
694 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
695 rxfilt |= RL_RXCFG_RX_MULTI;
696 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
697 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
698 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
699 return;
700 }
701
702 /* first, zot all the existing hash bits */
703 CSR_WRITE_4(sc, RL_MAR0, 0);
704 CSR_WRITE_4(sc, RL_MAR4, 0);
705
706 /* now program new ones */
707 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
708 ifma = ifma->ifma_link.le_next) {
709 if (ifma->ifma_addr->sa_family != AF_LINK)
710 continue;
711 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
712 if (h < 32)
713 hashes[0] |= (1 << h);
714 else
715 hashes[1] |= (1 << (h - 32));
716 mcnt++;
717 }
718
719 if (mcnt)
720 rxfilt |= RL_RXCFG_RX_MULTI;
721 else
722 rxfilt &= ~RL_RXCFG_RX_MULTI;
723
724 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
725 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
726 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
727
728 return;
729}
730
731static void rl_reset(sc)
732 struct rl_softc *sc;
733{
734 register int i;
735
736 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
737
738 for (i = 0; i < RL_TIMEOUT; i++) {
739 DELAY(10);
740 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
741 break;
742 }
743 if (i == RL_TIMEOUT)
744 printf("rl%d: reset never completed!\n", sc->rl_unit);
745
746 return;
747}
748
749/*
750 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
751 * IDs against our list and return a device name if we find a match.
752 */
753static int rl_probe(dev)
754 device_t dev;
755{
756 struct rl_type *t;
757
758 t = rl_devs;
759
760 while(t->rl_name != NULL) {
761 if ((pci_get_vendor(dev) == t->rl_vid) &&
762 (pci_get_device(dev) == t->rl_did)) {
763 device_set_desc(dev, t->rl_name);
764 return(0);
765 }
766 t++;
767 }
768
769 return(ENXIO);
770}
771
772/*
773 * Attach the interface. Allocate softc structures, do ifmedia
774 * setup and ethernet/BPF attach.
775 */
776static int rl_attach(dev)
777 device_t dev;
778{
779 int s;
780 u_char eaddr[ETHER_ADDR_LEN];
781 u_int32_t command;
782 struct rl_softc *sc;
783 struct ifnet *ifp;
784 u_int16_t rl_did = 0;
785 int unit, error = 0, rid;
786
787 s = splimp();
788
789 sc = device_get_softc(dev);
790 unit = device_get_unit(dev);
791 bzero(sc, sizeof(struct rl_softc));
792
793 /*
794 * Handle power management nonsense.
795 */
796
797 command = pci_read_config(dev, RL_PCI_CAPID, 4) & 0x000000FF;
798 if (command == 0x01) {
799
800 command = pci_read_config(dev, RL_PCI_PWRMGMTCTRL, 4);
801 if (command & RL_PSTATE_MASK) {
802 u_int32_t iobase, membase, irq;
803
804 /* Save important PCI config data. */
805 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
806 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
807 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
808
809 /* Reset the power state. */
810 printf("rl%d: chip is is in D%d power mode "
811 "-- setting to D0\n", unit, command & RL_PSTATE_MASK);
812 command &= 0xFFFFFFFC;
813 pci_write_config(dev, RL_PCI_PWRMGMTCTRL, command, 4);
814
815 /* Restore PCI config data. */
816 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
817 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
818 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
819 }
820 }
821
822 /*
823 * Map control/status registers.
824 */
825 command = pci_read_config(dev, PCIR_COMMAND, 4);
826 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
827 pci_write_config(dev, PCIR_COMMAND, command, 4);
828 command = pci_read_config(dev, PCIR_COMMAND, 4);
829
830#ifdef RL_USEIOSPACE
831 if (!(command & PCIM_CMD_PORTEN)) {
832 printf("rl%d: failed to enable I/O ports!\n", unit);
833 error = ENXIO;
834 goto fail;
835 }
836#else
837 if (!(command & PCIM_CMD_MEMEN)) {
838 printf("rl%d: failed to enable memory mapping!\n", unit);
839 error = ENXIO;
840 goto fail;
841 }
842#endif
843
844 rid = RL_RID;
845 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid,
846 0, ~0, 1, RF_ACTIVE);
847
848 if (sc->rl_res == NULL) {
849 printf ("rl%d: couldn't map ports/memory\n", unit);
850 error = ENXIO;
851 goto fail;
852 }
853
854 sc->rl_btag = rman_get_bustag(sc->rl_res);
855 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
856
857 rid = 0;
858 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
859 RF_SHAREABLE | RF_ACTIVE);
860
861 if (sc->rl_irq == NULL) {
862 printf("rl%d: couldn't map interrupt\n", unit);
863 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
864 error = ENXIO;
865 goto fail;
866 }
867
868 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
869 rl_intr, sc, &sc->rl_intrhand);
870
871 if (error) {
872 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res);
873 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
874 printf("rl%d: couldn't set up irq\n", unit);
875 goto fail;
876 }
877
878 callout_handle_init(&sc->rl_stat_ch);
879
880 /* Reset the adapter. */
881 rl_reset(sc);
882
883 /*
884 * Get station address from the EEPROM.
885 */
886 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
887
888 /*
889 * A RealTek chip was detected. Inform the world.
890 */
891 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
892
893 sc->rl_unit = unit;
894 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
895
896 /*
897 * Now read the exact device type from the EEPROM to find
898 * out if it's an 8129 or 8139.
899 */
900 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
901
902 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
903 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139)
904 sc->rl_type = RL_8139;
905 else if (rl_did == RT_DEVICEID_8129)
906 sc->rl_type = RL_8129;
907 else {
908 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
909 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
910 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res);
911 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
912 error = ENXIO;
913 goto fail;
914 }
915
916 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 1518, M_DEVBUF,
917 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
918
919 if (sc->rl_cdata.rl_rx_buf == NULL) {
920 printf("rl%d: no memory for list buffers!\n", unit);
921 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
922 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res);
923 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
924 error = ENXIO;
925 goto fail;
926 }
927
928 /* Leave a few bytes before the start of the RX ring buffer. */
929 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
930 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
931
932 /* Do MII setup */
933 if (mii_phy_probe(dev, &sc->rl_miibus,
934 rl_ifmedia_upd, rl_ifmedia_sts)) {
935 printf("rl%d: MII without any phy!\n", sc->rl_unit);
936 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
937 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res);
938 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
939 free(sc->rl_cdata.rl_rx_buf, M_DEVBUF);
940 error = ENXIO;
941 goto fail;
942 }
943
944 ifp = &sc->arpcom.ac_if;
945 ifp->if_softc = sc;
946 ifp->if_unit = unit;
947 ifp->if_name = "rl";
948 ifp->if_mtu = ETHERMTU;
949 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
950 ifp->if_ioctl = rl_ioctl;
951 ifp->if_output = ether_output;
952 ifp->if_start = rl_start;
953 ifp->if_watchdog = rl_watchdog;
954 ifp->if_init = rl_init;
955 ifp->if_baudrate = 10000000;
956 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
957
958 /*
959 * Call MI attach routines.
959 * Call MI attach routine.
960 */
960 */
961 if_attach(ifp);
962 ether_ifattach(ifp);
961 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
963
962
964 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
965
966fail:
967 splx(s);
968 return(error);
969}
970
971static int rl_detach(dev)
972 device_t dev;
973{
974 struct rl_softc *sc;
975 struct ifnet *ifp;
976 int s;
977
978 s = splimp();
979
980 sc = device_get_softc(dev);
981 ifp = &sc->arpcom.ac_if;
982
963fail:
964 splx(s);
965 return(error);
966}
967
968static int rl_detach(dev)
969 device_t dev;
970{
971 struct rl_softc *sc;
972 struct ifnet *ifp;
973 int s;
974
975 s = splimp();
976
977 sc = device_get_softc(dev);
978 ifp = &sc->arpcom.ac_if;
979
983 if_detach(ifp);
980 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
984 rl_stop(sc);
985
986 bus_generic_detach(dev);
987 device_delete_child(dev, sc->rl_miibus);
988
989 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
990 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res);
991 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
992
993 contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 32, M_DEVBUF);
994
995 splx(s);
996
997 return(0);
998}
999
1000/*
1001 * Initialize the transmit descriptors.
1002 */
1003static int rl_list_tx_init(sc)
1004 struct rl_softc *sc;
1005{
1006 struct rl_chain_data *cd;
1007 int i;
1008
1009 cd = &sc->rl_cdata;
1010 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1011 cd->rl_tx_chain[i] = NULL;
1012 CSR_WRITE_4(sc,
1013 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000);
1014 }
1015
1016 sc->rl_cdata.cur_tx = 0;
1017 sc->rl_cdata.last_tx = 0;
1018
1019 return(0);
1020}
1021
1022/*
1023 * A frame has been uploaded: pass the resulting mbuf chain up to
1024 * the higher level protocols.
1025 *
1026 * You know there's something wrong with a PCI bus-master chip design
1027 * when you have to use m_devget().
1028 *
1029 * The receive operation is badly documented in the datasheet, so I'll
1030 * attempt to document it here. The driver provides a buffer area and
1031 * places its base address in the RX buffer start address register.
1032 * The chip then begins copying frames into the RX buffer. Each frame
1033 * is preceeded by a 32-bit RX status word which specifies the length
1034 * of the frame and certain other status bits. Each frame (starting with
1035 * the status word) is also 32-bit aligned. The frame length is in the
1036 * first 16 bits of the status word; the lower 15 bits correspond with
1037 * the 'rx status register' mentioned in the datasheet.
1038 *
1039 * Note: to make the Alpha happy, the frame payload needs to be aligned
1040 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
1041 * the ring buffer starting at an address two bytes before the actual
1042 * data location. We can then shave off the first two bytes using m_adj().
1043 * The reason we do this is because m_devget() doesn't let us specify an
1044 * offset into the mbuf storage space, so we have to artificially create
1045 * one. The ring is allocated in such a way that there are a few unused
1046 * bytes of space preceecing it so that it will be safe for us to do the
1047 * 2-byte backstep even if reading from the ring at offset 0.
1048 */
1049static void rl_rxeof(sc)
1050 struct rl_softc *sc;
1051{
1052 struct ether_header *eh;
1053 struct mbuf *m;
1054 struct ifnet *ifp;
1055 int total_len = 0;
1056 u_int32_t rxstat;
1057 caddr_t rxbufpos;
1058 int wrap = 0;
1059 u_int16_t cur_rx;
1060 u_int16_t limit;
1061 u_int16_t rx_bytes = 0, max_bytes;
1062
1063 ifp = &sc->arpcom.ac_if;
1064
1065 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1066
1067 /* Do not try to read past this point. */
1068 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1069
1070 if (limit < cur_rx)
1071 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1072 else
1073 max_bytes = limit - cur_rx;
1074
1075 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1076 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1077 rxstat = *(u_int32_t *)rxbufpos;
1078
1079 /*
1080 * Here's a totally undocumented fact for you. When the
1081 * RealTek chip is in the process of copying a packet into
1082 * RAM for you, the length will be 0xfff0. If you spot a
1083 * packet header with this value, you need to stop. The
1084 * datasheet makes absolutely no mention of this and
1085 * RealTek should be shot for this.
1086 */
1087 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1088 break;
1089
1090 if (!(rxstat & RL_RXSTAT_RXOK)) {
1091 ifp->if_ierrors++;
1092 rl_init(sc);
1093 return;
1094 }
1095
1096 /* No errors; receive the packet. */
1097 total_len = rxstat >> 16;
1098 rx_bytes += total_len + 4;
1099
1100 /*
1101 * XXX The RealTek chip includes the CRC with every
1102 * received frame, and there's no way to turn this
1103 * behavior off (at least, I can't find anything in
1104 * the manual that explains how to do it) so we have
1105 * to trim off the CRC manually.
1106 */
1107 total_len -= ETHER_CRC_LEN;
1108
1109 /*
1110 * Avoid trying to read more bytes than we know
1111 * the chip has prepared for us.
1112 */
1113 if (rx_bytes > max_bytes)
1114 break;
1115
1116 rxbufpos = sc->rl_cdata.rl_rx_buf +
1117 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1118
1119 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1120 rxbufpos = sc->rl_cdata.rl_rx_buf;
1121
1122 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1123
1124 if (total_len > wrap) {
1125 /*
1126 * Fool m_devget() into thinking we want to copy
1127 * the whole buffer so we don't end up fragmenting
1128 * the data.
1129 */
1130 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1131 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1132 if (m == NULL) {
1133 ifp->if_ierrors++;
1134 printf("rl%d: out of mbufs, tried to "
1135 "copy %d bytes\n", sc->rl_unit, wrap);
1136 } else {
1137 m_adj(m, RL_ETHER_ALIGN);
1138 m_copyback(m, wrap, total_len - wrap,
1139 sc->rl_cdata.rl_rx_buf);
1140 }
1141 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1142 } else {
1143 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1144 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1145 if (m == NULL) {
1146 ifp->if_ierrors++;
1147 printf("rl%d: out of mbufs, tried to "
1148 "copy %d bytes\n", sc->rl_unit, total_len);
1149 } else
1150 m_adj(m, RL_ETHER_ALIGN);
1151 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1152 }
1153
1154 /*
1155 * Round up to 32-bit boundary.
1156 */
1157 cur_rx = (cur_rx + 3) & ~3;
1158 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1159
1160 if (m == NULL)
1161 continue;
1162
1163 eh = mtod(m, struct ether_header *);
1164 ifp->if_ipackets++;
1165
1166 /* Remove header from mbuf and pass it on. */
1167 m_adj(m, sizeof(struct ether_header));
1168 ether_input(ifp, eh, m);
1169 }
1170
1171 return;
1172}
1173
1174/*
1175 * A frame was downloaded to the chip. It's safe for us to clean up
1176 * the list buffers.
1177 */
1178static void rl_txeof(sc)
1179 struct rl_softc *sc;
1180{
1181 struct ifnet *ifp;
1182 u_int32_t txstat;
1183
1184 ifp = &sc->arpcom.ac_if;
1185
1186 /* Clear the timeout timer. */
1187 ifp->if_timer = 0;
1188
1189 /*
1190 * Go through our tx list and free mbufs for those
1191 * frames that have been uploaded.
1192 */
1193 do {
1194 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1195 if (!(txstat & (RL_TXSTAT_TX_OK|
1196 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1197 break;
1198
1199 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1200
1201 if (RL_LAST_TXMBUF(sc) != NULL) {
1202 m_freem(RL_LAST_TXMBUF(sc));
1203 RL_LAST_TXMBUF(sc) = NULL;
1204 }
1205 if (txstat & RL_TXSTAT_TX_OK)
1206 ifp->if_opackets++;
1207 else {
1208 int oldthresh;
1209 ifp->if_oerrors++;
1210 if ((txstat & RL_TXSTAT_TXABRT) ||
1211 (txstat & RL_TXSTAT_OUTOFWIN))
1212 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1213 oldthresh = sc->rl_txthresh;
1214 /* error recovery */
1215 rl_reset(sc);
1216 rl_init(sc);
1217 /*
1218 * If there was a transmit underrun,
1219 * bump the TX threshold.
1220 */
1221 if (txstat & RL_TXSTAT_TX_UNDERRUN)
1222 sc->rl_txthresh = oldthresh + 32;
1223 return;
1224 }
1225 RL_INC(sc->rl_cdata.last_tx);
1226 ifp->if_flags &= ~IFF_OACTIVE;
1227 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1228
1229 return;
1230}
1231
1232static void rl_tick(xsc)
1233 void *xsc;
1234{
1235 struct rl_softc *sc;
1236 struct mii_data *mii;
1237 int s;
1238
1239 s = splimp();
1240
1241 sc = xsc;
1242 mii = device_get_softc(sc->rl_miibus);
1243
1244 mii_tick(mii);
1245
1246 splx(s);
1247
1248 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1249
1250 return;
1251}
1252
1253static void rl_intr(arg)
1254 void *arg;
1255{
1256 struct rl_softc *sc;
1257 struct ifnet *ifp;
1258 u_int16_t status;
1259
1260 sc = arg;
1261 ifp = &sc->arpcom.ac_if;
1262
1263 /* Disable interrupts. */
1264 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1265
1266 for (;;) {
1267
1268 status = CSR_READ_2(sc, RL_ISR);
1269 if (status)
1270 CSR_WRITE_2(sc, RL_ISR, status);
1271
1272 if ((status & RL_INTRS) == 0)
1273 break;
1274
1275 if (status & RL_ISR_RX_OK)
1276 rl_rxeof(sc);
1277
1278 if (status & RL_ISR_RX_ERR)
1279 rl_rxeof(sc);
1280
1281 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1282 rl_txeof(sc);
1283
1284 if (status & RL_ISR_SYSTEM_ERR) {
1285 rl_reset(sc);
1286 rl_init(sc);
1287 }
1288
1289 }
1290
1291 /* Re-enable interrupts. */
1292 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1293
1294 if (ifp->if_snd.ifq_head != NULL)
1295 rl_start(ifp);
1296
1297 return;
1298}
1299
1300/*
1301 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1302 * pointers to the fragment pointers.
1303 */
1304static int rl_encap(sc, m_head)
1305 struct rl_softc *sc;
1306 struct mbuf *m_head;
1307{
1308 struct mbuf *m_new = NULL;
1309
1310 /*
1311 * The RealTek is brain damaged and wants longword-aligned
1312 * TX buffers, plus we can only have one fragment buffer
1313 * per packet. We have to copy pretty much all the time.
1314 */
1315
1316 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1317 if (m_new == NULL) {
1318 printf("rl%d: no memory for tx list", sc->rl_unit);
1319 return(1);
1320 }
1321 if (m_head->m_pkthdr.len > MHLEN) {
1322 MCLGET(m_new, M_DONTWAIT);
1323 if (!(m_new->m_flags & M_EXT)) {
1324 m_freem(m_new);
1325 printf("rl%d: no memory for tx list",
1326 sc->rl_unit);
1327 return(1);
1328 }
1329 }
1330 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1331 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1332 m_freem(m_head);
1333 m_head = m_new;
1334
1335 /* Pad frames to at least 60 bytes. */
1336 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1337 /*
1338 * Make security concious people happy: zero out the
1339 * bytes in the pad area, since we don't know what
1340 * this mbuf cluster buffer's previous user might
1341 * have left in it.
1342 */
1343 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1344 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1345 m_head->m_pkthdr.len +=
1346 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1347 m_head->m_len = m_head->m_pkthdr.len;
1348 }
1349
1350 RL_CUR_TXMBUF(sc) = m_head;
1351
1352 return(0);
1353}
1354
1355/*
1356 * Main transmit routine.
1357 */
1358
1359static void rl_start(ifp)
1360 struct ifnet *ifp;
1361{
1362 struct rl_softc *sc;
1363 struct mbuf *m_head = NULL;
1364
1365 sc = ifp->if_softc;
1366
1367 while(RL_CUR_TXMBUF(sc) == NULL) {
1368 IF_DEQUEUE(&ifp->if_snd, m_head);
1369 if (m_head == NULL)
1370 break;
1371
1372 if (rl_encap(sc, m_head)) {
1373 IF_PREPEND(&ifp->if_snd, m_head);
1374 ifp->if_flags |= IFF_OACTIVE;
1375 break;
1376 }
1377
1378 /*
1379 * If there's a BPF listener, bounce a copy of this frame
1380 * to him.
1381 */
1382 if (ifp->if_bpf)
1383 bpf_mtap(ifp, RL_CUR_TXMBUF(sc));
1384
1385 /*
1386 * Transmit the frame.
1387 */
1388 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc),
1389 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t)));
1390 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1391 RL_TXTHRESH(sc->rl_txthresh) |
1392 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1393
1394 RL_INC(sc->rl_cdata.cur_tx);
1395 }
1396
1397 /*
1398 * We broke out of the loop because all our TX slots are
1399 * full. Mark the NIC as busy until it drains some of the
1400 * packets from the queue.
1401 */
1402 if (RL_CUR_TXMBUF(sc) != NULL)
1403 ifp->if_flags |= IFF_OACTIVE;
1404
1405 /*
1406 * Set a timeout in case the chip goes out to lunch.
1407 */
1408 ifp->if_timer = 5;
1409
1410 return;
1411}
1412
1413static void rl_init(xsc)
1414 void *xsc;
1415{
1416 struct rl_softc *sc = xsc;
1417 struct ifnet *ifp = &sc->arpcom.ac_if;
1418 struct mii_data *mii;
1419 int s, i;
1420 u_int32_t rxcfg = 0;
1421
1422 s = splimp();
1423
1424 mii = device_get_softc(sc->rl_miibus);
1425
1426 /*
1427 * Cancel pending I/O and free all RX/TX buffers.
1428 */
1429 rl_stop(sc);
1430
1431 /* Init our MAC address */
1432 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1433 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
1434 }
1435
1436 /* Init the RX buffer pointer register. */
1437 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf));
1438
1439 /* Init TX descriptors. */
1440 rl_list_tx_init(sc);
1441
1442 /*
1443 * Enable transmit and receive.
1444 */
1445 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1446
1447 /*
1448 * Set the initial TX and RX configuration.
1449 */
1450 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1451 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1452
1453 /* Set the individual bit to receive frames for this host only. */
1454 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1455 rxcfg |= RL_RXCFG_RX_INDIV;
1456
1457 /* If we want promiscuous mode, set the allframes bit. */
1458 if (ifp->if_flags & IFF_PROMISC) {
1459 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1460 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1461 } else {
1462 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1463 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1464 }
1465
1466 /*
1467 * Set capture broadcast bit to capture broadcast frames.
1468 */
1469 if (ifp->if_flags & IFF_BROADCAST) {
1470 rxcfg |= RL_RXCFG_RX_BROAD;
1471 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1472 } else {
1473 rxcfg &= ~RL_RXCFG_RX_BROAD;
1474 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1475 }
1476
1477 /*
1478 * Program the multicast filter, if necessary.
1479 */
1480 rl_setmulti(sc);
1481
1482 /*
1483 * Enable interrupts.
1484 */
1485 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1486
1487 /* Set initial TX threshold */
1488 sc->rl_txthresh = RL_TX_THRESH_INIT;
1489
1490 /* Start RX/TX process. */
1491 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1492
1493 /* Enable receiver and transmitter. */
1494 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1495
1496 mii_mediachg(mii);
1497
1498 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1499
1500 ifp->if_flags |= IFF_RUNNING;
1501 ifp->if_flags &= ~IFF_OACTIVE;
1502
1503 (void)splx(s);
1504
1505 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1506
1507 return;
1508}
1509
1510/*
1511 * Set media options.
1512 */
1513static int rl_ifmedia_upd(ifp)
1514 struct ifnet *ifp;
1515{
1516 struct rl_softc *sc;
1517 struct mii_data *mii;
1518
1519 sc = ifp->if_softc;
1520 mii = device_get_softc(sc->rl_miibus);
1521 mii_mediachg(mii);
1522
1523 return(0);
1524}
1525
1526/*
1527 * Report current media status.
1528 */
1529static void rl_ifmedia_sts(ifp, ifmr)
1530 struct ifnet *ifp;
1531 struct ifmediareq *ifmr;
1532{
1533 struct rl_softc *sc;
1534 struct mii_data *mii;
1535
1536 sc = ifp->if_softc;
1537 mii = device_get_softc(sc->rl_miibus);
1538
1539 mii_pollstat(mii);
1540 ifmr->ifm_active = mii->mii_media_active;
1541 ifmr->ifm_status = mii->mii_media_status;
1542
1543 return;
1544}
1545
1546static int rl_ioctl(ifp, command, data)
1547 struct ifnet *ifp;
1548 u_long command;
1549 caddr_t data;
1550{
1551 struct rl_softc *sc = ifp->if_softc;
1552 struct ifreq *ifr = (struct ifreq *) data;
1553 struct mii_data *mii;
1554 int s, error = 0;
1555
1556 s = splimp();
1557
1558 switch(command) {
1559 case SIOCSIFADDR:
1560 case SIOCGIFADDR:
1561 case SIOCSIFMTU:
1562 error = ether_ioctl(ifp, command, data);
1563 break;
1564 case SIOCSIFFLAGS:
1565 if (ifp->if_flags & IFF_UP) {
1566 rl_init(sc);
1567 } else {
1568 if (ifp->if_flags & IFF_RUNNING)
1569 rl_stop(sc);
1570 }
1571 error = 0;
1572 break;
1573 case SIOCADDMULTI:
1574 case SIOCDELMULTI:
1575 rl_setmulti(sc);
1576 error = 0;
1577 break;
1578 case SIOCGIFMEDIA:
1579 case SIOCSIFMEDIA:
1580 mii = device_get_softc(sc->rl_miibus);
1581 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1582 break;
1583 default:
1584 error = EINVAL;
1585 break;
1586 }
1587
1588 (void)splx(s);
1589
1590 return(error);
1591}
1592
1593static void rl_watchdog(ifp)
1594 struct ifnet *ifp;
1595{
1596 struct rl_softc *sc;
1597
1598 sc = ifp->if_softc;
1599
1600 printf("rl%d: watchdog timeout\n", sc->rl_unit);
1601 ifp->if_oerrors++;
1602
1603 rl_txeof(sc);
1604 rl_rxeof(sc);
1605 rl_init(sc);
1606
1607 return;
1608}
1609
1610/*
1611 * Stop the adapter and free any mbufs allocated to the
1612 * RX and TX lists.
1613 */
1614static void rl_stop(sc)
1615 struct rl_softc *sc;
1616{
1617 register int i;
1618 struct ifnet *ifp;
1619
1620 ifp = &sc->arpcom.ac_if;
1621 ifp->if_timer = 0;
1622
1623 untimeout(rl_tick, sc, sc->rl_stat_ch);
1624
1625 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1626 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1627
1628 /*
1629 * Free the TX list buffers.
1630 */
1631 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1632 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1633 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1634 sc->rl_cdata.rl_tx_chain[i] = NULL;
1635 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
1636 }
1637 }
1638
1639 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1640
1641 return;
1642}
1643
1644/*
1645 * Stop all chip I/O so that the kernel's probe routines don't
1646 * get confused by errant DMAs when rebooting.
1647 */
1648static void rl_shutdown(dev)
1649 device_t dev;
1650{
1651 struct rl_softc *sc;
1652
1653 sc = device_get_softc(dev);
1654
1655 rl_stop(sc);
1656
1657 return;
1658}
981 rl_stop(sc);
982
983 bus_generic_detach(dev);
984 device_delete_child(dev, sc->rl_miibus);
985
986 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
987 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res);
988 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
989
990 contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 32, M_DEVBUF);
991
992 splx(s);
993
994 return(0);
995}
996
997/*
998 * Initialize the transmit descriptors.
999 */
1000static int rl_list_tx_init(sc)
1001 struct rl_softc *sc;
1002{
1003 struct rl_chain_data *cd;
1004 int i;
1005
1006 cd = &sc->rl_cdata;
1007 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1008 cd->rl_tx_chain[i] = NULL;
1009 CSR_WRITE_4(sc,
1010 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000);
1011 }
1012
1013 sc->rl_cdata.cur_tx = 0;
1014 sc->rl_cdata.last_tx = 0;
1015
1016 return(0);
1017}
1018
1019/*
1020 * A frame has been uploaded: pass the resulting mbuf chain up to
1021 * the higher level protocols.
1022 *
1023 * You know there's something wrong with a PCI bus-master chip design
1024 * when you have to use m_devget().
1025 *
1026 * The receive operation is badly documented in the datasheet, so I'll
1027 * attempt to document it here. The driver provides a buffer area and
1028 * places its base address in the RX buffer start address register.
1029 * The chip then begins copying frames into the RX buffer. Each frame
1030 * is preceeded by a 32-bit RX status word which specifies the length
1031 * of the frame and certain other status bits. Each frame (starting with
1032 * the status word) is also 32-bit aligned. The frame length is in the
1033 * first 16 bits of the status word; the lower 15 bits correspond with
1034 * the 'rx status register' mentioned in the datasheet.
1035 *
1036 * Note: to make the Alpha happy, the frame payload needs to be aligned
1037 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
1038 * the ring buffer starting at an address two bytes before the actual
1039 * data location. We can then shave off the first two bytes using m_adj().
1040 * The reason we do this is because m_devget() doesn't let us specify an
1041 * offset into the mbuf storage space, so we have to artificially create
1042 * one. The ring is allocated in such a way that there are a few unused
1043 * bytes of space preceecing it so that it will be safe for us to do the
1044 * 2-byte backstep even if reading from the ring at offset 0.
1045 */
1046static void rl_rxeof(sc)
1047 struct rl_softc *sc;
1048{
1049 struct ether_header *eh;
1050 struct mbuf *m;
1051 struct ifnet *ifp;
1052 int total_len = 0;
1053 u_int32_t rxstat;
1054 caddr_t rxbufpos;
1055 int wrap = 0;
1056 u_int16_t cur_rx;
1057 u_int16_t limit;
1058 u_int16_t rx_bytes = 0, max_bytes;
1059
1060 ifp = &sc->arpcom.ac_if;
1061
1062 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1063
1064 /* Do not try to read past this point. */
1065 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1066
1067 if (limit < cur_rx)
1068 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1069 else
1070 max_bytes = limit - cur_rx;
1071
1072 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1073 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1074 rxstat = *(u_int32_t *)rxbufpos;
1075
1076 /*
1077 * Here's a totally undocumented fact for you. When the
1078 * RealTek chip is in the process of copying a packet into
1079 * RAM for you, the length will be 0xfff0. If you spot a
1080 * packet header with this value, you need to stop. The
1081 * datasheet makes absolutely no mention of this and
1082 * RealTek should be shot for this.
1083 */
1084 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1085 break;
1086
1087 if (!(rxstat & RL_RXSTAT_RXOK)) {
1088 ifp->if_ierrors++;
1089 rl_init(sc);
1090 return;
1091 }
1092
1093 /* No errors; receive the packet. */
1094 total_len = rxstat >> 16;
1095 rx_bytes += total_len + 4;
1096
1097 /*
1098 * XXX The RealTek chip includes the CRC with every
1099 * received frame, and there's no way to turn this
1100 * behavior off (at least, I can't find anything in
1101 * the manual that explains how to do it) so we have
1102 * to trim off the CRC manually.
1103 */
1104 total_len -= ETHER_CRC_LEN;
1105
1106 /*
1107 * Avoid trying to read more bytes than we know
1108 * the chip has prepared for us.
1109 */
1110 if (rx_bytes > max_bytes)
1111 break;
1112
1113 rxbufpos = sc->rl_cdata.rl_rx_buf +
1114 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1115
1116 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1117 rxbufpos = sc->rl_cdata.rl_rx_buf;
1118
1119 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1120
1121 if (total_len > wrap) {
1122 /*
1123 * Fool m_devget() into thinking we want to copy
1124 * the whole buffer so we don't end up fragmenting
1125 * the data.
1126 */
1127 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1128 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1129 if (m == NULL) {
1130 ifp->if_ierrors++;
1131 printf("rl%d: out of mbufs, tried to "
1132 "copy %d bytes\n", sc->rl_unit, wrap);
1133 } else {
1134 m_adj(m, RL_ETHER_ALIGN);
1135 m_copyback(m, wrap, total_len - wrap,
1136 sc->rl_cdata.rl_rx_buf);
1137 }
1138 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1139 } else {
1140 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1141 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1142 if (m == NULL) {
1143 ifp->if_ierrors++;
1144 printf("rl%d: out of mbufs, tried to "
1145 "copy %d bytes\n", sc->rl_unit, total_len);
1146 } else
1147 m_adj(m, RL_ETHER_ALIGN);
1148 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1149 }
1150
1151 /*
1152 * Round up to 32-bit boundary.
1153 */
1154 cur_rx = (cur_rx + 3) & ~3;
1155 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1156
1157 if (m == NULL)
1158 continue;
1159
1160 eh = mtod(m, struct ether_header *);
1161 ifp->if_ipackets++;
1162
1163 /* Remove header from mbuf and pass it on. */
1164 m_adj(m, sizeof(struct ether_header));
1165 ether_input(ifp, eh, m);
1166 }
1167
1168 return;
1169}
1170
1171/*
1172 * A frame was downloaded to the chip. It's safe for us to clean up
1173 * the list buffers.
1174 */
1175static void rl_txeof(sc)
1176 struct rl_softc *sc;
1177{
1178 struct ifnet *ifp;
1179 u_int32_t txstat;
1180
1181 ifp = &sc->arpcom.ac_if;
1182
1183 /* Clear the timeout timer. */
1184 ifp->if_timer = 0;
1185
1186 /*
1187 * Go through our tx list and free mbufs for those
1188 * frames that have been uploaded.
1189 */
1190 do {
1191 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1192 if (!(txstat & (RL_TXSTAT_TX_OK|
1193 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1194 break;
1195
1196 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1197
1198 if (RL_LAST_TXMBUF(sc) != NULL) {
1199 m_freem(RL_LAST_TXMBUF(sc));
1200 RL_LAST_TXMBUF(sc) = NULL;
1201 }
1202 if (txstat & RL_TXSTAT_TX_OK)
1203 ifp->if_opackets++;
1204 else {
1205 int oldthresh;
1206 ifp->if_oerrors++;
1207 if ((txstat & RL_TXSTAT_TXABRT) ||
1208 (txstat & RL_TXSTAT_OUTOFWIN))
1209 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1210 oldthresh = sc->rl_txthresh;
1211 /* error recovery */
1212 rl_reset(sc);
1213 rl_init(sc);
1214 /*
1215 * If there was a transmit underrun,
1216 * bump the TX threshold.
1217 */
1218 if (txstat & RL_TXSTAT_TX_UNDERRUN)
1219 sc->rl_txthresh = oldthresh + 32;
1220 return;
1221 }
1222 RL_INC(sc->rl_cdata.last_tx);
1223 ifp->if_flags &= ~IFF_OACTIVE;
1224 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1225
1226 return;
1227}
1228
1229static void rl_tick(xsc)
1230 void *xsc;
1231{
1232 struct rl_softc *sc;
1233 struct mii_data *mii;
1234 int s;
1235
1236 s = splimp();
1237
1238 sc = xsc;
1239 mii = device_get_softc(sc->rl_miibus);
1240
1241 mii_tick(mii);
1242
1243 splx(s);
1244
1245 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1246
1247 return;
1248}
1249
1250static void rl_intr(arg)
1251 void *arg;
1252{
1253 struct rl_softc *sc;
1254 struct ifnet *ifp;
1255 u_int16_t status;
1256
1257 sc = arg;
1258 ifp = &sc->arpcom.ac_if;
1259
1260 /* Disable interrupts. */
1261 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1262
1263 for (;;) {
1264
1265 status = CSR_READ_2(sc, RL_ISR);
1266 if (status)
1267 CSR_WRITE_2(sc, RL_ISR, status);
1268
1269 if ((status & RL_INTRS) == 0)
1270 break;
1271
1272 if (status & RL_ISR_RX_OK)
1273 rl_rxeof(sc);
1274
1275 if (status & RL_ISR_RX_ERR)
1276 rl_rxeof(sc);
1277
1278 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1279 rl_txeof(sc);
1280
1281 if (status & RL_ISR_SYSTEM_ERR) {
1282 rl_reset(sc);
1283 rl_init(sc);
1284 }
1285
1286 }
1287
1288 /* Re-enable interrupts. */
1289 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1290
1291 if (ifp->if_snd.ifq_head != NULL)
1292 rl_start(ifp);
1293
1294 return;
1295}
1296
1297/*
1298 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1299 * pointers to the fragment pointers.
1300 */
1301static int rl_encap(sc, m_head)
1302 struct rl_softc *sc;
1303 struct mbuf *m_head;
1304{
1305 struct mbuf *m_new = NULL;
1306
1307 /*
1308 * The RealTek is brain damaged and wants longword-aligned
1309 * TX buffers, plus we can only have one fragment buffer
1310 * per packet. We have to copy pretty much all the time.
1311 */
1312
1313 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1314 if (m_new == NULL) {
1315 printf("rl%d: no memory for tx list", sc->rl_unit);
1316 return(1);
1317 }
1318 if (m_head->m_pkthdr.len > MHLEN) {
1319 MCLGET(m_new, M_DONTWAIT);
1320 if (!(m_new->m_flags & M_EXT)) {
1321 m_freem(m_new);
1322 printf("rl%d: no memory for tx list",
1323 sc->rl_unit);
1324 return(1);
1325 }
1326 }
1327 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1328 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1329 m_freem(m_head);
1330 m_head = m_new;
1331
1332 /* Pad frames to at least 60 bytes. */
1333 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1334 /*
1335 * Make security concious people happy: zero out the
1336 * bytes in the pad area, since we don't know what
1337 * this mbuf cluster buffer's previous user might
1338 * have left in it.
1339 */
1340 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1341 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1342 m_head->m_pkthdr.len +=
1343 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1344 m_head->m_len = m_head->m_pkthdr.len;
1345 }
1346
1347 RL_CUR_TXMBUF(sc) = m_head;
1348
1349 return(0);
1350}
1351
1352/*
1353 * Main transmit routine.
1354 */
1355
1356static void rl_start(ifp)
1357 struct ifnet *ifp;
1358{
1359 struct rl_softc *sc;
1360 struct mbuf *m_head = NULL;
1361
1362 sc = ifp->if_softc;
1363
1364 while(RL_CUR_TXMBUF(sc) == NULL) {
1365 IF_DEQUEUE(&ifp->if_snd, m_head);
1366 if (m_head == NULL)
1367 break;
1368
1369 if (rl_encap(sc, m_head)) {
1370 IF_PREPEND(&ifp->if_snd, m_head);
1371 ifp->if_flags |= IFF_OACTIVE;
1372 break;
1373 }
1374
1375 /*
1376 * If there's a BPF listener, bounce a copy of this frame
1377 * to him.
1378 */
1379 if (ifp->if_bpf)
1380 bpf_mtap(ifp, RL_CUR_TXMBUF(sc));
1381
1382 /*
1383 * Transmit the frame.
1384 */
1385 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc),
1386 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t)));
1387 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1388 RL_TXTHRESH(sc->rl_txthresh) |
1389 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1390
1391 RL_INC(sc->rl_cdata.cur_tx);
1392 }
1393
1394 /*
1395 * We broke out of the loop because all our TX slots are
1396 * full. Mark the NIC as busy until it drains some of the
1397 * packets from the queue.
1398 */
1399 if (RL_CUR_TXMBUF(sc) != NULL)
1400 ifp->if_flags |= IFF_OACTIVE;
1401
1402 /*
1403 * Set a timeout in case the chip goes out to lunch.
1404 */
1405 ifp->if_timer = 5;
1406
1407 return;
1408}
1409
1410static void rl_init(xsc)
1411 void *xsc;
1412{
1413 struct rl_softc *sc = xsc;
1414 struct ifnet *ifp = &sc->arpcom.ac_if;
1415 struct mii_data *mii;
1416 int s, i;
1417 u_int32_t rxcfg = 0;
1418
1419 s = splimp();
1420
1421 mii = device_get_softc(sc->rl_miibus);
1422
1423 /*
1424 * Cancel pending I/O and free all RX/TX buffers.
1425 */
1426 rl_stop(sc);
1427
1428 /* Init our MAC address */
1429 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1430 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
1431 }
1432
1433 /* Init the RX buffer pointer register. */
1434 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf));
1435
1436 /* Init TX descriptors. */
1437 rl_list_tx_init(sc);
1438
1439 /*
1440 * Enable transmit and receive.
1441 */
1442 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1443
1444 /*
1445 * Set the initial TX and RX configuration.
1446 */
1447 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1448 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1449
1450 /* Set the individual bit to receive frames for this host only. */
1451 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1452 rxcfg |= RL_RXCFG_RX_INDIV;
1453
1454 /* If we want promiscuous mode, set the allframes bit. */
1455 if (ifp->if_flags & IFF_PROMISC) {
1456 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1457 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1458 } else {
1459 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1460 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1461 }
1462
1463 /*
1464 * Set capture broadcast bit to capture broadcast frames.
1465 */
1466 if (ifp->if_flags & IFF_BROADCAST) {
1467 rxcfg |= RL_RXCFG_RX_BROAD;
1468 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1469 } else {
1470 rxcfg &= ~RL_RXCFG_RX_BROAD;
1471 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1472 }
1473
1474 /*
1475 * Program the multicast filter, if necessary.
1476 */
1477 rl_setmulti(sc);
1478
1479 /*
1480 * Enable interrupts.
1481 */
1482 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1483
1484 /* Set initial TX threshold */
1485 sc->rl_txthresh = RL_TX_THRESH_INIT;
1486
1487 /* Start RX/TX process. */
1488 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1489
1490 /* Enable receiver and transmitter. */
1491 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1492
1493 mii_mediachg(mii);
1494
1495 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1496
1497 ifp->if_flags |= IFF_RUNNING;
1498 ifp->if_flags &= ~IFF_OACTIVE;
1499
1500 (void)splx(s);
1501
1502 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1503
1504 return;
1505}
1506
1507/*
1508 * Set media options.
1509 */
1510static int rl_ifmedia_upd(ifp)
1511 struct ifnet *ifp;
1512{
1513 struct rl_softc *sc;
1514 struct mii_data *mii;
1515
1516 sc = ifp->if_softc;
1517 mii = device_get_softc(sc->rl_miibus);
1518 mii_mediachg(mii);
1519
1520 return(0);
1521}
1522
1523/*
1524 * Report current media status.
1525 */
1526static void rl_ifmedia_sts(ifp, ifmr)
1527 struct ifnet *ifp;
1528 struct ifmediareq *ifmr;
1529{
1530 struct rl_softc *sc;
1531 struct mii_data *mii;
1532
1533 sc = ifp->if_softc;
1534 mii = device_get_softc(sc->rl_miibus);
1535
1536 mii_pollstat(mii);
1537 ifmr->ifm_active = mii->mii_media_active;
1538 ifmr->ifm_status = mii->mii_media_status;
1539
1540 return;
1541}
1542
1543static int rl_ioctl(ifp, command, data)
1544 struct ifnet *ifp;
1545 u_long command;
1546 caddr_t data;
1547{
1548 struct rl_softc *sc = ifp->if_softc;
1549 struct ifreq *ifr = (struct ifreq *) data;
1550 struct mii_data *mii;
1551 int s, error = 0;
1552
1553 s = splimp();
1554
1555 switch(command) {
1556 case SIOCSIFADDR:
1557 case SIOCGIFADDR:
1558 case SIOCSIFMTU:
1559 error = ether_ioctl(ifp, command, data);
1560 break;
1561 case SIOCSIFFLAGS:
1562 if (ifp->if_flags & IFF_UP) {
1563 rl_init(sc);
1564 } else {
1565 if (ifp->if_flags & IFF_RUNNING)
1566 rl_stop(sc);
1567 }
1568 error = 0;
1569 break;
1570 case SIOCADDMULTI:
1571 case SIOCDELMULTI:
1572 rl_setmulti(sc);
1573 error = 0;
1574 break;
1575 case SIOCGIFMEDIA:
1576 case SIOCSIFMEDIA:
1577 mii = device_get_softc(sc->rl_miibus);
1578 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1579 break;
1580 default:
1581 error = EINVAL;
1582 break;
1583 }
1584
1585 (void)splx(s);
1586
1587 return(error);
1588}
1589
1590static void rl_watchdog(ifp)
1591 struct ifnet *ifp;
1592{
1593 struct rl_softc *sc;
1594
1595 sc = ifp->if_softc;
1596
1597 printf("rl%d: watchdog timeout\n", sc->rl_unit);
1598 ifp->if_oerrors++;
1599
1600 rl_txeof(sc);
1601 rl_rxeof(sc);
1602 rl_init(sc);
1603
1604 return;
1605}
1606
1607/*
1608 * Stop the adapter and free any mbufs allocated to the
1609 * RX and TX lists.
1610 */
1611static void rl_stop(sc)
1612 struct rl_softc *sc;
1613{
1614 register int i;
1615 struct ifnet *ifp;
1616
1617 ifp = &sc->arpcom.ac_if;
1618 ifp->if_timer = 0;
1619
1620 untimeout(rl_tick, sc, sc->rl_stat_ch);
1621
1622 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1623 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1624
1625 /*
1626 * Free the TX list buffers.
1627 */
1628 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1629 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1630 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1631 sc->rl_cdata.rl_tx_chain[i] = NULL;
1632 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
1633 }
1634 }
1635
1636 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1637
1638 return;
1639}
1640
1641/*
1642 * Stop all chip I/O so that the kernel's probe routines don't
1643 * get confused by errant DMAs when rebooting.
1644 */
1645static void rl_shutdown(dev)
1646 device_t dev;
1647{
1648 struct rl_softc *sc;
1649
1650 sc = device_get_softc(dev);
1651
1652 rl_stop(sc);
1653
1654 return;
1655}