181static int rl_ifmedia_upd __P((struct ifnet *));
182static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
183
184static void rl_eeprom_putbyte __P((struct rl_softc *, int));
185static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *));
186static void rl_read_eeprom __P((struct rl_softc *, caddr_t,
187 int, int, int));
188static void rl_mii_sync __P((struct rl_softc *));
189static void rl_mii_send __P((struct rl_softc *, u_int32_t, int));
190static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *));
191static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *));
192
193static u_int16_t rl_phy_readreg __P((struct rl_softc *, int));
194static void rl_phy_writereg __P((struct rl_softc *, int, int));
195
196static void rl_autoneg_xmit __P((struct rl_softc *));
197static void rl_autoneg_mii __P((struct rl_softc *, int, int));
198static void rl_setmode_mii __P((struct rl_softc *, int));
199static void rl_getmode_mii __P((struct rl_softc *));
200static u_int8_t rl_calchash __P((caddr_t));
201static void rl_setmulti __P((struct rl_softc *));
202static void rl_reset __P((struct rl_softc *));
203static int rl_list_tx_init __P((struct rl_softc *));
204
205#define EE_SET(x) \
206 CSR_WRITE_1(sc, RL_EECMD, \
207 CSR_READ_1(sc, RL_EECMD) | x)
208
209#define EE_CLR(x) \
210 CSR_WRITE_1(sc, RL_EECMD, \
211 CSR_READ_1(sc, RL_EECMD) & ~x)
212
213/*
214 * Send a read command and address to the EEPROM, check for ACK.
215 */
216static void rl_eeprom_putbyte(sc, addr)
217 struct rl_softc *sc;
218 int addr;
219{
220 register int d, i;
221
222 d = addr | RL_EECMD_READ;
223
224 /*
225 * Feed in each bit and stobe the clock.
226 */
227 for (i = 0x400; i; i >>= 1) {
228 if (d & i) {
229 EE_SET(RL_EE_DATAIN);
230 } else {
231 EE_CLR(RL_EE_DATAIN);
232 }
233 DELAY(100);
234 EE_SET(RL_EE_CLK);
235 DELAY(150);
236 EE_CLR(RL_EE_CLK);
237 DELAY(100);
238 }
239
240 return;
241}
242
243/*
244 * Read a word of data stored in the EEPROM at address 'addr.'
245 */
246static void rl_eeprom_getword(sc, addr, dest)
247 struct rl_softc *sc;
248 int addr;
249 u_int16_t *dest;
250{
251 register int i;
252 u_int16_t word = 0;
253
254 /* Enter EEPROM access mode. */
255 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
256
257 /*
258 * Send address of word we want to read.
259 */
260 rl_eeprom_putbyte(sc, addr);
261
262 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
263
264 /*
265 * Start reading bits from EEPROM.
266 */
267 for (i = 0x8000; i; i >>= 1) {
268 EE_SET(RL_EE_CLK);
269 DELAY(100);
270 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
271 word |= i;
272 EE_CLR(RL_EE_CLK);
273 DELAY(100);
274 }
275
276 /* Turn off EEPROM access mode. */
277 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
278
279 *dest = word;
280
281 return;
282}
283
284/*
285 * Read a sequence of words from the EEPROM.
286 */
287static void rl_read_eeprom(sc, dest, off, cnt, swap)
288 struct rl_softc *sc;
289 caddr_t dest;
290 int off;
291 int cnt;
292 int swap;
293{
294 int i;
295 u_int16_t word = 0, *ptr;
296
297 for (i = 0; i < cnt; i++) {
298 rl_eeprom_getword(sc, off + i, &word);
299 ptr = (u_int16_t *)(dest + (i * 2));
300 if (swap)
301 *ptr = ntohs(word);
302 else
303 *ptr = word;
304 }
305
306 return;
307}
308
309
310/*
311 * MII access routines are provided for the 8129, which
312 * doesn't have a built-in PHY. For the 8139, we fake things
313 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
314 * direct access PHY registers.
315 */
316#define MII_SET(x) \
317 CSR_WRITE_1(sc, RL_MII, \
318 CSR_READ_1(sc, RL_MII) | x)
319
320#define MII_CLR(x) \
321 CSR_WRITE_1(sc, RL_MII, \
322 CSR_READ_1(sc, RL_MII) & ~x)
323
324/*
325 * Sync the PHYs by setting data bit and strobing the clock 32 times.
326 */
327static void rl_mii_sync(sc)
328 struct rl_softc *sc;
329{
330 register int i;
331
332 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
333
334 for (i = 0; i < 32; i++) {
335 MII_SET(RL_MII_CLK);
336 DELAY(1);
337 MII_CLR(RL_MII_CLK);
338 DELAY(1);
339 }
340
341 return;
342}
343
344/*
345 * Clock a series of bits through the MII.
346 */
347static void rl_mii_send(sc, bits, cnt)
348 struct rl_softc *sc;
349 u_int32_t bits;
350 int cnt;
351{
352 int i;
353
354 MII_CLR(RL_MII_CLK);
355
356 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
357 if (bits & i) {
358 MII_SET(RL_MII_DATAOUT);
359 } else {
360 MII_CLR(RL_MII_DATAOUT);
361 }
362 DELAY(1);
363 MII_CLR(RL_MII_CLK);
364 DELAY(1);
365 MII_SET(RL_MII_CLK);
366 }
367}
368
369/*
370 * Read an PHY register through the MII.
371 */
372static int rl_mii_readreg(sc, frame)
373 struct rl_softc *sc;
374 struct rl_mii_frame *frame;
375
376{
377 int i, ack, s;
378
379 s = splimp();
380
381 /*
382 * Set up frame for RX.
383 */
384 frame->mii_stdelim = RL_MII_STARTDELIM;
385 frame->mii_opcode = RL_MII_READOP;
386 frame->mii_turnaround = 0;
387 frame->mii_data = 0;
388
389 CSR_WRITE_2(sc, RL_MII, 0);
390
391 /*
392 * Turn on data xmit.
393 */
394 MII_SET(RL_MII_DIR);
395
396 rl_mii_sync(sc);
397
398 /*
399 * Send command/address info.
400 */
401 rl_mii_send(sc, frame->mii_stdelim, 2);
402 rl_mii_send(sc, frame->mii_opcode, 2);
403 rl_mii_send(sc, frame->mii_phyaddr, 5);
404 rl_mii_send(sc, frame->mii_regaddr, 5);
405
406 /* Idle bit */
407 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
408 DELAY(1);
409 MII_SET(RL_MII_CLK);
410 DELAY(1);
411
412 /* Turn off xmit. */
413 MII_CLR(RL_MII_DIR);
414
415 /* Check for ack */
416 MII_CLR(RL_MII_CLK);
417 DELAY(1);
418 MII_SET(RL_MII_CLK);
419 DELAY(1);
420 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
421
422 /*
423 * Now try reading data bits. If the ack failed, we still
424 * need to clock through 16 cycles to keep the PHY(s) in sync.
425 */
426 if (ack) {
427 for(i = 0; i < 16; i++) {
428 MII_CLR(RL_MII_CLK);
429 DELAY(1);
430 MII_SET(RL_MII_CLK);
431 DELAY(1);
432 }
433 goto fail;
434 }
435
436 for (i = 0x8000; i; i >>= 1) {
437 MII_CLR(RL_MII_CLK);
438 DELAY(1);
439 if (!ack) {
440 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
441 frame->mii_data |= i;
442 DELAY(1);
443 }
444 MII_SET(RL_MII_CLK);
445 DELAY(1);
446 }
447
448fail:
449
450 MII_CLR(RL_MII_CLK);
451 DELAY(1);
452 MII_SET(RL_MII_CLK);
453 DELAY(1);
454
455 splx(s);
456
457 if (ack)
458 return(1);
459 return(0);
460}
461
462/*
463 * Write to a PHY register through the MII.
464 */
465static int rl_mii_writereg(sc, frame)
466 struct rl_softc *sc;
467 struct rl_mii_frame *frame;
468
469{
470 int s;
471
472 s = splimp();
473 /*
474 * Set up frame for TX.
475 */
476
477 frame->mii_stdelim = RL_MII_STARTDELIM;
478 frame->mii_opcode = RL_MII_WRITEOP;
479 frame->mii_turnaround = RL_MII_TURNAROUND;
480
481 /*
482 * Turn on data output.
483 */
484 MII_SET(RL_MII_DIR);
485
486 rl_mii_sync(sc);
487
488 rl_mii_send(sc, frame->mii_stdelim, 2);
489 rl_mii_send(sc, frame->mii_opcode, 2);
490 rl_mii_send(sc, frame->mii_phyaddr, 5);
491 rl_mii_send(sc, frame->mii_regaddr, 5);
492 rl_mii_send(sc, frame->mii_turnaround, 2);
493 rl_mii_send(sc, frame->mii_data, 16);
494
495 /* Idle bit. */
496 MII_SET(RL_MII_CLK);
497 DELAY(1);
498 MII_CLR(RL_MII_CLK);
499 DELAY(1);
500
501 /*
502 * Turn off xmit.
503 */
504 MII_CLR(RL_MII_DIR);
505
506 splx(s);
507
508 return(0);
509}
510
511static u_int16_t rl_phy_readreg(sc, reg)
512 struct rl_softc *sc;
513 int reg;
514{
515 struct rl_mii_frame frame;
516 u_int16_t rval = 0;
517 u_int16_t rl8139_reg = 0;
518
519 if (sc->rl_type == RL_8139) {
520 switch(reg) {
521 case PHY_BMCR:
522 rl8139_reg = RL_BMCR;
523 break;
524 case PHY_BMSR:
525 rl8139_reg = RL_BMSR;
526 break;
527 case PHY_ANAR:
528 rl8139_reg = RL_ANAR;
529 break;
530 case PHY_LPAR:
531 rl8139_reg = RL_LPAR;
532 break;
533 default:
534 printf("rl%d: bad phy register\n", sc->rl_unit);
535 return(0);
536 }
537 rval = CSR_READ_2(sc, rl8139_reg);
538 return(rval);
539 }
540
541 bzero((char *)&frame, sizeof(frame));
542
543 frame.mii_phyaddr = sc->rl_phy_addr;
544 frame.mii_regaddr = reg;
545 rl_mii_readreg(sc, &frame);
546
547 return(frame.mii_data);
548}
549
550static void rl_phy_writereg(sc, reg, data)
551 struct rl_softc *sc;
552 int reg;
553 int data;
554{
555 struct rl_mii_frame frame;
556 u_int16_t rl8139_reg = 0;
557
558 if (sc->rl_type == RL_8139) {
559 switch(reg) {
560 case PHY_BMCR:
561 rl8139_reg = RL_BMCR;
562 break;
563 case PHY_BMSR:
564 rl8139_reg = RL_BMSR;
565 break;
566 case PHY_ANAR:
567 rl8139_reg = RL_ANAR;
568 break;
569 case PHY_LPAR:
570 rl8139_reg = RL_LPAR;
571 break;
572 default:
573 printf("rl%d: bad phy register\n", sc->rl_unit);
574 return;
575 }
576 CSR_WRITE_2(sc, rl8139_reg, data);
577 return;
578 }
579
580 bzero((char *)&frame, sizeof(frame));
581
582 frame.mii_phyaddr = sc->rl_phy_addr;
583 frame.mii_regaddr = reg;
584 frame.mii_data = data;
585
586 rl_mii_writereg(sc, &frame);
587
588 return;
589}
590
591/*
592 * Calculate CRC of a multicast group address, return the upper 6 bits.
593 */
594static u_int8_t rl_calchash(addr)
595 caddr_t addr;
596{
597 u_int32_t crc, carry;
598 int i, j;
599 u_int8_t c;
600
601 /* Compute CRC for the address value. */
602 crc = 0xFFFFFFFF; /* initial value */
603
604 for (i = 0; i < 6; i++) {
605 c = *(addr + i);
606 for (j = 0; j < 8; j++) {
607 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
608 crc <<= 1;
609 c >>= 1;
610 if (carry)
611 crc = (crc ^ 0x04c11db6) | carry;
612 }
613 }
614
615 /* return the filter bit position */
616 return(crc >> 26);
617}
618
619/*
620 * Program the 64-bit multicast hash filter.
621 */
622static void rl_setmulti(sc)
623 struct rl_softc *sc;
624{
625 struct ifnet *ifp;
626 int h = 0;
627 u_int32_t hashes[2] = { 0, 0 };
628 struct ifmultiaddr *ifma;
629 u_int32_t rxfilt;
630 int mcnt = 0;
631
632 ifp = &sc->arpcom.ac_if;
633
634 rxfilt = CSR_READ_4(sc, RL_RXCFG);
635
636 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
637 rxfilt |= RL_RXCFG_RX_MULTI;
638 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
639 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
640 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
641 return;
642 }
643
644 /* first, zot all the existing hash bits */
645 CSR_WRITE_4(sc, RL_MAR0, 0);
646 CSR_WRITE_4(sc, RL_MAR4, 0);
647
648 /* now program new ones */
649 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
650 ifma = ifma->ifma_link.le_next) {
651 if (ifma->ifma_addr->sa_family != AF_LINK)
652 continue;
653 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
654 if (h < 32)
655 hashes[0] |= (1 << h);
656 else
657 hashes[1] |= (1 << (h - 32));
658 mcnt++;
659 }
660
661 if (mcnt)
662 rxfilt |= RL_RXCFG_RX_MULTI;
663 else
664 rxfilt &= ~RL_RXCFG_RX_MULTI;
665
666 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
667 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
668 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
669
670 return;
671}
672
673/*
674 * Initiate an autonegotiation session.
675 */
676static void rl_autoneg_xmit(sc)
677 struct rl_softc *sc;
678{
679 u_int16_t phy_sts;
680
681 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
682 DELAY(500);
683 while(rl_phy_readreg(sc, PHY_BMCR)
684 & PHY_BMCR_RESET);
685
686 phy_sts = rl_phy_readreg(sc, PHY_BMCR);
687 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
688 rl_phy_writereg(sc, PHY_BMCR, phy_sts);
689
690 return;
691}
692
693/*
694 * Invoke autonegotiation on a PHY. Also used with the 8139 internal
695 * transceiver.
696 */
697static void rl_autoneg_mii(sc, flag, verbose)
698 struct rl_softc *sc;
699 int flag;
700 int verbose;
701{
702 u_int16_t phy_sts = 0, media, advert, ability;
703 struct ifnet *ifp;
704 struct ifmedia *ifm;
705
706 ifm = &sc->ifmedia;
707 ifp = &sc->arpcom.ac_if;
708
709 /*
710 * The 100baseT4 PHY sometimes has the 'autoneg supported'
711 * bit cleared in the status register, but has the 'autoneg enabled'
712 * bit set in the control register. This is a contradiction, and
713 * I'm not sure how to handle it. If you want to force an attempt
714 * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR
715 * and see what happens.
716 */
717#ifndef FORCE_AUTONEG_TFOUR
718 /*
719 * First, see if autoneg is supported. If not, there's
720 * no point in continuing.
721 */
722 phy_sts = rl_phy_readreg(sc, PHY_BMSR);
723 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
724 if (verbose)
725 printf("rl%d: autonegotiation not supported\n",
726 sc->rl_unit);
727 return;
728 }
729#endif
730
731 switch (flag) {
732 case RL_FLAG_FORCEDELAY:
733 /*
734 * XXX Never use this option anywhere but in the probe
735 * routine: making the kernel stop dead in its tracks
736 * for three whole seconds after we've gone multi-user
737 * is really bad manners.
738 */
739 rl_autoneg_xmit(sc);
740 DELAY(5000000);
741 break;
742 case RL_FLAG_SCHEDDELAY:
743 /*
744 * Wait for the transmitter to go idle before starting
745 * an autoneg session, otherwise rl_start() may clobber
746 * our timeout, and we don't want to allow transmission
747 * during an autoneg session since that can screw it up.
748 */
749 if (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx) {
750 sc->rl_want_auto = 1;
751 return;
752 }
753 rl_autoneg_xmit(sc);
754 ifp->if_timer = 5;
755 sc->rl_autoneg = 1;
756 sc->rl_want_auto = 0;
757 return;
758 break;
759 case RL_FLAG_DELAYTIMEO:
760 ifp->if_timer = 0;
761 sc->rl_autoneg = 0;
762 break;
763 default:
764 printf("rl%d: invalid autoneg flag: %d\n", sc->rl_unit, flag);
765 return;
766 }
767
768 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
769 if (verbose)
770 printf("rl%d: autoneg complete, ", sc->rl_unit);
771 phy_sts = rl_phy_readreg(sc, PHY_BMSR);
772 } else {
773 if (verbose)
774 printf("rl%d: autoneg not complete, ", sc->rl_unit);
775 }
776
777 media = rl_phy_readreg(sc, PHY_BMCR);
778
779 /* Link is good. Report modes and set duplex mode. */
780 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
781 if (verbose)
782 printf("link status good ");
783 advert = rl_phy_readreg(sc, PHY_ANAR);
784 ability = rl_phy_readreg(sc, PHY_LPAR);
785
786 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
787 ifm->ifm_media = IFM_ETHER|IFM_100_T4;
788 media |= PHY_BMCR_SPEEDSEL;
789 media &= ~PHY_BMCR_DUPLEX;
790 printf("(100baseT4)\n");
791 } else if (advert & PHY_ANAR_100BTXFULL &&
792 ability & PHY_ANAR_100BTXFULL) {
793 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
794 media |= PHY_BMCR_SPEEDSEL;
795 media |= PHY_BMCR_DUPLEX;
796 printf("(full-duplex, 100Mbps)\n");
797 } else if (advert & PHY_ANAR_100BTXHALF &&
798 ability & PHY_ANAR_100BTXHALF) {
799 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
800 media |= PHY_BMCR_SPEEDSEL;
801 media &= ~PHY_BMCR_DUPLEX;
802 printf("(half-duplex, 100Mbps)\n");
803 } else if (advert & PHY_ANAR_10BTFULL &&
804 ability & PHY_ANAR_10BTFULL) {
805 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
806 media &= ~PHY_BMCR_SPEEDSEL;
807 media |= PHY_BMCR_DUPLEX;
808 printf("(full-duplex, 10Mbps)\n");
809 } else {
810 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
811 media &= ~PHY_BMCR_SPEEDSEL;
812 media &= ~PHY_BMCR_DUPLEX;
813 printf("(half-duplex, 10Mbps)\n");
814 }
815
816 /* Set ASIC's duplex mode to match the PHY. */
817 rl_phy_writereg(sc, PHY_BMCR, media);
818 } else {
819 if (verbose)
820 printf("no carrier\n");
821 }
822
823 rl_init(sc);
824
825 if (sc->rl_tx_pend) {
826 sc->rl_autoneg = 0;
827 sc->rl_tx_pend = 0;
828 rl_start(ifp);
829 }
830
831 return;
832}
833
834static void rl_getmode_mii(sc)
835 struct rl_softc *sc;
836{
837 u_int16_t bmsr;
838 struct ifnet *ifp;
839
840 ifp = &sc->arpcom.ac_if;
841
842 bmsr = rl_phy_readreg(sc, PHY_BMSR);
843 if (bootverbose)
844 printf("rl%d: PHY status word: %x\n", sc->rl_unit, bmsr);
845
846 /* fallback */
847 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
848
849 if (bmsr & PHY_BMSR_10BTHALF) {
850 if (bootverbose)
851 printf("rl%d: 10Mbps half-duplex mode supported\n",
852 sc->rl_unit);
853 ifmedia_add(&sc->ifmedia,
854 IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
855 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
856 }
857
858 if (bmsr & PHY_BMSR_10BTFULL) {
859 if (bootverbose)
860 printf("rl%d: 10Mbps full-duplex mode supported\n",
861 sc->rl_unit);
862 ifmedia_add(&sc->ifmedia,
863 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
864 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
865 }
866
867 if (bmsr & PHY_BMSR_100BTXHALF) {
868 if (bootverbose)
869 printf("rl%d: 100Mbps half-duplex mode supported\n",
870 sc->rl_unit);
871 ifp->if_baudrate = 100000000;
872 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
873 ifmedia_add(&sc->ifmedia,
874 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
875 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
876 }
877
878 if (bmsr & PHY_BMSR_100BTXFULL) {
879 if (bootverbose)
880 printf("rl%d: 100Mbps full-duplex mode supported\n",
881 sc->rl_unit);
882 ifp->if_baudrate = 100000000;
883 ifmedia_add(&sc->ifmedia,
884 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
885 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
886 }
887
888 /* Some also support 100BaseT4. */
889 if (bmsr & PHY_BMSR_100BT4) {
890 if (bootverbose)
891 printf("rl%d: 100baseT4 mode supported\n", sc->rl_unit);
892 ifp->if_baudrate = 100000000;
893 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL);
894 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4;
895#ifdef FORCE_AUTONEG_TFOUR
896 if (bootverbose)
897 printf("rl%d: forcing on autoneg support for BT4\n",
898 sc->rl_unit);
899 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL):
900 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
901#endif
902 }
903
904 if (bmsr & PHY_BMSR_CANAUTONEG) {
905 if (bootverbose)
906 printf("rl%d: autoneg supported\n", sc->rl_unit);
907 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
908 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
909 }
910
911 return;
912}
913
914/*
915 * Set speed and duplex mode.
916 */
917static void rl_setmode_mii(sc, media)
918 struct rl_softc *sc;
919 int media;
920{
921 u_int16_t bmcr;
922
923 printf("rl%d: selecting MII, ", sc->rl_unit);
924
925 bmcr = rl_phy_readreg(sc, PHY_BMCR);
926
927 bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL|
928 PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK);
929
930 if (IFM_SUBTYPE(media) == IFM_100_T4) {
931 printf("100Mbps/T4, half-duplex\n");
932 bmcr |= PHY_BMCR_SPEEDSEL;
933 bmcr &= ~PHY_BMCR_DUPLEX;
934 }
935
936 if (IFM_SUBTYPE(media) == IFM_100_TX) {
937 printf("100Mbps, ");
938 bmcr |= PHY_BMCR_SPEEDSEL;
939 }
940
941 if (IFM_SUBTYPE(media) == IFM_10_T) {
942 printf("10Mbps, ");
943 bmcr &= ~PHY_BMCR_SPEEDSEL;
944 }
945
946 if ((media & IFM_GMASK) == IFM_FDX) {
947 printf("full duplex\n");
948 bmcr |= PHY_BMCR_DUPLEX;
949 } else {
950 printf("half duplex\n");
951 bmcr &= ~PHY_BMCR_DUPLEX;
952 }
953
954 rl_phy_writereg(sc, PHY_BMCR, bmcr);
955
956 return;
957}
958
959static void rl_reset(sc)
960 struct rl_softc *sc;
961{
962 register int i;
963
964 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
965
966 for (i = 0; i < RL_TIMEOUT; i++) {
967 DELAY(10);
968 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
969 break;
970 }
971 if (i == RL_TIMEOUT)
972 printf("rl%d: reset never completed!\n", sc->rl_unit);
973
974 return;
975}
976
977/*
978 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
979 * IDs against our list and return a device name if we find a match.
980 */
981static const char *
982rl_probe(config_id, device_id)
983 pcici_t config_id;
984 pcidi_t device_id;
985{
986 struct rl_type *t;
987
988 t = rl_devs;
989
990 while(t->rl_name != NULL) {
991 if ((device_id & 0xFFFF) == t->rl_vid &&
992 ((device_id >> 16) & 0xFFFF) == t->rl_did) {
993 return(t->rl_name);
994 }
995 t++;
996 }
997
998 return(NULL);
999}
1000
1001/*
1002 * Attach the interface. Allocate softc structures, do ifmedia
1003 * setup and ethernet/BPF attach.
1004 */
1005static void
1006rl_attach(config_id, unit)
1007 pcici_t config_id;
1008 int unit;
1009{
1010 int s, i;
1011#ifndef RL_USEIOSPACE
1012 vm_offset_t pbase, vbase;
1013#endif
1014 u_char eaddr[ETHER_ADDR_LEN];
1015 u_int32_t command;
1016 struct rl_softc *sc;
1017 struct ifnet *ifp;
1018 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1019 struct rl_type *p;
1020 u_int16_t phy_vid, phy_did, phy_sts;
1021 u_int16_t rl_did = 0;
1022
1023 s = splimp();
1024
1025 sc = malloc(sizeof(struct rl_softc), M_DEVBUF, M_NOWAIT);
1026 if (sc == NULL) {
1027 printf("rl%d: no memory for softc struct!\n", unit);
1028 goto fail;
1029 }
1030 bzero(sc, sizeof(struct rl_softc));
1031
1032 /*
1033 * Handle power management nonsense.
1034 */
1035
1036 command = pci_conf_read(config_id, RL_PCI_CAPID) & 0x000000FF;
1037 if (command == 0x01) {
1038
1039 command = pci_conf_read(config_id, RL_PCI_PWRMGMTCTRL);
1040 if (command & RL_PSTATE_MASK) {
1041 u_int32_t iobase, membase, irq;
1042
1043 /* Save important PCI config data. */
1044 iobase = pci_conf_read(config_id, RL_PCI_LOIO);
1045 membase = pci_conf_read(config_id, RL_PCI_LOMEM);
1046 irq = pci_conf_read(config_id, RL_PCI_INTLINE);
1047
1048 /* Reset the power state. */
1049 printf("rl%d: chip is is in D%d power mode "
1050 "-- setting to D0\n", unit, command & RL_PSTATE_MASK);
1051 command &= 0xFFFFFFFC;
1052 pci_conf_write(config_id, RL_PCI_PWRMGMTCTRL, command);
1053
1054 /* Restore PCI config data. */
1055 pci_conf_write(config_id, RL_PCI_LOIO, iobase);
1056 pci_conf_write(config_id, RL_PCI_LOMEM, membase);
1057 pci_conf_write(config_id, RL_PCI_INTLINE, irq);
1058 }
1059 }
1060
1061 /*
1062 * Map control/status registers.
1063 */
1064 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1065 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1066 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command);
1067 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1068
1069#ifdef RL_USEIOSPACE
1070 if (!(command & PCIM_CMD_PORTEN)) {
1071 printf("rl%d: failed to enable I/O ports!\n", unit);
1072 free(sc, M_DEVBUF);
1073 goto fail;
1074 }
1075
1076 if (!pci_map_port(config_id, RL_PCI_LOIO,
1077 (pci_port_t *)&(sc->rl_bhandle))) {
1078 printf ("rl%d: couldn't map ports\n", unit);
1079 goto fail;
1080 }
1081#ifdef __i386__
1082 sc->rl_btag = I386_BUS_SPACE_IO;
1083#endif
1084#ifdef __alpha__
1085 sc->rl_btag = ALPHA_BUS_SPACE_IO;
1086#endif
1087#else
1088 if (!(command & PCIM_CMD_MEMEN)) {
1089 printf("rl%d: failed to enable memory mapping!\n", unit);
1090 goto fail;
1091 }
1092
1093 if (!pci_map_mem(config_id, RL_PCI_LOMEM, &vbase, &pbase)) {
1094 printf ("rl%d: couldn't map memory\n", unit);
1095 goto fail;
1096 }
1097#ifdef __i386__
1098 sc->rl_btag = I386_BUS_SPACE_MEM;
1099#endif
1100#ifdef __alpha__
1101 sc->rl_btag = ALPHA_BUS_SPACE_MEM;
1102#endif
1103 sc->rl_bhandle = vbase;
1104#endif
1105
1106 /* Allocate interrupt */
1107 if (!pci_map_int(config_id, rl_intr, sc, &net_imask)) {
1108 printf("rl%d: couldn't map interrupt\n", unit);
1109 goto fail;
1110 }
1111
1112 /* Reset the adapter. */
1113 rl_reset(sc);
1114
1115 /*
1116 * Get station address from the EEPROM.
1117 */
1118 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
1119
1120 /*
1121 * A RealTek chip was detected. Inform the world.
1122 */
1123 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
1124
1125 sc->rl_unit = unit;
1126 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1127
1128 /*
1129 * Now read the exact device type from the EEPROM to find
1130 * out if it's an 8129 or 8139.
1131 */
1132 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
1133
1134 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
1135 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139)
1136 sc->rl_type = RL_8139;
1137 else if (rl_did == RT_DEVICEID_8129)
1138 sc->rl_type = RL_8129;
1139 else {
1140 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
1141 free(sc, M_DEVBUF);
1142 goto fail;
1143 }
1144
1145 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 32, M_DEVBUF,
1146 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0);
1147
1148 if (sc->rl_cdata.rl_rx_buf == NULL) {
1149 free(sc, M_DEVBUF);
1150 printf("rl%d: no memory for list buffers!\n", unit);
1151 goto fail;
1152 }
1153
1154 /* Leave a few bytes before the start of the RX ring buffer. */
1155 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1156 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
1157
1158 ifp = &sc->arpcom.ac_if;
1159 ifp->if_softc = sc;
1160 ifp->if_unit = unit;
1161 ifp->if_name = "rl";
1162 ifp->if_mtu = ETHERMTU;
1163 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1164 ifp->if_ioctl = rl_ioctl;
1165 ifp->if_output = ether_output;
1166 ifp->if_start = rl_start;
1167 ifp->if_watchdog = rl_watchdog;
1168 ifp->if_init = rl_init;
1169 ifp->if_baudrate = 10000000;
1170 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1171
1172 if (sc->rl_type == RL_8129) {
1173 if (bootverbose)
1174 printf("rl%d: probing for a PHY\n", sc->rl_unit);
1175 for (i = RL_PHYADDR_MIN; i < RL_PHYADDR_MAX + 1; i++) {
1176 if (bootverbose)
1177 printf("rl%d: checking address: %d\n",
1178 sc->rl_unit, i);
1179 sc->rl_phy_addr = i;
1180 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
1181 DELAY(500);
1182 while(rl_phy_readreg(sc, PHY_BMCR)
1183 & PHY_BMCR_RESET);
1184 if ((phy_sts = rl_phy_readreg(sc, PHY_BMSR)))
1185 break;
1186 }
1187 if (phy_sts) {
1188 phy_vid = rl_phy_readreg(sc, PHY_VENID);
1189 phy_did = rl_phy_readreg(sc, PHY_DEVID);
1190 if (bootverbose)
1191 printf("rl%d: found PHY at address %d, ",
1192 sc->rl_unit, sc->rl_phy_addr);
1193 if (bootverbose)
1194 printf("vendor id: %x device id: %x\n",
1195 phy_vid, phy_did);
1196 p = rl_phys;
1197 while(p->rl_vid) {
1198 if (phy_vid == p->rl_vid &&
1199 (phy_did | 0x000F) == p->rl_did) {
1200 sc->rl_pinfo = p;
1201 break;
1202 }
1203 p++;
1204 }
1205 if (sc->rl_pinfo == NULL)
1206 sc->rl_pinfo = &rl_phys[PHY_UNKNOWN];
1207 if (bootverbose)
1208 printf("rl%d: PHY type: %s\n",
1209 sc->rl_unit, sc->rl_pinfo->rl_name);
1210 } else {
1211 printf("rl%d: MII without any phy!\n", sc->rl_unit);
1212 }
1213 }
1214
1215 /*
1216 * Do ifmedia setup.
1217 */
1218 ifmedia_init(&sc->ifmedia, 0, rl_ifmedia_upd, rl_ifmedia_sts);
1219
1220 rl_getmode_mii(sc);
1221
1222 /* Choose a default media. */
1223 media = IFM_ETHER|IFM_AUTO;
1224 ifmedia_set(&sc->ifmedia, media);
1225
1226 rl_autoneg_mii(sc, RL_FLAG_FORCEDELAY, 1);
1227
1228 /*
1229 * Call MI attach routines.
1230 */
1231 if_attach(ifp);
1232 ether_ifattach(ifp);
1233
1234#if NBPF > 0
1235 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1236#endif
| 181static int rl_ifmedia_upd __P((struct ifnet *));
182static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
183
184static void rl_eeprom_putbyte __P((struct rl_softc *, int));
185static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *));
186static void rl_read_eeprom __P((struct rl_softc *, caddr_t,
187 int, int, int));
188static void rl_mii_sync __P((struct rl_softc *));
189static void rl_mii_send __P((struct rl_softc *, u_int32_t, int));
190static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *));
191static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *));
192
193static u_int16_t rl_phy_readreg __P((struct rl_softc *, int));
194static void rl_phy_writereg __P((struct rl_softc *, int, int));
195
196static void rl_autoneg_xmit __P((struct rl_softc *));
197static void rl_autoneg_mii __P((struct rl_softc *, int, int));
198static void rl_setmode_mii __P((struct rl_softc *, int));
199static void rl_getmode_mii __P((struct rl_softc *));
200static u_int8_t rl_calchash __P((caddr_t));
201static void rl_setmulti __P((struct rl_softc *));
202static void rl_reset __P((struct rl_softc *));
203static int rl_list_tx_init __P((struct rl_softc *));
204
205#define EE_SET(x) \
206 CSR_WRITE_1(sc, RL_EECMD, \
207 CSR_READ_1(sc, RL_EECMD) | x)
208
209#define EE_CLR(x) \
210 CSR_WRITE_1(sc, RL_EECMD, \
211 CSR_READ_1(sc, RL_EECMD) & ~x)
212
213/*
214 * Send a read command and address to the EEPROM, check for ACK.
215 */
216static void rl_eeprom_putbyte(sc, addr)
217 struct rl_softc *sc;
218 int addr;
219{
220 register int d, i;
221
222 d = addr | RL_EECMD_READ;
223
224 /*
225 * Feed in each bit and stobe the clock.
226 */
227 for (i = 0x400; i; i >>= 1) {
228 if (d & i) {
229 EE_SET(RL_EE_DATAIN);
230 } else {
231 EE_CLR(RL_EE_DATAIN);
232 }
233 DELAY(100);
234 EE_SET(RL_EE_CLK);
235 DELAY(150);
236 EE_CLR(RL_EE_CLK);
237 DELAY(100);
238 }
239
240 return;
241}
242
243/*
244 * Read a word of data stored in the EEPROM at address 'addr.'
245 */
246static void rl_eeprom_getword(sc, addr, dest)
247 struct rl_softc *sc;
248 int addr;
249 u_int16_t *dest;
250{
251 register int i;
252 u_int16_t word = 0;
253
254 /* Enter EEPROM access mode. */
255 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
256
257 /*
258 * Send address of word we want to read.
259 */
260 rl_eeprom_putbyte(sc, addr);
261
262 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
263
264 /*
265 * Start reading bits from EEPROM.
266 */
267 for (i = 0x8000; i; i >>= 1) {
268 EE_SET(RL_EE_CLK);
269 DELAY(100);
270 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
271 word |= i;
272 EE_CLR(RL_EE_CLK);
273 DELAY(100);
274 }
275
276 /* Turn off EEPROM access mode. */
277 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
278
279 *dest = word;
280
281 return;
282}
283
284/*
285 * Read a sequence of words from the EEPROM.
286 */
287static void rl_read_eeprom(sc, dest, off, cnt, swap)
288 struct rl_softc *sc;
289 caddr_t dest;
290 int off;
291 int cnt;
292 int swap;
293{
294 int i;
295 u_int16_t word = 0, *ptr;
296
297 for (i = 0; i < cnt; i++) {
298 rl_eeprom_getword(sc, off + i, &word);
299 ptr = (u_int16_t *)(dest + (i * 2));
300 if (swap)
301 *ptr = ntohs(word);
302 else
303 *ptr = word;
304 }
305
306 return;
307}
308
309
310/*
311 * MII access routines are provided for the 8129, which
312 * doesn't have a built-in PHY. For the 8139, we fake things
313 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
314 * direct access PHY registers.
315 */
316#define MII_SET(x) \
317 CSR_WRITE_1(sc, RL_MII, \
318 CSR_READ_1(sc, RL_MII) | x)
319
320#define MII_CLR(x) \
321 CSR_WRITE_1(sc, RL_MII, \
322 CSR_READ_1(sc, RL_MII) & ~x)
323
324/*
325 * Sync the PHYs by setting data bit and strobing the clock 32 times.
326 */
327static void rl_mii_sync(sc)
328 struct rl_softc *sc;
329{
330 register int i;
331
332 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
333
334 for (i = 0; i < 32; i++) {
335 MII_SET(RL_MII_CLK);
336 DELAY(1);
337 MII_CLR(RL_MII_CLK);
338 DELAY(1);
339 }
340
341 return;
342}
343
344/*
345 * Clock a series of bits through the MII.
346 */
347static void rl_mii_send(sc, bits, cnt)
348 struct rl_softc *sc;
349 u_int32_t bits;
350 int cnt;
351{
352 int i;
353
354 MII_CLR(RL_MII_CLK);
355
356 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
357 if (bits & i) {
358 MII_SET(RL_MII_DATAOUT);
359 } else {
360 MII_CLR(RL_MII_DATAOUT);
361 }
362 DELAY(1);
363 MII_CLR(RL_MII_CLK);
364 DELAY(1);
365 MII_SET(RL_MII_CLK);
366 }
367}
368
369/*
370 * Read an PHY register through the MII.
371 */
372static int rl_mii_readreg(sc, frame)
373 struct rl_softc *sc;
374 struct rl_mii_frame *frame;
375
376{
377 int i, ack, s;
378
379 s = splimp();
380
381 /*
382 * Set up frame for RX.
383 */
384 frame->mii_stdelim = RL_MII_STARTDELIM;
385 frame->mii_opcode = RL_MII_READOP;
386 frame->mii_turnaround = 0;
387 frame->mii_data = 0;
388
389 CSR_WRITE_2(sc, RL_MII, 0);
390
391 /*
392 * Turn on data xmit.
393 */
394 MII_SET(RL_MII_DIR);
395
396 rl_mii_sync(sc);
397
398 /*
399 * Send command/address info.
400 */
401 rl_mii_send(sc, frame->mii_stdelim, 2);
402 rl_mii_send(sc, frame->mii_opcode, 2);
403 rl_mii_send(sc, frame->mii_phyaddr, 5);
404 rl_mii_send(sc, frame->mii_regaddr, 5);
405
406 /* Idle bit */
407 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
408 DELAY(1);
409 MII_SET(RL_MII_CLK);
410 DELAY(1);
411
412 /* Turn off xmit. */
413 MII_CLR(RL_MII_DIR);
414
415 /* Check for ack */
416 MII_CLR(RL_MII_CLK);
417 DELAY(1);
418 MII_SET(RL_MII_CLK);
419 DELAY(1);
420 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
421
422 /*
423 * Now try reading data bits. If the ack failed, we still
424 * need to clock through 16 cycles to keep the PHY(s) in sync.
425 */
426 if (ack) {
427 for(i = 0; i < 16; i++) {
428 MII_CLR(RL_MII_CLK);
429 DELAY(1);
430 MII_SET(RL_MII_CLK);
431 DELAY(1);
432 }
433 goto fail;
434 }
435
436 for (i = 0x8000; i; i >>= 1) {
437 MII_CLR(RL_MII_CLK);
438 DELAY(1);
439 if (!ack) {
440 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
441 frame->mii_data |= i;
442 DELAY(1);
443 }
444 MII_SET(RL_MII_CLK);
445 DELAY(1);
446 }
447
448fail:
449
450 MII_CLR(RL_MII_CLK);
451 DELAY(1);
452 MII_SET(RL_MII_CLK);
453 DELAY(1);
454
455 splx(s);
456
457 if (ack)
458 return(1);
459 return(0);
460}
461
462/*
463 * Write to a PHY register through the MII.
464 */
465static int rl_mii_writereg(sc, frame)
466 struct rl_softc *sc;
467 struct rl_mii_frame *frame;
468
469{
470 int s;
471
472 s = splimp();
473 /*
474 * Set up frame for TX.
475 */
476
477 frame->mii_stdelim = RL_MII_STARTDELIM;
478 frame->mii_opcode = RL_MII_WRITEOP;
479 frame->mii_turnaround = RL_MII_TURNAROUND;
480
481 /*
482 * Turn on data output.
483 */
484 MII_SET(RL_MII_DIR);
485
486 rl_mii_sync(sc);
487
488 rl_mii_send(sc, frame->mii_stdelim, 2);
489 rl_mii_send(sc, frame->mii_opcode, 2);
490 rl_mii_send(sc, frame->mii_phyaddr, 5);
491 rl_mii_send(sc, frame->mii_regaddr, 5);
492 rl_mii_send(sc, frame->mii_turnaround, 2);
493 rl_mii_send(sc, frame->mii_data, 16);
494
495 /* Idle bit. */
496 MII_SET(RL_MII_CLK);
497 DELAY(1);
498 MII_CLR(RL_MII_CLK);
499 DELAY(1);
500
501 /*
502 * Turn off xmit.
503 */
504 MII_CLR(RL_MII_DIR);
505
506 splx(s);
507
508 return(0);
509}
510
511static u_int16_t rl_phy_readreg(sc, reg)
512 struct rl_softc *sc;
513 int reg;
514{
515 struct rl_mii_frame frame;
516 u_int16_t rval = 0;
517 u_int16_t rl8139_reg = 0;
518
519 if (sc->rl_type == RL_8139) {
520 switch(reg) {
521 case PHY_BMCR:
522 rl8139_reg = RL_BMCR;
523 break;
524 case PHY_BMSR:
525 rl8139_reg = RL_BMSR;
526 break;
527 case PHY_ANAR:
528 rl8139_reg = RL_ANAR;
529 break;
530 case PHY_LPAR:
531 rl8139_reg = RL_LPAR;
532 break;
533 default:
534 printf("rl%d: bad phy register\n", sc->rl_unit);
535 return(0);
536 }
537 rval = CSR_READ_2(sc, rl8139_reg);
538 return(rval);
539 }
540
541 bzero((char *)&frame, sizeof(frame));
542
543 frame.mii_phyaddr = sc->rl_phy_addr;
544 frame.mii_regaddr = reg;
545 rl_mii_readreg(sc, &frame);
546
547 return(frame.mii_data);
548}
549
550static void rl_phy_writereg(sc, reg, data)
551 struct rl_softc *sc;
552 int reg;
553 int data;
554{
555 struct rl_mii_frame frame;
556 u_int16_t rl8139_reg = 0;
557
558 if (sc->rl_type == RL_8139) {
559 switch(reg) {
560 case PHY_BMCR:
561 rl8139_reg = RL_BMCR;
562 break;
563 case PHY_BMSR:
564 rl8139_reg = RL_BMSR;
565 break;
566 case PHY_ANAR:
567 rl8139_reg = RL_ANAR;
568 break;
569 case PHY_LPAR:
570 rl8139_reg = RL_LPAR;
571 break;
572 default:
573 printf("rl%d: bad phy register\n", sc->rl_unit);
574 return;
575 }
576 CSR_WRITE_2(sc, rl8139_reg, data);
577 return;
578 }
579
580 bzero((char *)&frame, sizeof(frame));
581
582 frame.mii_phyaddr = sc->rl_phy_addr;
583 frame.mii_regaddr = reg;
584 frame.mii_data = data;
585
586 rl_mii_writereg(sc, &frame);
587
588 return;
589}
590
591/*
592 * Calculate CRC of a multicast group address, return the upper 6 bits.
593 */
594static u_int8_t rl_calchash(addr)
595 caddr_t addr;
596{
597 u_int32_t crc, carry;
598 int i, j;
599 u_int8_t c;
600
601 /* Compute CRC for the address value. */
602 crc = 0xFFFFFFFF; /* initial value */
603
604 for (i = 0; i < 6; i++) {
605 c = *(addr + i);
606 for (j = 0; j < 8; j++) {
607 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
608 crc <<= 1;
609 c >>= 1;
610 if (carry)
611 crc = (crc ^ 0x04c11db6) | carry;
612 }
613 }
614
615 /* return the filter bit position */
616 return(crc >> 26);
617}
618
619/*
620 * Program the 64-bit multicast hash filter.
621 */
622static void rl_setmulti(sc)
623 struct rl_softc *sc;
624{
625 struct ifnet *ifp;
626 int h = 0;
627 u_int32_t hashes[2] = { 0, 0 };
628 struct ifmultiaddr *ifma;
629 u_int32_t rxfilt;
630 int mcnt = 0;
631
632 ifp = &sc->arpcom.ac_if;
633
634 rxfilt = CSR_READ_4(sc, RL_RXCFG);
635
636 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
637 rxfilt |= RL_RXCFG_RX_MULTI;
638 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
639 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
640 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
641 return;
642 }
643
644 /* first, zot all the existing hash bits */
645 CSR_WRITE_4(sc, RL_MAR0, 0);
646 CSR_WRITE_4(sc, RL_MAR4, 0);
647
648 /* now program new ones */
649 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
650 ifma = ifma->ifma_link.le_next) {
651 if (ifma->ifma_addr->sa_family != AF_LINK)
652 continue;
653 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
654 if (h < 32)
655 hashes[0] |= (1 << h);
656 else
657 hashes[1] |= (1 << (h - 32));
658 mcnt++;
659 }
660
661 if (mcnt)
662 rxfilt |= RL_RXCFG_RX_MULTI;
663 else
664 rxfilt &= ~RL_RXCFG_RX_MULTI;
665
666 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
667 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
668 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
669
670 return;
671}
672
673/*
674 * Initiate an autonegotiation session.
675 */
676static void rl_autoneg_xmit(sc)
677 struct rl_softc *sc;
678{
679 u_int16_t phy_sts;
680
681 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
682 DELAY(500);
683 while(rl_phy_readreg(sc, PHY_BMCR)
684 & PHY_BMCR_RESET);
685
686 phy_sts = rl_phy_readreg(sc, PHY_BMCR);
687 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
688 rl_phy_writereg(sc, PHY_BMCR, phy_sts);
689
690 return;
691}
692
693/*
694 * Invoke autonegotiation on a PHY. Also used with the 8139 internal
695 * transceiver.
696 */
697static void rl_autoneg_mii(sc, flag, verbose)
698 struct rl_softc *sc;
699 int flag;
700 int verbose;
701{
702 u_int16_t phy_sts = 0, media, advert, ability;
703 struct ifnet *ifp;
704 struct ifmedia *ifm;
705
706 ifm = &sc->ifmedia;
707 ifp = &sc->arpcom.ac_if;
708
709 /*
710 * The 100baseT4 PHY sometimes has the 'autoneg supported'
711 * bit cleared in the status register, but has the 'autoneg enabled'
712 * bit set in the control register. This is a contradiction, and
713 * I'm not sure how to handle it. If you want to force an attempt
714 * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR
715 * and see what happens.
716 */
717#ifndef FORCE_AUTONEG_TFOUR
718 /*
719 * First, see if autoneg is supported. If not, there's
720 * no point in continuing.
721 */
722 phy_sts = rl_phy_readreg(sc, PHY_BMSR);
723 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
724 if (verbose)
725 printf("rl%d: autonegotiation not supported\n",
726 sc->rl_unit);
727 return;
728 }
729#endif
730
731 switch (flag) {
732 case RL_FLAG_FORCEDELAY:
733 /*
734 * XXX Never use this option anywhere but in the probe
735 * routine: making the kernel stop dead in its tracks
736 * for three whole seconds after we've gone multi-user
737 * is really bad manners.
738 */
739 rl_autoneg_xmit(sc);
740 DELAY(5000000);
741 break;
742 case RL_FLAG_SCHEDDELAY:
743 /*
744 * Wait for the transmitter to go idle before starting
745 * an autoneg session, otherwise rl_start() may clobber
746 * our timeout, and we don't want to allow transmission
747 * during an autoneg session since that can screw it up.
748 */
749 if (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx) {
750 sc->rl_want_auto = 1;
751 return;
752 }
753 rl_autoneg_xmit(sc);
754 ifp->if_timer = 5;
755 sc->rl_autoneg = 1;
756 sc->rl_want_auto = 0;
757 return;
758 break;
759 case RL_FLAG_DELAYTIMEO:
760 ifp->if_timer = 0;
761 sc->rl_autoneg = 0;
762 break;
763 default:
764 printf("rl%d: invalid autoneg flag: %d\n", sc->rl_unit, flag);
765 return;
766 }
767
768 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
769 if (verbose)
770 printf("rl%d: autoneg complete, ", sc->rl_unit);
771 phy_sts = rl_phy_readreg(sc, PHY_BMSR);
772 } else {
773 if (verbose)
774 printf("rl%d: autoneg not complete, ", sc->rl_unit);
775 }
776
777 media = rl_phy_readreg(sc, PHY_BMCR);
778
779 /* Link is good. Report modes and set duplex mode. */
780 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
781 if (verbose)
782 printf("link status good ");
783 advert = rl_phy_readreg(sc, PHY_ANAR);
784 ability = rl_phy_readreg(sc, PHY_LPAR);
785
786 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
787 ifm->ifm_media = IFM_ETHER|IFM_100_T4;
788 media |= PHY_BMCR_SPEEDSEL;
789 media &= ~PHY_BMCR_DUPLEX;
790 printf("(100baseT4)\n");
791 } else if (advert & PHY_ANAR_100BTXFULL &&
792 ability & PHY_ANAR_100BTXFULL) {
793 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
794 media |= PHY_BMCR_SPEEDSEL;
795 media |= PHY_BMCR_DUPLEX;
796 printf("(full-duplex, 100Mbps)\n");
797 } else if (advert & PHY_ANAR_100BTXHALF &&
798 ability & PHY_ANAR_100BTXHALF) {
799 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
800 media |= PHY_BMCR_SPEEDSEL;
801 media &= ~PHY_BMCR_DUPLEX;
802 printf("(half-duplex, 100Mbps)\n");
803 } else if (advert & PHY_ANAR_10BTFULL &&
804 ability & PHY_ANAR_10BTFULL) {
805 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
806 media &= ~PHY_BMCR_SPEEDSEL;
807 media |= PHY_BMCR_DUPLEX;
808 printf("(full-duplex, 10Mbps)\n");
809 } else {
810 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
811 media &= ~PHY_BMCR_SPEEDSEL;
812 media &= ~PHY_BMCR_DUPLEX;
813 printf("(half-duplex, 10Mbps)\n");
814 }
815
816 /* Set ASIC's duplex mode to match the PHY. */
817 rl_phy_writereg(sc, PHY_BMCR, media);
818 } else {
819 if (verbose)
820 printf("no carrier\n");
821 }
822
823 rl_init(sc);
824
825 if (sc->rl_tx_pend) {
826 sc->rl_autoneg = 0;
827 sc->rl_tx_pend = 0;
828 rl_start(ifp);
829 }
830
831 return;
832}
833
834static void rl_getmode_mii(sc)
835 struct rl_softc *sc;
836{
837 u_int16_t bmsr;
838 struct ifnet *ifp;
839
840 ifp = &sc->arpcom.ac_if;
841
842 bmsr = rl_phy_readreg(sc, PHY_BMSR);
843 if (bootverbose)
844 printf("rl%d: PHY status word: %x\n", sc->rl_unit, bmsr);
845
846 /* fallback */
847 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
848
849 if (bmsr & PHY_BMSR_10BTHALF) {
850 if (bootverbose)
851 printf("rl%d: 10Mbps half-duplex mode supported\n",
852 sc->rl_unit);
853 ifmedia_add(&sc->ifmedia,
854 IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
855 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
856 }
857
858 if (bmsr & PHY_BMSR_10BTFULL) {
859 if (bootverbose)
860 printf("rl%d: 10Mbps full-duplex mode supported\n",
861 sc->rl_unit);
862 ifmedia_add(&sc->ifmedia,
863 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
864 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
865 }
866
867 if (bmsr & PHY_BMSR_100BTXHALF) {
868 if (bootverbose)
869 printf("rl%d: 100Mbps half-duplex mode supported\n",
870 sc->rl_unit);
871 ifp->if_baudrate = 100000000;
872 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
873 ifmedia_add(&sc->ifmedia,
874 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
875 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
876 }
877
878 if (bmsr & PHY_BMSR_100BTXFULL) {
879 if (bootverbose)
880 printf("rl%d: 100Mbps full-duplex mode supported\n",
881 sc->rl_unit);
882 ifp->if_baudrate = 100000000;
883 ifmedia_add(&sc->ifmedia,
884 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
885 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
886 }
887
888 /* Some also support 100BaseT4. */
889 if (bmsr & PHY_BMSR_100BT4) {
890 if (bootverbose)
891 printf("rl%d: 100baseT4 mode supported\n", sc->rl_unit);
892 ifp->if_baudrate = 100000000;
893 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL);
894 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4;
895#ifdef FORCE_AUTONEG_TFOUR
896 if (bootverbose)
897 printf("rl%d: forcing on autoneg support for BT4\n",
898 sc->rl_unit);
899 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL):
900 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
901#endif
902 }
903
904 if (bmsr & PHY_BMSR_CANAUTONEG) {
905 if (bootverbose)
906 printf("rl%d: autoneg supported\n", sc->rl_unit);
907 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
908 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
909 }
910
911 return;
912}
913
914/*
915 * Set speed and duplex mode.
916 */
917static void rl_setmode_mii(sc, media)
918 struct rl_softc *sc;
919 int media;
920{
921 u_int16_t bmcr;
922
923 printf("rl%d: selecting MII, ", sc->rl_unit);
924
925 bmcr = rl_phy_readreg(sc, PHY_BMCR);
926
927 bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL|
928 PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK);
929
930 if (IFM_SUBTYPE(media) == IFM_100_T4) {
931 printf("100Mbps/T4, half-duplex\n");
932 bmcr |= PHY_BMCR_SPEEDSEL;
933 bmcr &= ~PHY_BMCR_DUPLEX;
934 }
935
936 if (IFM_SUBTYPE(media) == IFM_100_TX) {
937 printf("100Mbps, ");
938 bmcr |= PHY_BMCR_SPEEDSEL;
939 }
940
941 if (IFM_SUBTYPE(media) == IFM_10_T) {
942 printf("10Mbps, ");
943 bmcr &= ~PHY_BMCR_SPEEDSEL;
944 }
945
946 if ((media & IFM_GMASK) == IFM_FDX) {
947 printf("full duplex\n");
948 bmcr |= PHY_BMCR_DUPLEX;
949 } else {
950 printf("half duplex\n");
951 bmcr &= ~PHY_BMCR_DUPLEX;
952 }
953
954 rl_phy_writereg(sc, PHY_BMCR, bmcr);
955
956 return;
957}
958
959static void rl_reset(sc)
960 struct rl_softc *sc;
961{
962 register int i;
963
964 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
965
966 for (i = 0; i < RL_TIMEOUT; i++) {
967 DELAY(10);
968 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
969 break;
970 }
971 if (i == RL_TIMEOUT)
972 printf("rl%d: reset never completed!\n", sc->rl_unit);
973
974 return;
975}
976
977/*
978 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
979 * IDs against our list and return a device name if we find a match.
980 */
981static const char *
982rl_probe(config_id, device_id)
983 pcici_t config_id;
984 pcidi_t device_id;
985{
986 struct rl_type *t;
987
988 t = rl_devs;
989
990 while(t->rl_name != NULL) {
991 if ((device_id & 0xFFFF) == t->rl_vid &&
992 ((device_id >> 16) & 0xFFFF) == t->rl_did) {
993 return(t->rl_name);
994 }
995 t++;
996 }
997
998 return(NULL);
999}
1000
1001/*
1002 * Attach the interface. Allocate softc structures, do ifmedia
1003 * setup and ethernet/BPF attach.
1004 */
1005static void
1006rl_attach(config_id, unit)
1007 pcici_t config_id;
1008 int unit;
1009{
1010 int s, i;
1011#ifndef RL_USEIOSPACE
1012 vm_offset_t pbase, vbase;
1013#endif
1014 u_char eaddr[ETHER_ADDR_LEN];
1015 u_int32_t command;
1016 struct rl_softc *sc;
1017 struct ifnet *ifp;
1018 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1019 struct rl_type *p;
1020 u_int16_t phy_vid, phy_did, phy_sts;
1021 u_int16_t rl_did = 0;
1022
1023 s = splimp();
1024
1025 sc = malloc(sizeof(struct rl_softc), M_DEVBUF, M_NOWAIT);
1026 if (sc == NULL) {
1027 printf("rl%d: no memory for softc struct!\n", unit);
1028 goto fail;
1029 }
1030 bzero(sc, sizeof(struct rl_softc));
1031
1032 /*
1033 * Handle power management nonsense.
1034 */
1035
1036 command = pci_conf_read(config_id, RL_PCI_CAPID) & 0x000000FF;
1037 if (command == 0x01) {
1038
1039 command = pci_conf_read(config_id, RL_PCI_PWRMGMTCTRL);
1040 if (command & RL_PSTATE_MASK) {
1041 u_int32_t iobase, membase, irq;
1042
1043 /* Save important PCI config data. */
1044 iobase = pci_conf_read(config_id, RL_PCI_LOIO);
1045 membase = pci_conf_read(config_id, RL_PCI_LOMEM);
1046 irq = pci_conf_read(config_id, RL_PCI_INTLINE);
1047
1048 /* Reset the power state. */
1049 printf("rl%d: chip is is in D%d power mode "
1050 "-- setting to D0\n", unit, command & RL_PSTATE_MASK);
1051 command &= 0xFFFFFFFC;
1052 pci_conf_write(config_id, RL_PCI_PWRMGMTCTRL, command);
1053
1054 /* Restore PCI config data. */
1055 pci_conf_write(config_id, RL_PCI_LOIO, iobase);
1056 pci_conf_write(config_id, RL_PCI_LOMEM, membase);
1057 pci_conf_write(config_id, RL_PCI_INTLINE, irq);
1058 }
1059 }
1060
1061 /*
1062 * Map control/status registers.
1063 */
1064 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1065 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1066 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command);
1067 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1068
1069#ifdef RL_USEIOSPACE
1070 if (!(command & PCIM_CMD_PORTEN)) {
1071 printf("rl%d: failed to enable I/O ports!\n", unit);
1072 free(sc, M_DEVBUF);
1073 goto fail;
1074 }
1075
1076 if (!pci_map_port(config_id, RL_PCI_LOIO,
1077 (pci_port_t *)&(sc->rl_bhandle))) {
1078 printf ("rl%d: couldn't map ports\n", unit);
1079 goto fail;
1080 }
1081#ifdef __i386__
1082 sc->rl_btag = I386_BUS_SPACE_IO;
1083#endif
1084#ifdef __alpha__
1085 sc->rl_btag = ALPHA_BUS_SPACE_IO;
1086#endif
1087#else
1088 if (!(command & PCIM_CMD_MEMEN)) {
1089 printf("rl%d: failed to enable memory mapping!\n", unit);
1090 goto fail;
1091 }
1092
1093 if (!pci_map_mem(config_id, RL_PCI_LOMEM, &vbase, &pbase)) {
1094 printf ("rl%d: couldn't map memory\n", unit);
1095 goto fail;
1096 }
1097#ifdef __i386__
1098 sc->rl_btag = I386_BUS_SPACE_MEM;
1099#endif
1100#ifdef __alpha__
1101 sc->rl_btag = ALPHA_BUS_SPACE_MEM;
1102#endif
1103 sc->rl_bhandle = vbase;
1104#endif
1105
1106 /* Allocate interrupt */
1107 if (!pci_map_int(config_id, rl_intr, sc, &net_imask)) {
1108 printf("rl%d: couldn't map interrupt\n", unit);
1109 goto fail;
1110 }
1111
1112 /* Reset the adapter. */
1113 rl_reset(sc);
1114
1115 /*
1116 * Get station address from the EEPROM.
1117 */
1118 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
1119
1120 /*
1121 * A RealTek chip was detected. Inform the world.
1122 */
1123 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
1124
1125 sc->rl_unit = unit;
1126 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1127
1128 /*
1129 * Now read the exact device type from the EEPROM to find
1130 * out if it's an 8129 or 8139.
1131 */
1132 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
1133
1134 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
1135 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139)
1136 sc->rl_type = RL_8139;
1137 else if (rl_did == RT_DEVICEID_8129)
1138 sc->rl_type = RL_8129;
1139 else {
1140 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
1141 free(sc, M_DEVBUF);
1142 goto fail;
1143 }
1144
1145 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 32, M_DEVBUF,
1146 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0);
1147
1148 if (sc->rl_cdata.rl_rx_buf == NULL) {
1149 free(sc, M_DEVBUF);
1150 printf("rl%d: no memory for list buffers!\n", unit);
1151 goto fail;
1152 }
1153
1154 /* Leave a few bytes before the start of the RX ring buffer. */
1155 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1156 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
1157
1158 ifp = &sc->arpcom.ac_if;
1159 ifp->if_softc = sc;
1160 ifp->if_unit = unit;
1161 ifp->if_name = "rl";
1162 ifp->if_mtu = ETHERMTU;
1163 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1164 ifp->if_ioctl = rl_ioctl;
1165 ifp->if_output = ether_output;
1166 ifp->if_start = rl_start;
1167 ifp->if_watchdog = rl_watchdog;
1168 ifp->if_init = rl_init;
1169 ifp->if_baudrate = 10000000;
1170 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1171
1172 if (sc->rl_type == RL_8129) {
1173 if (bootverbose)
1174 printf("rl%d: probing for a PHY\n", sc->rl_unit);
1175 for (i = RL_PHYADDR_MIN; i < RL_PHYADDR_MAX + 1; i++) {
1176 if (bootverbose)
1177 printf("rl%d: checking address: %d\n",
1178 sc->rl_unit, i);
1179 sc->rl_phy_addr = i;
1180 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
1181 DELAY(500);
1182 while(rl_phy_readreg(sc, PHY_BMCR)
1183 & PHY_BMCR_RESET);
1184 if ((phy_sts = rl_phy_readreg(sc, PHY_BMSR)))
1185 break;
1186 }
1187 if (phy_sts) {
1188 phy_vid = rl_phy_readreg(sc, PHY_VENID);
1189 phy_did = rl_phy_readreg(sc, PHY_DEVID);
1190 if (bootverbose)
1191 printf("rl%d: found PHY at address %d, ",
1192 sc->rl_unit, sc->rl_phy_addr);
1193 if (bootverbose)
1194 printf("vendor id: %x device id: %x\n",
1195 phy_vid, phy_did);
1196 p = rl_phys;
1197 while(p->rl_vid) {
1198 if (phy_vid == p->rl_vid &&
1199 (phy_did | 0x000F) == p->rl_did) {
1200 sc->rl_pinfo = p;
1201 break;
1202 }
1203 p++;
1204 }
1205 if (sc->rl_pinfo == NULL)
1206 sc->rl_pinfo = &rl_phys[PHY_UNKNOWN];
1207 if (bootverbose)
1208 printf("rl%d: PHY type: %s\n",
1209 sc->rl_unit, sc->rl_pinfo->rl_name);
1210 } else {
1211 printf("rl%d: MII without any phy!\n", sc->rl_unit);
1212 }
1213 }
1214
1215 /*
1216 * Do ifmedia setup.
1217 */
1218 ifmedia_init(&sc->ifmedia, 0, rl_ifmedia_upd, rl_ifmedia_sts);
1219
1220 rl_getmode_mii(sc);
1221
1222 /* Choose a default media. */
1223 media = IFM_ETHER|IFM_AUTO;
1224 ifmedia_set(&sc->ifmedia, media);
1225
1226 rl_autoneg_mii(sc, RL_FLAG_FORCEDELAY, 1);
1227
1228 /*
1229 * Call MI attach routines.
1230 */
1231 if_attach(ifp);
1232 ether_ifattach(ifp);
1233
1234#if NBPF > 0
1235 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1236#endif
|
1238
1239fail:
1240 splx(s);
1241 return;
1242}
1243
1244/*
1245 * Initialize the transmit descriptors.
1246 */
1247static int rl_list_tx_init(sc)
1248 struct rl_softc *sc;
1249{
1250 struct rl_chain_data *cd;
1251 int i;
1252
1253 cd = &sc->rl_cdata;
1254 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1255 cd->rl_tx_chain[i] = NULL;
1256 CSR_WRITE_4(sc,
1257 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000);
1258 }
1259
1260 sc->rl_cdata.cur_tx = 0;
1261 sc->rl_cdata.last_tx = 0;
1262
1263 return(0);
1264}
1265
1266/*
1267 * A frame has been uploaded: pass the resulting mbuf chain up to
1268 * the higher level protocols.
1269 *
1270 * You know there's something wrong with a PCI bus-master chip design
1271 * when you have to use m_devget().
1272 *
1273 * The receive operation is badly documented in the datasheet, so I'll
1274 * attempt to document it here. The driver provides a buffer area and
1275 * places its base address in the RX buffer start address register.
1276 * The chip then begins copying frames into the RX buffer. Each frame
1277 * is preceeded by a 32-bit RX status word which specifies the length
1278 * of the frame and certain other status bits. Each frame (starting with
1279 * the status word) is also 32-bit aligned. The frame length is in the
1280 * first 16 bits of the status word; the lower 15 bits correspond with
1281 * the 'rx status register' mentioned in the datasheet.
1282 *
1283 * Note: to make the Alpha happy, the frame payload needs to be aligned
1284 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
1285 * the ring buffer starting at an address two bytes before the actual
1286 * data location. We can then shave off the first two bytes using m_adj().
1287 * The reason we do this is because m_devget() doesn't let us specify an
1288 * offset into the mbuf storage space, so we have to artificially create
1289 * one. The ring is allocated in such a way that there are a few unused
1290 * bytes of space preceecing it so that it will be safe for us to do the
1291 * 2-byte backstep even if reading from the ring at offset 0.
1292 */
1293static void rl_rxeof(sc)
1294 struct rl_softc *sc;
1295{
1296 struct ether_header *eh;
1297 struct mbuf *m;
1298 struct ifnet *ifp;
1299 int total_len = 0;
1300 u_int32_t rxstat;
1301 caddr_t rxbufpos;
1302 int wrap = 0;
1303 u_int16_t cur_rx;
1304 u_int16_t limit;
1305 u_int16_t rx_bytes = 0, max_bytes;
1306
1307 ifp = &sc->arpcom.ac_if;
1308
1309 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1310
1311 /* Do not try to read past this point. */
1312 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1313
1314 if (limit < cur_rx)
1315 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1316 else
1317 max_bytes = limit - cur_rx;
1318
1319 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1320 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1321 rxstat = *(u_int32_t *)rxbufpos;
1322
1323 /*
1324 * Here's a totally undocumented fact for you. When the
1325 * RealTek chip is in the process of copying a packet into
1326 * RAM for you, the length will be 0xfff0. If you spot a
1327 * packet header with this value, you need to stop. The
1328 * datasheet makes absolutely no mention of this and
1329 * RealTek should be shot for this.
1330 */
1331 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1332 break;
1333
1334 if (!(rxstat & RL_RXSTAT_RXOK)) {
1335 ifp->if_ierrors++;
1336 if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT|
1337 RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR|
1338 RL_RXSTAT_ALIGNERR)) {
1339 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB);
1340 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB|
1341 RL_CMD_RX_ENB);
1342 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1343 CSR_WRITE_4(sc, RL_RXADDR,
1344 vtophys(sc->rl_cdata.rl_rx_buf));
1345 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1346 cur_rx = 0;
1347 }
1348 break;
1349 }
1350
1351 /* No errors; receive the packet. */
1352 total_len = rxstat >> 16;
1353 rx_bytes += total_len + 4;
1354
1355 /*
1356 * XXX The RealTek chip includes the CRC with every
1357 * received frame, and there's no way to turn this
1358 * behavior off (at least, I can't find anything in
1359 * the manual that explains how to do it) so we have
1360 * to trim off the CRC manually.
1361 */
1362 total_len -= ETHER_CRC_LEN;
1363
1364 /*
1365 * Avoid trying to read more bytes than we know
1366 * the chip has prepared for us.
1367 */
1368 if (rx_bytes > max_bytes)
1369 break;
1370
1371 rxbufpos = sc->rl_cdata.rl_rx_buf +
1372 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1373
1374 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1375 rxbufpos = sc->rl_cdata.rl_rx_buf;
1376
1377 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1378
1379 if (total_len > wrap) {
1380 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1381 wrap + RL_ETHER_ALIGN, 0, ifp, NULL);
1382 if (m == NULL) {
1383 ifp->if_ierrors++;
1384 printf("rl%d: out of mbufs, tried to "
1385 "copy %d bytes\n", sc->rl_unit, wrap);
1386 }
1387 else {
1388 m_adj(m, RL_ETHER_ALIGN);
1389 m_copyback(m, wrap, total_len - wrap,
1390 sc->rl_cdata.rl_rx_buf);
1391 }
1392 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1393 } else {
1394 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1395 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1396 if (m == NULL) {
1397 ifp->if_ierrors++;
1398 printf("rl%d: out of mbufs, tried to "
1399 "copy %d bytes\n", sc->rl_unit, total_len);
1400 } else
1401 m_adj(m, RL_ETHER_ALIGN);
1402 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1403 }
1404
1405 /*
1406 * Round up to 32-bit boundary.
1407 */
1408 cur_rx = (cur_rx + 3) & ~3;
1409 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1410
1411 if (m == NULL)
1412 continue;
1413
1414 eh = mtod(m, struct ether_header *);
1415 ifp->if_ipackets++;
1416
1417#if NBPF > 0
1418 /*
1419 * Handle BPF listeners. Let the BPF user see the packet, but
1420 * don't pass it up to the ether_input() layer unless it's
1421 * a broadcast packet, multicast packet, matches our ethernet
1422 * address or the interface is in promiscuous mode.
1423 */
1424 if (ifp->if_bpf) {
1425 bpf_mtap(ifp, m);
1426 if (ifp->if_flags & IFF_PROMISC &&
1427 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1428 ETHER_ADDR_LEN) &&
1429 (eh->ether_dhost[0] & 1) == 0)) {
1430 m_freem(m);
1431 continue;
1432 }
1433 }
1434#endif
1435 /* Remove header from mbuf and pass it on. */
1436 m_adj(m, sizeof(struct ether_header));
1437 ether_input(ifp, eh, m);
1438 }
1439
1440 return;
1441}
1442
1443/*
1444 * A frame was downloaded to the chip. It's safe for us to clean up
1445 * the list buffers.
1446 */
1447static void rl_txeof(sc)
1448 struct rl_softc *sc;
1449{
1450 struct ifnet *ifp;
1451 u_int32_t txstat;
1452
1453 ifp = &sc->arpcom.ac_if;
1454
1455 /* Clear the timeout timer. */
1456 ifp->if_timer = 0;
1457
1458 /*
1459 * Go through our tx list and free mbufs for those
1460 * frames that have been uploaded.
1461 */
1462 do {
1463 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1464 if (!(txstat & (RL_TXSTAT_TX_OK|
1465 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1466 break;
1467
1468 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1469
1470 if (RL_LAST_TXMBUF(sc) != NULL) {
1471 m_freem(RL_LAST_TXMBUF(sc));
1472 RL_LAST_TXMBUF(sc) = NULL;
1473 }
1474 if (txstat & RL_TXSTAT_TX_OK)
1475 ifp->if_opackets++;
1476 else {
1477 ifp->if_oerrors++;
1478 if ((txstat & RL_TXSTAT_TXABRT) ||
1479 (txstat & RL_TXSTAT_OUTOFWIN))
1480 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1481 }
1482 RL_INC(sc->rl_cdata.last_tx);
1483 ifp->if_flags &= ~IFF_OACTIVE;
1484 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1485
1486 if (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) {
1487 if (sc->rl_want_auto)
1488 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1);
1489 }
1490
1491 return;
1492}
1493
1494static void rl_intr(arg)
1495 void *arg;
1496{
1497 struct rl_softc *sc;
1498 struct ifnet *ifp;
1499 u_int16_t status;
1500
1501 sc = arg;
1502 ifp = &sc->arpcom.ac_if;
1503
1504 /* Disable interrupts. */
1505 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1506
1507 for (;;) {
1508
1509 status = CSR_READ_2(sc, RL_ISR);
1510 if (status)
1511 CSR_WRITE_2(sc, RL_ISR, status);
1512
1513 if ((status & RL_INTRS) == 0)
1514 break;
1515
1516 if (status & RL_ISR_RX_OK)
1517 rl_rxeof(sc);
1518
1519 if (status & RL_ISR_RX_ERR)
1520 rl_rxeof(sc);
1521
1522 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1523 rl_txeof(sc);
1524
1525 if (status & RL_ISR_SYSTEM_ERR) {
1526 rl_reset(sc);
1527 rl_init(sc);
1528 }
1529
1530 }
1531
1532 /* Re-enable interrupts. */
1533 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1534
1535 if (ifp->if_snd.ifq_head != NULL) {
1536 rl_start(ifp);
1537 }
1538
1539 return;
1540}
1541
1542/*
1543 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1544 * pointers to the fragment pointers.
1545 */
1546static int rl_encap(sc, m_head)
1547 struct rl_softc *sc;
1548 struct mbuf *m_head;
1549{
1550 struct mbuf *m_new = NULL;
1551
1552 /*
1553 * The RealTek is brain damaged and wants longword-aligned
1554 * TX buffers, plus we can only have one fragment buffer
1555 * per packet. We have to copy pretty much all the time.
1556 */
1557
1558 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1559 if (m_new == NULL) {
1560 printf("rl%d: no memory for tx list", sc->rl_unit);
1561 return(1);
1562 }
1563 if (m_head->m_pkthdr.len > MHLEN) {
1564 MCLGET(m_new, M_DONTWAIT);
1565 if (!(m_new->m_flags & M_EXT)) {
1566 m_freem(m_new);
1567 printf("rl%d: no memory for tx list",
1568 sc->rl_unit);
1569 return(1);
1570 }
1571 }
1572 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1573 mtod(m_new, caddr_t));
1574 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1575 m_freem(m_head);
1576 m_head = m_new;
1577
1578 /* Pad frames to at least 60 bytes. */
1579 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1580 m_head->m_pkthdr.len +=
1581 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1582 m_head->m_len = m_head->m_pkthdr.len;
1583 }
1584
1585 RL_CUR_TXMBUF(sc) = m_head;
1586
1587 return(0);
1588}
1589
1590/*
1591 * Main transmit routine.
1592 */
1593
1594static void rl_start(ifp)
1595 struct ifnet *ifp;
1596{
1597 struct rl_softc *sc;
1598 struct mbuf *m_head = NULL;
1599
1600 sc = ifp->if_softc;
1601
1602 if (sc->rl_autoneg) {
1603 sc->rl_tx_pend = 1;
1604 return;
1605 }
1606
1607 while(RL_CUR_TXMBUF(sc) == NULL) {
1608 IF_DEQUEUE(&ifp->if_snd, m_head);
1609 if (m_head == NULL)
1610 break;
1611
1612 rl_encap(sc, m_head);
1613
1614#if NBPF > 0
1615 /*
1616 * If there's a BPF listener, bounce a copy of this frame
1617 * to him.
1618 */
1619 if (ifp->if_bpf)
1620 bpf_mtap(ifp, RL_CUR_TXMBUF(sc));
1621#endif
1622 /*
1623 * Transmit the frame.
1624 */
1625 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc),
1626 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t)));
1627 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1628 RL_TX_EARLYTHRESH | RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1629
1630 RL_INC(sc->rl_cdata.cur_tx);
1631 }
1632
1633 /*
1634 * We broke out of the loop because all our TX slots are
1635 * full. Mark the NIC as busy until it drains some of the
1636 * packets from the queue.
1637 */
1638 if (RL_CUR_TXMBUF(sc) != NULL)
1639 ifp->if_flags |= IFF_OACTIVE;
1640
1641 /*
1642 * Set a timeout in case the chip goes out to lunch.
1643 */
1644 ifp->if_timer = 5;
1645
1646 return;
1647}
1648
1649static void rl_init(xsc)
1650 void *xsc;
1651{
1652 struct rl_softc *sc = xsc;
1653 struct ifnet *ifp = &sc->arpcom.ac_if;
1654 int s, i;
1655 u_int32_t rxcfg = 0;
1656 u_int16_t phy_bmcr = 0;
1657
1658 if (sc->rl_autoneg)
1659 return;
1660
1661 s = splimp();
1662
1663 /*
1664 * XXX Hack for the 8139: the built-in autoneg logic's state
1665 * gets reset by rl_init() when we don't want it to. Try
1666 * to preserve it. (For 8129 cards with real external PHYs,
1667 * the BMCR register doesn't change, but this doesn't hurt.)
1668 */
1669 if (sc->rl_type == RL_8139)
1670 phy_bmcr = rl_phy_readreg(sc, PHY_BMCR);
1671
1672 /*
1673 * Cancel pending I/O and free all RX/TX buffers.
1674 */
1675 rl_stop(sc);
1676
1677 /* Init our MAC address */
1678 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1679 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
1680 }
1681
1682 /* Init the RX buffer pointer register. */
1683 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf));
1684
1685 /* Init TX descriptors. */
1686 rl_list_tx_init(sc);
1687
1688 /*
1689 * Enable transmit and receive.
1690 */
1691 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1692
1693 /*
1694 * Set the initial TX and RX configuration.
1695 */
1696 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1697 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1698
1699 /* Set the individual bit to receive frames for this host only. */
1700 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1701 rxcfg |= RL_RXCFG_RX_INDIV;
1702
1703 /* If we want promiscuous mode, set the allframes bit. */
1704 if (ifp->if_flags & IFF_PROMISC) {
1705 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1706 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1707 } else {
1708 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1709 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1710 }
1711
1712 /*
1713 * Set capture broadcast bit to capture broadcast frames.
1714 */
1715 if (ifp->if_flags & IFF_BROADCAST) {
1716 rxcfg |= RL_RXCFG_RX_BROAD;
1717 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1718 } else {
1719 rxcfg &= ~RL_RXCFG_RX_BROAD;
1720 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1721 }
1722
1723 /*
1724 * Program the multicast filter, if necessary.
1725 */
1726 rl_setmulti(sc);
1727
1728 /*
1729 * Enable interrupts.
1730 */
1731 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1732
1733 /* Start RX/TX process. */
1734 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1735
1736 /* Enable receiver and transmitter. */
1737 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1738
1739 /* Restore state of BMCR */
1740 if (sc->rl_pinfo != NULL)
1741 rl_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1742
1743 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1744
1745 ifp->if_flags |= IFF_RUNNING;
1746 ifp->if_flags &= ~IFF_OACTIVE;
1747
1748 (void)splx(s);
1749
1750 return;
1751}
1752
1753/*
1754 * Set media options.
1755 */
1756static int rl_ifmedia_upd(ifp)
1757 struct ifnet *ifp;
1758{
1759 struct rl_softc *sc;
1760 struct ifmedia *ifm;
1761
1762 sc = ifp->if_softc;
1763 ifm = &sc->ifmedia;
1764
1765 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1766 return(EINVAL);
1767
1768 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1769 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1);
1770 else
1771 rl_setmode_mii(sc, ifm->ifm_media);
1772
1773 return(0);
1774}
1775
1776/*
1777 * Report current media status.
1778 */
1779static void rl_ifmedia_sts(ifp, ifmr)
1780 struct ifnet *ifp;
1781 struct ifmediareq *ifmr;
1782{
1783 struct rl_softc *sc;
1784 u_int16_t advert = 0, ability = 0;
1785
1786 sc = ifp->if_softc;
1787
1788 if (!(rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1789 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1790 ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
1791 else
1792 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
1793
1794 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1795 ifmr->ifm_active |= IFM_FDX;
1796 else
1797 ifmr->ifm_active |= IFM_HDX;
1798 return;
1799 }
1800
1801 ability = rl_phy_readreg(sc, PHY_LPAR);
1802 advert = rl_phy_readreg(sc, PHY_ANAR);
1803 if (advert & PHY_ANAR_100BT4 &&
1804 ability & PHY_ANAR_100BT4) {
1805 ifmr->ifm_active = IFM_ETHER|IFM_100_T4;
1806 } else if (advert & PHY_ANAR_100BTXFULL &&
1807 ability & PHY_ANAR_100BTXFULL) {
1808 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX;
1809 } else if (advert & PHY_ANAR_100BTXHALF &&
1810 ability & PHY_ANAR_100BTXHALF) {
1811 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX;
1812 } else if (advert & PHY_ANAR_10BTFULL &&
1813 ability & PHY_ANAR_10BTFULL) {
1814 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX;
1815 } else if (advert & PHY_ANAR_10BTHALF &&
1816 ability & PHY_ANAR_10BTHALF) {
1817 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX;
1818 }
1819
1820 return;
1821}
1822
1823static int rl_ioctl(ifp, command, data)
1824 struct ifnet *ifp;
1825 u_long command;
1826 caddr_t data;
1827{
1828 struct rl_softc *sc = ifp->if_softc;
1829 struct ifreq *ifr = (struct ifreq *) data;
1830 int s, error = 0;
1831
1832 s = splimp();
1833
1834 switch(command) {
1835 case SIOCSIFADDR:
1836 case SIOCGIFADDR:
1837 case SIOCSIFMTU:
1838 error = ether_ioctl(ifp, command, data);
1839 break;
1840 case SIOCSIFFLAGS:
1841 if (ifp->if_flags & IFF_UP) {
1842 rl_init(sc);
1843 } else {
1844 if (ifp->if_flags & IFF_RUNNING)
1845 rl_stop(sc);
1846 }
1847 error = 0;
1848 break;
1849 case SIOCADDMULTI:
1850 case SIOCDELMULTI:
1851 rl_setmulti(sc);
1852 error = 0;
1853 break;
1854 case SIOCGIFMEDIA:
1855 case SIOCSIFMEDIA:
1856 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1857 break;
1858 default:
1859 error = EINVAL;
1860 break;
1861 }
1862
1863 (void)splx(s);
1864
1865 return(error);
1866}
1867
1868static void rl_watchdog(ifp)
1869 struct ifnet *ifp;
1870{
1871 struct rl_softc *sc;
1872
1873 sc = ifp->if_softc;
1874
1875 if (sc->rl_autoneg) {
1876 rl_autoneg_mii(sc, RL_FLAG_DELAYTIMEO, 1);
1877 return;
1878 }
1879
1880 printf("rl%d: watchdog timeout\n", sc->rl_unit);
1881 ifp->if_oerrors++;
1882 if (!(rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1883 printf("rl%d: no carrier - transceiver cable problem?\n",
1884 sc->rl_unit);
1885 rl_txeof(sc);
1886 rl_rxeof(sc);
1887 rl_init(sc);
1888
1889 return;
1890}
1891
1892/*
1893 * Stop the adapter and free any mbufs allocated to the
1894 * RX and TX lists.
1895 */
1896static void rl_stop(sc)
1897 struct rl_softc *sc;
1898{
1899 register int i;
1900 struct ifnet *ifp;
1901
1902 ifp = &sc->arpcom.ac_if;
1903 ifp->if_timer = 0;
1904
1905 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1906 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1907
1908 /*
1909 * Free the TX list buffers.
1910 */
1911 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1912 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1913 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1914 sc->rl_cdata.rl_tx_chain[i] = NULL;
1915 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
1916 }
1917 }
1918
1919 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1920
1921 return;
1922}
1923
1924/*
1925 * Stop all chip I/O so that the kernel's probe routines don't
1926 * get confused by errant DMAs when rebooting.
1927 */
| 1239
1240fail:
1241 splx(s);
1242 return;
1243}
1244
1245/*
1246 * Initialize the transmit descriptors.
1247 */
1248static int rl_list_tx_init(sc)
1249 struct rl_softc *sc;
1250{
1251 struct rl_chain_data *cd;
1252 int i;
1253
1254 cd = &sc->rl_cdata;
1255 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1256 cd->rl_tx_chain[i] = NULL;
1257 CSR_WRITE_4(sc,
1258 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000);
1259 }
1260
1261 sc->rl_cdata.cur_tx = 0;
1262 sc->rl_cdata.last_tx = 0;
1263
1264 return(0);
1265}
1266
1267/*
1268 * A frame has been uploaded: pass the resulting mbuf chain up to
1269 * the higher level protocols.
1270 *
1271 * You know there's something wrong with a PCI bus-master chip design
1272 * when you have to use m_devget().
1273 *
1274 * The receive operation is badly documented in the datasheet, so I'll
1275 * attempt to document it here. The driver provides a buffer area and
1276 * places its base address in the RX buffer start address register.
1277 * The chip then begins copying frames into the RX buffer. Each frame
1278 * is preceeded by a 32-bit RX status word which specifies the length
1279 * of the frame and certain other status bits. Each frame (starting with
1280 * the status word) is also 32-bit aligned. The frame length is in the
1281 * first 16 bits of the status word; the lower 15 bits correspond with
1282 * the 'rx status register' mentioned in the datasheet.
1283 *
1284 * Note: to make the Alpha happy, the frame payload needs to be aligned
1285 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
1286 * the ring buffer starting at an address two bytes before the actual
1287 * data location. We can then shave off the first two bytes using m_adj().
1288 * The reason we do this is because m_devget() doesn't let us specify an
1289 * offset into the mbuf storage space, so we have to artificially create
1290 * one. The ring is allocated in such a way that there are a few unused
1291 * bytes of space preceecing it so that it will be safe for us to do the
1292 * 2-byte backstep even if reading from the ring at offset 0.
1293 */
1294static void rl_rxeof(sc)
1295 struct rl_softc *sc;
1296{
1297 struct ether_header *eh;
1298 struct mbuf *m;
1299 struct ifnet *ifp;
1300 int total_len = 0;
1301 u_int32_t rxstat;
1302 caddr_t rxbufpos;
1303 int wrap = 0;
1304 u_int16_t cur_rx;
1305 u_int16_t limit;
1306 u_int16_t rx_bytes = 0, max_bytes;
1307
1308 ifp = &sc->arpcom.ac_if;
1309
1310 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1311
1312 /* Do not try to read past this point. */
1313 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1314
1315 if (limit < cur_rx)
1316 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1317 else
1318 max_bytes = limit - cur_rx;
1319
1320 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1321 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1322 rxstat = *(u_int32_t *)rxbufpos;
1323
1324 /*
1325 * Here's a totally undocumented fact for you. When the
1326 * RealTek chip is in the process of copying a packet into
1327 * RAM for you, the length will be 0xfff0. If you spot a
1328 * packet header with this value, you need to stop. The
1329 * datasheet makes absolutely no mention of this and
1330 * RealTek should be shot for this.
1331 */
1332 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1333 break;
1334
1335 if (!(rxstat & RL_RXSTAT_RXOK)) {
1336 ifp->if_ierrors++;
1337 if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT|
1338 RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR|
1339 RL_RXSTAT_ALIGNERR)) {
1340 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB);
1341 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB|
1342 RL_CMD_RX_ENB);
1343 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1344 CSR_WRITE_4(sc, RL_RXADDR,
1345 vtophys(sc->rl_cdata.rl_rx_buf));
1346 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1347 cur_rx = 0;
1348 }
1349 break;
1350 }
1351
1352 /* No errors; receive the packet. */
1353 total_len = rxstat >> 16;
1354 rx_bytes += total_len + 4;
1355
1356 /*
1357 * XXX The RealTek chip includes the CRC with every
1358 * received frame, and there's no way to turn this
1359 * behavior off (at least, I can't find anything in
1360 * the manual that explains how to do it) so we have
1361 * to trim off the CRC manually.
1362 */
1363 total_len -= ETHER_CRC_LEN;
1364
1365 /*
1366 * Avoid trying to read more bytes than we know
1367 * the chip has prepared for us.
1368 */
1369 if (rx_bytes > max_bytes)
1370 break;
1371
1372 rxbufpos = sc->rl_cdata.rl_rx_buf +
1373 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1374
1375 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1376 rxbufpos = sc->rl_cdata.rl_rx_buf;
1377
1378 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1379
1380 if (total_len > wrap) {
1381 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1382 wrap + RL_ETHER_ALIGN, 0, ifp, NULL);
1383 if (m == NULL) {
1384 ifp->if_ierrors++;
1385 printf("rl%d: out of mbufs, tried to "
1386 "copy %d bytes\n", sc->rl_unit, wrap);
1387 }
1388 else {
1389 m_adj(m, RL_ETHER_ALIGN);
1390 m_copyback(m, wrap, total_len - wrap,
1391 sc->rl_cdata.rl_rx_buf);
1392 }
1393 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1394 } else {
1395 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1396 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1397 if (m == NULL) {
1398 ifp->if_ierrors++;
1399 printf("rl%d: out of mbufs, tried to "
1400 "copy %d bytes\n", sc->rl_unit, total_len);
1401 } else
1402 m_adj(m, RL_ETHER_ALIGN);
1403 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1404 }
1405
1406 /*
1407 * Round up to 32-bit boundary.
1408 */
1409 cur_rx = (cur_rx + 3) & ~3;
1410 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1411
1412 if (m == NULL)
1413 continue;
1414
1415 eh = mtod(m, struct ether_header *);
1416 ifp->if_ipackets++;
1417
1418#if NBPF > 0
1419 /*
1420 * Handle BPF listeners. Let the BPF user see the packet, but
1421 * don't pass it up to the ether_input() layer unless it's
1422 * a broadcast packet, multicast packet, matches our ethernet
1423 * address or the interface is in promiscuous mode.
1424 */
1425 if (ifp->if_bpf) {
1426 bpf_mtap(ifp, m);
1427 if (ifp->if_flags & IFF_PROMISC &&
1428 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1429 ETHER_ADDR_LEN) &&
1430 (eh->ether_dhost[0] & 1) == 0)) {
1431 m_freem(m);
1432 continue;
1433 }
1434 }
1435#endif
1436 /* Remove header from mbuf and pass it on. */
1437 m_adj(m, sizeof(struct ether_header));
1438 ether_input(ifp, eh, m);
1439 }
1440
1441 return;
1442}
1443
1444/*
1445 * A frame was downloaded to the chip. It's safe for us to clean up
1446 * the list buffers.
1447 */
1448static void rl_txeof(sc)
1449 struct rl_softc *sc;
1450{
1451 struct ifnet *ifp;
1452 u_int32_t txstat;
1453
1454 ifp = &sc->arpcom.ac_if;
1455
1456 /* Clear the timeout timer. */
1457 ifp->if_timer = 0;
1458
1459 /*
1460 * Go through our tx list and free mbufs for those
1461 * frames that have been uploaded.
1462 */
1463 do {
1464 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1465 if (!(txstat & (RL_TXSTAT_TX_OK|
1466 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1467 break;
1468
1469 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1470
1471 if (RL_LAST_TXMBUF(sc) != NULL) {
1472 m_freem(RL_LAST_TXMBUF(sc));
1473 RL_LAST_TXMBUF(sc) = NULL;
1474 }
1475 if (txstat & RL_TXSTAT_TX_OK)
1476 ifp->if_opackets++;
1477 else {
1478 ifp->if_oerrors++;
1479 if ((txstat & RL_TXSTAT_TXABRT) ||
1480 (txstat & RL_TXSTAT_OUTOFWIN))
1481 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1482 }
1483 RL_INC(sc->rl_cdata.last_tx);
1484 ifp->if_flags &= ~IFF_OACTIVE;
1485 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1486
1487 if (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) {
1488 if (sc->rl_want_auto)
1489 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1);
1490 }
1491
1492 return;
1493}
1494
1495static void rl_intr(arg)
1496 void *arg;
1497{
1498 struct rl_softc *sc;
1499 struct ifnet *ifp;
1500 u_int16_t status;
1501
1502 sc = arg;
1503 ifp = &sc->arpcom.ac_if;
1504
1505 /* Disable interrupts. */
1506 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1507
1508 for (;;) {
1509
1510 status = CSR_READ_2(sc, RL_ISR);
1511 if (status)
1512 CSR_WRITE_2(sc, RL_ISR, status);
1513
1514 if ((status & RL_INTRS) == 0)
1515 break;
1516
1517 if (status & RL_ISR_RX_OK)
1518 rl_rxeof(sc);
1519
1520 if (status & RL_ISR_RX_ERR)
1521 rl_rxeof(sc);
1522
1523 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1524 rl_txeof(sc);
1525
1526 if (status & RL_ISR_SYSTEM_ERR) {
1527 rl_reset(sc);
1528 rl_init(sc);
1529 }
1530
1531 }
1532
1533 /* Re-enable interrupts. */
1534 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1535
1536 if (ifp->if_snd.ifq_head != NULL) {
1537 rl_start(ifp);
1538 }
1539
1540 return;
1541}
1542
1543/*
1544 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1545 * pointers to the fragment pointers.
1546 */
1547static int rl_encap(sc, m_head)
1548 struct rl_softc *sc;
1549 struct mbuf *m_head;
1550{
1551 struct mbuf *m_new = NULL;
1552
1553 /*
1554 * The RealTek is brain damaged and wants longword-aligned
1555 * TX buffers, plus we can only have one fragment buffer
1556 * per packet. We have to copy pretty much all the time.
1557 */
1558
1559 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1560 if (m_new == NULL) {
1561 printf("rl%d: no memory for tx list", sc->rl_unit);
1562 return(1);
1563 }
1564 if (m_head->m_pkthdr.len > MHLEN) {
1565 MCLGET(m_new, M_DONTWAIT);
1566 if (!(m_new->m_flags & M_EXT)) {
1567 m_freem(m_new);
1568 printf("rl%d: no memory for tx list",
1569 sc->rl_unit);
1570 return(1);
1571 }
1572 }
1573 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1574 mtod(m_new, caddr_t));
1575 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1576 m_freem(m_head);
1577 m_head = m_new;
1578
1579 /* Pad frames to at least 60 bytes. */
1580 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1581 m_head->m_pkthdr.len +=
1582 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1583 m_head->m_len = m_head->m_pkthdr.len;
1584 }
1585
1586 RL_CUR_TXMBUF(sc) = m_head;
1587
1588 return(0);
1589}
1590
1591/*
1592 * Main transmit routine.
1593 */
1594
1595static void rl_start(ifp)
1596 struct ifnet *ifp;
1597{
1598 struct rl_softc *sc;
1599 struct mbuf *m_head = NULL;
1600
1601 sc = ifp->if_softc;
1602
1603 if (sc->rl_autoneg) {
1604 sc->rl_tx_pend = 1;
1605 return;
1606 }
1607
1608 while(RL_CUR_TXMBUF(sc) == NULL) {
1609 IF_DEQUEUE(&ifp->if_snd, m_head);
1610 if (m_head == NULL)
1611 break;
1612
1613 rl_encap(sc, m_head);
1614
1615#if NBPF > 0
1616 /*
1617 * If there's a BPF listener, bounce a copy of this frame
1618 * to him.
1619 */
1620 if (ifp->if_bpf)
1621 bpf_mtap(ifp, RL_CUR_TXMBUF(sc));
1622#endif
1623 /*
1624 * Transmit the frame.
1625 */
1626 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc),
1627 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t)));
1628 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1629 RL_TX_EARLYTHRESH | RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1630
1631 RL_INC(sc->rl_cdata.cur_tx);
1632 }
1633
1634 /*
1635 * We broke out of the loop because all our TX slots are
1636 * full. Mark the NIC as busy until it drains some of the
1637 * packets from the queue.
1638 */
1639 if (RL_CUR_TXMBUF(sc) != NULL)
1640 ifp->if_flags |= IFF_OACTIVE;
1641
1642 /*
1643 * Set a timeout in case the chip goes out to lunch.
1644 */
1645 ifp->if_timer = 5;
1646
1647 return;
1648}
1649
1650static void rl_init(xsc)
1651 void *xsc;
1652{
1653 struct rl_softc *sc = xsc;
1654 struct ifnet *ifp = &sc->arpcom.ac_if;
1655 int s, i;
1656 u_int32_t rxcfg = 0;
1657 u_int16_t phy_bmcr = 0;
1658
1659 if (sc->rl_autoneg)
1660 return;
1661
1662 s = splimp();
1663
1664 /*
1665 * XXX Hack for the 8139: the built-in autoneg logic's state
1666 * gets reset by rl_init() when we don't want it to. Try
1667 * to preserve it. (For 8129 cards with real external PHYs,
1668 * the BMCR register doesn't change, but this doesn't hurt.)
1669 */
1670 if (sc->rl_type == RL_8139)
1671 phy_bmcr = rl_phy_readreg(sc, PHY_BMCR);
1672
1673 /*
1674 * Cancel pending I/O and free all RX/TX buffers.
1675 */
1676 rl_stop(sc);
1677
1678 /* Init our MAC address */
1679 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1680 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
1681 }
1682
1683 /* Init the RX buffer pointer register. */
1684 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf));
1685
1686 /* Init TX descriptors. */
1687 rl_list_tx_init(sc);
1688
1689 /*
1690 * Enable transmit and receive.
1691 */
1692 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1693
1694 /*
1695 * Set the initial TX and RX configuration.
1696 */
1697 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1698 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1699
1700 /* Set the individual bit to receive frames for this host only. */
1701 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1702 rxcfg |= RL_RXCFG_RX_INDIV;
1703
1704 /* If we want promiscuous mode, set the allframes bit. */
1705 if (ifp->if_flags & IFF_PROMISC) {
1706 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1707 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1708 } else {
1709 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1710 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1711 }
1712
1713 /*
1714 * Set capture broadcast bit to capture broadcast frames.
1715 */
1716 if (ifp->if_flags & IFF_BROADCAST) {
1717 rxcfg |= RL_RXCFG_RX_BROAD;
1718 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1719 } else {
1720 rxcfg &= ~RL_RXCFG_RX_BROAD;
1721 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1722 }
1723
1724 /*
1725 * Program the multicast filter, if necessary.
1726 */
1727 rl_setmulti(sc);
1728
1729 /*
1730 * Enable interrupts.
1731 */
1732 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1733
1734 /* Start RX/TX process. */
1735 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1736
1737 /* Enable receiver and transmitter. */
1738 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1739
1740 /* Restore state of BMCR */
1741 if (sc->rl_pinfo != NULL)
1742 rl_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1743
1744 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1745
1746 ifp->if_flags |= IFF_RUNNING;
1747 ifp->if_flags &= ~IFF_OACTIVE;
1748
1749 (void)splx(s);
1750
1751 return;
1752}
1753
1754/*
1755 * Set media options.
1756 */
1757static int rl_ifmedia_upd(ifp)
1758 struct ifnet *ifp;
1759{
1760 struct rl_softc *sc;
1761 struct ifmedia *ifm;
1762
1763 sc = ifp->if_softc;
1764 ifm = &sc->ifmedia;
1765
1766 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1767 return(EINVAL);
1768
1769 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1770 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1);
1771 else
1772 rl_setmode_mii(sc, ifm->ifm_media);
1773
1774 return(0);
1775}
1776
1777/*
1778 * Report current media status.
1779 */
1780static void rl_ifmedia_sts(ifp, ifmr)
1781 struct ifnet *ifp;
1782 struct ifmediareq *ifmr;
1783{
1784 struct rl_softc *sc;
1785 u_int16_t advert = 0, ability = 0;
1786
1787 sc = ifp->if_softc;
1788
1789 if (!(rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1790 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1791 ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
1792 else
1793 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
1794
1795 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1796 ifmr->ifm_active |= IFM_FDX;
1797 else
1798 ifmr->ifm_active |= IFM_HDX;
1799 return;
1800 }
1801
1802 ability = rl_phy_readreg(sc, PHY_LPAR);
1803 advert = rl_phy_readreg(sc, PHY_ANAR);
1804 if (advert & PHY_ANAR_100BT4 &&
1805 ability & PHY_ANAR_100BT4) {
1806 ifmr->ifm_active = IFM_ETHER|IFM_100_T4;
1807 } else if (advert & PHY_ANAR_100BTXFULL &&
1808 ability & PHY_ANAR_100BTXFULL) {
1809 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX;
1810 } else if (advert & PHY_ANAR_100BTXHALF &&
1811 ability & PHY_ANAR_100BTXHALF) {
1812 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX;
1813 } else if (advert & PHY_ANAR_10BTFULL &&
1814 ability & PHY_ANAR_10BTFULL) {
1815 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX;
1816 } else if (advert & PHY_ANAR_10BTHALF &&
1817 ability & PHY_ANAR_10BTHALF) {
1818 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX;
1819 }
1820
1821 return;
1822}
1823
1824static int rl_ioctl(ifp, command, data)
1825 struct ifnet *ifp;
1826 u_long command;
1827 caddr_t data;
1828{
1829 struct rl_softc *sc = ifp->if_softc;
1830 struct ifreq *ifr = (struct ifreq *) data;
1831 int s, error = 0;
1832
1833 s = splimp();
1834
1835 switch(command) {
1836 case SIOCSIFADDR:
1837 case SIOCGIFADDR:
1838 case SIOCSIFMTU:
1839 error = ether_ioctl(ifp, command, data);
1840 break;
1841 case SIOCSIFFLAGS:
1842 if (ifp->if_flags & IFF_UP) {
1843 rl_init(sc);
1844 } else {
1845 if (ifp->if_flags & IFF_RUNNING)
1846 rl_stop(sc);
1847 }
1848 error = 0;
1849 break;
1850 case SIOCADDMULTI:
1851 case SIOCDELMULTI:
1852 rl_setmulti(sc);
1853 error = 0;
1854 break;
1855 case SIOCGIFMEDIA:
1856 case SIOCSIFMEDIA:
1857 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1858 break;
1859 default:
1860 error = EINVAL;
1861 break;
1862 }
1863
1864 (void)splx(s);
1865
1866 return(error);
1867}
1868
1869static void rl_watchdog(ifp)
1870 struct ifnet *ifp;
1871{
1872 struct rl_softc *sc;
1873
1874 sc = ifp->if_softc;
1875
1876 if (sc->rl_autoneg) {
1877 rl_autoneg_mii(sc, RL_FLAG_DELAYTIMEO, 1);
1878 return;
1879 }
1880
1881 printf("rl%d: watchdog timeout\n", sc->rl_unit);
1882 ifp->if_oerrors++;
1883 if (!(rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1884 printf("rl%d: no carrier - transceiver cable problem?\n",
1885 sc->rl_unit);
1886 rl_txeof(sc);
1887 rl_rxeof(sc);
1888 rl_init(sc);
1889
1890 return;
1891}
1892
1893/*
1894 * Stop the adapter and free any mbufs allocated to the
1895 * RX and TX lists.
1896 */
1897static void rl_stop(sc)
1898 struct rl_softc *sc;
1899{
1900 register int i;
1901 struct ifnet *ifp;
1902
1903 ifp = &sc->arpcom.ac_if;
1904 ifp->if_timer = 0;
1905
1906 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1907 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1908
1909 /*
1910 * Free the TX list buffers.
1911 */
1912 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1913 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1914 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1915 sc->rl_cdata.rl_tx_chain[i] = NULL;
1916 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
1917 }
1918 }
1919
1920 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1921
1922 return;
1923}
1924
1925/*
1926 * Stop all chip I/O so that the kernel's probe routines don't
1927 * get confused by errant DMAs when rebooting.
1928 */
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