169 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
170 "Planex FNW-3800-TX" },
171 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
172 "Compaq HNE-300" },
173 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
174 "LevelOne FPC-0106TX" },
175 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
176 "Edimax EP-4103DL CardBus" },
177 { 0, 0, 0, NULL }
178};
179
180static int rl_attach(device_t);
181static int rl_detach(device_t);
182static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int);
183static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int);
184static void rl_eeprom_putbyte(struct rl_softc *, int);
185static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
186static int rl_encap(struct rl_softc *, struct mbuf * );
187static int rl_list_tx_init(struct rl_softc *);
188static int rl_ifmedia_upd(struct ifnet *);
189static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
190static int rl_ioctl(struct ifnet *, u_long, caddr_t);
191static void rl_intr(void *);
192static void rl_init(void *);
193static void rl_init_locked(struct rl_softc *sc);
194static void rl_mii_send(struct rl_softc *, uint32_t, int);
195static void rl_mii_sync(struct rl_softc *);
196static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
197static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
198static int rl_miibus_readreg(device_t, int, int);
199static void rl_miibus_statchg(device_t);
200static int rl_miibus_writereg(device_t, int, int, int);
201#ifdef DEVICE_POLLING
202static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
203static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
204#endif
205static int rl_probe(device_t);
206static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
207static void rl_reset(struct rl_softc *);
208static int rl_resume(device_t);
209static void rl_rxeof(struct rl_softc *);
210static void rl_setmulti(struct rl_softc *);
211static int rl_shutdown(device_t);
212static void rl_start(struct ifnet *);
213static void rl_start_locked(struct ifnet *);
214static void rl_stop(struct rl_softc *);
215static int rl_suspend(device_t);
216static void rl_tick(void *);
217static void rl_txeof(struct rl_softc *);
218static void rl_watchdog(struct rl_softc *);
219
220#ifdef RL_USEIOSPACE
221#define RL_RES SYS_RES_IOPORT
222#define RL_RID RL_PCI_LOIO
223#else
224#define RL_RES SYS_RES_MEMORY
225#define RL_RID RL_PCI_LOMEM
226#endif
227
228static device_method_t rl_methods[] = {
229 /* Device interface */
230 DEVMETHOD(device_probe, rl_probe),
231 DEVMETHOD(device_attach, rl_attach),
232 DEVMETHOD(device_detach, rl_detach),
233 DEVMETHOD(device_suspend, rl_suspend),
234 DEVMETHOD(device_resume, rl_resume),
235 DEVMETHOD(device_shutdown, rl_shutdown),
236
237 /* bus interface */
238 DEVMETHOD(bus_print_child, bus_generic_print_child),
239 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
240
241 /* MII interface */
242 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
243 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
244 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
245
246 { 0, 0 }
247};
248
249static driver_t rl_driver = {
250 "rl",
251 rl_methods,
252 sizeof(struct rl_softc)
253};
254
255static devclass_t rl_devclass;
256
257DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
258DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
259DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
260
261#define EE_SET(x) \
262 CSR_WRITE_1(sc, RL_EECMD, \
263 CSR_READ_1(sc, RL_EECMD) | x)
264
265#define EE_CLR(x) \
266 CSR_WRITE_1(sc, RL_EECMD, \
267 CSR_READ_1(sc, RL_EECMD) & ~x)
268
269static void
270rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
271{
272 struct rl_softc *sc = arg;
273
274 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
275}
276
277static void
278rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
279{
280 struct rl_softc *sc = arg;
281
282 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
283}
284
285/*
286 * Send a read command and address to the EEPROM, check for ACK.
287 */
288static void
289rl_eeprom_putbyte(struct rl_softc *sc, int addr)
290{
291 register int d, i;
292
293 d = addr | sc->rl_eecmd_read;
294
295 /*
296 * Feed in each bit and strobe the clock.
297 */
298 for (i = 0x400; i; i >>= 1) {
299 if (d & i) {
300 EE_SET(RL_EE_DATAIN);
301 } else {
302 EE_CLR(RL_EE_DATAIN);
303 }
304 DELAY(100);
305 EE_SET(RL_EE_CLK);
306 DELAY(150);
307 EE_CLR(RL_EE_CLK);
308 DELAY(100);
309 }
310}
311
312/*
313 * Read a word of data stored in the EEPROM at address 'addr.'
314 */
315static void
316rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
317{
318 register int i;
319 uint16_t word = 0;
320
321 /* Enter EEPROM access mode. */
322 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
323
324 /*
325 * Send address of word we want to read.
326 */
327 rl_eeprom_putbyte(sc, addr);
328
329 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
330
331 /*
332 * Start reading bits from EEPROM.
333 */
334 for (i = 0x8000; i; i >>= 1) {
335 EE_SET(RL_EE_CLK);
336 DELAY(100);
337 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
338 word |= i;
339 EE_CLR(RL_EE_CLK);
340 DELAY(100);
341 }
342
343 /* Turn off EEPROM access mode. */
344 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
345
346 *dest = word;
347}
348
349/*
350 * Read a sequence of words from the EEPROM.
351 */
352static void
353rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
354{
355 int i;
356 uint16_t word = 0, *ptr;
357
358 for (i = 0; i < cnt; i++) {
359 rl_eeprom_getword(sc, off + i, &word);
360 ptr = (uint16_t *)(dest + (i * 2));
361 if (swap)
362 *ptr = ntohs(word);
363 else
364 *ptr = word;
365 }
366}
367
368/*
369 * MII access routines are provided for the 8129, which
370 * doesn't have a built-in PHY. For the 8139, we fake things
371 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
372 * direct access PHY registers.
373 */
374#define MII_SET(x) \
375 CSR_WRITE_1(sc, RL_MII, \
376 CSR_READ_1(sc, RL_MII) | (x))
377
378#define MII_CLR(x) \
379 CSR_WRITE_1(sc, RL_MII, \
380 CSR_READ_1(sc, RL_MII) & ~(x))
381
382/*
383 * Sync the PHYs by setting data bit and strobing the clock 32 times.
384 */
385static void
386rl_mii_sync(struct rl_softc *sc)
387{
388 register int i;
389
390 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
391
392 for (i = 0; i < 32; i++) {
393 MII_SET(RL_MII_CLK);
394 DELAY(1);
395 MII_CLR(RL_MII_CLK);
396 DELAY(1);
397 }
398}
399
400/*
401 * Clock a series of bits through the MII.
402 */
403static void
404rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
405{
406 int i;
407
408 MII_CLR(RL_MII_CLK);
409
410 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
411 if (bits & i) {
412 MII_SET(RL_MII_DATAOUT);
413 } else {
414 MII_CLR(RL_MII_DATAOUT);
415 }
416 DELAY(1);
417 MII_CLR(RL_MII_CLK);
418 DELAY(1);
419 MII_SET(RL_MII_CLK);
420 }
421}
422
423/*
424 * Read an PHY register through the MII.
425 */
426static int
427rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
428{
429 int i, ack;
430
431 /* Set up frame for RX. */
432 frame->mii_stdelim = RL_MII_STARTDELIM;
433 frame->mii_opcode = RL_MII_READOP;
434 frame->mii_turnaround = 0;
435 frame->mii_data = 0;
436
437 CSR_WRITE_2(sc, RL_MII, 0);
438
439 /* Turn on data xmit. */
440 MII_SET(RL_MII_DIR);
441
442 rl_mii_sync(sc);
443
444 /* Send command/address info. */
445 rl_mii_send(sc, frame->mii_stdelim, 2);
446 rl_mii_send(sc, frame->mii_opcode, 2);
447 rl_mii_send(sc, frame->mii_phyaddr, 5);
448 rl_mii_send(sc, frame->mii_regaddr, 5);
449
450 /* Idle bit */
451 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
452 DELAY(1);
453 MII_SET(RL_MII_CLK);
454 DELAY(1);
455
456 /* Turn off xmit. */
457 MII_CLR(RL_MII_DIR);
458
459 /* Check for ack */
460 MII_CLR(RL_MII_CLK);
461 DELAY(1);
462 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
463 MII_SET(RL_MII_CLK);
464 DELAY(1);
465
466 /*
467 * Now try reading data bits. If the ack failed, we still
468 * need to clock through 16 cycles to keep the PHY(s) in sync.
469 */
470 if (ack) {
471 for(i = 0; i < 16; i++) {
472 MII_CLR(RL_MII_CLK);
473 DELAY(1);
474 MII_SET(RL_MII_CLK);
475 DELAY(1);
476 }
477 goto fail;
478 }
479
480 for (i = 0x8000; i; i >>= 1) {
481 MII_CLR(RL_MII_CLK);
482 DELAY(1);
483 if (!ack) {
484 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
485 frame->mii_data |= i;
486 DELAY(1);
487 }
488 MII_SET(RL_MII_CLK);
489 DELAY(1);
490 }
491
492fail:
493 MII_CLR(RL_MII_CLK);
494 DELAY(1);
495 MII_SET(RL_MII_CLK);
496 DELAY(1);
497
498 return (ack ? 1 : 0);
499}
500
501/*
502 * Write to a PHY register through the MII.
503 */
504static int
505rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
506{
507
508 /* Set up frame for TX. */
509 frame->mii_stdelim = RL_MII_STARTDELIM;
510 frame->mii_opcode = RL_MII_WRITEOP;
511 frame->mii_turnaround = RL_MII_TURNAROUND;
512
513 /* Turn on data output. */
514 MII_SET(RL_MII_DIR);
515
516 rl_mii_sync(sc);
517
518 rl_mii_send(sc, frame->mii_stdelim, 2);
519 rl_mii_send(sc, frame->mii_opcode, 2);
520 rl_mii_send(sc, frame->mii_phyaddr, 5);
521 rl_mii_send(sc, frame->mii_regaddr, 5);
522 rl_mii_send(sc, frame->mii_turnaround, 2);
523 rl_mii_send(sc, frame->mii_data, 16);
524
525 /* Idle bit. */
526 MII_SET(RL_MII_CLK);
527 DELAY(1);
528 MII_CLR(RL_MII_CLK);
529 DELAY(1);
530
531 /* Turn off xmit. */
532 MII_CLR(RL_MII_DIR);
533
534 return (0);
535}
536
537static int
538rl_miibus_readreg(device_t dev, int phy, int reg)
539{
540 struct rl_softc *sc;
541 struct rl_mii_frame frame;
542 uint16_t rval = 0;
543 uint16_t rl8139_reg = 0;
544
545 sc = device_get_softc(dev);
546
547 if (sc->rl_type == RL_8139) {
548 /* Pretend the internal PHY is only at address 0 */
549 if (phy) {
550 return (0);
551 }
552 switch (reg) {
553 case MII_BMCR:
554 rl8139_reg = RL_BMCR;
555 break;
556 case MII_BMSR:
557 rl8139_reg = RL_BMSR;
558 break;
559 case MII_ANAR:
560 rl8139_reg = RL_ANAR;
561 break;
562 case MII_ANER:
563 rl8139_reg = RL_ANER;
564 break;
565 case MII_ANLPAR:
566 rl8139_reg = RL_LPAR;
567 break;
568 case MII_PHYIDR1:
569 case MII_PHYIDR2:
570 return (0);
571 /*
572 * Allow the rlphy driver to read the media status
573 * register. If we have a link partner which does not
574 * support NWAY, this is the register which will tell
575 * us the results of parallel detection.
576 */
577 case RL_MEDIASTAT:
578 rval = CSR_READ_1(sc, RL_MEDIASTAT);
579 return (rval);
580 default:
581 device_printf(sc->rl_dev, "bad phy register\n");
582 return (0);
583 }
584 rval = CSR_READ_2(sc, rl8139_reg);
585 return (rval);
586 }
587
588 bzero((char *)&frame, sizeof(frame));
589 frame.mii_phyaddr = phy;
590 frame.mii_regaddr = reg;
591 rl_mii_readreg(sc, &frame);
592
593 return (frame.mii_data);
594}
595
596static int
597rl_miibus_writereg(device_t dev, int phy, int reg, int data)
598{
599 struct rl_softc *sc;
600 struct rl_mii_frame frame;
601 uint16_t rl8139_reg = 0;
602
603 sc = device_get_softc(dev);
604
605 if (sc->rl_type == RL_8139) {
606 /* Pretend the internal PHY is only at address 0 */
607 if (phy) {
608 return (0);
609 }
610 switch (reg) {
611 case MII_BMCR:
612 rl8139_reg = RL_BMCR;
613 break;
614 case MII_BMSR:
615 rl8139_reg = RL_BMSR;
616 break;
617 case MII_ANAR:
618 rl8139_reg = RL_ANAR;
619 break;
620 case MII_ANER:
621 rl8139_reg = RL_ANER;
622 break;
623 case MII_ANLPAR:
624 rl8139_reg = RL_LPAR;
625 break;
626 case MII_PHYIDR1:
627 case MII_PHYIDR2:
628 return (0);
629 break;
630 default:
631 device_printf(sc->rl_dev, "bad phy register\n");
632 return (0);
633 }
634 CSR_WRITE_2(sc, rl8139_reg, data);
635 return (0);
636 }
637
638 bzero((char *)&frame, sizeof(frame));
639 frame.mii_phyaddr = phy;
640 frame.mii_regaddr = reg;
641 frame.mii_data = data;
642 rl_mii_writereg(sc, &frame);
643
644 return (0);
645}
646
647static void
648rl_miibus_statchg(device_t dev)
649{
650}
651
652/*
653 * Program the 64-bit multicast hash filter.
654 */
655static void
656rl_setmulti(struct rl_softc *sc)
657{
658 struct ifnet *ifp = sc->rl_ifp;
659 int h = 0;
660 uint32_t hashes[2] = { 0, 0 };
661 struct ifmultiaddr *ifma;
662 uint32_t rxfilt;
663 int mcnt = 0;
664
665 RL_LOCK_ASSERT(sc);
666
667 rxfilt = CSR_READ_4(sc, RL_RXCFG);
668
669 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
670 rxfilt |= RL_RXCFG_RX_MULTI;
671 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
672 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
673 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
674 return;
675 }
676
677 /* first, zot all the existing hash bits */
678 CSR_WRITE_4(sc, RL_MAR0, 0);
679 CSR_WRITE_4(sc, RL_MAR4, 0);
680
681 /* now program new ones */
682 IF_ADDR_LOCK(ifp);
683 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
684 if (ifma->ifma_addr->sa_family != AF_LINK)
685 continue;
686 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
687 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
688 if (h < 32)
689 hashes[0] |= (1 << h);
690 else
691 hashes[1] |= (1 << (h - 32));
692 mcnt++;
693 }
694 IF_ADDR_UNLOCK(ifp);
695
696 if (mcnt)
697 rxfilt |= RL_RXCFG_RX_MULTI;
698 else
699 rxfilt &= ~RL_RXCFG_RX_MULTI;
700
701 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
702 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
703 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
704}
705
706static void
707rl_reset(struct rl_softc *sc)
708{
709 register int i;
710
711 RL_LOCK_ASSERT(sc);
712
713 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
714
715 for (i = 0; i < RL_TIMEOUT; i++) {
716 DELAY(10);
717 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
718 break;
719 }
720 if (i == RL_TIMEOUT)
721 device_printf(sc->rl_dev, "reset never completed!\n");
722}
723
724/*
725 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
726 * IDs against our list and return a device name if we find a match.
727 */
728static int
729rl_probe(device_t dev)
730{
731 struct rl_softc *sc;
732 struct rl_type *t = rl_devs;
733 int rid;
734 uint32_t hwrev;
735
736 sc = device_get_softc(dev);
737
738 while (t->rl_name != NULL) {
739 if ((pci_get_vendor(dev) == t->rl_vid) &&
740 (pci_get_device(dev) == t->rl_did)) {
741 /*
742 * Temporarily map the I/O space
743 * so we can read the chip ID register.
744 */
745 rid = RL_RID;
746 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
747 RF_ACTIVE);
748 if (sc->rl_res == NULL) {
749 device_printf(dev,
750 "couldn't map ports/memory\n");
751 return (ENXIO);
752 }
753 sc->rl_btag = rman_get_bustag(sc->rl_res);
754 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
755
756 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
757 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
758
759 /* Don't attach to 8139C+ or 8169/8110 chips. */
760 if (hwrev == RL_HWREV_8139CPLUS ||
761 (hwrev == RL_HWREV_8169 &&
762 t->rl_did == RT_DEVICEID_8169) ||
763 hwrev == RL_HWREV_8169S ||
764 hwrev == RL_HWREV_8110S) {
765 t++;
766 continue;
767 }
768
769 device_set_desc(dev, t->rl_name);
770 return (BUS_PROBE_DEFAULT);
771 }
772 t++;
773 }
774
775 return (ENXIO);
776}
777
778/*
779 * Attach the interface. Allocate softc structures, do ifmedia
780 * setup and ethernet/BPF attach.
781 */
782static int
783rl_attach(device_t dev)
784{
785 uint8_t eaddr[ETHER_ADDR_LEN];
786 uint16_t as[3];
787 struct ifnet *ifp;
788 struct rl_softc *sc;
789 struct rl_type *t;
790 int error = 0, i, rid;
791 int unit;
792 uint16_t rl_did = 0;
793
794 sc = device_get_softc(dev);
795 unit = device_get_unit(dev);
796 sc->rl_dev = dev;
797
798 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
799 MTX_DEF);
800 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
801
802 pci_enable_busmaster(dev);
803
804 /* Map control/status registers. */
805 rid = RL_RID;
806 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
807
808 if (sc->rl_res == NULL) {
809 device_printf(dev, "couldn't map ports/memory\n");
810 error = ENXIO;
811 goto fail;
812 }
813
814#ifdef notdef
815 /*
816 * Detect the Realtek 8139B. For some reason, this chip is very
817 * unstable when left to autoselect the media
818 * The best workaround is to set the device to the required
819 * media type or to set it to the 10 Meg speed.
820 */
821 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
822 device_printf(dev,
823"Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
824#endif
825
826 sc->rl_btag = rman_get_bustag(sc->rl_res);
827 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
828
829 /* Allocate interrupt */
830 rid = 0;
831 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
832 RF_SHAREABLE | RF_ACTIVE);
833
834 if (sc->rl_irq[0] == NULL) {
835 device_printf(dev, "couldn't map interrupt\n");
836 error = ENXIO;
837 goto fail;
838 }
839
840 /*
841 * Reset the adapter. Only take the lock here as it's needed in
842 * order to call rl_reset().
843 */
844 RL_LOCK(sc);
845 rl_reset(sc);
846 RL_UNLOCK(sc);
847
848 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
849 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
850 if (rl_did != 0x8129)
851 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
852
853 /*
854 * Get station address from the EEPROM.
855 */
856 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
857 for (i = 0; i < 3; i++) {
858 eaddr[(i * 2) + 0] = as[i] & 0xff;
859 eaddr[(i * 2) + 1] = as[i] >> 8;
860 }
861
862 /*
863 * Now read the exact device type from the EEPROM to find
864 * out if it's an 8129 or 8139.
865 */
866 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
867
868 t = rl_devs;
869 sc->rl_type = 0;
870 while(t->rl_name != NULL) {
871 if (rl_did == t->rl_did) {
872 sc->rl_type = t->rl_basetype;
873 break;
874 }
875 t++;
876 }
877
878 if (sc->rl_type == 0) {
879 device_printf(dev, "unknown device ID: %x\n", rl_did);
880 error = ENXIO;
881 goto fail;
882 }
883
884 /*
885 * Allocate the parent bus DMA tag appropriate for PCI.
886 */
887#define RL_NSEG_NEW 32
888 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
889 1, 0, /* alignment, boundary */
890 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
891 BUS_SPACE_MAXADDR, /* highaddr */
892 NULL, NULL, /* filter, filterarg */
893 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
894 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
895 BUS_DMA_ALLOCNOW, /* flags */
896 NULL, NULL, /* lockfunc, lockarg */
897 &sc->rl_parent_tag);
898 if (error)
899 goto fail;
900
901 /*
902 * Now allocate a tag for the DMA descriptor lists.
903 * All of our lists are allocated as a contiguous block
904 * of memory.
905 */
906 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
907 1, 0, /* alignment, boundary */
908 BUS_SPACE_MAXADDR, /* lowaddr */
909 BUS_SPACE_MAXADDR, /* highaddr */
910 NULL, NULL, /* filter, filterarg */
911 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */
912 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
913 BUS_DMA_ALLOCNOW, /* flags */
914 NULL, NULL, /* lockfunc, lockarg */
915 &sc->rl_tag);
916 if (error)
917 goto fail;
918
919 /*
920 * Now allocate a chunk of DMA-able memory based on the
921 * tag we just created.
922 */
923 error = bus_dmamem_alloc(sc->rl_tag,
924 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
925 &sc->rl_cdata.rl_rx_dmamap);
926 if (error) {
927 device_printf(dev, "no memory for list buffers!\n");
928 bus_dma_tag_destroy(sc->rl_tag);
929 sc->rl_tag = NULL;
930 goto fail;
931 }
932
933 /* Leave a few bytes before the start of the RX ring buffer. */
934 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
935 sc->rl_cdata.rl_rx_buf += sizeof(uint64_t);
936
937 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
938 if (ifp == NULL) {
939 device_printf(dev, "can not if_alloc()\n");
940 error = ENOSPC;
941 goto fail;
942 }
943
944 /* Do MII setup */
945 if (mii_phy_probe(dev, &sc->rl_miibus,
946 rl_ifmedia_upd, rl_ifmedia_sts)) {
947 device_printf(dev, "MII without any phy!\n");
948 error = ENXIO;
949 goto fail;
950 }
951
952 ifp->if_softc = sc;
953 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
954 ifp->if_mtu = ETHERMTU;
955 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
956 ifp->if_ioctl = rl_ioctl;
957 ifp->if_start = rl_start;
958 ifp->if_init = rl_init;
959 ifp->if_capabilities = IFCAP_VLAN_MTU;
960 ifp->if_capenable = ifp->if_capabilities;
961#ifdef DEVICE_POLLING
962 ifp->if_capabilities |= IFCAP_POLLING;
963#endif
964 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
965 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
966 IFQ_SET_READY(&ifp->if_snd);
967
968 /*
969 * Call MI attach routine.
970 */
971 ether_ifattach(ifp, eaddr);
972
973 /* Hook interrupt last to avoid having to lock softc */
974 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
975 NULL, rl_intr, sc, &sc->rl_intrhand[0]);
976 if (error) {
977 device_printf(sc->rl_dev, "couldn't set up irq\n");
978 ether_ifdetach(ifp);
979 }
980
981fail:
982 if (error)
983 rl_detach(dev);
984
985 return (error);
986}
987
988/*
989 * Shutdown hardware and free up resources. This can be called any
990 * time after the mutex has been initialized. It is called in both
991 * the error case in attach and the normal detach case so it needs
992 * to be careful about only freeing resources that have actually been
993 * allocated.
994 */
995static int
996rl_detach(device_t dev)
997{
998 struct rl_softc *sc;
999 struct ifnet *ifp;
1000
1001 sc = device_get_softc(dev);
1002 ifp = sc->rl_ifp;
1003
1004 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
1005
1006#ifdef DEVICE_POLLING
1007 if (ifp->if_capenable & IFCAP_POLLING)
1008 ether_poll_deregister(ifp);
1009#endif
1010 /* These should only be active if attach succeeded */
1011 if (device_is_attached(dev)) {
1012 RL_LOCK(sc);
1013 rl_stop(sc);
1014 RL_UNLOCK(sc);
1015 callout_drain(&sc->rl_stat_callout);
1016 ether_ifdetach(ifp);
1017 }
1018#if 0
1019 sc->suspended = 1;
1020#endif
1021 if (sc->rl_miibus)
1022 device_delete_child(dev, sc->rl_miibus);
1023 bus_generic_detach(dev);
1024
1025 if (sc->rl_intrhand[0])
1026 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1027 if (sc->rl_irq[0])
1028 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
1029 if (sc->rl_res)
1030 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1031
1032 if (ifp)
1033 if_free(ifp);
1034
1035 if (sc->rl_tag) {
1036 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1037 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
1038 sc->rl_cdata.rl_rx_dmamap);
1039 bus_dma_tag_destroy(sc->rl_tag);
1040 }
1041 if (sc->rl_parent_tag)
1042 bus_dma_tag_destroy(sc->rl_parent_tag);
1043
1044 mtx_destroy(&sc->rl_mtx);
1045
1046 return (0);
1047}
1048
1049/*
1050 * Initialize the transmit descriptors.
1051 */
1052static int
1053rl_list_tx_init(struct rl_softc *sc)
1054{
1055 struct rl_chain_data *cd;
1056 int i;
1057
1058 RL_LOCK_ASSERT(sc);
1059
1060 cd = &sc->rl_cdata;
1061 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1062 cd->rl_tx_chain[i] = NULL;
1063 CSR_WRITE_4(sc,
1064 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1065 }
1066
1067 sc->rl_cdata.cur_tx = 0;
1068 sc->rl_cdata.last_tx = 0;
1069
1070 return (0);
1071}
1072
1073/*
1074 * A frame has been uploaded: pass the resulting mbuf chain up to
1075 * the higher level protocols.
1076 *
1077 * You know there's something wrong with a PCI bus-master chip design
1078 * when you have to use m_devget().
1079 *
1080 * The receive operation is badly documented in the datasheet, so I'll
1081 * attempt to document it here. The driver provides a buffer area and
1082 * places its base address in the RX buffer start address register.
1083 * The chip then begins copying frames into the RX buffer. Each frame
1084 * is preceded by a 32-bit RX status word which specifies the length
1085 * of the frame and certain other status bits. Each frame (starting with
1086 * the status word) is also 32-bit aligned. The frame length is in the
1087 * first 16 bits of the status word; the lower 15 bits correspond with
1088 * the 'rx status register' mentioned in the datasheet.
1089 *
1090 * Note: to make the Alpha happy, the frame payload needs to be aligned
1091 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1092 * as the offset argument to m_devget().
1093 */
1094static void
1095rl_rxeof(struct rl_softc *sc)
1096{
1097 struct mbuf *m;
1098 struct ifnet *ifp = sc->rl_ifp;
1099 uint8_t *rxbufpos;
1100 int total_len = 0;
1101 int wrap = 0;
1102 uint32_t rxstat;
1103 uint16_t cur_rx;
1104 uint16_t limit;
1105 uint16_t max_bytes, rx_bytes = 0;
1106
1107 RL_LOCK_ASSERT(sc);
1108
1109 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1110 BUS_DMASYNC_POSTREAD);
1111
1112 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1113
1114 /* Do not try to read past this point. */
1115 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1116
1117 if (limit < cur_rx)
1118 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1119 else
1120 max_bytes = limit - cur_rx;
1121
1122 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1123#ifdef DEVICE_POLLING
1124 if (ifp->if_capenable & IFCAP_POLLING) {
1125 if (sc->rxcycles <= 0)
1126 break;
1127 sc->rxcycles--;
1128 }
1129#endif
1130 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1131 rxstat = le32toh(*(uint32_t *)rxbufpos);
1132
1133 /*
1134 * Here's a totally undocumented fact for you. When the
1135 * RealTek chip is in the process of copying a packet into
1136 * RAM for you, the length will be 0xfff0. If you spot a
1137 * packet header with this value, you need to stop. The
1138 * datasheet makes absolutely no mention of this and
1139 * RealTek should be shot for this.
1140 */
1141 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1142 break;
1143
1144 if (!(rxstat & RL_RXSTAT_RXOK)) {
1145 ifp->if_ierrors++;
1146 rl_init_locked(sc);
1147 return;
1148 }
1149
1150 /* No errors; receive the packet. */
1151 total_len = rxstat >> 16;
1152 rx_bytes += total_len + 4;
1153
1154 /*
1155 * XXX The RealTek chip includes the CRC with every
1156 * received frame, and there's no way to turn this
1157 * behavior off (at least, I can't find anything in
1158 * the manual that explains how to do it) so we have
1159 * to trim off the CRC manually.
1160 */
1161 total_len -= ETHER_CRC_LEN;
1162
1163 /*
1164 * Avoid trying to read more bytes than we know
1165 * the chip has prepared for us.
1166 */
1167 if (rx_bytes > max_bytes)
1168 break;
1169
1170 rxbufpos = sc->rl_cdata.rl_rx_buf +
1171 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1172 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1173 rxbufpos = sc->rl_cdata.rl_rx_buf;
1174
1175 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1176 if (total_len > wrap) {
1177 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1178 NULL);
1179 if (m == NULL) {
1180 ifp->if_ierrors++;
1181 } else {
1182 m_copyback(m, wrap, total_len - wrap,
1183 sc->rl_cdata.rl_rx_buf);
1184 }
1185 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1186 } else {
1187 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1188 NULL);
1189 if (m == NULL)
1190 ifp->if_ierrors++;
1191 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1192 }
1193
1194 /* Round up to 32-bit boundary. */
1195 cur_rx = (cur_rx + 3) & ~3;
1196 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1197
1198 if (m == NULL)
1199 continue;
1200
1201 ifp->if_ipackets++;
1202 RL_UNLOCK(sc);
1203 (*ifp->if_input)(ifp, m);
1204 RL_LOCK(sc);
1205 }
1206}
1207
1208/*
1209 * A frame was downloaded to the chip. It's safe for us to clean up
1210 * the list buffers.
1211 */
1212static void
1213rl_txeof(struct rl_softc *sc)
1214{
1215 struct ifnet *ifp = sc->rl_ifp;
1216 uint32_t txstat;
1217
1218 RL_LOCK_ASSERT(sc);
1219
1220 /*
1221 * Go through our tx list and free mbufs for those
1222 * frames that have been uploaded.
1223 */
1224 do {
1225 if (RL_LAST_TXMBUF(sc) == NULL)
1226 break;
1227 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1228 if (!(txstat & (RL_TXSTAT_TX_OK|
1229 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1230 break;
1231
1232 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1233
1234 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1235 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1236 m_freem(RL_LAST_TXMBUF(sc));
1237 RL_LAST_TXMBUF(sc) = NULL;
1238 /*
1239 * If there was a transmit underrun, bump the TX threshold.
1240 * Make sure not to overflow the 63 * 32byte we can address
1241 * with the 6 available bit.
1242 */
1243 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1244 (sc->rl_txthresh < 2016))
1245 sc->rl_txthresh += 32;
1246 if (txstat & RL_TXSTAT_TX_OK)
1247 ifp->if_opackets++;
1248 else {
1249 int oldthresh;
1250 ifp->if_oerrors++;
1251 if ((txstat & RL_TXSTAT_TXABRT) ||
1252 (txstat & RL_TXSTAT_OUTOFWIN))
1253 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1254 oldthresh = sc->rl_txthresh;
1255 /* error recovery */
1256 rl_reset(sc);
1257 rl_init_locked(sc);
1258 /* restore original threshold */
1259 sc->rl_txthresh = oldthresh;
1260 return;
1261 }
1262 RL_INC(sc->rl_cdata.last_tx);
1263 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1264 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1265
1266 if (RL_LAST_TXMBUF(sc) == NULL)
1267 sc->rl_watchdog_timer = 0;
1268 else if (sc->rl_watchdog_timer == 0)
1269 sc->rl_watchdog_timer = 5;
1270}
1271
1272static void
1273rl_tick(void *xsc)
1274{
1275 struct rl_softc *sc = xsc;
1276 struct mii_data *mii;
1277
1278 RL_LOCK_ASSERT(sc);
1279 mii = device_get_softc(sc->rl_miibus);
1280 mii_tick(mii);
1281
1282 rl_watchdog(sc);
1283
1284 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1285}
1286
1287#ifdef DEVICE_POLLING
1288static void
1289rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1290{
1291 struct rl_softc *sc = ifp->if_softc;
1292
1293 RL_LOCK(sc);
1294 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1295 rl_poll_locked(ifp, cmd, count);
1296 RL_UNLOCK(sc);
1297}
1298
1299static void
1300rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1301{
1302 struct rl_softc *sc = ifp->if_softc;
1303
1304 RL_LOCK_ASSERT(sc);
1305
1306 sc->rxcycles = count;
1307 rl_rxeof(sc);
1308 rl_txeof(sc);
1309
1310 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1311 rl_start_locked(ifp);
1312
1313 if (cmd == POLL_AND_CHECK_STATUS) {
1314 uint16_t status;
1315
1316 /* We should also check the status register. */
1317 status = CSR_READ_2(sc, RL_ISR);
1318 if (status == 0xffff)
1319 return;
1320 if (status != 0)
1321 CSR_WRITE_2(sc, RL_ISR, status);
1322
1323 /* XXX We should check behaviour on receiver stalls. */
1324
1325 if (status & RL_ISR_SYSTEM_ERR) {
1326 rl_reset(sc);
1327 rl_init_locked(sc);
1328 }
1329 }
1330}
1331#endif /* DEVICE_POLLING */
1332
1333static void
1334rl_intr(void *arg)
1335{
1336 struct rl_softc *sc = arg;
1337 struct ifnet *ifp = sc->rl_ifp;
1338 uint16_t status;
1339
1340 RL_LOCK(sc);
1341
1342 if (sc->suspended)
1343 goto done_locked;
1344
1345#ifdef DEVICE_POLLING
1346 if (ifp->if_capenable & IFCAP_POLLING)
1347 goto done_locked;
1348#endif
1349
1350 for (;;) {
1351 status = CSR_READ_2(sc, RL_ISR);
1352 /* If the card has gone away, the read returns 0xffff. */
1353 if (status == 0xffff)
1354 break;
1355 if (status != 0)
1356 CSR_WRITE_2(sc, RL_ISR, status);
1357 if ((status & RL_INTRS) == 0)
1358 break;
1359 if (status & RL_ISR_RX_OK)
1360 rl_rxeof(sc);
1361 if (status & RL_ISR_RX_ERR)
1362 rl_rxeof(sc);
1363 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1364 rl_txeof(sc);
1365 if (status & RL_ISR_SYSTEM_ERR) {
1366 rl_reset(sc);
1367 rl_init_locked(sc);
1368 }
1369 }
1370
1371 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1372 rl_start_locked(ifp);
1373
1374done_locked:
1375 RL_UNLOCK(sc);
1376}
1377
1378/*
1379 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1380 * pointers to the fragment pointers.
1381 */
1382static int
1383rl_encap(struct rl_softc *sc, struct mbuf *m_head)
1384{
1385 struct mbuf *m_new = NULL;
1386
1387 RL_LOCK_ASSERT(sc);
1388
1389 /*
1390 * The RealTek is brain damaged and wants longword-aligned
1391 * TX buffers, plus we can only have one fragment buffer
1392 * per packet. We have to copy pretty much all the time.
1393 */
1394 m_new = m_defrag(m_head, M_DONTWAIT);
1395
1396 if (m_new == NULL) {
1397 m_freem(m_head);
1398 return (1);
1399 }
1400 m_head = m_new;
1401
1402 /* Pad frames to at least 60 bytes. */
1403 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1404 /*
1405 * Make security concious people happy: zero out the
1406 * bytes in the pad area, since we don't know what
1407 * this mbuf cluster buffer's previous user might
1408 * have left in it.
1409 */
1410 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1411 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1412 m_head->m_pkthdr.len +=
1413 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1414 m_head->m_len = m_head->m_pkthdr.len;
1415 }
1416
1417 RL_CUR_TXMBUF(sc) = m_head;
1418
1419 return (0);
1420}
1421
1422/*
1423 * Main transmit routine.
1424 */
1425static void
1426rl_start(struct ifnet *ifp)
1427{
1428 struct rl_softc *sc = ifp->if_softc;
1429
1430 RL_LOCK(sc);
1431 rl_start_locked(ifp);
1432 RL_UNLOCK(sc);
1433}
1434
1435static void
1436rl_start_locked(struct ifnet *ifp)
1437{
1438 struct rl_softc *sc = ifp->if_softc;
1439 struct mbuf *m_head = NULL;
1440
1441 RL_LOCK_ASSERT(sc);
1442
1443 while (RL_CUR_TXMBUF(sc) == NULL) {
1444
1445 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1446
1447 if (m_head == NULL)
1448 break;
1449
1450 if (rl_encap(sc, m_head))
1451 break;
1452
1453 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1454 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1455
1456 /* Transmit the frame. */
1457 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1458 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1459 mtod(RL_CUR_TXMBUF(sc), void *),
1460 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
1461 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1462 BUS_DMASYNC_PREREAD);
1463 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1464 RL_TXTHRESH(sc->rl_txthresh) |
1465 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1466
1467 RL_INC(sc->rl_cdata.cur_tx);
1468
1469 /* Set a timeout in case the chip goes out to lunch. */
1470 sc->rl_watchdog_timer = 5;
1471 }
1472
1473 /*
1474 * We broke out of the loop because all our TX slots are
1475 * full. Mark the NIC as busy until it drains some of the
1476 * packets from the queue.
1477 */
1478 if (RL_CUR_TXMBUF(sc) != NULL)
1479 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1480}
1481
1482static void
1483rl_init(void *xsc)
1484{
1485 struct rl_softc *sc = xsc;
1486
1487 RL_LOCK(sc);
1488 rl_init_locked(sc);
1489 RL_UNLOCK(sc);
1490}
1491
1492static void
1493rl_init_locked(struct rl_softc *sc)
1494{
1495 struct ifnet *ifp = sc->rl_ifp;
1496 struct mii_data *mii;
1497 uint32_t rxcfg = 0;
1498 uint32_t eaddr[2];
1499
1500 RL_LOCK_ASSERT(sc);
1501
1502 mii = device_get_softc(sc->rl_miibus);
1503
1504 /*
1505 * Cancel pending I/O and free all RX/TX buffers.
1506 */
1507 rl_stop(sc);
1508
1509 /*
1510 * Init our MAC address. Even though the chipset
1511 * documentation doesn't mention it, we need to enter "Config
1512 * register write enable" mode to modify the ID registers.
1513 */
1514 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1515 bzero(eaddr, sizeof(eaddr));
1516 bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1517 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1518 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1519 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1520
1521 /* Init the RX buffer pointer register. */
1522 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1523 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
1524 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1525 BUS_DMASYNC_PREWRITE);
1526
1527 /* Init TX descriptors. */
1528 rl_list_tx_init(sc);
1529
1530 /*
1531 * Enable transmit and receive.
1532 */
1533 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1534
1535 /*
1536 * Set the initial TX and RX configuration.
1537 */
1538 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1539 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1540
1541 /* Set the individual bit to receive frames for this host only. */
1542 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1543 rxcfg |= RL_RXCFG_RX_INDIV;
1544
1545 /* If we want promiscuous mode, set the allframes bit. */
1546 if (ifp->if_flags & IFF_PROMISC) {
1547 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1548 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1549 } else {
1550 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1551 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1552 }
1553
1554 /* Set capture broadcast bit to capture broadcast frames. */
1555 if (ifp->if_flags & IFF_BROADCAST) {
1556 rxcfg |= RL_RXCFG_RX_BROAD;
1557 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1558 } else {
1559 rxcfg &= ~RL_RXCFG_RX_BROAD;
1560 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1561 }
1562
1563 /* Program the multicast filter, if necessary. */
1564 rl_setmulti(sc);
1565
1566#ifdef DEVICE_POLLING
1567 /* Disable interrupts if we are polling. */
1568 if (ifp->if_capenable & IFCAP_POLLING)
1569 CSR_WRITE_2(sc, RL_IMR, 0);
1570 else
1571#endif
1572 /* Enable interrupts. */
1573 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1574
1575 /* Set initial TX threshold */
1576 sc->rl_txthresh = RL_TX_THRESH_INIT;
1577
1578 /* Start RX/TX process. */
1579 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1580
1581 /* Enable receiver and transmitter. */
1582 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1583
1584 mii_mediachg(mii);
1585
1586 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1587
1588 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1589 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1590
1591 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1592}
1593
1594/*
1595 * Set media options.
1596 */
1597static int
1598rl_ifmedia_upd(struct ifnet *ifp)
1599{
1600 struct rl_softc *sc = ifp->if_softc;
1601 struct mii_data *mii;
1602
1603 mii = device_get_softc(sc->rl_miibus);
1604
1605 RL_LOCK(sc);
1606 mii_mediachg(mii);
1607 RL_UNLOCK(sc);
1608
1609 return (0);
1610}
1611
1612/*
1613 * Report current media status.
1614 */
1615static void
1616rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1617{
1618 struct rl_softc *sc = ifp->if_softc;
1619 struct mii_data *mii;
1620
1621 mii = device_get_softc(sc->rl_miibus);
1622
1623 RL_LOCK(sc);
1624 mii_pollstat(mii);
1625 RL_UNLOCK(sc);
1626 ifmr->ifm_active = mii->mii_media_active;
1627 ifmr->ifm_status = mii->mii_media_status;
1628}
1629
1630static int
1631rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1632{
1633 struct ifreq *ifr = (struct ifreq *)data;
1634 struct mii_data *mii;
1635 struct rl_softc *sc = ifp->if_softc;
1636 int error = 0;
1637
1638 switch (command) {
1639 case SIOCSIFFLAGS:
1640 RL_LOCK(sc);
1641 if (ifp->if_flags & IFF_UP) {
1642 rl_init_locked(sc);
1643 } else {
1644 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1645 rl_stop(sc);
1646 }
1647 RL_UNLOCK(sc);
1648 error = 0;
1649 break;
1650 case SIOCADDMULTI:
1651 case SIOCDELMULTI:
1652 RL_LOCK(sc);
1653 rl_setmulti(sc);
1654 RL_UNLOCK(sc);
1655 error = 0;
1656 break;
1657 case SIOCGIFMEDIA:
1658 case SIOCSIFMEDIA:
1659 mii = device_get_softc(sc->rl_miibus);
1660 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1661 break;
1662 case SIOCSIFCAP:
1663#ifdef DEVICE_POLLING
1664 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1665 !(ifp->if_capenable & IFCAP_POLLING)) {
1666 error = ether_poll_register(rl_poll, ifp);
1667 if (error)
1668 return(error);
1669 RL_LOCK(sc);
1670 /* Disable interrupts */
1671 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1672 ifp->if_capenable |= IFCAP_POLLING;
1673 RL_UNLOCK(sc);
1674 return (error);
1675
1676 }
1677 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1678 ifp->if_capenable & IFCAP_POLLING) {
1679 error = ether_poll_deregister(ifp);
1680 /* Enable interrupts. */
1681 RL_LOCK(sc);
1682 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1683 ifp->if_capenable &= ~IFCAP_POLLING;
1684 RL_UNLOCK(sc);
1685 return (error);
1686 }
1687#endif /* DEVICE_POLLING */
1688 break;
1689 default:
1690 error = ether_ioctl(ifp, command, data);
1691 break;
1692 }
1693
1694 return (error);
1695}
1696
1697static void
1698rl_watchdog(struct rl_softc *sc)
1699{
1700
1701 RL_LOCK_ASSERT(sc);
1702
1703 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
1704 return;
1705
1706 device_printf(sc->rl_dev, "watchdog timeout\n");
1707 sc->rl_ifp->if_oerrors++;
1708
1709 rl_txeof(sc);
1710 rl_rxeof(sc);
1711 rl_init_locked(sc);
1712}
1713
1714/*
1715 * Stop the adapter and free any mbufs allocated to the
1716 * RX and TX lists.
1717 */
1718static void
1719rl_stop(struct rl_softc *sc)
1720{
1721 register int i;
1722 struct ifnet *ifp = sc->rl_ifp;
1723
1724 RL_LOCK_ASSERT(sc);
1725
1726 sc->rl_watchdog_timer = 0;
1727 callout_stop(&sc->rl_stat_callout);
1728 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1729
1730 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1731 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1732 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1733
1734 /*
1735 * Free the TX list buffers.
1736 */
1737 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1738 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1739 bus_dmamap_unload(sc->rl_tag,
1740 sc->rl_cdata.rl_tx_dmamap[i]);
1741 bus_dmamap_destroy(sc->rl_tag,
1742 sc->rl_cdata.rl_tx_dmamap[i]);
1743 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1744 sc->rl_cdata.rl_tx_chain[i] = NULL;
1745 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1746 0x0000000);
1747 }
1748 }
1749}
1750
1751/*
1752 * Device suspend routine. Stop the interface and save some PCI
1753 * settings in case the BIOS doesn't restore them properly on
1754 * resume.
1755 */
1756static int
1757rl_suspend(device_t dev)
1758{
1759 struct rl_softc *sc;
1760
1761 sc = device_get_softc(dev);
1762
1763 RL_LOCK(sc);
1764 rl_stop(sc);
1765 sc->suspended = 1;
1766 RL_UNLOCK(sc);
1767
1768 return (0);
1769}
1770
1771/*
1772 * Device resume routine. Restore some PCI settings in case the BIOS
1773 * doesn't, re-enable busmastering, and restart the interface if
1774 * appropriate.
1775 */
1776static int
1777rl_resume(device_t dev)
1778{
1779 struct rl_softc *sc;
1780 struct ifnet *ifp;
1781
1782 sc = device_get_softc(dev);
1783 ifp = sc->rl_ifp;
1784
1785 RL_LOCK(sc);
1786
1787 /* reinitialize interface if necessary */
1788 if (ifp->if_flags & IFF_UP)
1789 rl_init_locked(sc);
1790
1791 sc->suspended = 0;
1792
1793 RL_UNLOCK(sc);
1794
1795 return (0);
1796}
1797
1798/*
1799 * Stop all chip I/O so that the kernel's probe routines don't
1800 * get confused by errant DMAs when rebooting.
1801 */
1802static int
1803rl_shutdown(device_t dev)
1804{
1805 struct rl_softc *sc;
1806
1807 sc = device_get_softc(dev);
1808
1809 RL_LOCK(sc);
1810 rl_stop(sc);
1811 RL_UNLOCK(sc);
1812
1813 return (0);
1814}
| 171 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
172 "Planex FNW-3800-TX" },
173 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
174 "Compaq HNE-300" },
175 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
176 "LevelOne FPC-0106TX" },
177 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
178 "Edimax EP-4103DL CardBus" },
179 { 0, 0, 0, NULL }
180};
181
182static int rl_attach(device_t);
183static int rl_detach(device_t);
184static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int);
185static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int);
186static void rl_eeprom_putbyte(struct rl_softc *, int);
187static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
188static int rl_encap(struct rl_softc *, struct mbuf * );
189static int rl_list_tx_init(struct rl_softc *);
190static int rl_ifmedia_upd(struct ifnet *);
191static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
192static int rl_ioctl(struct ifnet *, u_long, caddr_t);
193static void rl_intr(void *);
194static void rl_init(void *);
195static void rl_init_locked(struct rl_softc *sc);
196static void rl_mii_send(struct rl_softc *, uint32_t, int);
197static void rl_mii_sync(struct rl_softc *);
198static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
199static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
200static int rl_miibus_readreg(device_t, int, int);
201static void rl_miibus_statchg(device_t);
202static int rl_miibus_writereg(device_t, int, int, int);
203#ifdef DEVICE_POLLING
204static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
205static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
206#endif
207static int rl_probe(device_t);
208static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
209static void rl_reset(struct rl_softc *);
210static int rl_resume(device_t);
211static void rl_rxeof(struct rl_softc *);
212static void rl_setmulti(struct rl_softc *);
213static int rl_shutdown(device_t);
214static void rl_start(struct ifnet *);
215static void rl_start_locked(struct ifnet *);
216static void rl_stop(struct rl_softc *);
217static int rl_suspend(device_t);
218static void rl_tick(void *);
219static void rl_txeof(struct rl_softc *);
220static void rl_watchdog(struct rl_softc *);
221
222#ifdef RL_USEIOSPACE
223#define RL_RES SYS_RES_IOPORT
224#define RL_RID RL_PCI_LOIO
225#else
226#define RL_RES SYS_RES_MEMORY
227#define RL_RID RL_PCI_LOMEM
228#endif
229
230static device_method_t rl_methods[] = {
231 /* Device interface */
232 DEVMETHOD(device_probe, rl_probe),
233 DEVMETHOD(device_attach, rl_attach),
234 DEVMETHOD(device_detach, rl_detach),
235 DEVMETHOD(device_suspend, rl_suspend),
236 DEVMETHOD(device_resume, rl_resume),
237 DEVMETHOD(device_shutdown, rl_shutdown),
238
239 /* bus interface */
240 DEVMETHOD(bus_print_child, bus_generic_print_child),
241 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
242
243 /* MII interface */
244 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
245 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
246 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
247
248 { 0, 0 }
249};
250
251static driver_t rl_driver = {
252 "rl",
253 rl_methods,
254 sizeof(struct rl_softc)
255};
256
257static devclass_t rl_devclass;
258
259DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
260DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
261DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
262
263#define EE_SET(x) \
264 CSR_WRITE_1(sc, RL_EECMD, \
265 CSR_READ_1(sc, RL_EECMD) | x)
266
267#define EE_CLR(x) \
268 CSR_WRITE_1(sc, RL_EECMD, \
269 CSR_READ_1(sc, RL_EECMD) & ~x)
270
271static void
272rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
273{
274 struct rl_softc *sc = arg;
275
276 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
277}
278
279static void
280rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
281{
282 struct rl_softc *sc = arg;
283
284 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
285}
286
287/*
288 * Send a read command and address to the EEPROM, check for ACK.
289 */
290static void
291rl_eeprom_putbyte(struct rl_softc *sc, int addr)
292{
293 register int d, i;
294
295 d = addr | sc->rl_eecmd_read;
296
297 /*
298 * Feed in each bit and strobe the clock.
299 */
300 for (i = 0x400; i; i >>= 1) {
301 if (d & i) {
302 EE_SET(RL_EE_DATAIN);
303 } else {
304 EE_CLR(RL_EE_DATAIN);
305 }
306 DELAY(100);
307 EE_SET(RL_EE_CLK);
308 DELAY(150);
309 EE_CLR(RL_EE_CLK);
310 DELAY(100);
311 }
312}
313
314/*
315 * Read a word of data stored in the EEPROM at address 'addr.'
316 */
317static void
318rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
319{
320 register int i;
321 uint16_t word = 0;
322
323 /* Enter EEPROM access mode. */
324 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
325
326 /*
327 * Send address of word we want to read.
328 */
329 rl_eeprom_putbyte(sc, addr);
330
331 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
332
333 /*
334 * Start reading bits from EEPROM.
335 */
336 for (i = 0x8000; i; i >>= 1) {
337 EE_SET(RL_EE_CLK);
338 DELAY(100);
339 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
340 word |= i;
341 EE_CLR(RL_EE_CLK);
342 DELAY(100);
343 }
344
345 /* Turn off EEPROM access mode. */
346 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
347
348 *dest = word;
349}
350
351/*
352 * Read a sequence of words from the EEPROM.
353 */
354static void
355rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
356{
357 int i;
358 uint16_t word = 0, *ptr;
359
360 for (i = 0; i < cnt; i++) {
361 rl_eeprom_getword(sc, off + i, &word);
362 ptr = (uint16_t *)(dest + (i * 2));
363 if (swap)
364 *ptr = ntohs(word);
365 else
366 *ptr = word;
367 }
368}
369
370/*
371 * MII access routines are provided for the 8129, which
372 * doesn't have a built-in PHY. For the 8139, we fake things
373 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
374 * direct access PHY registers.
375 */
376#define MII_SET(x) \
377 CSR_WRITE_1(sc, RL_MII, \
378 CSR_READ_1(sc, RL_MII) | (x))
379
380#define MII_CLR(x) \
381 CSR_WRITE_1(sc, RL_MII, \
382 CSR_READ_1(sc, RL_MII) & ~(x))
383
384/*
385 * Sync the PHYs by setting data bit and strobing the clock 32 times.
386 */
387static void
388rl_mii_sync(struct rl_softc *sc)
389{
390 register int i;
391
392 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
393
394 for (i = 0; i < 32; i++) {
395 MII_SET(RL_MII_CLK);
396 DELAY(1);
397 MII_CLR(RL_MII_CLK);
398 DELAY(1);
399 }
400}
401
402/*
403 * Clock a series of bits through the MII.
404 */
405static void
406rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
407{
408 int i;
409
410 MII_CLR(RL_MII_CLK);
411
412 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
413 if (bits & i) {
414 MII_SET(RL_MII_DATAOUT);
415 } else {
416 MII_CLR(RL_MII_DATAOUT);
417 }
418 DELAY(1);
419 MII_CLR(RL_MII_CLK);
420 DELAY(1);
421 MII_SET(RL_MII_CLK);
422 }
423}
424
425/*
426 * Read an PHY register through the MII.
427 */
428static int
429rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
430{
431 int i, ack;
432
433 /* Set up frame for RX. */
434 frame->mii_stdelim = RL_MII_STARTDELIM;
435 frame->mii_opcode = RL_MII_READOP;
436 frame->mii_turnaround = 0;
437 frame->mii_data = 0;
438
439 CSR_WRITE_2(sc, RL_MII, 0);
440
441 /* Turn on data xmit. */
442 MII_SET(RL_MII_DIR);
443
444 rl_mii_sync(sc);
445
446 /* Send command/address info. */
447 rl_mii_send(sc, frame->mii_stdelim, 2);
448 rl_mii_send(sc, frame->mii_opcode, 2);
449 rl_mii_send(sc, frame->mii_phyaddr, 5);
450 rl_mii_send(sc, frame->mii_regaddr, 5);
451
452 /* Idle bit */
453 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
454 DELAY(1);
455 MII_SET(RL_MII_CLK);
456 DELAY(1);
457
458 /* Turn off xmit. */
459 MII_CLR(RL_MII_DIR);
460
461 /* Check for ack */
462 MII_CLR(RL_MII_CLK);
463 DELAY(1);
464 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
465 MII_SET(RL_MII_CLK);
466 DELAY(1);
467
468 /*
469 * Now try reading data bits. If the ack failed, we still
470 * need to clock through 16 cycles to keep the PHY(s) in sync.
471 */
472 if (ack) {
473 for(i = 0; i < 16; i++) {
474 MII_CLR(RL_MII_CLK);
475 DELAY(1);
476 MII_SET(RL_MII_CLK);
477 DELAY(1);
478 }
479 goto fail;
480 }
481
482 for (i = 0x8000; i; i >>= 1) {
483 MII_CLR(RL_MII_CLK);
484 DELAY(1);
485 if (!ack) {
486 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
487 frame->mii_data |= i;
488 DELAY(1);
489 }
490 MII_SET(RL_MII_CLK);
491 DELAY(1);
492 }
493
494fail:
495 MII_CLR(RL_MII_CLK);
496 DELAY(1);
497 MII_SET(RL_MII_CLK);
498 DELAY(1);
499
500 return (ack ? 1 : 0);
501}
502
503/*
504 * Write to a PHY register through the MII.
505 */
506static int
507rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
508{
509
510 /* Set up frame for TX. */
511 frame->mii_stdelim = RL_MII_STARTDELIM;
512 frame->mii_opcode = RL_MII_WRITEOP;
513 frame->mii_turnaround = RL_MII_TURNAROUND;
514
515 /* Turn on data output. */
516 MII_SET(RL_MII_DIR);
517
518 rl_mii_sync(sc);
519
520 rl_mii_send(sc, frame->mii_stdelim, 2);
521 rl_mii_send(sc, frame->mii_opcode, 2);
522 rl_mii_send(sc, frame->mii_phyaddr, 5);
523 rl_mii_send(sc, frame->mii_regaddr, 5);
524 rl_mii_send(sc, frame->mii_turnaround, 2);
525 rl_mii_send(sc, frame->mii_data, 16);
526
527 /* Idle bit. */
528 MII_SET(RL_MII_CLK);
529 DELAY(1);
530 MII_CLR(RL_MII_CLK);
531 DELAY(1);
532
533 /* Turn off xmit. */
534 MII_CLR(RL_MII_DIR);
535
536 return (0);
537}
538
539static int
540rl_miibus_readreg(device_t dev, int phy, int reg)
541{
542 struct rl_softc *sc;
543 struct rl_mii_frame frame;
544 uint16_t rval = 0;
545 uint16_t rl8139_reg = 0;
546
547 sc = device_get_softc(dev);
548
549 if (sc->rl_type == RL_8139) {
550 /* Pretend the internal PHY is only at address 0 */
551 if (phy) {
552 return (0);
553 }
554 switch (reg) {
555 case MII_BMCR:
556 rl8139_reg = RL_BMCR;
557 break;
558 case MII_BMSR:
559 rl8139_reg = RL_BMSR;
560 break;
561 case MII_ANAR:
562 rl8139_reg = RL_ANAR;
563 break;
564 case MII_ANER:
565 rl8139_reg = RL_ANER;
566 break;
567 case MII_ANLPAR:
568 rl8139_reg = RL_LPAR;
569 break;
570 case MII_PHYIDR1:
571 case MII_PHYIDR2:
572 return (0);
573 /*
574 * Allow the rlphy driver to read the media status
575 * register. If we have a link partner which does not
576 * support NWAY, this is the register which will tell
577 * us the results of parallel detection.
578 */
579 case RL_MEDIASTAT:
580 rval = CSR_READ_1(sc, RL_MEDIASTAT);
581 return (rval);
582 default:
583 device_printf(sc->rl_dev, "bad phy register\n");
584 return (0);
585 }
586 rval = CSR_READ_2(sc, rl8139_reg);
587 return (rval);
588 }
589
590 bzero((char *)&frame, sizeof(frame));
591 frame.mii_phyaddr = phy;
592 frame.mii_regaddr = reg;
593 rl_mii_readreg(sc, &frame);
594
595 return (frame.mii_data);
596}
597
598static int
599rl_miibus_writereg(device_t dev, int phy, int reg, int data)
600{
601 struct rl_softc *sc;
602 struct rl_mii_frame frame;
603 uint16_t rl8139_reg = 0;
604
605 sc = device_get_softc(dev);
606
607 if (sc->rl_type == RL_8139) {
608 /* Pretend the internal PHY is only at address 0 */
609 if (phy) {
610 return (0);
611 }
612 switch (reg) {
613 case MII_BMCR:
614 rl8139_reg = RL_BMCR;
615 break;
616 case MII_BMSR:
617 rl8139_reg = RL_BMSR;
618 break;
619 case MII_ANAR:
620 rl8139_reg = RL_ANAR;
621 break;
622 case MII_ANER:
623 rl8139_reg = RL_ANER;
624 break;
625 case MII_ANLPAR:
626 rl8139_reg = RL_LPAR;
627 break;
628 case MII_PHYIDR1:
629 case MII_PHYIDR2:
630 return (0);
631 break;
632 default:
633 device_printf(sc->rl_dev, "bad phy register\n");
634 return (0);
635 }
636 CSR_WRITE_2(sc, rl8139_reg, data);
637 return (0);
638 }
639
640 bzero((char *)&frame, sizeof(frame));
641 frame.mii_phyaddr = phy;
642 frame.mii_regaddr = reg;
643 frame.mii_data = data;
644 rl_mii_writereg(sc, &frame);
645
646 return (0);
647}
648
649static void
650rl_miibus_statchg(device_t dev)
651{
652}
653
654/*
655 * Program the 64-bit multicast hash filter.
656 */
657static void
658rl_setmulti(struct rl_softc *sc)
659{
660 struct ifnet *ifp = sc->rl_ifp;
661 int h = 0;
662 uint32_t hashes[2] = { 0, 0 };
663 struct ifmultiaddr *ifma;
664 uint32_t rxfilt;
665 int mcnt = 0;
666
667 RL_LOCK_ASSERT(sc);
668
669 rxfilt = CSR_READ_4(sc, RL_RXCFG);
670
671 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
672 rxfilt |= RL_RXCFG_RX_MULTI;
673 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
674 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
675 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
676 return;
677 }
678
679 /* first, zot all the existing hash bits */
680 CSR_WRITE_4(sc, RL_MAR0, 0);
681 CSR_WRITE_4(sc, RL_MAR4, 0);
682
683 /* now program new ones */
684 IF_ADDR_LOCK(ifp);
685 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
686 if (ifma->ifma_addr->sa_family != AF_LINK)
687 continue;
688 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
689 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
690 if (h < 32)
691 hashes[0] |= (1 << h);
692 else
693 hashes[1] |= (1 << (h - 32));
694 mcnt++;
695 }
696 IF_ADDR_UNLOCK(ifp);
697
698 if (mcnt)
699 rxfilt |= RL_RXCFG_RX_MULTI;
700 else
701 rxfilt &= ~RL_RXCFG_RX_MULTI;
702
703 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
704 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
705 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
706}
707
708static void
709rl_reset(struct rl_softc *sc)
710{
711 register int i;
712
713 RL_LOCK_ASSERT(sc);
714
715 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
716
717 for (i = 0; i < RL_TIMEOUT; i++) {
718 DELAY(10);
719 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
720 break;
721 }
722 if (i == RL_TIMEOUT)
723 device_printf(sc->rl_dev, "reset never completed!\n");
724}
725
726/*
727 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
728 * IDs against our list and return a device name if we find a match.
729 */
730static int
731rl_probe(device_t dev)
732{
733 struct rl_softc *sc;
734 struct rl_type *t = rl_devs;
735 int rid;
736 uint32_t hwrev;
737
738 sc = device_get_softc(dev);
739
740 while (t->rl_name != NULL) {
741 if ((pci_get_vendor(dev) == t->rl_vid) &&
742 (pci_get_device(dev) == t->rl_did)) {
743 /*
744 * Temporarily map the I/O space
745 * so we can read the chip ID register.
746 */
747 rid = RL_RID;
748 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
749 RF_ACTIVE);
750 if (sc->rl_res == NULL) {
751 device_printf(dev,
752 "couldn't map ports/memory\n");
753 return (ENXIO);
754 }
755 sc->rl_btag = rman_get_bustag(sc->rl_res);
756 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
757
758 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
759 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
760
761 /* Don't attach to 8139C+ or 8169/8110 chips. */
762 if (hwrev == RL_HWREV_8139CPLUS ||
763 (hwrev == RL_HWREV_8169 &&
764 t->rl_did == RT_DEVICEID_8169) ||
765 hwrev == RL_HWREV_8169S ||
766 hwrev == RL_HWREV_8110S) {
767 t++;
768 continue;
769 }
770
771 device_set_desc(dev, t->rl_name);
772 return (BUS_PROBE_DEFAULT);
773 }
774 t++;
775 }
776
777 return (ENXIO);
778}
779
780/*
781 * Attach the interface. Allocate softc structures, do ifmedia
782 * setup and ethernet/BPF attach.
783 */
784static int
785rl_attach(device_t dev)
786{
787 uint8_t eaddr[ETHER_ADDR_LEN];
788 uint16_t as[3];
789 struct ifnet *ifp;
790 struct rl_softc *sc;
791 struct rl_type *t;
792 int error = 0, i, rid;
793 int unit;
794 uint16_t rl_did = 0;
795
796 sc = device_get_softc(dev);
797 unit = device_get_unit(dev);
798 sc->rl_dev = dev;
799
800 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
801 MTX_DEF);
802 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
803
804 pci_enable_busmaster(dev);
805
806 /* Map control/status registers. */
807 rid = RL_RID;
808 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
809
810 if (sc->rl_res == NULL) {
811 device_printf(dev, "couldn't map ports/memory\n");
812 error = ENXIO;
813 goto fail;
814 }
815
816#ifdef notdef
817 /*
818 * Detect the Realtek 8139B. For some reason, this chip is very
819 * unstable when left to autoselect the media
820 * The best workaround is to set the device to the required
821 * media type or to set it to the 10 Meg speed.
822 */
823 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
824 device_printf(dev,
825"Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
826#endif
827
828 sc->rl_btag = rman_get_bustag(sc->rl_res);
829 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
830
831 /* Allocate interrupt */
832 rid = 0;
833 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
834 RF_SHAREABLE | RF_ACTIVE);
835
836 if (sc->rl_irq[0] == NULL) {
837 device_printf(dev, "couldn't map interrupt\n");
838 error = ENXIO;
839 goto fail;
840 }
841
842 /*
843 * Reset the adapter. Only take the lock here as it's needed in
844 * order to call rl_reset().
845 */
846 RL_LOCK(sc);
847 rl_reset(sc);
848 RL_UNLOCK(sc);
849
850 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
851 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
852 if (rl_did != 0x8129)
853 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
854
855 /*
856 * Get station address from the EEPROM.
857 */
858 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
859 for (i = 0; i < 3; i++) {
860 eaddr[(i * 2) + 0] = as[i] & 0xff;
861 eaddr[(i * 2) + 1] = as[i] >> 8;
862 }
863
864 /*
865 * Now read the exact device type from the EEPROM to find
866 * out if it's an 8129 or 8139.
867 */
868 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
869
870 t = rl_devs;
871 sc->rl_type = 0;
872 while(t->rl_name != NULL) {
873 if (rl_did == t->rl_did) {
874 sc->rl_type = t->rl_basetype;
875 break;
876 }
877 t++;
878 }
879
880 if (sc->rl_type == 0) {
881 device_printf(dev, "unknown device ID: %x\n", rl_did);
882 error = ENXIO;
883 goto fail;
884 }
885
886 /*
887 * Allocate the parent bus DMA tag appropriate for PCI.
888 */
889#define RL_NSEG_NEW 32
890 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
891 1, 0, /* alignment, boundary */
892 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
893 BUS_SPACE_MAXADDR, /* highaddr */
894 NULL, NULL, /* filter, filterarg */
895 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
896 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
897 BUS_DMA_ALLOCNOW, /* flags */
898 NULL, NULL, /* lockfunc, lockarg */
899 &sc->rl_parent_tag);
900 if (error)
901 goto fail;
902
903 /*
904 * Now allocate a tag for the DMA descriptor lists.
905 * All of our lists are allocated as a contiguous block
906 * of memory.
907 */
908 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
909 1, 0, /* alignment, boundary */
910 BUS_SPACE_MAXADDR, /* lowaddr */
911 BUS_SPACE_MAXADDR, /* highaddr */
912 NULL, NULL, /* filter, filterarg */
913 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */
914 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
915 BUS_DMA_ALLOCNOW, /* flags */
916 NULL, NULL, /* lockfunc, lockarg */
917 &sc->rl_tag);
918 if (error)
919 goto fail;
920
921 /*
922 * Now allocate a chunk of DMA-able memory based on the
923 * tag we just created.
924 */
925 error = bus_dmamem_alloc(sc->rl_tag,
926 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
927 &sc->rl_cdata.rl_rx_dmamap);
928 if (error) {
929 device_printf(dev, "no memory for list buffers!\n");
930 bus_dma_tag_destroy(sc->rl_tag);
931 sc->rl_tag = NULL;
932 goto fail;
933 }
934
935 /* Leave a few bytes before the start of the RX ring buffer. */
936 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
937 sc->rl_cdata.rl_rx_buf += sizeof(uint64_t);
938
939 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
940 if (ifp == NULL) {
941 device_printf(dev, "can not if_alloc()\n");
942 error = ENOSPC;
943 goto fail;
944 }
945
946 /* Do MII setup */
947 if (mii_phy_probe(dev, &sc->rl_miibus,
948 rl_ifmedia_upd, rl_ifmedia_sts)) {
949 device_printf(dev, "MII without any phy!\n");
950 error = ENXIO;
951 goto fail;
952 }
953
954 ifp->if_softc = sc;
955 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
956 ifp->if_mtu = ETHERMTU;
957 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
958 ifp->if_ioctl = rl_ioctl;
959 ifp->if_start = rl_start;
960 ifp->if_init = rl_init;
961 ifp->if_capabilities = IFCAP_VLAN_MTU;
962 ifp->if_capenable = ifp->if_capabilities;
963#ifdef DEVICE_POLLING
964 ifp->if_capabilities |= IFCAP_POLLING;
965#endif
966 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
967 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
968 IFQ_SET_READY(&ifp->if_snd);
969
970 /*
971 * Call MI attach routine.
972 */
973 ether_ifattach(ifp, eaddr);
974
975 /* Hook interrupt last to avoid having to lock softc */
976 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
977 NULL, rl_intr, sc, &sc->rl_intrhand[0]);
978 if (error) {
979 device_printf(sc->rl_dev, "couldn't set up irq\n");
980 ether_ifdetach(ifp);
981 }
982
983fail:
984 if (error)
985 rl_detach(dev);
986
987 return (error);
988}
989
990/*
991 * Shutdown hardware and free up resources. This can be called any
992 * time after the mutex has been initialized. It is called in both
993 * the error case in attach and the normal detach case so it needs
994 * to be careful about only freeing resources that have actually been
995 * allocated.
996 */
997static int
998rl_detach(device_t dev)
999{
1000 struct rl_softc *sc;
1001 struct ifnet *ifp;
1002
1003 sc = device_get_softc(dev);
1004 ifp = sc->rl_ifp;
1005
1006 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
1007
1008#ifdef DEVICE_POLLING
1009 if (ifp->if_capenable & IFCAP_POLLING)
1010 ether_poll_deregister(ifp);
1011#endif
1012 /* These should only be active if attach succeeded */
1013 if (device_is_attached(dev)) {
1014 RL_LOCK(sc);
1015 rl_stop(sc);
1016 RL_UNLOCK(sc);
1017 callout_drain(&sc->rl_stat_callout);
1018 ether_ifdetach(ifp);
1019 }
1020#if 0
1021 sc->suspended = 1;
1022#endif
1023 if (sc->rl_miibus)
1024 device_delete_child(dev, sc->rl_miibus);
1025 bus_generic_detach(dev);
1026
1027 if (sc->rl_intrhand[0])
1028 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1029 if (sc->rl_irq[0])
1030 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
1031 if (sc->rl_res)
1032 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1033
1034 if (ifp)
1035 if_free(ifp);
1036
1037 if (sc->rl_tag) {
1038 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1039 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
1040 sc->rl_cdata.rl_rx_dmamap);
1041 bus_dma_tag_destroy(sc->rl_tag);
1042 }
1043 if (sc->rl_parent_tag)
1044 bus_dma_tag_destroy(sc->rl_parent_tag);
1045
1046 mtx_destroy(&sc->rl_mtx);
1047
1048 return (0);
1049}
1050
1051/*
1052 * Initialize the transmit descriptors.
1053 */
1054static int
1055rl_list_tx_init(struct rl_softc *sc)
1056{
1057 struct rl_chain_data *cd;
1058 int i;
1059
1060 RL_LOCK_ASSERT(sc);
1061
1062 cd = &sc->rl_cdata;
1063 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1064 cd->rl_tx_chain[i] = NULL;
1065 CSR_WRITE_4(sc,
1066 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1067 }
1068
1069 sc->rl_cdata.cur_tx = 0;
1070 sc->rl_cdata.last_tx = 0;
1071
1072 return (0);
1073}
1074
1075/*
1076 * A frame has been uploaded: pass the resulting mbuf chain up to
1077 * the higher level protocols.
1078 *
1079 * You know there's something wrong with a PCI bus-master chip design
1080 * when you have to use m_devget().
1081 *
1082 * The receive operation is badly documented in the datasheet, so I'll
1083 * attempt to document it here. The driver provides a buffer area and
1084 * places its base address in the RX buffer start address register.
1085 * The chip then begins copying frames into the RX buffer. Each frame
1086 * is preceded by a 32-bit RX status word which specifies the length
1087 * of the frame and certain other status bits. Each frame (starting with
1088 * the status word) is also 32-bit aligned. The frame length is in the
1089 * first 16 bits of the status word; the lower 15 bits correspond with
1090 * the 'rx status register' mentioned in the datasheet.
1091 *
1092 * Note: to make the Alpha happy, the frame payload needs to be aligned
1093 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1094 * as the offset argument to m_devget().
1095 */
1096static void
1097rl_rxeof(struct rl_softc *sc)
1098{
1099 struct mbuf *m;
1100 struct ifnet *ifp = sc->rl_ifp;
1101 uint8_t *rxbufpos;
1102 int total_len = 0;
1103 int wrap = 0;
1104 uint32_t rxstat;
1105 uint16_t cur_rx;
1106 uint16_t limit;
1107 uint16_t max_bytes, rx_bytes = 0;
1108
1109 RL_LOCK_ASSERT(sc);
1110
1111 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1112 BUS_DMASYNC_POSTREAD);
1113
1114 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1115
1116 /* Do not try to read past this point. */
1117 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1118
1119 if (limit < cur_rx)
1120 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1121 else
1122 max_bytes = limit - cur_rx;
1123
1124 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1125#ifdef DEVICE_POLLING
1126 if (ifp->if_capenable & IFCAP_POLLING) {
1127 if (sc->rxcycles <= 0)
1128 break;
1129 sc->rxcycles--;
1130 }
1131#endif
1132 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1133 rxstat = le32toh(*(uint32_t *)rxbufpos);
1134
1135 /*
1136 * Here's a totally undocumented fact for you. When the
1137 * RealTek chip is in the process of copying a packet into
1138 * RAM for you, the length will be 0xfff0. If you spot a
1139 * packet header with this value, you need to stop. The
1140 * datasheet makes absolutely no mention of this and
1141 * RealTek should be shot for this.
1142 */
1143 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1144 break;
1145
1146 if (!(rxstat & RL_RXSTAT_RXOK)) {
1147 ifp->if_ierrors++;
1148 rl_init_locked(sc);
1149 return;
1150 }
1151
1152 /* No errors; receive the packet. */
1153 total_len = rxstat >> 16;
1154 rx_bytes += total_len + 4;
1155
1156 /*
1157 * XXX The RealTek chip includes the CRC with every
1158 * received frame, and there's no way to turn this
1159 * behavior off (at least, I can't find anything in
1160 * the manual that explains how to do it) so we have
1161 * to trim off the CRC manually.
1162 */
1163 total_len -= ETHER_CRC_LEN;
1164
1165 /*
1166 * Avoid trying to read more bytes than we know
1167 * the chip has prepared for us.
1168 */
1169 if (rx_bytes > max_bytes)
1170 break;
1171
1172 rxbufpos = sc->rl_cdata.rl_rx_buf +
1173 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1174 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1175 rxbufpos = sc->rl_cdata.rl_rx_buf;
1176
1177 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1178 if (total_len > wrap) {
1179 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1180 NULL);
1181 if (m == NULL) {
1182 ifp->if_ierrors++;
1183 } else {
1184 m_copyback(m, wrap, total_len - wrap,
1185 sc->rl_cdata.rl_rx_buf);
1186 }
1187 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1188 } else {
1189 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1190 NULL);
1191 if (m == NULL)
1192 ifp->if_ierrors++;
1193 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1194 }
1195
1196 /* Round up to 32-bit boundary. */
1197 cur_rx = (cur_rx + 3) & ~3;
1198 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1199
1200 if (m == NULL)
1201 continue;
1202
1203 ifp->if_ipackets++;
1204 RL_UNLOCK(sc);
1205 (*ifp->if_input)(ifp, m);
1206 RL_LOCK(sc);
1207 }
1208}
1209
1210/*
1211 * A frame was downloaded to the chip. It's safe for us to clean up
1212 * the list buffers.
1213 */
1214static void
1215rl_txeof(struct rl_softc *sc)
1216{
1217 struct ifnet *ifp = sc->rl_ifp;
1218 uint32_t txstat;
1219
1220 RL_LOCK_ASSERT(sc);
1221
1222 /*
1223 * Go through our tx list and free mbufs for those
1224 * frames that have been uploaded.
1225 */
1226 do {
1227 if (RL_LAST_TXMBUF(sc) == NULL)
1228 break;
1229 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1230 if (!(txstat & (RL_TXSTAT_TX_OK|
1231 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1232 break;
1233
1234 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1235
1236 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1237 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1238 m_freem(RL_LAST_TXMBUF(sc));
1239 RL_LAST_TXMBUF(sc) = NULL;
1240 /*
1241 * If there was a transmit underrun, bump the TX threshold.
1242 * Make sure not to overflow the 63 * 32byte we can address
1243 * with the 6 available bit.
1244 */
1245 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1246 (sc->rl_txthresh < 2016))
1247 sc->rl_txthresh += 32;
1248 if (txstat & RL_TXSTAT_TX_OK)
1249 ifp->if_opackets++;
1250 else {
1251 int oldthresh;
1252 ifp->if_oerrors++;
1253 if ((txstat & RL_TXSTAT_TXABRT) ||
1254 (txstat & RL_TXSTAT_OUTOFWIN))
1255 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1256 oldthresh = sc->rl_txthresh;
1257 /* error recovery */
1258 rl_reset(sc);
1259 rl_init_locked(sc);
1260 /* restore original threshold */
1261 sc->rl_txthresh = oldthresh;
1262 return;
1263 }
1264 RL_INC(sc->rl_cdata.last_tx);
1265 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1266 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1267
1268 if (RL_LAST_TXMBUF(sc) == NULL)
1269 sc->rl_watchdog_timer = 0;
1270 else if (sc->rl_watchdog_timer == 0)
1271 sc->rl_watchdog_timer = 5;
1272}
1273
1274static void
1275rl_tick(void *xsc)
1276{
1277 struct rl_softc *sc = xsc;
1278 struct mii_data *mii;
1279
1280 RL_LOCK_ASSERT(sc);
1281 mii = device_get_softc(sc->rl_miibus);
1282 mii_tick(mii);
1283
1284 rl_watchdog(sc);
1285
1286 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1287}
1288
1289#ifdef DEVICE_POLLING
1290static void
1291rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1292{
1293 struct rl_softc *sc = ifp->if_softc;
1294
1295 RL_LOCK(sc);
1296 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1297 rl_poll_locked(ifp, cmd, count);
1298 RL_UNLOCK(sc);
1299}
1300
1301static void
1302rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1303{
1304 struct rl_softc *sc = ifp->if_softc;
1305
1306 RL_LOCK_ASSERT(sc);
1307
1308 sc->rxcycles = count;
1309 rl_rxeof(sc);
1310 rl_txeof(sc);
1311
1312 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1313 rl_start_locked(ifp);
1314
1315 if (cmd == POLL_AND_CHECK_STATUS) {
1316 uint16_t status;
1317
1318 /* We should also check the status register. */
1319 status = CSR_READ_2(sc, RL_ISR);
1320 if (status == 0xffff)
1321 return;
1322 if (status != 0)
1323 CSR_WRITE_2(sc, RL_ISR, status);
1324
1325 /* XXX We should check behaviour on receiver stalls. */
1326
1327 if (status & RL_ISR_SYSTEM_ERR) {
1328 rl_reset(sc);
1329 rl_init_locked(sc);
1330 }
1331 }
1332}
1333#endif /* DEVICE_POLLING */
1334
1335static void
1336rl_intr(void *arg)
1337{
1338 struct rl_softc *sc = arg;
1339 struct ifnet *ifp = sc->rl_ifp;
1340 uint16_t status;
1341
1342 RL_LOCK(sc);
1343
1344 if (sc->suspended)
1345 goto done_locked;
1346
1347#ifdef DEVICE_POLLING
1348 if (ifp->if_capenable & IFCAP_POLLING)
1349 goto done_locked;
1350#endif
1351
1352 for (;;) {
1353 status = CSR_READ_2(sc, RL_ISR);
1354 /* If the card has gone away, the read returns 0xffff. */
1355 if (status == 0xffff)
1356 break;
1357 if (status != 0)
1358 CSR_WRITE_2(sc, RL_ISR, status);
1359 if ((status & RL_INTRS) == 0)
1360 break;
1361 if (status & RL_ISR_RX_OK)
1362 rl_rxeof(sc);
1363 if (status & RL_ISR_RX_ERR)
1364 rl_rxeof(sc);
1365 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1366 rl_txeof(sc);
1367 if (status & RL_ISR_SYSTEM_ERR) {
1368 rl_reset(sc);
1369 rl_init_locked(sc);
1370 }
1371 }
1372
1373 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1374 rl_start_locked(ifp);
1375
1376done_locked:
1377 RL_UNLOCK(sc);
1378}
1379
1380/*
1381 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1382 * pointers to the fragment pointers.
1383 */
1384static int
1385rl_encap(struct rl_softc *sc, struct mbuf *m_head)
1386{
1387 struct mbuf *m_new = NULL;
1388
1389 RL_LOCK_ASSERT(sc);
1390
1391 /*
1392 * The RealTek is brain damaged and wants longword-aligned
1393 * TX buffers, plus we can only have one fragment buffer
1394 * per packet. We have to copy pretty much all the time.
1395 */
1396 m_new = m_defrag(m_head, M_DONTWAIT);
1397
1398 if (m_new == NULL) {
1399 m_freem(m_head);
1400 return (1);
1401 }
1402 m_head = m_new;
1403
1404 /* Pad frames to at least 60 bytes. */
1405 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1406 /*
1407 * Make security concious people happy: zero out the
1408 * bytes in the pad area, since we don't know what
1409 * this mbuf cluster buffer's previous user might
1410 * have left in it.
1411 */
1412 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1413 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1414 m_head->m_pkthdr.len +=
1415 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1416 m_head->m_len = m_head->m_pkthdr.len;
1417 }
1418
1419 RL_CUR_TXMBUF(sc) = m_head;
1420
1421 return (0);
1422}
1423
1424/*
1425 * Main transmit routine.
1426 */
1427static void
1428rl_start(struct ifnet *ifp)
1429{
1430 struct rl_softc *sc = ifp->if_softc;
1431
1432 RL_LOCK(sc);
1433 rl_start_locked(ifp);
1434 RL_UNLOCK(sc);
1435}
1436
1437static void
1438rl_start_locked(struct ifnet *ifp)
1439{
1440 struct rl_softc *sc = ifp->if_softc;
1441 struct mbuf *m_head = NULL;
1442
1443 RL_LOCK_ASSERT(sc);
1444
1445 while (RL_CUR_TXMBUF(sc) == NULL) {
1446
1447 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1448
1449 if (m_head == NULL)
1450 break;
1451
1452 if (rl_encap(sc, m_head))
1453 break;
1454
1455 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1456 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1457
1458 /* Transmit the frame. */
1459 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1460 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1461 mtod(RL_CUR_TXMBUF(sc), void *),
1462 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
1463 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1464 BUS_DMASYNC_PREREAD);
1465 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1466 RL_TXTHRESH(sc->rl_txthresh) |
1467 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1468
1469 RL_INC(sc->rl_cdata.cur_tx);
1470
1471 /* Set a timeout in case the chip goes out to lunch. */
1472 sc->rl_watchdog_timer = 5;
1473 }
1474
1475 /*
1476 * We broke out of the loop because all our TX slots are
1477 * full. Mark the NIC as busy until it drains some of the
1478 * packets from the queue.
1479 */
1480 if (RL_CUR_TXMBUF(sc) != NULL)
1481 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1482}
1483
1484static void
1485rl_init(void *xsc)
1486{
1487 struct rl_softc *sc = xsc;
1488
1489 RL_LOCK(sc);
1490 rl_init_locked(sc);
1491 RL_UNLOCK(sc);
1492}
1493
1494static void
1495rl_init_locked(struct rl_softc *sc)
1496{
1497 struct ifnet *ifp = sc->rl_ifp;
1498 struct mii_data *mii;
1499 uint32_t rxcfg = 0;
1500 uint32_t eaddr[2];
1501
1502 RL_LOCK_ASSERT(sc);
1503
1504 mii = device_get_softc(sc->rl_miibus);
1505
1506 /*
1507 * Cancel pending I/O and free all RX/TX buffers.
1508 */
1509 rl_stop(sc);
1510
1511 /*
1512 * Init our MAC address. Even though the chipset
1513 * documentation doesn't mention it, we need to enter "Config
1514 * register write enable" mode to modify the ID registers.
1515 */
1516 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1517 bzero(eaddr, sizeof(eaddr));
1518 bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1519 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1520 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1521 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1522
1523 /* Init the RX buffer pointer register. */
1524 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1525 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
1526 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1527 BUS_DMASYNC_PREWRITE);
1528
1529 /* Init TX descriptors. */
1530 rl_list_tx_init(sc);
1531
1532 /*
1533 * Enable transmit and receive.
1534 */
1535 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1536
1537 /*
1538 * Set the initial TX and RX configuration.
1539 */
1540 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1541 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1542
1543 /* Set the individual bit to receive frames for this host only. */
1544 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1545 rxcfg |= RL_RXCFG_RX_INDIV;
1546
1547 /* If we want promiscuous mode, set the allframes bit. */
1548 if (ifp->if_flags & IFF_PROMISC) {
1549 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1550 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1551 } else {
1552 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1553 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1554 }
1555
1556 /* Set capture broadcast bit to capture broadcast frames. */
1557 if (ifp->if_flags & IFF_BROADCAST) {
1558 rxcfg |= RL_RXCFG_RX_BROAD;
1559 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1560 } else {
1561 rxcfg &= ~RL_RXCFG_RX_BROAD;
1562 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1563 }
1564
1565 /* Program the multicast filter, if necessary. */
1566 rl_setmulti(sc);
1567
1568#ifdef DEVICE_POLLING
1569 /* Disable interrupts if we are polling. */
1570 if (ifp->if_capenable & IFCAP_POLLING)
1571 CSR_WRITE_2(sc, RL_IMR, 0);
1572 else
1573#endif
1574 /* Enable interrupts. */
1575 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1576
1577 /* Set initial TX threshold */
1578 sc->rl_txthresh = RL_TX_THRESH_INIT;
1579
1580 /* Start RX/TX process. */
1581 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1582
1583 /* Enable receiver and transmitter. */
1584 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1585
1586 mii_mediachg(mii);
1587
1588 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1589
1590 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1591 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1592
1593 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1594}
1595
1596/*
1597 * Set media options.
1598 */
1599static int
1600rl_ifmedia_upd(struct ifnet *ifp)
1601{
1602 struct rl_softc *sc = ifp->if_softc;
1603 struct mii_data *mii;
1604
1605 mii = device_get_softc(sc->rl_miibus);
1606
1607 RL_LOCK(sc);
1608 mii_mediachg(mii);
1609 RL_UNLOCK(sc);
1610
1611 return (0);
1612}
1613
1614/*
1615 * Report current media status.
1616 */
1617static void
1618rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1619{
1620 struct rl_softc *sc = ifp->if_softc;
1621 struct mii_data *mii;
1622
1623 mii = device_get_softc(sc->rl_miibus);
1624
1625 RL_LOCK(sc);
1626 mii_pollstat(mii);
1627 RL_UNLOCK(sc);
1628 ifmr->ifm_active = mii->mii_media_active;
1629 ifmr->ifm_status = mii->mii_media_status;
1630}
1631
1632static int
1633rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1634{
1635 struct ifreq *ifr = (struct ifreq *)data;
1636 struct mii_data *mii;
1637 struct rl_softc *sc = ifp->if_softc;
1638 int error = 0;
1639
1640 switch (command) {
1641 case SIOCSIFFLAGS:
1642 RL_LOCK(sc);
1643 if (ifp->if_flags & IFF_UP) {
1644 rl_init_locked(sc);
1645 } else {
1646 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1647 rl_stop(sc);
1648 }
1649 RL_UNLOCK(sc);
1650 error = 0;
1651 break;
1652 case SIOCADDMULTI:
1653 case SIOCDELMULTI:
1654 RL_LOCK(sc);
1655 rl_setmulti(sc);
1656 RL_UNLOCK(sc);
1657 error = 0;
1658 break;
1659 case SIOCGIFMEDIA:
1660 case SIOCSIFMEDIA:
1661 mii = device_get_softc(sc->rl_miibus);
1662 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1663 break;
1664 case SIOCSIFCAP:
1665#ifdef DEVICE_POLLING
1666 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1667 !(ifp->if_capenable & IFCAP_POLLING)) {
1668 error = ether_poll_register(rl_poll, ifp);
1669 if (error)
1670 return(error);
1671 RL_LOCK(sc);
1672 /* Disable interrupts */
1673 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1674 ifp->if_capenable |= IFCAP_POLLING;
1675 RL_UNLOCK(sc);
1676 return (error);
1677
1678 }
1679 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1680 ifp->if_capenable & IFCAP_POLLING) {
1681 error = ether_poll_deregister(ifp);
1682 /* Enable interrupts. */
1683 RL_LOCK(sc);
1684 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1685 ifp->if_capenable &= ~IFCAP_POLLING;
1686 RL_UNLOCK(sc);
1687 return (error);
1688 }
1689#endif /* DEVICE_POLLING */
1690 break;
1691 default:
1692 error = ether_ioctl(ifp, command, data);
1693 break;
1694 }
1695
1696 return (error);
1697}
1698
1699static void
1700rl_watchdog(struct rl_softc *sc)
1701{
1702
1703 RL_LOCK_ASSERT(sc);
1704
1705 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
1706 return;
1707
1708 device_printf(sc->rl_dev, "watchdog timeout\n");
1709 sc->rl_ifp->if_oerrors++;
1710
1711 rl_txeof(sc);
1712 rl_rxeof(sc);
1713 rl_init_locked(sc);
1714}
1715
1716/*
1717 * Stop the adapter and free any mbufs allocated to the
1718 * RX and TX lists.
1719 */
1720static void
1721rl_stop(struct rl_softc *sc)
1722{
1723 register int i;
1724 struct ifnet *ifp = sc->rl_ifp;
1725
1726 RL_LOCK_ASSERT(sc);
1727
1728 sc->rl_watchdog_timer = 0;
1729 callout_stop(&sc->rl_stat_callout);
1730 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1731
1732 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1733 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1734 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1735
1736 /*
1737 * Free the TX list buffers.
1738 */
1739 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1740 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1741 bus_dmamap_unload(sc->rl_tag,
1742 sc->rl_cdata.rl_tx_dmamap[i]);
1743 bus_dmamap_destroy(sc->rl_tag,
1744 sc->rl_cdata.rl_tx_dmamap[i]);
1745 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1746 sc->rl_cdata.rl_tx_chain[i] = NULL;
1747 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1748 0x0000000);
1749 }
1750 }
1751}
1752
1753/*
1754 * Device suspend routine. Stop the interface and save some PCI
1755 * settings in case the BIOS doesn't restore them properly on
1756 * resume.
1757 */
1758static int
1759rl_suspend(device_t dev)
1760{
1761 struct rl_softc *sc;
1762
1763 sc = device_get_softc(dev);
1764
1765 RL_LOCK(sc);
1766 rl_stop(sc);
1767 sc->suspended = 1;
1768 RL_UNLOCK(sc);
1769
1770 return (0);
1771}
1772
1773/*
1774 * Device resume routine. Restore some PCI settings in case the BIOS
1775 * doesn't, re-enable busmastering, and restart the interface if
1776 * appropriate.
1777 */
1778static int
1779rl_resume(device_t dev)
1780{
1781 struct rl_softc *sc;
1782 struct ifnet *ifp;
1783
1784 sc = device_get_softc(dev);
1785 ifp = sc->rl_ifp;
1786
1787 RL_LOCK(sc);
1788
1789 /* reinitialize interface if necessary */
1790 if (ifp->if_flags & IFF_UP)
1791 rl_init_locked(sc);
1792
1793 sc->suspended = 0;
1794
1795 RL_UNLOCK(sc);
1796
1797 return (0);
1798}
1799
1800/*
1801 * Stop all chip I/O so that the kernel's probe routines don't
1802 * get confused by errant DMAs when rebooting.
1803 */
1804static int
1805rl_shutdown(device_t dev)
1806{
1807 struct rl_softc *sc;
1808
1809 sc = device_get_softc(dev);
1810
1811 RL_LOCK(sc);
1812 rl_stop(sc);
1813 RL_UNLOCK(sc);
1814
1815 return (0);
1816}
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