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if_my.c (93746) if_my.c (94863)
1/*
2 * Copyright (c) 2002 Myson Technology Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/
27 *
1/*
2 * Copyright (c) 2002 Myson Technology Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/
27 *
28 * $FreeBSD: head/sys/dev/my/if_my.c 93746 2002-04-04 05:22:13Z julian $
28 * $FreeBSD: head/sys/dev/my/if_my.c 94863 2002-04-16 19:31:55Z julian $
29 *
30 * Myson fast ethernet PCI NIC driver
31 */
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/sockio.h>
35#include <sys/mbuf.h>
36#include <sys/malloc.h>

--- 623 unchanged lines hidden (view full) ---

660#ifdef FORCE_AUTONEG_TFOUR
661 if (bootverbose)
662 printf("my%d: forcing on autoneg support for BT4\n",
663 sc->my_unit);
664 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
665 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
666#endif
667 }
29 *
30 * Myson fast ethernet PCI NIC driver
31 */
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/sockio.h>
35#include <sys/mbuf.h>
36#include <sys/malloc.h>

--- 623 unchanged lines hidden (view full) ---

660#ifdef FORCE_AUTONEG_TFOUR
661 if (bootverbose)
662 printf("my%d: forcing on autoneg support for BT4\n",
663 sc->my_unit);
664 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
665 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
666#endif
667 }
668#if 0
669 /* this version did not support 1000M, */
668#if 0 /* this version did not support 1000M, */
670 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
671 if (bootverbose)
672 printf("my%d: 1000Mbps half-duplex mode supported\n",
673 sc->my_unit);
674
675 ifp->if_baudrate = 1000000000;
676 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX, 0, NULL);
677 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX | IFM_HDX,

--- 37 unchanged lines hidden (view full) ---

715 bmcr = my_phy_readreg(sc, PHY_BMCR);
716 bmcr &= ~PHY_BMCR_AUTONEGENBL;
717 my_phy_writereg(sc, PHY_BMCR, bmcr);
718 }
719 printf("my%d: selecting MII, ", sc->my_unit);
720 bmcr = my_phy_readreg(sc, PHY_BMCR);
721 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
722 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
669 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
670 if (bootverbose)
671 printf("my%d: 1000Mbps half-duplex mode supported\n",
672 sc->my_unit);
673
674 ifp->if_baudrate = 1000000000;
675 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX, 0, NULL);
676 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX | IFM_HDX,

--- 37 unchanged lines hidden (view full) ---

714 bmcr = my_phy_readreg(sc, PHY_BMCR);
715 bmcr &= ~PHY_BMCR_AUTONEGENBL;
716 my_phy_writereg(sc, PHY_BMCR, bmcr);
717 }
718 printf("my%d: selecting MII, ", sc->my_unit);
719 bmcr = my_phy_readreg(sc, PHY_BMCR);
720 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
721 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
723 /*
724 * this version did not support 1000M,
725 */
726#if 0
727 if (IFM_SUBTYPE(media) ==
728 IFM_1000_TX) {
722
723#if 0 /* this version did not support 1000M, */
724 if (IFM_SUBTYPE(media) == IFM_1000_TX) {
729 printf("1000Mbps/T4, half-duplex\n");
730 bmcr &= ~PHY_BMCR_SPEEDSEL;
731 bmcr &= ~PHY_BMCR_DUPLEX;
732 bmcr |= PHY_BMCR_1000;
733 }
734#endif
735 if (IFM_SUBTYPE(media) == IFM_100_T4) {
736 printf("100Mbps/T4, half-duplex\n");

--- 134 unchanged lines hidden (view full) ---

871 }
872 bzero(sc, sizeof(struct my_softc));
873 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
874 MY_LOCK(sc);
875
876 /*
877 * Map control/status registers.
878 */
725 printf("1000Mbps/T4, half-duplex\n");
726 bmcr &= ~PHY_BMCR_SPEEDSEL;
727 bmcr &= ~PHY_BMCR_DUPLEX;
728 bmcr |= PHY_BMCR_1000;
729 }
730#endif
731 if (IFM_SUBTYPE(media) == IFM_100_T4) {
732 printf("100Mbps/T4, half-duplex\n");

--- 134 unchanged lines hidden (view full) ---

867 }
868 bzero(sc, sizeof(struct my_softc));
869 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
870 MY_LOCK(sc);
871
872 /*
873 * Map control/status registers.
874 */
879 /*
880 * command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); command
881 * |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
882 * pci_write_config(dev, PCI_COMMAND_STATUS_REG, command &
883 * 0x000000ff, 4); command = pci_read_config(dev,
884 * PCI_COMMAND_STATUS_REG, 4);
885 */
875#if 0
876 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
877 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
878 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4);
879 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
880#endif
886 command = pci_read_config(dev, PCIR_COMMAND, 4);
887 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
888 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4);
889 command = pci_read_config(dev, PCIR_COMMAND, 4);
890
891 if (my_info_tmp->my_did == MTD800ID) {
892 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
893 if (iobase & 0x300)
894 MY_USEIOSPACE = 0;
895 }
896 if (MY_USEIOSPACE) {
897 if (!(command & PCIM_CMD_PORTEN)) {
898 printf("my%d: failed to enable I/O ports!\n", unit);
899 free(sc, M_DEVBUF);
900 error = ENXIO;
901 goto fail;
902 }
903#if 0
881 command = pci_read_config(dev, PCIR_COMMAND, 4);
882 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
883 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4);
884 command = pci_read_config(dev, PCIR_COMMAND, 4);
885
886 if (my_info_tmp->my_did == MTD800ID) {
887 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
888 if (iobase & 0x300)
889 MY_USEIOSPACE = 0;
890 }
891 if (MY_USEIOSPACE) {
892 if (!(command & PCIM_CMD_PORTEN)) {
893 printf("my%d: failed to enable I/O ports!\n", unit);
894 free(sc, M_DEVBUF);
895 error = ENXIO;
896 goto fail;
897 }
898#if 0
904 if (!pci_map_port(config_id, MY_PCI_LOIO,
905 (u_int16_t *)&(sc->my_bhandle))) {
906 printf ("my%d: couldn't map ports\n",
907 unit); error = ENXIO; goto fail;
899 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) {
900 printf("my%d: couldn't map ports\n", unit);
901 error = ENXIO;
902 goto fail;
908 }
909
910 sc->my_btag = I386_BUS_SPACE_IO;
911#endif
912 } else {
913 if (!(command & PCIM_CMD_MEMEN)) {
914 printf("my%d: failed to enable memory mapping!\n",
915 unit);
916 error = ENXIO;
917 goto fail;
918 }
919#if 0
920 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) {
921 printf ("my%d: couldn't map memory\n", unit);
922 error = ENXIO;
923 goto fail;
924 }
903 }
904
905 sc->my_btag = I386_BUS_SPACE_IO;
906#endif
907 } else {
908 if (!(command & PCIM_CMD_MEMEN)) {
909 printf("my%d: failed to enable memory mapping!\n",
910 unit);
911 error = ENXIO;
912 goto fail;
913 }
914#if 0
915 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) {
916 printf ("my%d: couldn't map memory\n", unit);
917 error = ENXIO;
918 goto fail;
919 }
925
926 sc->my_btag = I386_BUS_SPACE_MEM; sc->my_bhandle = vbase;
920 sc->my_btag = I386_BUS_SPACE_MEM;
921 sc->my_bhandle = vbase;
927#endif
928 }
929
930 rid = MY_RID;
931 sc->my_res = bus_alloc_resource(dev, MY_RES, &rid,
932 0, ~0, 1, RF_ACTIVE);
933
934 if (sc->my_res == NULL) {

--- 158 unchanged lines hidden (view full) ---

1093
1094 s = splimp();
1095 sc = device_get_softc(dev);
1096 MY_LOCK(sc);
1097 ifp = &sc->arpcom.ac_if;
1098 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1099 my_stop(sc);
1100
922#endif
923 }
924
925 rid = MY_RID;
926 sc->my_res = bus_alloc_resource(dev, MY_RES, &rid,
927 0, ~0, 1, RF_ACTIVE);
928
929 if (sc->my_res == NULL) {

--- 158 unchanged lines hidden (view full) ---

1088
1089 s = splimp();
1090 sc = device_get_softc(dev);
1091 MY_LOCK(sc);
1092 ifp = &sc->arpcom.ac_if;
1093 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1094 my_stop(sc);
1095
1101 /*
1102 * bus_generic_detach(dev); device_delete_child(dev, sc->rl_miibus);
1103 */
1096#if 0
1097 bus_generic_detach(dev);
1098 device_delete_child(dev, sc->rl_miibus);
1099#endif
1100
1104 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
1105 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
1106 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1101 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
1102 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
1103 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1107 /*
1108 * contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF);
1109 */
1104#if 0
1105 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF);
1106#endif
1110 free(sc, M_DEVBUF);
1111 MY_UNLOCK(sc);
1112 splx(s);
1113 mtx_destroy(&sc->my_mtx);
1114 return (0);
1115}
1116
1117

--- 293 unchanged lines hidden (view full) ---

1411#endif
1412 }
1413 if (status & MY_TI) /* tx interrupt */
1414 my_txeof(sc);
1415 if (status & MY_ETI) /* tx early interrupt */
1416 my_txeof(sc);
1417 if (status & MY_TBU) /* tx buffer unavailable */
1418 my_txeoc(sc);
1107 free(sc, M_DEVBUF);
1108 MY_UNLOCK(sc);
1109 splx(s);
1110 mtx_destroy(&sc->my_mtx);
1111 return (0);
1112}
1113
1114

--- 293 unchanged lines hidden (view full) ---

1408#endif
1409 }
1410 if (status & MY_TI) /* tx interrupt */
1411 my_txeof(sc);
1412 if (status & MY_ETI) /* tx early interrupt */
1413 my_txeof(sc);
1414 if (status & MY_TBU) /* tx buffer unavailable */
1415 my_txeoc(sc);
1419 /*
1420 * 90/1/18 delete if (status & MY_FBE) { my_reset(sc);
1421 * my_init(sc); }
1422 */
1416
1417#if 0 /* 90/1/18 delete */
1418 if (status & MY_FBE) {
1419 my_reset(sc);
1420 my_init(sc);
1421 }
1422#endif
1423
1423 }
1424
1425 /* Re-enable interrupts. */
1426 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1427 if (ifp->if_snd.ifq_head != NULL)
1428 my_start(ifp);
1429 MY_UNLOCK(sc);
1430 return;

--- 156 unchanged lines hidden (view full) ---

1587 * Cancel pending I/O and free all RX/TX buffers.
1588 */
1589 my_stop(sc);
1590 my_reset(sc);
1591
1592 /*
1593 * Set cache alignment and burst length.
1594 */
1424 }
1425
1426 /* Re-enable interrupts. */
1427 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1428 if (ifp->if_snd.ifq_head != NULL)
1429 my_start(ifp);
1430 MY_UNLOCK(sc);
1431 return;

--- 156 unchanged lines hidden (view full) ---

1588 * Cancel pending I/O and free all RX/TX buffers.
1589 */
1590 my_stop(sc);
1591 my_reset(sc);
1592
1593 /*
1594 * Set cache alignment and burst length.
1595 */
1595 /*
1596 * 89/9/1 modify, CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1597 * CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1598 */
1596#if 0 /* 89/9/1 modify, */
1597 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1598 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1599#endif
1599 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1600 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1601 /*
1602 * 89/12/29 add, for mtd891,
1603 */
1604 if (sc->my_info->my_did == MTD891ID) {
1605 MY_SETBIT(sc, MY_BCR, MY_PROG);
1606 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);

--- 92 unchanged lines hidden (view full) ---

1699{
1700 struct my_softc *sc;
1701 u_int16_t advert = 0, ability = 0;
1702
1703 sc = ifp->if_softc;
1704 MY_LOCK(sc);
1705 ifmr->ifm_active = IFM_ETHER;
1706 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1600 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1601 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1602 /*
1603 * 89/12/29 add, for mtd891,
1604 */
1605 if (sc->my_info->my_did == MTD891ID) {
1606 MY_SETBIT(sc, MY_BCR, MY_PROG);
1607 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);

--- 92 unchanged lines hidden (view full) ---

1700{
1701 struct my_softc *sc;
1702 u_int16_t advert = 0, ability = 0;
1703
1704 sc = ifp->if_softc;
1705 MY_LOCK(sc);
1706 ifmr->ifm_active = IFM_ETHER;
1707 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1707 /*
1708 * this version did not support 1000M, if (my_phy_readreg(sc,
1709 * PHY_BMCR) & PHY_BMCR_1000) ifmr->ifm_active =
1710 * IFM_ETHER|IFM_1000TX;
1711 */
1708#if 0 /* this version did not support 1000M, */
1709 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1710 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1711#endif
1712 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1713 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1714 else
1715 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1716 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1717 ifmr->ifm_active |= IFM_FDX;
1718 else
1719 ifmr->ifm_active |= IFM_HDX;
1720
1721 MY_UNLOCK(sc);
1722 return;
1723 }
1724 ability = my_phy_readreg(sc, PHY_LPAR);
1725 advert = my_phy_readreg(sc, PHY_ANAR);
1726
1712 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1713 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1714 else
1715 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1716 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1717 ifmr->ifm_active |= IFM_FDX;
1718 else
1719 ifmr->ifm_active |= IFM_HDX;
1720
1721 MY_UNLOCK(sc);
1722 return;
1723 }
1724 ability = my_phy_readreg(sc, PHY_LPAR);
1725 advert = my_phy_readreg(sc, PHY_ANAR);
1726
1727 /*
1728 * this version did not support 1000M,
1729 */
1730#if 0
1727#if 0 /* this version did not support 1000M, */
1731 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1732 ability2 = my_phy_readreg(sc, PHY_1000SR);
1733 if (ability2 & PHY_1000SR_1000BTXFULL) {
1734 advert = 0;
1735 ability = 0;
1736 ifmr->ifm_active = IFM_ETHER|IFM_1000_TX|IFM_FDX;
1737 } else if (ability & PHY_1000SR_1000BTXHALF) {
1738 advert = 0;

--- 144 unchanged lines hidden --- 		1728 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1729 ability2 = my_phy_readreg(sc, PHY_1000SR);
1730 if (ability2 & PHY_1000SR_1000BTXFULL) {
1731 advert = 0;
1732 ability = 0;
1733 ifmr->ifm_active = IFM_ETHER|IFM_1000_TX|IFM_FDX;
1734 } else if (ability & PHY_1000SR_1000BTXHALF) {
1735 advert = 0;

--- 144 unchanged lines hidden ---