1/*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> |
34__FBSDID("$FreeBSD: head/sys/dev/mii/brgphy.c 215297 2010-11-14 13:26:10Z marius $"); |
35 36/* 37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38 */ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> --- 51 unchanged lines hidden (view full) --- 94 "brgphy", 95 brgphy_methods, 96 sizeof(struct brgphy_softc) 97}; 98 99DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 100 101static int brgphy_service(struct mii_softc *, struct mii_data *, int); |
102static void brgphy_setmedia(struct mii_softc *, int); |
103static void brgphy_status(struct mii_softc *); |
104static void brgphy_mii_phy_auto(struct mii_softc *, int); |
105static void brgphy_reset(struct mii_softc *); 106static void brgphy_enable_loopback(struct mii_softc *); 107static void bcm5401_load_dspcode(struct mii_softc *); 108static void bcm5411_load_dspcode(struct mii_softc *); 109static void bcm54k2_load_dspcode(struct mii_softc *); 110static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 111static void brgphy_fixup_adc_bug(struct mii_softc *); 112static void brgphy_fixup_adjust_trim(struct mii_softc *); --- 51 unchanged lines hidden (view full) --- 164 return (0); 165 return (1); 166} 167 168/* Search for our PHY in the list of known PHYs */ 169static int 170brgphy_probe(device_t dev) 171{ |
172 |
173 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 174} 175 176/* Attach the PHY to the MII bus */ 177static int 178brgphy_attach(device_t dev) 179{ 180 struct brgphy_softc *bsc; 181 struct bge_softc *bge_sc = NULL; 182 struct bce_softc *bce_sc = NULL; 183 struct mii_softc *sc; 184 struct mii_attach_args *ma; 185 struct mii_data *mii; 186 struct ifnet *ifp; |
187 188 bsc = device_get_softc(dev); 189 sc = &bsc->mii_sc; 190 ma = device_get_ivars(dev); 191 sc->mii_dev = device_get_parent(dev); 192 mii = ma->mii_data; 193 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 194 195 /* Initialize mii_softc structure */ 196 sc->mii_flags = miibus_get_flags(dev); 197 sc->mii_inst = mii->mii_instance++; 198 sc->mii_phy = ma->mii_phyno; 199 sc->mii_service = brgphy_service; 200 sc->mii_pdata = mii; 201 202 /* 203 * At least some variants wedge when isolating, at least some also 204 * don't support loopback. 205 */ |
206 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP | MIIF_NOMANPAUSE; |
207 208 /* Initialize brgphy_softc structure */ 209 bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 210 bsc->mii_model = MII_MODEL(ma->mii_id2); 211 bsc->mii_rev = MII_REV(ma->mii_id2); 212 bsc->serdes_flags = 0; 213 |
214 if (bootverbose) 215 device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n", 216 bsc->mii_oui, bsc->mii_model, bsc->mii_rev); 217 218 /* Handle any special cases based on the PHY ID */ 219 switch (bsc->mii_oui) { 220 case MII_OUI_BROADCOM: 221 case MII_OUI_BROADCOM2: --- 49 unchanged lines hidden (view full) --- 271 /* Todo: Need to add additional controllers such as 5906 & 5787F */ 272 /* The 590x chips are 10/100 only. */ 273 if (bge_sc && 274 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 275 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 276 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2 || 277 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906 || 278 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906M)) { |
279 ma->mii_capmask &= ~BMSR_EXTSTAT; |
280 } 281 282 brgphy_reset(sc); 283 284 /* Read the PHY's capabilities. */ 285 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 286 if (sc->mii_capabilities & BMSR_EXTSTAT) 287 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 288 device_printf(dev, " "); 289 290#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 291 292 /* Add the supported media types */ 293 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { |
294 mii_phy_add_media(sc); 295 printf("\n"); |
296 } else { |
297 sc->mii_anegticks = MII_ANEGTICKS_GIGE; |
298 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 299 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 300 printf("1000baseSX-FDX, "); 301 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */ 302 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) { 303 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0); 304 printf("2500baseSX-FDX, "); 305 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc && --- 5 unchanged lines hidden (view full) --- 311 * complete. This happens with a specific chip id 312 * only and when the 1000baseSX-FDX is the only 313 * mode. Workaround this issue since it's unlikely 314 * to be ever addressed. 315 */ 316 printf("auto-neg workaround, "); 317 bsc->serdes_flags |= BRGPHY_NOANWAIT; 318 } |
319 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 320 printf("auto\n"); |
321 } 322 |
323#undef ADD 324 MIIBUS_MEDIAINIT(sc->mii_dev); 325 return (0); 326} 327 328static int 329brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 330{ --- 9 unchanged lines hidden (view full) --- 340 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 341 break; 342 343 /* Todo: Why is this here? Is it really needed? */ 344 brgphy_reset(sc); /* XXX hardware bug work-around */ 345 346 switch (IFM_SUBTYPE(ife->ifm_media)) { 347 case IFM_AUTO: |
348 brgphy_mii_phy_auto(sc, ife->ifm_media); |
349 break; 350 case IFM_2500_SX: 351 case IFM_1000_SX: 352 case IFM_1000_T: 353 case IFM_100_TX: 354 case IFM_10_T: |
355 brgphy_setmedia(sc, ife->ifm_media); |
356 break; 357 default: 358 return (EINVAL); 359 } 360 break; 361 case MII_TICK: 362 /* Bail if the interface isn't up. */ 363 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) --- 5 unchanged lines hidden (view full) --- 369 sc->mii_ticks = 0; 370 break; 371 } 372 373 /* 374 * Check to see if we have link. If we do, we don't 375 * need to restart the autonegotiation process. 376 */ |
377 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); |
378 if (val & BMSR_LINK) { 379 sc->mii_ticks = 0; /* Reset autoneg timer. */ 380 break; 381 } 382 383 /* Announce link loss right after it happens. */ 384 if (sc->mii_ticks++ == 0) 385 break; 386 387 /* Only retry autonegotiation every mii_anegticks seconds. */ 388 if (sc->mii_ticks <= sc->mii_anegticks) 389 break; 390 391 392 /* Retry autonegotiation */ 393 sc->mii_ticks = 0; |
394 brgphy_mii_phy_auto(sc, ife->ifm_media); |
395 break; 396 } 397 398 /* Update the media status. */ 399 brgphy_status(sc); 400 401 /* 402 * Callback if something changed. Note that we need to poke --- 25 unchanged lines hidden (view full) --- 428 case MII_OUI_xxBROADCOM_ALT1: 429 break; 430 } 431 } 432 mii_phy_update(sc, cmd); 433 return (0); 434} 435 |
436/****************************************************************************/ 437/* Sets the PHY link speed. */ 438/* */ 439/* Returns: */ 440/* None */ 441/****************************************************************************/ 442static void |
443brgphy_setmedia(struct mii_softc *sc, int media) |
444{ |
445 int bmcr = 0, gig; 446 |
447 switch (IFM_SUBTYPE(media)) { 448 case IFM_2500_SX: 449 break; 450 case IFM_1000_SX: 451 case IFM_1000_T: 452 bmcr = BRGPHY_S1000; 453 break; 454 case IFM_100_TX: 455 bmcr = BRGPHY_S100; 456 break; 457 case IFM_10_T: 458 default: 459 bmcr = BRGPHY_S10; 460 break; 461 } 462 |
463 if ((media & IFM_GMASK) == IFM_FDX) { 464 bmcr |= BRGPHY_BMCR_FDX; 465 gig = BRGPHY_1000CTL_AFD; 466 } else { 467 gig = BRGPHY_1000CTL_AHD; 468 } 469 |
470 /* Force loopback to disconnect PHY from Ethernet medium. */ |
471 brgphy_enable_loopback(sc); 472 |
473 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); |
474 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); |
475 |
476 if (IFM_SUBTYPE(media) != IFM_1000_T && 477 IFM_SUBTYPE(media) != IFM_1000_SX) { 478 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 479 return; 480 } |
481 |
482 if (IFM_SUBTYPE(media) == IFM_1000_T) { 483 gig |= BRGPHY_1000CTL_MSE; 484 if ((media & IFM_ETH_MASTER) != 0) 485 gig |= BRGPHY_1000CTL_MSC; 486 } |
487 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); |
488 PHY_WRITE(sc, BRGPHY_MII_BMCR, 489 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); |
490} 491 492/****************************************************************************/ 493/* Set the media status based on the PHY settings. */ |
494/* */ 495/* Returns: */ 496/* None */ 497/****************************************************************************/ 498static void 499brgphy_status(struct mii_softc *sc) 500{ 501 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 502 struct mii_data *mii = sc->mii_pdata; |
503 int aux, bmcr, bmsr, val, xstat; 504 u_int flowstat; |
505 |
506 mii->mii_media_status = IFM_AVALID; 507 mii->mii_media_active = IFM_ETHER; 508 509 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 510 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); |
511 |
512 if (bmcr & BRGPHY_BMCR_LOOP) { |
513 mii->mii_media_active |= IFM_LOOP; 514 } 515 |
516 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 517 (bmsr & BRGPHY_BMSR_ACOMP) == 0 && 518 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) { 519 /* Erg, still trying, I guess... */ 520 mii->mii_media_active |= IFM_NONE; |
521 return; |
522 } 523 |
524 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { |
525 /* 526 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS 527 * wedges at least the PHY of BCM5704 (but not others). 528 */ 529 flowstat = mii_phy_flowstatus(sc); 530 xstat = PHY_READ(sc, BRGPHY_MII_1000STS); |
531 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 532 533 /* If copper link is up, get the negotiated speed/duplex. */ 534 if (aux & BRGPHY_AUXSTS_LINK) { 535 mii->mii_media_status |= IFM_ACTIVE; 536 switch (aux & BRGPHY_AUXSTS_AN_RES) { 537 case BRGPHY_RES_1000FD: 538 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; --- 7 unchanged lines hidden (view full) --- 546 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 547 case BRGPHY_RES_10FD: 548 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 549 case BRGPHY_RES_10HD: 550 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 551 default: 552 mii->mii_media_active |= IFM_NONE; break; 553 } |
554 555 if ((mii->mii_media_active & IFM_FDX) != 0) 556 mii->mii_media_active |= flowstat; 557 558 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T && 559 (xstat & BRGPHY_1000STS_MSR) != 0) 560 mii->mii_media_active |= IFM_ETH_MASTER; |
561 } 562 } else { |
563 /* Todo: Add support for flow control. */ |
564 /* If serdes link is up, get the negotiated speed/duplex. */ 565 if (bmsr & BRGPHY_BMSR_LINK) { 566 mii->mii_media_status |= IFM_ACTIVE; 567 } 568 569 /* Check the link speed/duplex based on the PHY type. */ 570 if (bsc->serdes_flags & BRGPHY_5706S) { 571 mii->mii_media_active |= IFM_1000_SX; 572 573 /* If autoneg enabled, read negotiated duplex settings */ 574 if (bmcr & BRGPHY_BMCR_AUTOEN) { 575 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 576 if (val & BRGPHY_SERDES_ANAR_FDX) 577 mii->mii_media_active |= IFM_FDX; 578 else 579 mii->mii_media_active |= IFM_HDX; 580 } |
581 } else if (bsc->serdes_flags & BRGPHY_5708S) { 582 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 583 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 584 585 /* Check for MRBE auto-negotiated speed results. */ 586 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 587 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 588 mii->mii_media_active |= IFM_10_FL; break; --- 5 unchanged lines hidden (view full) --- 594 mii->mii_media_active |= IFM_2500_SX; break; 595 } 596 597 /* Check for MRBE auto-negotiated duplex results. */ 598 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 599 mii->mii_media_active |= IFM_FDX; 600 else 601 mii->mii_media_active |= IFM_HDX; |
602 } else if (bsc->serdes_flags & BRGPHY_5709S) { |
603 /* Select GP Status Block of the AN MMD, get autoneg results. */ 604 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 605 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 606 607 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 608 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 609 610 /* Check for MRBE auto-negotiated speed results. */ --- 9 unchanged lines hidden (view full) --- 620 } 621 622 /* Check for MRBE auto-negotiated duplex results. */ 623 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 624 mii->mii_media_active |= IFM_FDX; 625 else 626 mii->mii_media_active |= IFM_HDX; 627 } |
628 } |
629} 630 631static void |
632brgphy_mii_phy_auto(struct mii_softc *sc, int media) |
633{ 634 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; |
635 int anar, ktcr = 0; |
636 637 brgphy_reset(sc); 638 |
639 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { |
640 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 641 if ((media & IFM_FLOW) != 0 || 642 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 643 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP; 644 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar); |
645 } else { |
646 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX; 647 if ((media & IFM_FLOW) != 0 || 648 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 649 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE; 650 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar); |
651 } 652 |
653 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 654 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701) 655 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 656 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 657 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); 658 |
659 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN | 660 BRGPHY_BMCR_STARTNEG); |
661 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); |
662} 663 |
664/* Enable loopback to force the link down. */ 665static void 666brgphy_enable_loopback(struct mii_softc *sc) 667{ 668 int i; 669 670 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 671 for (i = 0; i < 15000; i++) { --- 178 unchanged lines hidden (view full) --- 850 { 0, 0 }, 851 }; 852 int i; 853 854 for (i = 0; dspcode[i].reg != 0; i++) 855 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 856} 857 |
858static void 859brgphy_fixup_disable_early_dac(struct mii_softc *sc) 860{ 861 uint32_t val; 862 863 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 864 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 865 val &= ~(1 << 8); 866 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 867 868} 869 |
870static void 871brgphy_ethernet_wirespeed(struct mii_softc *sc) 872{ 873 uint32_t val; 874 875 /* Enable Ethernet@WireSpeed. */ 876 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 877 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 878 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 879} 880 |
881static void 882brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 883{ 884 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 885 uint32_t val; 886 887 /* Set or clear jumbo frame settings in the PHY. */ 888 if (mtu > ETHER_MAX_LEN) { --- 24 unchanged lines hidden (view full) --- 913 914static void 915brgphy_reset(struct mii_softc *sc) 916{ 917 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 918 struct bge_softc *bge_sc = NULL; 919 struct bce_softc *bce_sc = NULL; 920 struct ifnet *ifp; |
921 int val; |
922 923 /* Perform a standard PHY reset. */ 924 mii_phy_reset(sc); 925 926 /* Handle any PHY specific procedures following the reset. */ 927 switch (bsc->mii_oui) { 928 case MII_OUI_BROADCOM: 929 break; --- 23 unchanged lines hidden (view full) --- 953 954 /* Find the driver associated with this PHY. */ 955 if (strcmp(ifp->if_dname, "bge") == 0) { 956 bge_sc = ifp->if_softc; 957 } else if (strcmp(ifp->if_dname, "bce") == 0) { 958 bce_sc = ifp->if_softc; 959 } 960 |
961 if (bge_sc) { 962 /* Fix up various bugs */ 963 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG) 964 brgphy_fixup_5704_a0_bug(sc); 965 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG) 966 brgphy_fixup_adc_bug(sc); 967 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM) 968 brgphy_fixup_adjust_trim(sc); --- 14 unchanged lines hidden (view full) --- 983 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 984 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 985 ~BRGPHY_PHY_EXTCTL_3_LED); 986 } 987 988 /* Adjust output voltage (From Linux driver) */ 989 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 990 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); |
991 } else if (bce_sc) { |
992 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 993 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 994 995 /* Store autoneg capabilities/results in digital block (Page 0) */ 996 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 997 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 998 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 999 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); --- 74 unchanged lines hidden (view full) --- 1074 /* Enable MRBE speed autoneg. */ 1075 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1076 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1077 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1078 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1079 1080 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1081 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); |
1082 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1083 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1084 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1085 brgphy_fixup_disable_early_dac(sc); 1086 1087 brgphy_jumbo_settings(sc, ifp->if_mtu); 1088 brgphy_ethernet_wirespeed(sc); 1089 } else { 1090 brgphy_fixup_ber_bug(sc); 1091 brgphy_jumbo_settings(sc, ifp->if_mtu); 1092 brgphy_ethernet_wirespeed(sc); 1093 } |
1094 } 1095} |