1/*-
2 * Copyright (c) 2000
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2000
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
|
34__FBSDID("$FreeBSD: head/sys/dev/mii/brgphy.c 146413 2005-05-19 21:08:59Z ps $");
| 34__FBSDID("$FreeBSD: head/sys/dev/mii/brgphy.c 150763 2005-09-30 19:39:27Z imp $");
|
35
36/*
37 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always
38 * 1000mbps; all we need to negotiate here is full or half duplex.
39 */
40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/kernel.h>
44#include <sys/module.h>
45#include <sys/socket.h>
46#include <sys/bus.h>
47
48#include <machine/clock.h>
49
50#include <net/if.h>
51#include <net/if_media.h>
52
53#include <dev/mii/mii.h>
54#include <dev/mii/miivar.h>
55#include "miidevs.h"
56
57#include <dev/mii/brgphyreg.h>
58#include <net/if_arp.h>
59#include <machine/bus.h>
60#include <dev/bge/if_bgereg.h>
61
62#include <dev/pci/pcireg.h>
63#include <dev/pci/pcivar.h>
64
65#include "miibus_if.h"
66
67static int brgphy_probe(device_t);
68static int brgphy_attach(device_t);
69
70static device_method_t brgphy_methods[] = {
71 /* device interface */
72 DEVMETHOD(device_probe, brgphy_probe),
73 DEVMETHOD(device_attach, brgphy_attach),
74 DEVMETHOD(device_detach, mii_phy_detach),
75 DEVMETHOD(device_shutdown, bus_generic_shutdown),
76 { 0, 0 }
77};
78
79static devclass_t brgphy_devclass;
80
81static driver_t brgphy_driver = {
82 "brgphy",
83 brgphy_methods,
84 sizeof(struct mii_softc)
85};
86
87DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
88
89static int brgphy_service(struct mii_softc *, struct mii_data *, int);
90static void brgphy_status(struct mii_softc *);
91static int brgphy_mii_phy_auto(struct mii_softc *);
92static void brgphy_reset(struct mii_softc *);
93static void brgphy_loop(struct mii_softc *);
94static void bcm5401_load_dspcode(struct mii_softc *);
95static void bcm5411_load_dspcode(struct mii_softc *);
96static void bcm5703_load_dspcode(struct mii_softc *);
97static void bcm5750_load_dspcode(struct mii_softc *);
98static int brgphy_mii_model;
99
100static int
| 35
36/*
37 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always
38 * 1000mbps; all we need to negotiate here is full or half duplex.
39 */
40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/kernel.h>
44#include <sys/module.h>
45#include <sys/socket.h>
46#include <sys/bus.h>
47
48#include <machine/clock.h>
49
50#include <net/if.h>
51#include <net/if_media.h>
52
53#include <dev/mii/mii.h>
54#include <dev/mii/miivar.h>
55#include "miidevs.h"
56
57#include <dev/mii/brgphyreg.h>
58#include <net/if_arp.h>
59#include <machine/bus.h>
60#include <dev/bge/if_bgereg.h>
61
62#include <dev/pci/pcireg.h>
63#include <dev/pci/pcivar.h>
64
65#include "miibus_if.h"
66
67static int brgphy_probe(device_t);
68static int brgphy_attach(device_t);
69
70static device_method_t brgphy_methods[] = {
71 /* device interface */
72 DEVMETHOD(device_probe, brgphy_probe),
73 DEVMETHOD(device_attach, brgphy_attach),
74 DEVMETHOD(device_detach, mii_phy_detach),
75 DEVMETHOD(device_shutdown, bus_generic_shutdown),
76 { 0, 0 }
77};
78
79static devclass_t brgphy_devclass;
80
81static driver_t brgphy_driver = {
82 "brgphy",
83 brgphy_methods,
84 sizeof(struct mii_softc)
85};
86
87DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
88
89static int brgphy_service(struct mii_softc *, struct mii_data *, int);
90static void brgphy_status(struct mii_softc *);
91static int brgphy_mii_phy_auto(struct mii_softc *);
92static void brgphy_reset(struct mii_softc *);
93static void brgphy_loop(struct mii_softc *);
94static void bcm5401_load_dspcode(struct mii_softc *);
95static void bcm5411_load_dspcode(struct mii_softc *);
96static void bcm5703_load_dspcode(struct mii_softc *);
97static void bcm5750_load_dspcode(struct mii_softc *);
98static int brgphy_mii_model;
99
100static int
|
101brgphy_probe(dev)
102 device_t dev;
| 101brgphy_probe(device_t dev)
|
103{
104 struct mii_attach_args *ma;
105
106 ma = device_get_ivars(dev);
107
108 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
109 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) {
110 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400);
111 return(0);
112 }
113
114 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
115 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) {
116 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401);
117 return(0);
118 }
119
120 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
121 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) {
122 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411);
123 return(0);
124 }
125
126 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
127 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) {
128 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701);
129 return(0);
130 }
131
132 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
133 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) {
134 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703);
135 return(0);
136 }
137
138 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
139 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) {
140 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704);
141 return(0);
142 }
143
144 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
145 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705) {
146 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5705);
147 return(0);
148 }
149
150 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
151 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5750) {
152 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5750);
153 return(0);
154 }
155
156 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
157 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5714) {
158 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5714);
159 return(0);
160 }
161
162 return(ENXIO);
163}
164
165static int
| 102{
103 struct mii_attach_args *ma;
104
105 ma = device_get_ivars(dev);
106
107 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
108 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) {
109 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400);
110 return(0);
111 }
112
113 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
114 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) {
115 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401);
116 return(0);
117 }
118
119 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
120 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) {
121 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411);
122 return(0);
123 }
124
125 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
126 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) {
127 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701);
128 return(0);
129 }
130
131 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
132 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) {
133 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703);
134 return(0);
135 }
136
137 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
138 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) {
139 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704);
140 return(0);
141 }
142
143 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
144 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705) {
145 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5705);
146 return(0);
147 }
148
149 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
150 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5750) {
151 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5750);
152 return(0);
153 }
154
155 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
156 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5714) {
157 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5714);
158 return(0);
159 }
160
161 return(ENXIO);
162}
163
164static int
|
166brgphy_attach(dev)
167 device_t dev;
| 165brgphy_attach(device_t dev)
|
168{
169 struct mii_softc *sc;
170 struct mii_attach_args *ma;
171 struct mii_data *mii;
172 const char *sep = "";
173 struct bge_softc *bge_sc;
174 int fast_ether_only = FALSE;
175
176 sc = device_get_softc(dev);
177 ma = device_get_ivars(dev);
178 sc->mii_dev = device_get_parent(dev);
179 mii = device_get_softc(sc->mii_dev);
180 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
181
182 sc->mii_inst = mii->mii_instance;
183 sc->mii_phy = ma->mii_phyno;
184 sc->mii_service = brgphy_service;
185 sc->mii_pdata = mii;
186
187 sc->mii_flags |= MIIF_NOISOLATE;
188 mii->mii_instance++;
189
190#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
191#define PRINT(s) printf("%s%s", sep, s); sep = ", "
192
193 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
194 BMCR_ISO);
195#if 0
196 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
197 BMCR_LOOP|BMCR_S100);
198#endif
199
200 brgphy_mii_model = MII_MODEL(ma->mii_id2);
201 brgphy_reset(sc);
202
203
204 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
205 sc->mii_capabilities &= ~BMSR_ANEG;
206 device_printf(dev, " ");
207 mii_add_media(sc);
208
209 /* The 590x chips are 10/100 only. */
210
211 bge_sc = mii->mii_ifp->if_softc;
212
213 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 &&
214 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID &&
215 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 ||
216 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2))
217 fast_ether_only = TRUE;
218
219 if (fast_ether_only == FALSE) {
220 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0,
221 sc->mii_inst), BRGPHY_BMCR_FDX);
222 PRINT(", 1000baseTX");
223 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T,
224 IFM_FDX, sc->mii_inst), 0);
225 PRINT("1000baseTX-FDX");
226 }
227
228 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
229 PRINT("auto");
230
231 printf("\n");
232#undef ADD
233#undef PRINT
234
235 MIIBUS_MEDIAINIT(sc->mii_dev);
236 return(0);
237}
238
239static int
| 166{
167 struct mii_softc *sc;
168 struct mii_attach_args *ma;
169 struct mii_data *mii;
170 const char *sep = "";
171 struct bge_softc *bge_sc;
172 int fast_ether_only = FALSE;
173
174 sc = device_get_softc(dev);
175 ma = device_get_ivars(dev);
176 sc->mii_dev = device_get_parent(dev);
177 mii = device_get_softc(sc->mii_dev);
178 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
179
180 sc->mii_inst = mii->mii_instance;
181 sc->mii_phy = ma->mii_phyno;
182 sc->mii_service = brgphy_service;
183 sc->mii_pdata = mii;
184
185 sc->mii_flags |= MIIF_NOISOLATE;
186 mii->mii_instance++;
187
188#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
189#define PRINT(s) printf("%s%s", sep, s); sep = ", "
190
191 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
192 BMCR_ISO);
193#if 0
194 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
195 BMCR_LOOP|BMCR_S100);
196#endif
197
198 brgphy_mii_model = MII_MODEL(ma->mii_id2);
199 brgphy_reset(sc);
200
201
202 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
203 sc->mii_capabilities &= ~BMSR_ANEG;
204 device_printf(dev, " ");
205 mii_add_media(sc);
206
207 /* The 590x chips are 10/100 only. */
208
209 bge_sc = mii->mii_ifp->if_softc;
210
211 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 &&
212 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID &&
213 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 ||
214 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2))
215 fast_ether_only = TRUE;
216
217 if (fast_ether_only == FALSE) {
218 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0,
219 sc->mii_inst), BRGPHY_BMCR_FDX);
220 PRINT(", 1000baseTX");
221 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T,
222 IFM_FDX, sc->mii_inst), 0);
223 PRINT("1000baseTX-FDX");
224 }
225
226 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
227 PRINT("auto");
228
229 printf("\n");
230#undef ADD
231#undef PRINT
232
233 MIIBUS_MEDIAINIT(sc->mii_dev);
234 return(0);
235}
236
237static int
|
240brgphy_service(sc, mii, cmd)
241 struct mii_softc *sc;
242 struct mii_data *mii;
243 int cmd;
| 238brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
|
244{
245 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
246 int reg, speed, gig;
247
248 switch (cmd) {
249 case MII_POLLSTAT:
250 /*
251 * If we're not polling our PHY instance, just return.
252 */
253 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
254 return (0);
255 break;
256
257 case MII_MEDIACHG:
258 /*
259 * If the media indicates a different PHY instance,
260 * isolate ourselves.
261 */
262 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
263 reg = PHY_READ(sc, MII_BMCR);
264 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
265 return (0);
266 }
267
268 /*
269 * If the interface is not up, don't do anything.
270 */
271 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
272 break;
273
274 brgphy_reset(sc); /* XXX hardware bug work-around */
275
276 switch (IFM_SUBTYPE(ife->ifm_media)) {
277 case IFM_AUTO:
278#ifdef foo
279 /*
280 * If we're already in auto mode, just return.
281 */
282 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
283 return (0);
284#endif
285 (void) brgphy_mii_phy_auto(sc);
286 break;
287 case IFM_1000_T:
288 speed = BRGPHY_S1000;
289 goto setit;
290 case IFM_100_TX:
291 speed = BRGPHY_S100;
292 goto setit;
293 case IFM_10_T:
294 speed = BRGPHY_S10;
295setit:
296 brgphy_loop(sc);
297 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
298 speed |= BRGPHY_BMCR_FDX;
299 gig = BRGPHY_1000CTL_AFD;
300 } else {
301 gig = BRGPHY_1000CTL_AHD;
302 }
303
304 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
305 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed);
306 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
307
308 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
309 break;
310
311 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
312 PHY_WRITE(sc, BRGPHY_MII_BMCR,
313 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG);
314
315 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701)
316 break;
317
318 /*
319 * When settning the link manually, one side must
320 * be the master and the other the slave. However
321 * ifmedia doesn't give us a good way to specify
322 * this, so we fake it by using one of the LINK
323 * flags. If LINK0 is set, we program the PHY to
324 * be a master, otherwise it's a slave.
325 */
326 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
327 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
328 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC);
329 } else {
330 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
331 gig|BRGPHY_1000CTL_MSE);
332 }
333 break;
334#ifdef foo
335 case IFM_NONE:
336 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
337 break;
338#endif
339 case IFM_100_T4:
340 default:
341 return (EINVAL);
342 }
343 break;
344
345 case MII_TICK:
346 /*
347 * If we're not currently selected, just return.
348 */
349 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
350 return (0);
351
352 /*
353 * Is the interface even up?
354 */
355 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
356 return (0);
357
358 /*
359 * Only used for autonegotiation.
360 */
361 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
362 break;
363
364 /*
365 * Check to see if we have link. If we do, we don't
366 * need to restart the autonegotiation process. Read
367 * the BMSR twice in case it's latched.
368 */
369 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS);
370 if (reg & BRGPHY_AUXSTS_LINK)
371 break;
372
373 /*
374 * Only retry autonegotiation every 5 seconds.
375 */
376 if (++sc->mii_ticks <= 5)
377 break;
378
379 sc->mii_ticks = 0;
380 brgphy_mii_phy_auto(sc);
381 return (0);
382 }
383
384 /* Update the media status. */
385 brgphy_status(sc);
386
387 /*
388 * Callback if something changed. Note that we need to poke
389 * the DSP on the Broadcom PHYs if the media changes.
390 *
391 */
392 if (sc->mii_media_active != mii->mii_media_active ||
393 sc->mii_media_status != mii->mii_media_status ||
394 cmd == MII_MEDIACHG) {
395 switch (brgphy_mii_model) {
396 case MII_MODEL_xxBROADCOM_BCM5401:
397 bcm5401_load_dspcode(sc);
398 break;
399 case MII_MODEL_xxBROADCOM_BCM5411:
400 bcm5411_load_dspcode(sc);
401 break;
402 }
403 }
404 mii_phy_update(sc, cmd);
405 return (0);
406}
407
408static void
| 239{
240 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
241 int reg, speed, gig;
242
243 switch (cmd) {
244 case MII_POLLSTAT:
245 /*
246 * If we're not polling our PHY instance, just return.
247 */
248 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
249 return (0);
250 break;
251
252 case MII_MEDIACHG:
253 /*
254 * If the media indicates a different PHY instance,
255 * isolate ourselves.
256 */
257 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
258 reg = PHY_READ(sc, MII_BMCR);
259 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
260 return (0);
261 }
262
263 /*
264 * If the interface is not up, don't do anything.
265 */
266 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
267 break;
268
269 brgphy_reset(sc); /* XXX hardware bug work-around */
270
271 switch (IFM_SUBTYPE(ife->ifm_media)) {
272 case IFM_AUTO:
273#ifdef foo
274 /*
275 * If we're already in auto mode, just return.
276 */
277 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
278 return (0);
279#endif
280 (void) brgphy_mii_phy_auto(sc);
281 break;
282 case IFM_1000_T:
283 speed = BRGPHY_S1000;
284 goto setit;
285 case IFM_100_TX:
286 speed = BRGPHY_S100;
287 goto setit;
288 case IFM_10_T:
289 speed = BRGPHY_S10;
290setit:
291 brgphy_loop(sc);
292 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
293 speed |= BRGPHY_BMCR_FDX;
294 gig = BRGPHY_1000CTL_AFD;
295 } else {
296 gig = BRGPHY_1000CTL_AHD;
297 }
298
299 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
300 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed);
301 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
302
303 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
304 break;
305
306 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
307 PHY_WRITE(sc, BRGPHY_MII_BMCR,
308 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG);
309
310 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701)
311 break;
312
313 /*
314 * When settning the link manually, one side must
315 * be the master and the other the slave. However
316 * ifmedia doesn't give us a good way to specify
317 * this, so we fake it by using one of the LINK
318 * flags. If LINK0 is set, we program the PHY to
319 * be a master, otherwise it's a slave.
320 */
321 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
322 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
323 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC);
324 } else {
325 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
326 gig|BRGPHY_1000CTL_MSE);
327 }
328 break;
329#ifdef foo
330 case IFM_NONE:
331 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
332 break;
333#endif
334 case IFM_100_T4:
335 default:
336 return (EINVAL);
337 }
338 break;
339
340 case MII_TICK:
341 /*
342 * If we're not currently selected, just return.
343 */
344 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
345 return (0);
346
347 /*
348 * Is the interface even up?
349 */
350 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
351 return (0);
352
353 /*
354 * Only used for autonegotiation.
355 */
356 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
357 break;
358
359 /*
360 * Check to see if we have link. If we do, we don't
361 * need to restart the autonegotiation process. Read
362 * the BMSR twice in case it's latched.
363 */
364 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS);
365 if (reg & BRGPHY_AUXSTS_LINK)
366 break;
367
368 /*
369 * Only retry autonegotiation every 5 seconds.
370 */
371 if (++sc->mii_ticks <= 5)
372 break;
373
374 sc->mii_ticks = 0;
375 brgphy_mii_phy_auto(sc);
376 return (0);
377 }
378
379 /* Update the media status. */
380 brgphy_status(sc);
381
382 /*
383 * Callback if something changed. Note that we need to poke
384 * the DSP on the Broadcom PHYs if the media changes.
385 *
386 */
387 if (sc->mii_media_active != mii->mii_media_active ||
388 sc->mii_media_status != mii->mii_media_status ||
389 cmd == MII_MEDIACHG) {
390 switch (brgphy_mii_model) {
391 case MII_MODEL_xxBROADCOM_BCM5401:
392 bcm5401_load_dspcode(sc);
393 break;
394 case MII_MODEL_xxBROADCOM_BCM5411:
395 bcm5411_load_dspcode(sc);
396 break;
397 }
398 }
399 mii_phy_update(sc, cmd);
400 return (0);
401}
402
403static void
|
409brgphy_status(sc)
410 struct mii_softc *sc;
| 404brgphy_status(struct mii_softc *sc)
|
411{
412 struct mii_data *mii = sc->mii_pdata;
413 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
414 int bmsr, bmcr;
415
416 mii->mii_media_status = IFM_AVALID;
417 mii->mii_media_active = IFM_ETHER;
418
419 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
420 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK)
421 mii->mii_media_status |= IFM_ACTIVE;
422
423 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
424
425 if (bmcr & BRGPHY_BMCR_LOOP)
426 mii->mii_media_active |= IFM_LOOP;
427
428 if (bmcr & BRGPHY_BMCR_AUTOEN) {
429 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) {
430 /* Erg, still trying, I guess... */
431 mii->mii_media_active |= IFM_NONE;
432 return;
433 }
434
435 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) &
436 BRGPHY_AUXSTS_AN_RES) {
437 case BRGPHY_RES_1000FD:
438 mii->mii_media_active |= IFM_1000_T | IFM_FDX;
439 break;
440 case BRGPHY_RES_1000HD:
441 mii->mii_media_active |= IFM_1000_T | IFM_HDX;
442 break;
443 case BRGPHY_RES_100FD:
444 mii->mii_media_active |= IFM_100_TX | IFM_FDX;
445 break;
446 case BRGPHY_RES_100T4:
447 mii->mii_media_active |= IFM_100_T4;
448 break;
449 case BRGPHY_RES_100HD:
450 mii->mii_media_active |= IFM_100_TX | IFM_HDX;
451 break;
452 case BRGPHY_RES_10FD:
453 mii->mii_media_active |= IFM_10_T | IFM_FDX;
454 break;
455 case BRGPHY_RES_10HD:
456 mii->mii_media_active |= IFM_10_T | IFM_HDX;
457 break;
458 default:
459 mii->mii_media_active |= IFM_NONE;
460 break;
461 }
462 return;
463 }
464
465 mii->mii_media_active = ife->ifm_media;
466
467 return;
468}
469
470
471static int
| 405{
406 struct mii_data *mii = sc->mii_pdata;
407 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
408 int bmsr, bmcr;
409
410 mii->mii_media_status = IFM_AVALID;
411 mii->mii_media_active = IFM_ETHER;
412
413 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
414 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK)
415 mii->mii_media_status |= IFM_ACTIVE;
416
417 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
418
419 if (bmcr & BRGPHY_BMCR_LOOP)
420 mii->mii_media_active |= IFM_LOOP;
421
422 if (bmcr & BRGPHY_BMCR_AUTOEN) {
423 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) {
424 /* Erg, still trying, I guess... */
425 mii->mii_media_active |= IFM_NONE;
426 return;
427 }
428
429 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) &
430 BRGPHY_AUXSTS_AN_RES) {
431 case BRGPHY_RES_1000FD:
432 mii->mii_media_active |= IFM_1000_T | IFM_FDX;
433 break;
434 case BRGPHY_RES_1000HD:
435 mii->mii_media_active |= IFM_1000_T | IFM_HDX;
436 break;
437 case BRGPHY_RES_100FD:
438 mii->mii_media_active |= IFM_100_TX | IFM_FDX;
439 break;
440 case BRGPHY_RES_100T4:
441 mii->mii_media_active |= IFM_100_T4;
442 break;
443 case BRGPHY_RES_100HD:
444 mii->mii_media_active |= IFM_100_TX | IFM_HDX;
445 break;
446 case BRGPHY_RES_10FD:
447 mii->mii_media_active |= IFM_10_T | IFM_FDX;
448 break;
449 case BRGPHY_RES_10HD:
450 mii->mii_media_active |= IFM_10_T | IFM_HDX;
451 break;
452 default:
453 mii->mii_media_active |= IFM_NONE;
454 break;
455 }
456 return;
457 }
458
459 mii->mii_media_active = ife->ifm_media;
460
461 return;
462}
463
464
465static int
|
472brgphy_mii_phy_auto(mii)
473 struct mii_softc *mii;
| 466brgphy_mii_phy_auto(struct mii_softc *mii)
|
474{
475 int ktcr = 0;
476
477 brgphy_loop(mii);
478 brgphy_reset(mii);
479 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD;
480 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701)
481 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC;
482 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr);
483 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL);
484 DELAY(1000);
485 PHY_WRITE(mii, BRGPHY_MII_ANAR,
486 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
487 DELAY(1000);
488 PHY_WRITE(mii, BRGPHY_MII_BMCR,
489 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
490 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00);
491 return (EJUSTRETURN);
492}
493
494static void
495brgphy_loop(struct mii_softc *sc)
496{
497 u_int32_t bmsr;
498 int i;
499
500 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
501 for (i = 0; i < 15000; i++) {
502 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
503 if (!(bmsr & BRGPHY_BMSR_LINK)) {
504#if 0
505 device_printf(sc->mii_dev, "looped %d\n", i);
506#endif
507 break;
508 }
509 DELAY(10);
510 }
511}
512
513/* Turn off tap power management on 5401. */
514static void
515bcm5401_load_dspcode(struct mii_softc *sc)
516{
517 static const struct {
518 int reg;
519 uint16_t val;
520 } dspcode[] = {
521 { BRGPHY_MII_AUXCTL, 0x0c20 },
522 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
523 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
524 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
525 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
526 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
527 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
528 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
529 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
530 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
531 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
532 { 0, 0 },
533 };
534 int i;
535
536 for (i = 0; dspcode[i].reg != 0; i++)
537 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
538 DELAY(40);
539}
540
541static void
542bcm5411_load_dspcode(struct mii_softc *sc)
543{
544 static const struct {
545 int reg;
546 uint16_t val;
547 } dspcode[] = {
548 { 0x1c, 0x8c23 },
549 { 0x1c, 0x8ca3 },
550 { 0x1c, 0x8c23 },
551 { 0, 0 },
552 };
553 int i;
554
555 for (i = 0; dspcode[i].reg != 0; i++)
556 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
557}
558
559static void
560bcm5703_load_dspcode(struct mii_softc *sc)
561{
562 static const struct {
563 int reg;
564 uint16_t val;
565 } dspcode[] = {
566 { BRGPHY_MII_AUXCTL, 0x0c00 },
567 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
568 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
569 { 0, 0 },
570 };
571 int i;
572
573 for (i = 0; dspcode[i].reg != 0; i++)
574 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
575}
576
577static void
578bcm5704_load_dspcode(struct mii_softc *sc)
579{
580 static const struct {
581 int reg;
582 u_int16_t val;
583 } dspcode[] = {
584 { 0x1c, 0x8d68 },
585 { 0x1c, 0x8d68 },
586 { 0, 0 },
587 };
588 int i;
589
590 for (i = 0; dspcode[i].reg != 0; i++)
591 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
592}
593
594static void
595bcm5750_load_dspcode(struct mii_softc *sc)
596{
597 static const struct {
598 int reg;
599 u_int16_t val;
600 } dspcode[] = {
601 { 0x18, 0x0c00 },
602 { 0x17, 0x000a },
603 { 0x15, 0x310b },
604 { 0x17, 0x201f },
605 { 0x15, 0x9506 },
606 { 0x17, 0x401f },
607 { 0x15, 0x14e2 },
608 { 0x18, 0x0400 },
609 { 0, 0 },
610 };
611 int i;
612
613 for (i = 0; dspcode[i].reg != 0; i++)
614 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
615}
616
617static void
618brgphy_reset(struct mii_softc *sc)
619{
620 u_int32_t val;
621 struct ifnet *ifp;
622 struct bge_softc *bge_sc;
623
624 mii_phy_reset(sc);
625
626 switch (brgphy_mii_model) {
627 case MII_MODEL_xxBROADCOM_BCM5401:
628 bcm5401_load_dspcode(sc);
629 break;
630 case MII_MODEL_xxBROADCOM_BCM5411:
631 bcm5411_load_dspcode(sc);
632 break;
633 case MII_MODEL_xxBROADCOM_BCM5703:
634 bcm5703_load_dspcode(sc);
635 break;
636 case MII_MODEL_xxBROADCOM_BCM5704:
637 bcm5704_load_dspcode(sc);
638 break;
639 case MII_MODEL_xxBROADCOM_BCM5750:
640 case MII_MODEL_xxBROADCOM_BCM5714:
641 bcm5750_load_dspcode(sc);
642 break;
643 }
644
645 ifp = sc->mii_pdata->mii_ifp;
646 bge_sc = ifp->if_softc;
647
648 /*
649 * Don't enable Ethernet@WireSpeed for the 5700 or the
650 * 5705 A1 and A2 chips. Make sure we only do this test
651 * on "bge" NICs, since other drivers may use this same
652 * PHY subdriver.
653 */
654 if (strcmp(ifp->if_dname, "bge") == 0 &&
655 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
656 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 ||
657 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2))
658 return;
659
660 /* Enable Ethernet@WireSpeed. */
661 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
662 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
663 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
664
665 /* Enable Link LED on Dell boxes */
666 if (bge_sc->bge_no_3_led) {
667 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
668 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
669 & ~BRGPHY_PHY_EXTCTL_3_LED);
670 }
671}
| 467{
468 int ktcr = 0;
469
470 brgphy_loop(mii);
471 brgphy_reset(mii);
472 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD;
473 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701)
474 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC;
475 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr);
476 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL);
477 DELAY(1000);
478 PHY_WRITE(mii, BRGPHY_MII_ANAR,
479 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
480 DELAY(1000);
481 PHY_WRITE(mii, BRGPHY_MII_BMCR,
482 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
483 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00);
484 return (EJUSTRETURN);
485}
486
487static void
488brgphy_loop(struct mii_softc *sc)
489{
490 u_int32_t bmsr;
491 int i;
492
493 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
494 for (i = 0; i < 15000; i++) {
495 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
496 if (!(bmsr & BRGPHY_BMSR_LINK)) {
497#if 0
498 device_printf(sc->mii_dev, "looped %d\n", i);
499#endif
500 break;
501 }
502 DELAY(10);
503 }
504}
505
506/* Turn off tap power management on 5401. */
507static void
508bcm5401_load_dspcode(struct mii_softc *sc)
509{
510 static const struct {
511 int reg;
512 uint16_t val;
513 } dspcode[] = {
514 { BRGPHY_MII_AUXCTL, 0x0c20 },
515 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
516 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
517 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
518 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
519 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
520 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
521 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
522 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
523 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
524 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
525 { 0, 0 },
526 };
527 int i;
528
529 for (i = 0; dspcode[i].reg != 0; i++)
530 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
531 DELAY(40);
532}
533
534static void
535bcm5411_load_dspcode(struct mii_softc *sc)
536{
537 static const struct {
538 int reg;
539 uint16_t val;
540 } dspcode[] = {
541 { 0x1c, 0x8c23 },
542 { 0x1c, 0x8ca3 },
543 { 0x1c, 0x8c23 },
544 { 0, 0 },
545 };
546 int i;
547
548 for (i = 0; dspcode[i].reg != 0; i++)
549 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
550}
551
552static void
553bcm5703_load_dspcode(struct mii_softc *sc)
554{
555 static const struct {
556 int reg;
557 uint16_t val;
558 } dspcode[] = {
559 { BRGPHY_MII_AUXCTL, 0x0c00 },
560 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
561 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
562 { 0, 0 },
563 };
564 int i;
565
566 for (i = 0; dspcode[i].reg != 0; i++)
567 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
568}
569
570static void
571bcm5704_load_dspcode(struct mii_softc *sc)
572{
573 static const struct {
574 int reg;
575 u_int16_t val;
576 } dspcode[] = {
577 { 0x1c, 0x8d68 },
578 { 0x1c, 0x8d68 },
579 { 0, 0 },
580 };
581 int i;
582
583 for (i = 0; dspcode[i].reg != 0; i++)
584 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
585}
586
587static void
588bcm5750_load_dspcode(struct mii_softc *sc)
589{
590 static const struct {
591 int reg;
592 u_int16_t val;
593 } dspcode[] = {
594 { 0x18, 0x0c00 },
595 { 0x17, 0x000a },
596 { 0x15, 0x310b },
597 { 0x17, 0x201f },
598 { 0x15, 0x9506 },
599 { 0x17, 0x401f },
600 { 0x15, 0x14e2 },
601 { 0x18, 0x0400 },
602 { 0, 0 },
603 };
604 int i;
605
606 for (i = 0; dspcode[i].reg != 0; i++)
607 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
608}
609
610static void
611brgphy_reset(struct mii_softc *sc)
612{
613 u_int32_t val;
614 struct ifnet *ifp;
615 struct bge_softc *bge_sc;
616
617 mii_phy_reset(sc);
618
619 switch (brgphy_mii_model) {
620 case MII_MODEL_xxBROADCOM_BCM5401:
621 bcm5401_load_dspcode(sc);
622 break;
623 case MII_MODEL_xxBROADCOM_BCM5411:
624 bcm5411_load_dspcode(sc);
625 break;
626 case MII_MODEL_xxBROADCOM_BCM5703:
627 bcm5703_load_dspcode(sc);
628 break;
629 case MII_MODEL_xxBROADCOM_BCM5704:
630 bcm5704_load_dspcode(sc);
631 break;
632 case MII_MODEL_xxBROADCOM_BCM5750:
633 case MII_MODEL_xxBROADCOM_BCM5714:
634 bcm5750_load_dspcode(sc);
635 break;
636 }
637
638 ifp = sc->mii_pdata->mii_ifp;
639 bge_sc = ifp->if_softc;
640
641 /*
642 * Don't enable Ethernet@WireSpeed for the 5700 or the
643 * 5705 A1 and A2 chips. Make sure we only do this test
644 * on "bge" NICs, since other drivers may use this same
645 * PHY subdriver.
646 */
647 if (strcmp(ifp->if_dname, "bge") == 0 &&
648 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
649 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 ||
650 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2))
651 return;
652
653 /* Enable Ethernet@WireSpeed. */
654 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
655 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
656 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
657
658 /* Enable Link LED on Dell boxes */
659 if (bge_sc->bge_no_3_led) {
660 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
661 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
662 & ~BRGPHY_PHY_EXTCTL_3_LED);
663 }
664}
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