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intpm.c (306140) intpm.c (306814)
1/*-
2 * Copyright (c) 1998, 1999 Takanori Watanabe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1998, 1999 Takanori Watanabe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: stable/11/sys/dev/intpm/intpm.c 306140 2016-09-21 19:51:59Z avg $");
28__FBSDID("$FreeBSD: stable/11/sys/dev/intpm/intpm.c 306814 2016-10-07 18:50:50Z avg $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/kernel.h>
34#include <sys/lock.h>
35#include <sys/module.h>
36#include <sys/mutex.h>
37#include <sys/rman.h>
38#include <machine/bus.h>
39#include <dev/smbus/smbconf.h>
40
41#include "smbus_if.h"
42
43#include <dev/pci/pcireg.h>
44#include <dev/pci/pcivar.h>
45#include <dev/intpm/intpmreg.h>
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/kernel.h>
34#include <sys/lock.h>
35#include <sys/module.h>
36#include <sys/mutex.h>
37#include <sys/rman.h>
38#include <machine/bus.h>
39#include <dev/smbus/smbconf.h>
40
41#include "smbus_if.h"
42
43#include <dev/pci/pcireg.h>
44#include <dev/pci/pcivar.h>
45#include <dev/intpm/intpmreg.h>
46#include <dev/amdsbwd/amd_chipset.h>
46
47#include "opt_intpm.h"
48
49struct intsmb_softc {
50 device_t dev;
51 struct resource *io_res;
52 struct resource *irq_res;
53 void *irq_hand;

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98 /* Not a good idea yet, this stops isab0 functioning */
99 case 0x02001166: /* ServerWorks OSB4 */
100#endif
101 device_set_desc(dev, "Intel PIIX4 SMBUS Interface");
102 break;
103 case 0x43721002:
104 device_set_desc(dev, "ATI IXP400 SMBus Controller");
105 break;
47
48#include "opt_intpm.h"
49
50struct intsmb_softc {
51 device_t dev;
52 struct resource *io_res;
53 struct resource *irq_res;
54 void *irq_hand;

--- 44 unchanged lines hidden (view full) ---

99 /* Not a good idea yet, this stops isab0 functioning */
100 case 0x02001166: /* ServerWorks OSB4 */
101#endif
102 device_set_desc(dev, "Intel PIIX4 SMBUS Interface");
103 break;
104 case 0x43721002:
105 device_set_desc(dev, "ATI IXP400 SMBus Controller");
106 break;
106 case 0x43851002:
107 case AMDSB_SMBUS_DEVID:
107 device_set_desc(dev, "AMD SB600/7xx/8xx/9xx SMBus Controller");
108 break;
108 device_set_desc(dev, "AMD SB600/7xx/8xx/9xx SMBus Controller");
109 break;
109 case 0x780b1022: /* AMD FCH */
110 if (pci_get_revid(dev) < 0x40)
111 return (ENXIO);
110 case AMDFCH_SMBUS_DEVID: /* AMD FCH */
111 case AMDCZ_SMBUS_DEVID: /* AMD Carizzo FCH */
112 device_set_desc(dev, "AMD FCH SMBus Controller");
113 break;
114 default:
115 return (ENXIO);
116 }
117
118 return (BUS_PROBE_DEFAULT);
119}
120
121static uint8_t
112 device_set_desc(dev, "AMD FCH SMBus Controller");
113 break;
114 default:
115 return (ENXIO);
116 }
117
118 return (BUS_PROBE_DEFAULT);
119}
120
121static uint8_t
122sb8xx_pmio_read(struct resource *res, uint8_t reg)
122amd_pmio_read(struct resource *res, uint8_t reg)
123{
124 bus_write_1(res, 0, reg); /* Index */
125 return (bus_read_1(res, 1)); /* Data */
126}
127
128static int
129sb8xx_attach(device_t dev)
130{
123{
124 bus_write_1(res, 0, reg); /* Index */
125 return (bus_read_1(res, 1)); /* Data */
126}
127
128static int
129sb8xx_attach(device_t dev)
130{
131 static const int AMDSB_PMIO_INDEX = 0xcd6;
132 static const int AMDSB_PMIO_WIDTH = 2;
133 static const int AMDSB8_SMBUS_ADDR = 0x2c;
134 static const int AMDSB8_SMBUS_EN = 0x01;
135 static const int AMDSB8_SMBUS_ADDR_MASK = ~0x1fu;
136 static const int AMDSB_SMBIO_WIDTH = 0x14;
131 static const int AMDSB_SMBIO_WIDTH = 0x14;
137 static const int AMDSB_SMBUS_CFG = 0x10;
138 static const int AMDSB_SMBUS_IRQ = 0x01;
139 static const int AMDSB_SMBUS_REV_MASK = ~0x0fu;
140 static const int AMDSB_SMBUS_REV_SHIFT = 4;
141 static const int AMDSB_IO_RID = 0;
142
143 struct intsmb_softc *sc;
144 struct resource *res;
132 struct intsmb_softc *sc;
133 struct resource *res;
134 uint32_t devid;
135 uint8_t revid;
145 uint16_t addr;
136 uint16_t addr;
146 uint8_t cfg;
147 int rid;
148 int rc;
137 int rid;
138 int rc;
139 bool enabled;
149
150 sc = device_get_softc(dev);
140
141 sc = device_get_softc(dev);
151 rid = AMDSB_IO_RID;
142 rid = 0;
152 rc = bus_set_resource(dev, SYS_RES_IOPORT, rid, AMDSB_PMIO_INDEX,
153 AMDSB_PMIO_WIDTH);
154 if (rc != 0) {
155 device_printf(dev, "bus_set_resource for PM IO failed\n");
156 return (ENXIO);
157 }
158 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
143 rc = bus_set_resource(dev, SYS_RES_IOPORT, rid, AMDSB_PMIO_INDEX,
144 AMDSB_PMIO_WIDTH);
145 if (rc != 0) {
146 device_printf(dev, "bus_set_resource for PM IO failed\n");
147 return (ENXIO);
148 }
149 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
159 RF_ACTIVE | RF_SHAREABLE);
150 RF_ACTIVE);
160 if (res == NULL) {
161 device_printf(dev, "bus_alloc_resource for PM IO failed\n");
162 return (ENXIO);
163 }
164
151 if (res == NULL) {
152 device_printf(dev, "bus_alloc_resource for PM IO failed\n");
153 return (ENXIO);
154 }
155
165 addr = sb8xx_pmio_read(res, AMDSB8_SMBUS_ADDR + 1);
166 addr <<= 8;
167 addr |= sb8xx_pmio_read(res, AMDSB8_SMBUS_ADDR);
156 devid = pci_get_devid(dev);
157 revid = pci_get_revid(dev);
158 if (devid == AMDSB_SMBUS_DEVID ||
159 (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) ||
160 (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID)) {
161 addr = amd_pmio_read(res, AMDSB8_PM_SMBUS_EN + 1);
162 addr <<= 8;
163 addr |= amd_pmio_read(res, AMDSB8_PM_SMBUS_EN);
164 enabled = (addr & AMDSB8_SMBUS_EN) != 0;
165 addr &= AMDSB8_SMBUS_ADDR_MASK;
166 } else {
167 addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN0);
168 enabled = (addr & AMDFCH41_SMBUS_EN) != 0;
169 addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN1);
170 addr <<= 8;
171 }
168
169 bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
170 bus_delete_resource(dev, SYS_RES_IOPORT, rid);
171
172
173 bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
174 bus_delete_resource(dev, SYS_RES_IOPORT, rid);
175
172 if ((addr & AMDSB8_SMBUS_EN) == 0) {
173 device_printf(dev, "SB8xx SMBus not enabled\n");
176 if (!enabled) {
177 device_printf(dev, "SB8xx/SB9xx/FCH SMBus not enabled\n");
174 return (ENXIO);
175 }
176
178 return (ENXIO);
179 }
180
177 addr &= AMDSB8_SMBUS_ADDR_MASK;
178 sc->io_rid = AMDSB_IO_RID;
181 sc->io_rid = 0;
179 rc = bus_set_resource(dev, SYS_RES_IOPORT, sc->io_rid, addr,
180 AMDSB_SMBIO_WIDTH);
181 if (rc != 0) {
182 device_printf(dev, "bus_set_resource for SMBus IO failed\n");
183 return (ENXIO);
184 }
185 if (res == NULL) {
186 device_printf(dev, "bus_alloc_resource for SMBus IO failed\n");
187 return (ENXIO);
188 }
189 sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->io_rid,
182 rc = bus_set_resource(dev, SYS_RES_IOPORT, sc->io_rid, addr,
183 AMDSB_SMBIO_WIDTH);
184 if (rc != 0) {
185 device_printf(dev, "bus_set_resource for SMBus IO failed\n");
186 return (ENXIO);
187 }
188 if (res == NULL) {
189 device_printf(dev, "bus_alloc_resource for SMBus IO failed\n");
190 return (ENXIO);
191 }
192 sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->io_rid,
190 RF_ACTIVE | RF_SHAREABLE);
191 cfg = bus_read_1(sc->io_res, AMDSB_SMBUS_CFG);
192
193 RF_ACTIVE);
193 sc->poll = 1;
194 sc->poll = 1;
194 device_printf(dev, "intr %s disabled ",
195 (cfg & AMDSB_SMBUS_IRQ) != 0 ? "IRQ" : "SMI");
196 printf("revision %d\n",
197 (cfg & AMDSB_SMBUS_REV_MASK) >> AMDSB_SMBUS_REV_SHIFT);
198
199 return (0);
200}
201
202static void
203intsmb_release_resources(device_t dev)
204{
205 struct intsmb_softc *sc = device_get_softc(dev);
206

--- 25 unchanged lines hidden (view full) ---

232 switch (pci_get_devid(dev)) {
233#ifndef NO_CHANGE_PCICONF
234 case 0x71138086: /* Intel 82371AB */
235 case 0x719b8086: /* Intel 82443MX */
236 /* Changing configuration is allowed. */
237 sc->cfg_irq9 = 1;
238 break;
239#endif
195 return (0);
196}
197
198static void
199intsmb_release_resources(device_t dev)
200{
201 struct intsmb_softc *sc = device_get_softc(dev);
202

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228 switch (pci_get_devid(dev)) {
229#ifndef NO_CHANGE_PCICONF
230 case 0x71138086: /* Intel 82371AB */
231 case 0x719b8086: /* Intel 82443MX */
232 /* Changing configuration is allowed. */
233 sc->cfg_irq9 = 1;
234 break;
235#endif
240 case 0x43851002:
241 if (pci_get_revid(dev) >= 0x40)
236 case AMDSB_SMBUS_DEVID:
237 if (pci_get_revid(dev) >= AMDSB8_SMBUS_REVID)
242 sc->sb8xx = 1;
243 break;
238 sc->sb8xx = 1;
239 break;
244 case 0x780b1022:
240 case AMDFCH_SMBUS_DEVID:
241 case AMDCZ_SMBUS_DEVID:
245 sc->sb8xx = 1;
246 break;
247 }
248
249 if (sc->sb8xx) {
250 error = sb8xx_attach(dev);
251 if (error != 0)
252 goto fail;

--- 679 unchanged lines hidden --- 		242 sc->sb8xx = 1;
243 break;
244 }
245
246 if (sc->sb8xx) {
247 error = sb8xx_attach(dev);
248 if (error != 0)
249 goto fail;

--- 679 unchanged lines hidden ---