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intel_iic.c (278152) intel_iic.c (280183)
1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright �� 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 40 unchanged lines hidden (view full) ---

49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
54 * SUCH DAMAGE.
55 */
56#include <sys/cdefs.h>
1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright �� 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 40 unchanged lines hidden (view full) ---

49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
54 * SUCH DAMAGE.
55 */
56#include <sys/cdefs.h>
57__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/intel_iic.c 278152 2015-02-03 13:43:03Z kib $");
57__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/intel_iic.c 280183 2015-03-17 18:50:33Z dumbbell $");
58
59#include <dev/drm2/drmP.h>
60#include <dev/drm2/drm.h>
61#include <dev/drm2/i915/i915_drm.h>
62#include <dev/drm2/i915/i915_drv.h>
63#include <dev/drm2/i915/intel_drv.h>
64#include <dev/iicbus/iic.h>
65#include <dev/iicbus/iiconf.h>

--- 187 unchanged lines hidden (view full) ---

253 u32 val, loop = 0;
254 u32 gmbus2;
255
256 ret = _intel_wait_for(sc->drm_dev,
257 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
258 (GMBUS_SATOER | GMBUS_HW_RDY)),
259 50, 1, "915gbr");
260 if (ret)
58
59#include <dev/drm2/drmP.h>
60#include <dev/drm2/drm.h>
61#include <dev/drm2/i915/i915_drm.h>
62#include <dev/drm2/i915/i915_drv.h>
63#include <dev/drm2/i915/intel_drv.h>
64#include <dev/iicbus/iic.h>
65#include <dev/iicbus/iiconf.h>

--- 187 unchanged lines hidden (view full) ---

253 u32 val, loop = 0;
254 u32 gmbus2;
255
256 ret = _intel_wait_for(sc->drm_dev,
257 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
258 (GMBUS_SATOER | GMBUS_HW_RDY)),
259 50, 1, "915gbr");
260 if (ret)
261 return (ETIMEDOUT);
261 return (-ETIMEDOUT);
262 if (gmbus2 & GMBUS_SATOER)
262 if (gmbus2 & GMBUS_SATOER)
263 return (ENXIO);
263 return (-ENXIO);
264
265 val = I915_READ(GMBUS3 + reg_offset);
266 do {
267 *buf++ = val & 0xff;
268 val >>= 8;
269 } while (--len != 0 && ++loop < 4);
270 }
271

--- 31 unchanged lines hidden (view full) ---

303
304 I915_WRITE(GMBUS3 + reg_offset, val);
305
306 ret = _intel_wait_for(sc->drm_dev,
307 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
308 (GMBUS_SATOER | GMBUS_HW_RDY)),
309 50, 1, "915gbw");
310 if (ret)
264
265 val = I915_READ(GMBUS3 + reg_offset);
266 do {
267 *buf++ = val & 0xff;
268 val >>= 8;
269 } while (--len != 0 && ++loop < 4);
270 }
271

--- 31 unchanged lines hidden (view full) ---

303
304 I915_WRITE(GMBUS3 + reg_offset, val);
305
306 ret = _intel_wait_for(sc->drm_dev,
307 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
308 (GMBUS_SATOER | GMBUS_HW_RDY)),
309 50, 1, "915gbw");
310 if (ret)
311 return (ETIMEDOUT);
311 return (-ETIMEDOUT);
312 if (gmbus2 & GMBUS_SATOER)
312 if (gmbus2 & GMBUS_SATOER)
313 return (ENXIO);
313 return (-ENXIO);
314 }
315 return 0;
316}
317
318/*
319 * The gmbus controller can combine a 1 or 2 byte write with a read that
320 * immediately follows it by using an "INDEX" cycle.
321 */

--- 42 unchanged lines hidden (view full) ---

364
365 error = 0;
366 sc = device_get_softc(idev);
367 dev_priv = sc->drm_dev->dev_private;
368 unit = device_get_unit(idev);
369
370 sx_xlock(&dev_priv->gmbus_sx);
371 if (sc->force_bit_dev) {
314 }
315 return 0;
316}
317
318/*
319 * The gmbus controller can combine a 1 or 2 byte write with a read that
320 * immediately follows it by using an "INDEX" cycle.
321 */

--- 42 unchanged lines hidden (view full) ---

364
365 error = 0;
366 sc = device_get_softc(idev);
367 dev_priv = sc->drm_dev->dev_private;
368 unit = device_get_unit(idev);
369
370 sx_xlock(&dev_priv->gmbus_sx);
371 if (sc->force_bit_dev) {
372 error = IICBUS_TRANSFER(dev_priv->bbbus[unit], msgs, nmsgs);
372 error = -IICBUS_TRANSFER(dev_priv->bbbus[unit], msgs, nmsgs);
373 goto out;
374 }
375
376 reg_offset = dev_priv->gpio_mmio_base;
377
378 I915_WRITE(GMBUS0 + reg_offset, sc->reg0);
379
380 for (i = 0; i < nmsgs; i++) {
381 u32 gmbus2;
382
383 if (gmbus_is_index_read(msgs, i, nmsgs)) {
384 error = gmbus_xfer_index_read(dev_priv, &msgs[i]);
385 i += 1; /* set i to the index of the read xfer */
386 } else if (msgs[i].flags & IIC_M_RD) {
387 error = gmbus_xfer_read(dev_priv, &msgs[i], 0);
388 } else {
389 error = gmbus_xfer_write(dev_priv, &msgs[i]);
390 }
391
373 goto out;
374 }
375
376 reg_offset = dev_priv->gpio_mmio_base;
377
378 I915_WRITE(GMBUS0 + reg_offset, sc->reg0);
379
380 for (i = 0; i < nmsgs; i++) {
381 u32 gmbus2;
382
383 if (gmbus_is_index_read(msgs, i, nmsgs)) {
384 error = gmbus_xfer_index_read(dev_priv, &msgs[i]);
385 i += 1; /* set i to the index of the read xfer */
386 } else if (msgs[i].flags & IIC_M_RD) {
387 error = gmbus_xfer_read(dev_priv, &msgs[i], 0);
388 } else {
389 error = gmbus_xfer_write(dev_priv, &msgs[i]);
390 }
391
392 if (error == ETIMEDOUT)
392 if (error == -ETIMEDOUT)
393 goto timeout;
393 goto timeout;
394 if (error == ENXIO)
394 if (error == -ENXIO)
395 goto clear_err;
396
397 ret = _intel_wait_for(sc->drm_dev,
398 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
399 (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE)),
400 50, 1, "915gbh");
401 if (ret)
402 goto timeout;

--- 11 unchanged lines hidden (view full) ---

414 * We will re-enable it at the start of the next xfer,
415 * till then let it sleep.
416 */
417 if (_intel_wait_for(dev,
418 (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
419 10, 1, "915gbu")) {
420 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
421 sc->name);
395 goto clear_err;
396
397 ret = _intel_wait_for(sc->drm_dev,
398 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
399 (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE)),
400 50, 1, "915gbh");
401 if (ret)
402 goto timeout;

--- 11 unchanged lines hidden (view full) ---

414 * We will re-enable it at the start of the next xfer,
415 * till then let it sleep.
416 */
417 if (_intel_wait_for(dev,
418 (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
419 10, 1, "915gbu")) {
420 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
421 sc->name);
422 error = ETIMEDOUT;
422 error = -ETIMEDOUT;
423 }
424 I915_WRITE(GMBUS0 + reg_offset, 0);
425 goto out;
426
427clear_err:
428 /*
429 * Wait for bus to IDLE before clearing NAK.
430 * If we clear the NAK while bus is still active, then it will stay

--- 18 unchanged lines hidden (view full) ---

449
450 /*
451 * If no ACK is received during the address phase of a transaction,
452 * the adapter must report -ENXIO.
453 * It is not clear what to return if no ACK is received at other times.
454 * So, we always return -ENXIO in all NAK cases, to ensure we send
455 * it at least during the one case that is specified.
456 */
423 }
424 I915_WRITE(GMBUS0 + reg_offset, 0);
425 goto out;
426
427clear_err:
428 /*
429 * Wait for bus to IDLE before clearing NAK.
430 * If we clear the NAK while bus is still active, then it will stay

--- 18 unchanged lines hidden (view full) ---

449
450 /*
451 * If no ACK is received during the address phase of a transaction,
452 * the adapter must report -ENXIO.
453 * It is not clear what to return if no ACK is received at other times.
454 * So, we always return -ENXIO in all NAK cases, to ensure we send
455 * it at least during the one case that is specified.
456 */
457 error = ENXIO;
457 error = -ENXIO;
458 goto out;
459
460timeout:
461 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
462 sc->name, sc->reg0 & 0xff);
463 I915_WRITE(GMBUS0 + reg_offset, 0);
464
465 /*
466 * Hardware may not support GMBUS over these pins?
467 * Try GPIO bitbanging instead.
468 */
469 sc->force_bit_dev = true;
458 goto out;
459
460timeout:
461 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
462 sc->name, sc->reg0 & 0xff);
463 I915_WRITE(GMBUS0 + reg_offset, 0);
464
465 /*
466 * Hardware may not support GMBUS over these pins?
467 * Try GPIO bitbanging instead.
468 */
469 sc->force_bit_dev = true;
470 error = IICBUS_TRANSFER(idev, msgs, nmsgs);
470 error = -IICBUS_TRANSFER(idev, msgs, nmsgs);
471 goto out;
472
473out:
474 sx_xunlock(&dev_priv->gmbus_sx);
471 goto out;
472
473out:
474 sx_xunlock(&dev_priv->gmbus_sx);
475 return (error);
475 return (-error);
476}
477
478device_t
479intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
480 unsigned port)
481{
482
483 if (!intel_gmbus_is_port_valid(port))

--- 241 unchanged lines hidden (view full) ---

725 */
726 mtx_lock(&Giant);
727 for (i = 0; i <= GMBUS_NUM_PORTS; i++) {
728 /*
729 * Initialized bbbus_bridge before gmbus_bridge, since
730 * gmbus may decide to force quirk transfer in the
731 * attachment code.
732 */
476}
477
478device_t
479intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
480 unsigned port)
481{
482
483 if (!intel_gmbus_is_port_valid(port))

--- 241 unchanged lines hidden (view full) ---

725 */
726 mtx_lock(&Giant);
727 for (i = 0; i <= GMBUS_NUM_PORTS; i++) {
728 /*
729 * Initialized bbbus_bridge before gmbus_bridge, since
730 * gmbus may decide to force quirk transfer in the
731 * attachment code.
732 */
733 dev_priv->bbbus_bridge[i] = device_add_child(dev->device,
733 dev_priv->bbbus_bridge[i] = device_add_child(dev->dev,
734 "intel_iicbb", i);
735 if (dev_priv->bbbus_bridge[i] == NULL) {
736 DRM_ERROR("bbbus bridge %d creation failed\n", i);
734 "intel_iicbb", i);
735 if (dev_priv->bbbus_bridge[i] == NULL) {
736 DRM_ERROR("bbbus bridge %d creation failed\n", i);
737 ret = ENXIO;
737 ret = -ENXIO;
738 goto err;
739 }
740 device_quiet(dev_priv->bbbus_bridge[i]);
738 goto err;
739 }
740 device_quiet(dev_priv->bbbus_bridge[i]);
741 ret = device_probe_and_attach(dev_priv->bbbus_bridge[i]);
741 ret = -device_probe_and_attach(dev_priv->bbbus_bridge[i]);
742 if (ret != 0) {
743 DRM_ERROR("bbbus bridge %d attach failed, %d\n", i,
744 ret);
745 goto err;
746 }
747
748 iic_dev = device_find_child(dev_priv->bbbus_bridge[i], "iicbb",
749 -1);

--- 5 unchanged lines hidden (view full) ---

755 if (iic_dev == NULL) {
756 DRM_ERROR(
757 "bbbus bridge doesn't have iicbus grandchild\n");
758 goto err;
759 }
760
761 dev_priv->bbbus[i] = iic_dev;
762
742 if (ret != 0) {
743 DRM_ERROR("bbbus bridge %d attach failed, %d\n", i,
744 ret);
745 goto err;
746 }
747
748 iic_dev = device_find_child(dev_priv->bbbus_bridge[i], "iicbb",
749 -1);

--- 5 unchanged lines hidden (view full) ---

755 if (iic_dev == NULL) {
756 DRM_ERROR(
757 "bbbus bridge doesn't have iicbus grandchild\n");
758 goto err;
759 }
760
761 dev_priv->bbbus[i] = iic_dev;
762
763 dev_priv->gmbus_bridge[i] = device_add_child(dev->device,
763 dev_priv->gmbus_bridge[i] = device_add_child(dev->dev,
764 "intel_gmbus", i);
765 if (dev_priv->gmbus_bridge[i] == NULL) {
766 DRM_ERROR("gmbus bridge %d creation failed\n", i);
764 "intel_gmbus", i);
765 if (dev_priv->gmbus_bridge[i] == NULL) {
766 DRM_ERROR("gmbus bridge %d creation failed\n", i);
767 ret = ENXIO;
767 ret = -ENXIO;
768 goto err;
769 }
770 device_quiet(dev_priv->gmbus_bridge[i]);
768 goto err;
769 }
770 device_quiet(dev_priv->gmbus_bridge[i]);
771 ret = device_probe_and_attach(dev_priv->gmbus_bridge[i]);
771 ret = -device_probe_and_attach(dev_priv->gmbus_bridge[i]);
772 if (ret != 0) {
773 DRM_ERROR("gmbus bridge %d attach failed, %d\n", i,
774 ret);
772 if (ret != 0) {
773 DRM_ERROR("gmbus bridge %d attach failed, %d\n", i,
774 ret);
775 ret = ENXIO;
775 ret = -ENXIO;
776 goto err;
777 }
778
779 iic_dev = device_find_child(dev_priv->gmbus_bridge[i],
780 "iicbus", -1);
781 if (iic_dev == NULL) {
782 DRM_ERROR("gmbus bridge doesn't have iicbus child\n");
783 goto err;

--- 33 unchanged lines hidden --- 		776 goto err;
777 }
778
779 iic_dev = device_find_child(dev_priv->gmbus_bridge[i],
780 "iicbus", -1);
781 if (iic_dev == NULL) {
782 DRM_ERROR("gmbus bridge doesn't have iicbus child\n");
783 goto err;

--- 33 unchanged lines hidden ---