Deleted Added
sdiff udiff text old ( 268564 ) new ( 277487 )
full compact
intel_iic.c (268564) intel_iic.c (277487)
1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright �� 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 40 unchanged lines hidden (view full) ---

49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
54 * SUCH DAMAGE.
55 */
56#include <sys/cdefs.h>
1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright �� 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 40 unchanged lines hidden (view full) ---

49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
54 * SUCH DAMAGE.
55 */
56#include <sys/cdefs.h>
57__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/intel_iic.c 268564 2014-07-12 06:23:42Z rpaulo $");
57__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/intel_iic.c 277487 2015-01-21 16:10:37Z kib $");
58
59#include <dev/drm2/drmP.h>
60#include <dev/drm2/drm.h>
61#include <dev/drm2/i915/i915_drm.h>
62#include <dev/drm2/i915/i915_drv.h>
63#include <dev/drm2/i915/intel_drv.h>
64#include <dev/iicbus/iic.h>
65#include <dev/iicbus/iiconf.h>
66#include <dev/iicbus/iicbus.h>
67#include "iicbus_if.h"
68#include "iicbb_if.h"
69
58
59#include <dev/drm2/drmP.h>
60#include <dev/drm2/drm.h>
61#include <dev/drm2/i915/i915_drm.h>
62#include <dev/drm2/i915/i915_drv.h>
63#include <dev/drm2/i915/intel_drv.h>
64#include <dev/iicbus/iic.h>
65#include <dev/iicbus/iiconf.h>
66#include <dev/iicbus/iicbus.h>
67#include "iicbus_if.h"
68#include "iicbb_if.h"
69
70static int intel_iic_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs);
71static void intel_teardown_gmbus_m(struct drm_device *dev, int m);
72
70static void intel_teardown_gmbus_m(struct drm_device *dev, int m);
71
72struct gmbus_port {
73 const char *name;
74 int reg;
75};
76
77static const struct gmbus_port gmbus_ports[] = {
78 { "ssc", GPIOB },
79 { "vga", GPIOA },
80 { "panel", GPIOC },
81 { "dpc", GPIOD },
82 { "dpb", GPIOE },
83 { "dpd", GPIOF },
84};
85
73/* Intel GPIO access functions */
74
75#define I2C_RISEFALL_TIME 10
76
77struct intel_iic_softc {
78 struct drm_device *drm_dev;
79 device_t iic_dev;
80 bool force_bit_dev;

--- 42 unchanged lines hidden (view full) ---

123}
124
125void
126intel_iic_reset(struct drm_device *dev)
127{
128 struct drm_i915_private *dev_priv;
129
130 dev_priv = dev->dev_private;
86/* Intel GPIO access functions */
87
88#define I2C_RISEFALL_TIME 10
89
90struct intel_iic_softc {
91 struct drm_device *drm_dev;
92 device_t iic_dev;
93 bool force_bit_dev;

--- 42 unchanged lines hidden (view full) ---

136}
137
138void
139intel_iic_reset(struct drm_device *dev)
140{
141 struct drm_i915_private *dev_priv;
142
143 dev_priv = dev->dev_private;
131 if (HAS_PCH_SPLIT(dev))
132 I915_WRITE(PCH_GMBUS0, 0);
133 else
134 I915_WRITE(GMBUS0, 0);
144 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
135}
136
137static int
138intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr)
139{
140 struct intel_iic_softc *sc;
141 struct drm_device *dev;
142

--- 77 unchanged lines hidden (view full) ---

220 reserved = intel_iic_get_reserved(idev);
221
222 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK);
223 I915_WRITE_NOTRACE(sc->reg, reserved);
224 return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0);
225}
226
227static int
145}
146
147static int
148intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr)
149{
150 struct intel_iic_softc *sc;
151 struct drm_device *dev;
152

--- 77 unchanged lines hidden (view full) ---

230 reserved = intel_iic_get_reserved(idev);
231
232 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK);
233 I915_WRITE_NOTRACE(sc->reg, reserved);
234 return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0);
235}
236
237static int
238gmbus_xfer_read(struct drm_i915_private *dev_priv, struct iic_msg *msg,
239 u32 gmbus1_index)
240{
241 int reg_offset = dev_priv->gpio_mmio_base;
242 u16 len = msg->len;
243 u8 *buf = msg->buf;
244
245 I915_WRITE(GMBUS1 + reg_offset,
246 gmbus1_index |
247 GMBUS_CYCLE_WAIT |
248 (len << GMBUS_BYTE_COUNT_SHIFT) |
249 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) |
250 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
251 while (len) {
252 int ret;
253 u32 val, loop = 0;
254 u32 gmbus2;
255
256 ret = _intel_wait_for(sc->drm_dev,
257 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
258 (GMBUS_SATOER | GMBUS_HW_RDY)),
259 50, 1, "915gbr");
260 if (ret)
261 return (ETIMEDOUT);
262 if (gmbus2 & GMBUS_SATOER)
263 return (ENXIO);
264
265 val = I915_READ(GMBUS3 + reg_offset);
266 do {
267 *buf++ = val & 0xff;
268 val >>= 8;
269 } while (--len != 0 && ++loop < 4);
270 }
271
272 return 0;
273}
274
275static int
276gmbus_xfer_write(struct drm_i915_private *dev_priv, struct iic_msg *msg)
277{
278 int reg_offset = dev_priv->gpio_mmio_base;
279 u16 len = msg->len;
280 u8 *buf = msg->buf;
281 u32 val, loop;
282
283 val = loop = 0;
284 while (len && loop < 4) {
285 val |= *buf++ << (8 * loop++);
286 len -= 1;
287 }
288
289 I915_WRITE(GMBUS3 + reg_offset, val);
290 I915_WRITE(GMBUS1 + reg_offset,
291 GMBUS_CYCLE_WAIT |
292 (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
293 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) |
294 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
295 while (len) {
296 int ret;
297 u32 gmbus2;
298
299 val = loop = 0;
300 do {
301 val |= *buf++ << (8 * loop);
302 } while (--len != 0 && ++loop < 4);
303
304 I915_WRITE(GMBUS3 + reg_offset, val);
305
306 ret = _intel_wait_for(sc->drm_dev,
307 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
308 (GMBUS_SATOER | GMBUS_HW_RDY)),
309 50, 1, "915gbw");
310 if (ret)
311 return (ETIMEDOUT);
312 if (gmbus2 & GMBUS_SATOER)
313 return (ENXIO);
314 }
315 return 0;
316}
317
318/*
319 * The gmbus controller can combine a 1 or 2 byte write with a read that
320 * immediately follows it by using an "INDEX" cycle.
321 */
322static bool
323gmbus_is_index_read(struct iic_msg *msgs, int i, int num)
324{
325 return (i + 1 < num &&
326 !(msgs[i].flags & IIC_M_RD) && msgs[i].len <= 2 &&
327 (msgs[i + 1].flags & IIC_M_RD));
328}
329
330static int
331gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct iic_msg *msgs)
332{
333 int reg_offset = dev_priv->gpio_mmio_base;
334 u32 gmbus1_index = 0;
335 u32 gmbus5 = 0;
336 int ret;
337
338 if (msgs[0].len == 2)
339 gmbus5 = GMBUS_2BYTE_INDEX_EN |
340 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
341 if (msgs[0].len == 1)
342 gmbus1_index = GMBUS_CYCLE_INDEX |
343 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
344
345 /* GMBUS5 holds 16-bit index */
346 if (gmbus5)
347 I915_WRITE(GMBUS5 + reg_offset, gmbus5);
348
349 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
350
351 /* Clear GMBUS5 after each index transfer */
352 if (gmbus5)
353 I915_WRITE(GMBUS5 + reg_offset, 0);
354
355 return ret;
356}
357
358static int
228intel_gmbus_transfer(device_t idev, struct iic_msg *msgs, uint32_t nmsgs)
229{
230 struct intel_iic_softc *sc;
231 struct drm_i915_private *dev_priv;
359intel_gmbus_transfer(device_t idev, struct iic_msg *msgs, uint32_t nmsgs)
360{
361 struct intel_iic_softc *sc;
362 struct drm_i915_private *dev_priv;
232 u8 *buf;
233 int error, i, reg_offset, unit;
234 u32 val, loop;
235 u16 len;
363 int error, i, ret, reg_offset, unit;
236
364
365 error = 0;
237 sc = device_get_softc(idev);
238 dev_priv = sc->drm_dev->dev_private;
239 unit = device_get_unit(idev);
240
241 sx_xlock(&dev_priv->gmbus_sx);
242 if (sc->force_bit_dev) {
366 sc = device_get_softc(idev);
367 dev_priv = sc->drm_dev->dev_private;
368 unit = device_get_unit(idev);
369
370 sx_xlock(&dev_priv->gmbus_sx);
371 if (sc->force_bit_dev) {
243 error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs);
372 error = IICBUS_TRANSFER(dev_priv->bbbus[unit], msgs, nmsgs);
244 goto out;
245 }
246
373 goto out;
374 }
375
247 reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
376 reg_offset = dev_priv->gpio_mmio_base;
248
249 I915_WRITE(GMBUS0 + reg_offset, sc->reg0);
250
251 for (i = 0; i < nmsgs; i++) {
377
378 I915_WRITE(GMBUS0 + reg_offset, sc->reg0);
379
380 for (i = 0; i < nmsgs; i++) {
252 len = msgs[i].len;
253 buf = msgs[i].buf;
381 u32 gmbus2;
254
382
255 if ((msgs[i].flags & IIC_M_RD) != 0) {
256 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT |
257 (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) |
258 (len << GMBUS_BYTE_COUNT_SHIFT) |
259 (msgs[i].slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) |
260 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
261 POSTING_READ(GMBUS2 + reg_offset);
262 do {
263 loop = 0;
264
265 if (_intel_wait_for(sc->drm_dev,
266 (I915_READ(GMBUS2 + reg_offset) &
267 (GMBUS_SATOER | GMBUS_HW_RDY)) != 0,
268 50, 1, "915gbr"))
269 goto timeout;
270 if ((I915_READ(GMBUS2 + reg_offset) &
271 GMBUS_SATOER) != 0)
272 goto clear_err;
273
274 val = I915_READ(GMBUS3 + reg_offset);
275 do {
276 *buf++ = val & 0xff;
277 val >>= 8;
278 } while (--len != 0 && ++loop < 4);
279 } while (len != 0);
383 if (gmbus_is_index_read(msgs, i, nmsgs)) {
384 error = gmbus_xfer_index_read(dev_priv, &msgs[i]);
385 i += 1; /* set i to the index of the read xfer */
386 } else if (msgs[i].flags & IIC_M_RD) {
387 error = gmbus_xfer_read(dev_priv, &msgs[i], 0);
280 } else {
388 } else {
281 val = loop = 0;
282 do {
283 val |= *buf++ << (8 * loop);
284 } while (--len != 0 && ++loop < 4);
285
286 I915_WRITE(GMBUS3 + reg_offset, val);
287 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT |
288 (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) |
289 (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
290 (msgs[i].slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) |
291 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
292 POSTING_READ(GMBUS2+reg_offset);
293
294 while (len != 0) {
295 if (_intel_wait_for(sc->drm_dev,
296 (I915_READ(GMBUS2 + reg_offset) &
297 (GMBUS_SATOER | GMBUS_HW_RDY)) != 0,
298 50, 1, "915gbw"))
299 goto timeout;
300 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
301 goto clear_err;
302
303 val = loop = 0;
304 do {
305 val |= *buf++ << (8 * loop);
306 } while (--len != 0 && ++loop < 4);
307
308 I915_WRITE(GMBUS3 + reg_offset, val);
309 POSTING_READ(GMBUS2 + reg_offset);
310 }
389 error = gmbus_xfer_write(dev_priv, &msgs[i]);
311 }
312
390 }
391
313 if (i + 1 < nmsgs && _intel_wait_for(sc->drm_dev,
314 (I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER |
315 GMBUS_HW_WAIT_PHASE)) != 0,
316 50, 1, "915gbh"))
392 if (error == ETIMEDOUT)
317 goto timeout;
393 goto timeout;
318 if ((I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) != 0)
394 if (error == ENXIO)
319 goto clear_err;
395 goto clear_err;
396
397 ret = _intel_wait_for(sc->drm_dev,
398 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
399 (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE)),
400 50, 1, "915gbh");
401 if (ret)
402 goto timeout;
403 if (gmbus2 & GMBUS_SATOER)
404 goto clear_err;
320 }
321
405 }
406
322 error = 0;
323done:
407 /* Generate a STOP condition on the bus. Note that gmbus can't generata
408 * a STOP on the very first cycle. To simplify the code we
409 * unconditionally generate the STOP condition with an additional gmbus
410 * cycle. */
411 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
412
324 /* Mark the GMBUS interface as disabled after waiting for idle.
325 * We will re-enable it at the start of the next xfer,
326 * till then let it sleep.
327 */
328 if (_intel_wait_for(dev,
329 (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
413 /* Mark the GMBUS interface as disabled after waiting for idle.
414 * We will re-enable it at the start of the next xfer,
415 * till then let it sleep.
416 */
417 if (_intel_wait_for(dev,
418 (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
330 10, 1, "915gbu"))
331 DRM_INFO("GMBUS timed out waiting for idle\n");
419 10, 1, "915gbu")) {
420 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
421 sc->name);
422 error = ETIMEDOUT;
423 }
332 I915_WRITE(GMBUS0 + reg_offset, 0);
424 I915_WRITE(GMBUS0 + reg_offset, 0);
333out:
334 sx_xunlock(&dev_priv->gmbus_sx);
335 return (error);
425 goto out;
336
337clear_err:
426
427clear_err:
428 /*
429 * Wait for bus to IDLE before clearing NAK.
430 * If we clear the NAK while bus is still active, then it will stay
431 * active and the next transaction may fail.
432 */
433 if (_intel_wait_for(dev,
434 (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
435 10, 1, "915gbu"))
436 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", sc->name);
437
338 /* Toggle the Software Clear Interrupt bit. This has the effect
339 * of resetting the GMBUS controller and so clearing the
340 * BUS_ERROR raised by the slave's NAK.
341 */
342 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
343 I915_WRITE(GMBUS1 + reg_offset, 0);
438 /* Toggle the Software Clear Interrupt bit. This has the effect
439 * of resetting the GMBUS controller and so clearing the
440 * BUS_ERROR raised by the slave's NAK.
441 */
442 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
443 I915_WRITE(GMBUS1 + reg_offset, 0);
344 error = EIO;
345 goto done;
444 I915_WRITE(GMBUS0 + reg_offset, 0);
346
445
446 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
447 sc->name, msgs[i].slave,
448 (msgs[i].flags & IIC_M_RD) ? 'r' : 'w', msgs[i].len);
449
450 /*
451 * If no ACK is received during the address phase of a transaction,
452 * the adapter must report -ENXIO.
453 * It is not clear what to return if no ACK is received at other times.
454 * So, we always return -ENXIO in all NAK cases, to ensure we send
455 * it at least during the one case that is specified.
456 */
457 error = ENXIO;
458 goto out;
459
347timeout:
460timeout:
348 DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
349 sc->reg0 & 0xff, sc->name);
461 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
462 sc->name, sc->reg0 & 0xff);
350 I915_WRITE(GMBUS0 + reg_offset, 0);
351
352 /*
353 * Hardware may not support GMBUS over these pins?
354 * Try GPIO bitbanging instead.
355 */
356 sc->force_bit_dev = true;
463 I915_WRITE(GMBUS0 + reg_offset, 0);
464
465 /*
466 * Hardware may not support GMBUS over these pins?
467 * Try GPIO bitbanging instead.
468 */
469 sc->force_bit_dev = true;
357
358 error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs);
470 error = IICBUS_TRANSFER(idev, msgs, nmsgs);
359 goto out;
471 goto out;
472
473out:
474 sx_xunlock(&dev_priv->gmbus_sx);
475 return (error);
360}
361
476}
477
478device_t
479intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
480 unsigned port)
481{
482
483 if (!intel_gmbus_is_port_valid(port))
484 DRM_ERROR("GMBUS get adapter %d: invalid port\n", port);
485 return (intel_gmbus_is_port_valid(port) ? dev_priv->gmbus[port - 1] :
486 NULL);
487}
488
362void
363intel_gmbus_set_speed(device_t idev, int speed)
364{
365 struct intel_iic_softc *sc;
366
367 sc = device_get_softc(device_get_parent(idev));
368
369 sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed;

--- 4 unchanged lines hidden (view full) ---

374{
375 struct intel_iic_softc *sc;
376
377 sc = device_get_softc(device_get_parent(idev));
378 sc->force_bit_dev = force_bit;
379}
380
381static int
489void
490intel_gmbus_set_speed(device_t idev, int speed)
491{
492 struct intel_iic_softc *sc;
493
494 sc = device_get_softc(device_get_parent(idev));
495
496 sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed;

--- 4 unchanged lines hidden (view full) ---

501{
502 struct intel_iic_softc *sc;
503
504 sc = device_get_softc(device_get_parent(idev));
505 sc->force_bit_dev = force_bit;
506}
507
508static int
382intel_iic_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs)
509intel_iicbb_pre_xfer(device_t idev)
383{
510{
384 device_t bridge_dev;
385 struct intel_iic_softc *sc;
386 struct drm_i915_private *dev_priv;
511 struct intel_iic_softc *sc;
512 struct drm_i915_private *dev_priv;
387 int ret;
388 int i;
389
513
390 bridge_dev = device_get_parent(device_get_parent(idev));
391 sc = device_get_softc(bridge_dev);
514 sc = device_get_softc(idev);
392 dev_priv = sc->drm_dev->dev_private;
393
394 intel_iic_reset(sc->drm_dev);
395 intel_iic_quirk_set(dev_priv, true);
515 dev_priv = sc->drm_dev->dev_private;
516
517 intel_iic_reset(sc->drm_dev);
518 intel_iic_quirk_set(dev_priv, true);
396 IICBB_SETSDA(bridge_dev, 1);
397 IICBB_SETSCL(bridge_dev, 1);
519 IICBB_SETSDA(idev, 1);
520 IICBB_SETSCL(idev, 1);
398 DELAY(I2C_RISEFALL_TIME);
521 DELAY(I2C_RISEFALL_TIME);
522 return (0);
523}
399
524
400 for (i = 0; i < nmsgs - 1; i++) {
401 /* force use of repeated start instead of default stop+start */
402 msgs[i].flags |= IIC_M_NOSTOP;
403 }
404 ret = iicbus_transfer(idev, msgs, nmsgs);
405 IICBB_SETSDA(bridge_dev, 1);
406 IICBB_SETSCL(bridge_dev, 1);
407 intel_iic_quirk_set(dev_priv, false);
525static void
526intel_iicbb_post_xfer(device_t idev)
527{
528 struct intel_iic_softc *sc;
529 struct drm_i915_private *dev_priv;
408
530
409 return (ret);
531 sc = device_get_softc(idev);
532 dev_priv = sc->drm_dev->dev_private;
533
534 IICBB_SETSDA(idev, 1);
535 IICBB_SETSCL(idev, 1);
536 intel_iic_quirk_set(dev_priv, false);
410}
411
537}
538
412static const char *gpio_names[GMBUS_NUM_PORTS] = {
413 "disabled",
414 "ssc",
415 "vga",
416 "panel",
417 "dpc",
418 "dpb",
419 "reserved",
420 "dpd",
421};
422
423static int
424intel_gmbus_probe(device_t dev)
425{
426
427 return (BUS_PROBE_SPECIFIC);
428}
429
430static int
431intel_gmbus_attach(device_t idev)
432{
433 struct drm_i915_private *dev_priv;
434 struct intel_iic_softc *sc;
539static int
540intel_gmbus_probe(device_t dev)
541{
542
543 return (BUS_PROBE_SPECIFIC);
544}
545
546static int
547intel_gmbus_attach(device_t idev)
548{
549 struct drm_i915_private *dev_priv;
550 struct intel_iic_softc *sc;
435 int pin;
551 int pin, port;
436
437 sc = device_get_softc(idev);
438 sc->drm_dev = device_get_softc(device_get_parent(idev));
439 dev_priv = sc->drm_dev->dev_private;
440 pin = device_get_unit(idev);
552
553 sc = device_get_softc(idev);
554 sc->drm_dev = device_get_softc(device_get_parent(idev));
555 dev_priv = sc->drm_dev->dev_private;
556 pin = device_get_unit(idev);
557 port = pin + 1;
441
558
442 snprintf(sc->name, sizeof(sc->name), "gmbus bus %s", gpio_names[pin]);
559 snprintf(sc->name, sizeof(sc->name), "gmbus %s", gmbus_ports[pin].name);
443 device_set_desc(idev, sc->name);
444
445 /* By default use a conservative clock rate */
560 device_set_desc(idev, sc->name);
561
562 /* By default use a conservative clock rate */
446 sc->reg0 = pin | GMBUS_RATE_100KHZ;
563 sc->reg0 = port | GMBUS_RATE_100KHZ;
447
564
448 /* XXX force bit banging until GMBUS is fully debugged */
565 /* gmbus seems to be broken on i830 */
566 if (IS_I830(sc->drm_dev))
567 sc->force_bit_dev = true;
568#if 0
449 if (IS_GEN2(sc->drm_dev)) {
450 sc->force_bit_dev = true;
451 }
569 if (IS_GEN2(sc->drm_dev)) {
570 sc->force_bit_dev = true;
571 }
572#endif
452
453 /* add bus interface device */
454 sc->iic_dev = device_add_child(idev, "iicbus", -1);
455 if (sc->iic_dev == NULL)
456 return (ENXIO);
457 device_quiet(sc->iic_dev);
458 bus_generic_attach(idev);
459

--- 25 unchanged lines hidden (view full) ---

485{
486
487 return (BUS_PROBE_DEFAULT);
488}
489
490static int
491intel_iicbb_attach(device_t idev)
492{
573
574 /* add bus interface device */
575 sc->iic_dev = device_add_child(idev, "iicbus", -1);
576 if (sc->iic_dev == NULL)
577 return (ENXIO);
578 device_quiet(sc->iic_dev);
579 bus_generic_attach(idev);
580

--- 25 unchanged lines hidden (view full) ---

606{
607
608 return (BUS_PROBE_DEFAULT);
609}
610
611static int
612intel_iicbb_attach(device_t idev)
613{
493 static const int map_pin_to_reg[] = {
494 0,
495 GPIOB,
496 GPIOA,
497 GPIOC,
498 GPIOD,
499 GPIOE,
500 0,
501 GPIOF
502 };
503
504 struct intel_iic_softc *sc;
505 struct drm_i915_private *dev_priv;
506 int pin;
507
508 sc = device_get_softc(idev);
509 sc->drm_dev = device_get_softc(device_get_parent(idev));
510 dev_priv = sc->drm_dev->dev_private;
511 pin = device_get_unit(idev);
512
614 struct intel_iic_softc *sc;
615 struct drm_i915_private *dev_priv;
616 int pin;
617
618 sc = device_get_softc(idev);
619 sc->drm_dev = device_get_softc(device_get_parent(idev));
620 dev_priv = sc->drm_dev->dev_private;
621 pin = device_get_unit(idev);
622
513 snprintf(sc->name, sizeof(sc->name), "i915 iicbb %s", gpio_names[pin]);
623 snprintf(sc->name, sizeof(sc->name), "i915 iicbb %s",
624 gmbus_ports[pin].name);
514 device_set_desc(idev, sc->name);
515
516 sc->reg0 = pin | GMBUS_RATE_100KHZ;
625 device_set_desc(idev, sc->name);
626
627 sc->reg0 = pin | GMBUS_RATE_100KHZ;
517 sc->reg = map_pin_to_reg[pin];
518 if (HAS_PCH_SPLIT(dev_priv->dev))
519 sc->reg += PCH_GPIOA - GPIOA;
628 sc->reg = dev_priv->gpio_mmio_base + gmbus_ports[pin].reg;
520
521 /* add generic bit-banging code */
522 sc->iic_dev = device_add_child(idev, "iicbb", -1);
523 if (sc->iic_dev == NULL)
524 return (ENXIO);
525 device_quiet(sc->iic_dev);
526 bus_generic_attach(idev);
629
630 /* add generic bit-banging code */
631 sc->iic_dev = device_add_child(idev, "iicbb", -1);
632 if (sc->iic_dev == NULL)
633 return (ENXIO);
634 device_quiet(sc->iic_dev);
635 bus_generic_attach(idev);
636 iicbus_set_nostop(idev, true);
527
528 return (0);
529}
530
531static int
532intel_iicbb_detach(device_t idev)
533{
534 struct intel_iic_softc *sc;

--- 34 unchanged lines hidden (view full) ---

569 DEVMETHOD(bus_print_child, bus_generic_print_child),
570
571 DEVMETHOD(iicbb_callback, iicbus_null_callback),
572 DEVMETHOD(iicbb_reset, intel_iicbus_reset),
573 DEVMETHOD(iicbb_setsda, intel_iicbb_setsda),
574 DEVMETHOD(iicbb_setscl, intel_iicbb_setscl),
575 DEVMETHOD(iicbb_getsda, intel_iicbb_getsda),
576 DEVMETHOD(iicbb_getscl, intel_iicbb_getscl),
637
638 return (0);
639}
640
641static int
642intel_iicbb_detach(device_t idev)
643{
644 struct intel_iic_softc *sc;

--- 34 unchanged lines hidden (view full) ---

679 DEVMETHOD(bus_print_child, bus_generic_print_child),
680
681 DEVMETHOD(iicbb_callback, iicbus_null_callback),
682 DEVMETHOD(iicbb_reset, intel_iicbus_reset),
683 DEVMETHOD(iicbb_setsda, intel_iicbb_setsda),
684 DEVMETHOD(iicbb_setscl, intel_iicbb_setscl),
685 DEVMETHOD(iicbb_getsda, intel_iicbb_getsda),
686 DEVMETHOD(iicbb_getscl, intel_iicbb_getscl),
687 DEVMETHOD(iicbb_pre_xfer, intel_iicbb_pre_xfer),
688 DEVMETHOD(iicbb_post_xfer, intel_iicbb_post_xfer),
577 DEVMETHOD_END
578};
579static driver_t intel_iicbb_driver = {
580 "intel_iicbb",
581 intel_iicbb_methods,
582 sizeof(struct intel_iic_softc)
583};
584static devclass_t intel_iicbb_devclass;

--- 5 unchanged lines hidden (view full) ---

590intel_setup_gmbus(struct drm_device *dev)
591{
592 struct drm_i915_private *dev_priv;
593 device_t iic_dev;
594 int i, ret;
595
596 dev_priv = dev->dev_private;
597 sx_init(&dev_priv->gmbus_sx, "gmbus");
689 DEVMETHOD_END
690};
691static driver_t intel_iicbb_driver = {
692 "intel_iicbb",
693 intel_iicbb_methods,
694 sizeof(struct intel_iic_softc)
695};
696static devclass_t intel_iicbb_devclass;

--- 5 unchanged lines hidden (view full) ---

702intel_setup_gmbus(struct drm_device *dev)
703{
704 struct drm_i915_private *dev_priv;
705 device_t iic_dev;
706 int i, ret;
707
708 dev_priv = dev->dev_private;
709 sx_init(&dev_priv->gmbus_sx, "gmbus");
598 dev_priv->gmbus_bridge = malloc(sizeof(device_t) * GMBUS_NUM_PORTS,
599 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
600 dev_priv->bbbus_bridge = malloc(sizeof(device_t) * GMBUS_NUM_PORTS,
601 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
602 dev_priv->gmbus = malloc(sizeof(device_t) * GMBUS_NUM_PORTS,
603 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
604 dev_priv->bbbus = malloc(sizeof(device_t) * GMBUS_NUM_PORTS,
605 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
710 if (HAS_PCH_SPLIT(dev))
711 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
712 else
713 dev_priv->gpio_mmio_base = 0;
606
607 /*
608 * The Giant there is recursed, most likely. Normally, the
609 * intel_setup_gmbus() is called from the attach method of the
610 * driver.
611 */
612 mtx_lock(&Giant);
714
715 /*
716 * The Giant there is recursed, most likely. Normally, the
717 * intel_setup_gmbus() is called from the attach method of the
718 * driver.
719 */
720 mtx_lock(&Giant);
613 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
721 for (i = 0; i <= GMBUS_NUM_PORTS; i++) {
614 /*
615 * Initialized bbbus_bridge before gmbus_bridge, since
616 * gmbus may decide to force quirk transfer in the
617 * attachment code.
618 */
619 dev_priv->bbbus_bridge[i] = device_add_child(dev->device,
620 "intel_iicbb", i);
621 if (dev_priv->bbbus_bridge[i] == NULL) {

--- 62 unchanged lines hidden (view full) ---

684
685static void
686intel_teardown_gmbus_m(struct drm_device *dev, int m)
687{
688 struct drm_i915_private *dev_priv;
689
690 dev_priv = dev->dev_private;
691
722 /*
723 * Initialized bbbus_bridge before gmbus_bridge, since
724 * gmbus may decide to force quirk transfer in the
725 * attachment code.
726 */
727 dev_priv->bbbus_bridge[i] = device_add_child(dev->device,
728 "intel_iicbb", i);
729 if (dev_priv->bbbus_bridge[i] == NULL) {

--- 62 unchanged lines hidden (view full) ---

792
793static void
794intel_teardown_gmbus_m(struct drm_device *dev, int m)
795{
796 struct drm_i915_private *dev_priv;
797
798 dev_priv = dev->dev_private;
799
692 free(dev_priv->gmbus, DRM_MEM_DRIVER);
693 dev_priv->gmbus = NULL;
694 free(dev_priv->bbbus, DRM_MEM_DRIVER);
695 dev_priv->bbbus = NULL;
696 free(dev_priv->gmbus_bridge, DRM_MEM_DRIVER);
697 dev_priv->gmbus_bridge = NULL;
698 free(dev_priv->bbbus_bridge, DRM_MEM_DRIVER);
699 dev_priv->bbbus_bridge = NULL;
700 sx_destroy(&dev_priv->gmbus_sx);
701}
702
703void
704intel_teardown_gmbus(struct drm_device *dev)
705{
706
707 mtx_lock(&Giant);
708 intel_teardown_gmbus_m(dev, GMBUS_NUM_PORTS);
709 mtx_unlock(&Giant);
710}
800 sx_destroy(&dev_priv->gmbus_sx);
801}
802
803void
804intel_teardown_gmbus(struct drm_device *dev)
805{
806
807 mtx_lock(&Giant);
808 intel_teardown_gmbus_m(dev, GMBUS_NUM_PORTS);
809 mtx_unlock(&Giant);
810}