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if_bwn.c (204657) if_bwn.c (204922)
1/*-
2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 14 unchanged lines hidden (view full) ---

23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 14 unchanged lines hidden (view full) ---

23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/bwn/if_bwn.c 204657 2010-03-03 20:06:09Z weongyo $");
31__FBSDID("$FreeBSD: head/sys/dev/bwn/if_bwn.c 204922 2010-03-09 19:58:00Z weongyo $");
32
33/*
34 * The Broadcom Wireless LAN controller driver.
35 */
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/module.h>

--- 89 unchanged lines hidden (view full) ---

129 "uses DMA");
130TUNABLE_INT("hw.bwn.usedma", &bwn_usedma);
131static int bwn_wme = 1;
132SYSCTL_INT(_hw_bwn, OID_AUTO, wme, CTLFLAG_RW, &bwn_wme, 0,
133 "uses WME support");
134
135static int bwn_attach_pre(struct bwn_softc *);
136static int bwn_attach_post(struct bwn_softc *);
32
33/*
34 * The Broadcom Wireless LAN controller driver.
35 */
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/module.h>

--- 89 unchanged lines hidden (view full) ---

129 "uses DMA");
130TUNABLE_INT("hw.bwn.usedma", &bwn_usedma);
131static int bwn_wme = 1;
132SYSCTL_INT(_hw_bwn, OID_AUTO, wme, CTLFLAG_RW, &bwn_wme, 0,
133 "uses WME support");
134
135static int bwn_attach_pre(struct bwn_softc *);
136static int bwn_attach_post(struct bwn_softc *);
137static void bwn_sprom_bugfixes(struct siba_softc *);
137static void bwn_sprom_bugfixes(device_t);
138static void bwn_init(void *);
139static int bwn_init_locked(struct bwn_softc *);
140static int bwn_ioctl(struct ifnet *, u_long, caddr_t);
141static void bwn_start(struct ifnet *);
142static int bwn_attach_core(struct bwn_mac *);
143static void bwn_reset_core(struct bwn_mac *, uint32_t);
144static int bwn_phy_getinfo(struct bwn_mac *, int);
145static int bwn_chiptest(struct bwn_mac *);

--- 54 unchanged lines hidden (view full) ---

200 int, const uint8_t [IEEE80211_ADDR_LEN],
201 const uint8_t [IEEE80211_ADDR_LEN]);
202static void bwn_vap_delete(struct ieee80211vap *);
203static void bwn_stop(struct bwn_softc *, int);
204static void bwn_stop_locked(struct bwn_softc *, int);
205static int bwn_core_init(struct bwn_mac *);
206static void bwn_core_start(struct bwn_mac *);
207static void bwn_core_exit(struct bwn_mac *);
138static void bwn_init(void *);
139static int bwn_init_locked(struct bwn_softc *);
140static int bwn_ioctl(struct ifnet *, u_long, caddr_t);
141static void bwn_start(struct ifnet *);
142static int bwn_attach_core(struct bwn_mac *);
143static void bwn_reset_core(struct bwn_mac *, uint32_t);
144static int bwn_phy_getinfo(struct bwn_mac *, int);
145static int bwn_chiptest(struct bwn_mac *);

--- 54 unchanged lines hidden (view full) ---

200 int, const uint8_t [IEEE80211_ADDR_LEN],
201 const uint8_t [IEEE80211_ADDR_LEN]);
202static void bwn_vap_delete(struct ieee80211vap *);
203static void bwn_stop(struct bwn_softc *, int);
204static void bwn_stop_locked(struct bwn_softc *, int);
205static int bwn_core_init(struct bwn_mac *);
206static void bwn_core_start(struct bwn_mac *);
207static void bwn_core_exit(struct bwn_mac *);
208static void bwn_fix_imcfglobug(struct bwn_mac *);
209static void bwn_bt_disable(struct bwn_mac *);
210static int bwn_chip_init(struct bwn_mac *);
211static uint64_t bwn_hf_read(struct bwn_mac *);
212static void bwn_hf_write(struct bwn_mac *, uint64_t);
213static void bwn_set_txretry(struct bwn_mac *, int, int);
214static void bwn_rate_init(struct bwn_mac *);
215static void bwn_set_phytxctl(struct bwn_mac *);
216static void bwn_spu_setdelay(struct bwn_mac *, int);
217static void bwn_bt_enable(struct bwn_mac *);
218static void bwn_set_macaddr(struct bwn_mac *);
219static void bwn_crypt_init(struct bwn_mac *);
220static void bwn_chip_exit(struct bwn_mac *);
221static int bwn_fw_fillinfo(struct bwn_mac *);
222static int bwn_fw_loaducode(struct bwn_mac *);
223static int bwn_gpio_init(struct bwn_mac *);
224static int bwn_fw_loadinitvals(struct bwn_mac *);
225static int bwn_phy_init(struct bwn_mac *);
226static void bwn_set_txantenna(struct bwn_mac *, int);
227static void bwn_set_opmode(struct bwn_mac *);
208static void bwn_bt_disable(struct bwn_mac *);
209static int bwn_chip_init(struct bwn_mac *);
210static uint64_t bwn_hf_read(struct bwn_mac *);
211static void bwn_hf_write(struct bwn_mac *, uint64_t);
212static void bwn_set_txretry(struct bwn_mac *, int, int);
213static void bwn_rate_init(struct bwn_mac *);
214static void bwn_set_phytxctl(struct bwn_mac *);
215static void bwn_spu_setdelay(struct bwn_mac *, int);
216static void bwn_bt_enable(struct bwn_mac *);
217static void bwn_set_macaddr(struct bwn_mac *);
218static void bwn_crypt_init(struct bwn_mac *);
219static void bwn_chip_exit(struct bwn_mac *);
220static int bwn_fw_fillinfo(struct bwn_mac *);
221static int bwn_fw_loaducode(struct bwn_mac *);
222static int bwn_gpio_init(struct bwn_mac *);
223static int bwn_fw_loadinitvals(struct bwn_mac *);
224static int bwn_phy_init(struct bwn_mac *);
225static void bwn_set_txantenna(struct bwn_mac *, int);
226static void bwn_set_opmode(struct bwn_mac *);
228static void bwn_gpio_cleanup(struct bwn_mac *);
229static void bwn_rate_write(struct bwn_mac *, uint16_t, int);
230static uint8_t bwn_plcp_getcck(const uint8_t);
231static uint8_t bwn_plcp_getofdm(const uint8_t);
232static void bwn_pio_init(struct bwn_mac *);
233static uint16_t bwn_pio_idx2base(struct bwn_mac *, int);
234static void bwn_pio_set_txqueue(struct bwn_mac *, struct bwn_pio_txqueue *,
235 int);
236static void bwn_pio_setupqueue_rx(struct bwn_mac *,

--- 668 unchanged lines hidden (view full) ---

905 SIBA_DEV(BROADCOM, 80211, 13, "Revision 13"),
906 SIBA_DEV(BROADCOM, 80211, 15, "Revision 15"),
907 SIBA_DEV(BROADCOM, 80211, 16, "Revision 16")
908};
909
910static int
911bwn_probe(device_t dev)
912{
227static void bwn_rate_write(struct bwn_mac *, uint16_t, int);
228static uint8_t bwn_plcp_getcck(const uint8_t);
229static uint8_t bwn_plcp_getofdm(const uint8_t);
230static void bwn_pio_init(struct bwn_mac *);
231static uint16_t bwn_pio_idx2base(struct bwn_mac *, int);
232static void bwn_pio_set_txqueue(struct bwn_mac *, struct bwn_pio_txqueue *,
233 int);
234static void bwn_pio_setupqueue_rx(struct bwn_mac *,

--- 668 unchanged lines hidden (view full) ---

903 SIBA_DEV(BROADCOM, 80211, 13, "Revision 13"),
904 SIBA_DEV(BROADCOM, 80211, 15, "Revision 15"),
905 SIBA_DEV(BROADCOM, 80211, 16, "Revision 16")
906};
907
908static int
909bwn_probe(device_t dev)
910{
913 struct siba_dev_softc *sd = device_get_ivars(dev);
914 int i;
915
916 for (i = 0; i < sizeof(bwn_devs) / sizeof(bwn_devs[0]); i++) {
911 int i;
912
913 for (i = 0; i < sizeof(bwn_devs) / sizeof(bwn_devs[0]); i++) {
917 if (sd->sd_id.sd_vendor == bwn_devs[i].sd_vendor &&
918 sd->sd_id.sd_device == bwn_devs[i].sd_device &&
919 sd->sd_id.sd_rev == bwn_devs[i].sd_rev)
914 if (siba_get_vendor(dev) == bwn_devs[i].sd_vendor &&
915 siba_get_device(dev) == bwn_devs[i].sd_device &&
916 siba_get_revid(dev) == bwn_devs[i].sd_rev)
920 return (BUS_PROBE_DEFAULT);
921 }
922
923 return (ENXIO);
924}
925
926static int
927bwn_attach(device_t dev)
928{
929 struct bwn_mac *mac;
930 struct bwn_softc *sc = device_get_softc(dev);
917 return (BUS_PROBE_DEFAULT);
918 }
919
920 return (ENXIO);
921}
922
923static int
924bwn_attach(device_t dev)
925{
926 struct bwn_mac *mac;
927 struct bwn_softc *sc = device_get_softc(dev);
931 struct siba_dev_softc *sd = device_get_ivars(dev);
932 struct siba_softc *siba = sd->sd_bus;
933 int error, i, msic, reg;
934
935 sc->sc_dev = dev;
928 int error, i, msic, reg;
929
930 sc->sc_dev = dev;
936 sc->sc_sd = sd;
937#ifdef BWN_DEBUG
938 sc->sc_debug = bwn_debug;
939#endif
940
941 if ((sc->sc_flags & BWN_FLAG_ATTACHED) == 0) {
942 error = bwn_attach_pre(sc);
943 if (error != 0)
944 return (error);
931#ifdef BWN_DEBUG
932 sc->sc_debug = bwn_debug;
933#endif
934
935 if ((sc->sc_flags & BWN_FLAG_ATTACHED) == 0) {
936 error = bwn_attach_pre(sc);
937 if (error != 0)
938 return (error);
945 bwn_sprom_bugfixes(sd->sd_bus);
939 bwn_sprom_bugfixes(dev);
946 sc->sc_flags |= BWN_FLAG_ATTACHED;
947 }
948
949 if (!TAILQ_EMPTY(&sc->sc_maclist)) {
940 sc->sc_flags |= BWN_FLAG_ATTACHED;
941 }
942
943 if (!TAILQ_EMPTY(&sc->sc_maclist)) {
950 if (siba->siba_pci_did != 0x4313 &&
951 siba->siba_pci_did != 0x431a &&
952 siba->siba_pci_did != 0x4321) {
944 if (siba_get_pci_device(dev) != 0x4313 &&
945 siba_get_pci_device(dev) != 0x431a &&
946 siba_get_pci_device(dev) != 0x4321) {
953 device_printf(sc->sc_dev,
954 "skip 802.11 cores\n");
955 return (ENODEV);
956 }
957 }
958
959 mac = (struct bwn_mac *)malloc(sizeof(*mac), M_DEVBUF,
960 M_NOWAIT | M_ZERO);
961 if (mac == NULL)
962 return (ENOMEM);
963 mac->mac_sc = sc;
947 device_printf(sc->sc_dev,
948 "skip 802.11 cores\n");
949 return (ENODEV);
950 }
951 }
952
953 mac = (struct bwn_mac *)malloc(sizeof(*mac), M_DEVBUF,
954 M_NOWAIT | M_ZERO);
955 if (mac == NULL)
956 return (ENOMEM);
957 mac->mac_sc = sc;
964 mac->mac_sd = sd;
965 mac->mac_status = BWN_MAC_STATUS_UNINIT;
966 if (bwn_bfp != 0)
967 mac->mac_flags |= BWN_MAC_FLAG_BADFRAME_PREEMP;
968
969 TASK_INIT(&mac->mac_hwreset, 0, bwn_hwreset, mac);
970 TASK_INIT(&mac->mac_intrtask, 0, bwn_intrtask, mac);
971 TASK_INIT(&mac->mac_txpower, 0, bwn_txpwr, mac);
972
973 error = bwn_attach_core(mac);
974 if (error)
975 goto fail0;
976 bwn_led_attach(mac);
977
978 device_printf(sc->sc_dev, "WLAN (chipid %#x rev %u) "
979 "PHY (analog %d type %d rev %d) RADIO (manuf %#x ver %#x rev %d)\n",
958 mac->mac_status = BWN_MAC_STATUS_UNINIT;
959 if (bwn_bfp != 0)
960 mac->mac_flags |= BWN_MAC_FLAG_BADFRAME_PREEMP;
961
962 TASK_INIT(&mac->mac_hwreset, 0, bwn_hwreset, mac);
963 TASK_INIT(&mac->mac_intrtask, 0, bwn_intrtask, mac);
964 TASK_INIT(&mac->mac_txpower, 0, bwn_txpwr, mac);
965
966 error = bwn_attach_core(mac);
967 if (error)
968 goto fail0;
969 bwn_led_attach(mac);
970
971 device_printf(sc->sc_dev, "WLAN (chipid %#x rev %u) "
972 "PHY (analog %d type %d rev %d) RADIO (manuf %#x ver %#x rev %d)\n",
980 sd->sd_bus->siba_chipid, sd->sd_id.sd_rev,
973 siba_get_chipid(sc->sc_dev), siba_get_revid(sc->sc_dev),
981 mac->mac_phy.analog, mac->mac_phy.type, mac->mac_phy.rev,
982 mac->mac_phy.rf_manuf, mac->mac_phy.rf_ver,
983 mac->mac_phy.rf_rev);
984 if (mac->mac_flags & BWN_MAC_FLAG_DMA)
985 device_printf(sc->sc_dev, "DMA (%d bits)\n",
986 mac->mac_method.dma.dmatype);
987 else
988 device_printf(sc->sc_dev, "PIO\n");

--- 71 unchanged lines hidden (view full) ---

1060 return (TRUE);
1061}
1062
1063static int
1064bwn_attach_post(struct bwn_softc *sc)
1065{
1066 struct ieee80211com *ic;
1067 struct ifnet *ifp = sc->sc_ifp;
974 mac->mac_phy.analog, mac->mac_phy.type, mac->mac_phy.rev,
975 mac->mac_phy.rf_manuf, mac->mac_phy.rf_ver,
976 mac->mac_phy.rf_rev);
977 if (mac->mac_flags & BWN_MAC_FLAG_DMA)
978 device_printf(sc->sc_dev, "DMA (%d bits)\n",
979 mac->mac_method.dma.dmatype);
980 else
981 device_printf(sc->sc_dev, "PIO\n");

--- 71 unchanged lines hidden (view full) ---

1053 return (TRUE);
1054}
1055
1056static int
1057bwn_attach_post(struct bwn_softc *sc)
1058{
1059 struct ieee80211com *ic;
1060 struct ifnet *ifp = sc->sc_ifp;
1068 struct siba_dev_softc *sd = sc->sc_sd;
1069 struct siba_sprom *sprom = &sd->sd_bus->siba_sprom;
1070
1071 ic = ifp->if_l2com;
1072 ic->ic_ifp = ifp;
1073 /* XXX not right but it's not used anywhere important */
1074 ic->ic_phytype = IEEE80211_T_OFDM;
1075 ic->ic_opmode = IEEE80211_M_STA;
1076 ic->ic_caps =
1077 IEEE80211_C_STA /* station mode supported */

--- 4 unchanged lines hidden (view full) ---

1082 | IEEE80211_C_WME /* WME/WMM supported */
1083 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
1084 | IEEE80211_C_BGSCAN /* capable of bg scanning */
1085 | IEEE80211_C_TXPMGT /* capable of txpow mgt */
1086 ;
1087
1088 /* call MI attach routine. */
1089 ieee80211_ifattach(ic,
1061
1062 ic = ifp->if_l2com;
1063 ic->ic_ifp = ifp;
1064 /* XXX not right but it's not used anywhere important */
1065 ic->ic_phytype = IEEE80211_T_OFDM;
1066 ic->ic_opmode = IEEE80211_M_STA;
1067 ic->ic_caps =
1068 IEEE80211_C_STA /* station mode supported */

--- 4 unchanged lines hidden (view full) ---

1073 | IEEE80211_C_WME /* WME/WMM supported */
1074 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
1075 | IEEE80211_C_BGSCAN /* capable of bg scanning */
1076 | IEEE80211_C_TXPMGT /* capable of txpow mgt */
1077 ;
1078
1079 /* call MI attach routine. */
1080 ieee80211_ifattach(ic,
1090 bwn_is_valid_ether_addr(sprom->mac_80211a) ? sprom->mac_80211a :
1091 sprom->mac_80211bg);
1081 bwn_is_valid_ether_addr(siba_sprom_get_mac_80211a(sc->sc_dev)) ?
1082 siba_sprom_get_mac_80211a(sc->sc_dev) :
1083 siba_sprom_get_mac_80211bg(sc->sc_dev));
1092
1093 ic->ic_headroom = sizeof(struct bwn_txhdr);
1094
1095 /* override default methods */
1096 ic->ic_raw_xmit = bwn_raw_xmit;
1097 ic->ic_newassoc = bwn_newassoc;
1098 ic->ic_updateslot = bwn_updateslot;
1099 ic->ic_update_promisc = bwn_update_promisc;

--- 114 unchanged lines hidden (view full) ---

1214
1215 return (0);
1216
1217fail: BWN_LOCK_DESTROY(sc);
1218 return (error);
1219}
1220
1221static void
1084
1085 ic->ic_headroom = sizeof(struct bwn_txhdr);
1086
1087 /* override default methods */
1088 ic->ic_raw_xmit = bwn_raw_xmit;
1089 ic->ic_newassoc = bwn_newassoc;
1090 ic->ic_updateslot = bwn_updateslot;
1091 ic->ic_update_promisc = bwn_update_promisc;

--- 114 unchanged lines hidden (view full) ---

1206
1207 return (0);
1208
1209fail: BWN_LOCK_DESTROY(sc);
1210 return (error);
1211}
1212
1213static void
1222bwn_sprom_bugfixes(struct siba_softc *siba)
1214bwn_sprom_bugfixes(device_t dev)
1223{
1224#define BWN_ISDEV(_vendor, _device, _subvendor, _subdevice) \
1215{
1216#define BWN_ISDEV(_vendor, _device, _subvendor, _subdevice) \
1225 ((siba->siba_pci_vid == PCI_VENDOR_##_vendor) && \
1226 (siba->siba_pci_did == _device) && \
1227 (siba->siba_pci_subvid == PCI_VENDOR_##_subvendor) && \
1228 (siba->siba_pci_subdid == _subdevice))
1217 ((siba_get_pci_vendor(dev) == PCI_VENDOR_##_vendor) && \
1218 (siba_get_pci_device(dev) == _device) && \
1219 (siba_get_pci_subvendor(dev) == PCI_VENDOR_##_subvendor) && \
1220 (siba_get_pci_subdevice(dev) == _subdevice))
1229
1221
1230 if (siba->siba_board_vendor == PCI_VENDOR_APPLE &&
1231 siba->siba_board_type == 0x4e && siba->siba_board_rev > 0x40)
1232 siba->siba_sprom.bf_lo |= BWN_BFL_PACTRL;
1233 if (siba->siba_board_vendor == SIBA_BOARDVENDOR_DELL &&
1234 siba->siba_chipid == 0x4301 && siba->siba_board_rev == 0x74)
1235 siba->siba_sprom.bf_lo |= BWN_BFL_BTCOEXIST;
1236 if (siba->siba_type == SIBA_TYPE_PCI) {
1222 if (siba_get_pci_subvendor(dev) == PCI_VENDOR_APPLE &&
1223 siba_get_pci_subdevice(dev) == 0x4e &&
1224 siba_get_pci_revid(dev) > 0x40)
1225 siba_sprom_set_bf_lo(dev,
1226 siba_sprom_get_bf_lo(dev) | BWN_BFL_PACTRL);
1227 if (siba_get_pci_subvendor(dev) == SIBA_BOARDVENDOR_DELL &&
1228 siba_get_chipid(dev) == 0x4301 && siba_get_pci_revid(dev) == 0x74)
1229 siba_sprom_set_bf_lo(dev,
1230 siba_sprom_get_bf_lo(dev) | BWN_BFL_BTCOEXIST);
1231 if (siba_get_type(dev) == SIBA_TYPE_PCI) {
1237 if (BWN_ISDEV(BROADCOM, 0x4318, ASUSTEK, 0x100f) ||
1238 BWN_ISDEV(BROADCOM, 0x4320, DELL, 0x0003) ||
1239 BWN_ISDEV(BROADCOM, 0x4320, HP, 0x12f8) ||
1240 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0013) ||
1241 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0014) ||
1242 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0015) ||
1243 BWN_ISDEV(BROADCOM, 0x4320, MOTOROLA, 0x7010))
1232 if (BWN_ISDEV(BROADCOM, 0x4318, ASUSTEK, 0x100f) ||
1233 BWN_ISDEV(BROADCOM, 0x4320, DELL, 0x0003) ||
1234 BWN_ISDEV(BROADCOM, 0x4320, HP, 0x12f8) ||
1235 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0013) ||
1236 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0014) ||
1237 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0015) ||
1238 BWN_ISDEV(BROADCOM, 0x4320, MOTOROLA, 0x7010))
1244 siba->siba_sprom.bf_lo &= ~BWN_BFL_BTCOEXIST;
1239 siba_sprom_set_bf_lo(dev,
1240 siba_sprom_get_bf_lo(dev) & ~BWN_BFL_BTCOEXIST);
1245 }
1246#undef BWN_ISDEV
1247}
1248
1249static int
1250bwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1251{
1252#define IS_RUNNING(ifp) \

--- 176 unchanged lines hidden (view full) ---

1429 device_printf(sc->sc_dev, "tx fail\n");
1430 return (error);
1431 }
1432
1433 TAILQ_REMOVE(&tq->tq_pktlist, tp, tp_list);
1434 tq->tq_used += roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4);
1435 tq->tq_free--;
1436
1241 }
1242#undef BWN_ISDEV
1243}
1244
1245static int
1246bwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1247{
1248#define IS_RUNNING(ifp) \

--- 176 unchanged lines hidden (view full) ---

1425 device_printf(sc->sc_dev, "tx fail\n");
1426 return (error);
1427 }
1428
1429 TAILQ_REMOVE(&tq->tq_pktlist, tp, tp_list);
1430 tq->tq_used += roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4);
1431 tq->tq_free--;
1432
1437 if (mac->mac_sd->sd_id.sd_rev >= 8) {
1433 if (siba_get_revid(sc->sc_dev) >= 8) {
1438 /*
1439 * XXX please removes m_defrag(9)
1440 */
1441 m_new = m_defrag(m, M_DONTWAIT);
1442 if (m_new == NULL) {
1443 device_printf(sc->sc_dev,
1444 "%s: can't defrag TX buffer\n",
1445 __func__);

--- 155 unchanged lines hidden (view full) ---

1601 }
1602 callout_schedule(&sc->sc_watchdog_ch, hz);
1603}
1604
1605static int
1606bwn_attach_core(struct bwn_mac *mac)
1607{
1608 struct bwn_softc *sc = mac->mac_sc;
1434 /*
1435 * XXX please removes m_defrag(9)
1436 */
1437 m_new = m_defrag(m, M_DONTWAIT);
1438 if (m_new == NULL) {
1439 device_printf(sc->sc_dev,
1440 "%s: can't defrag TX buffer\n",
1441 __func__);

--- 155 unchanged lines hidden (view full) ---

1597 }
1598 callout_schedule(&sc->sc_watchdog_ch, hz);
1599}
1600
1601static int
1602bwn_attach_core(struct bwn_mac *mac)
1603{
1604 struct bwn_softc *sc = mac->mac_sc;
1609 struct siba_dev_softc *sd = mac->mac_sd;
1610 struct siba_softc *siba = sd->sd_bus;
1611 int error, have_bg = 0, have_a = 0;
1612 uint32_t high;
1613
1605 int error, have_bg = 0, have_a = 0;
1606 uint32_t high;
1607
1614 KASSERT(sd->sd_id.sd_rev >= 5,
1615 ("unsupported revision %d", sd->sd_id.sd_rev));
1608 KASSERT(siba_get_revid(sc->sc_dev) >= 5,
1609 ("unsupported revision %d", siba_get_revid(sc->sc_dev)));
1616
1610
1617 siba_powerup(siba, 0);
1611 siba_powerup(sc->sc_dev, 0);
1618
1612
1619 high = siba_read_4(sd, SIBA_TGSHIGH);
1613 high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH);
1620 bwn_reset_core(mac,
1621 (high & BWN_TGSHIGH_HAVE_2GHZ) ? BWN_TGSLOW_SUPPORT_G : 0);
1622 error = bwn_phy_getinfo(mac, high);
1623 if (error)
1624 goto fail;
1625
1626 have_a = (high & BWN_TGSHIGH_HAVE_5GHZ) ? 1 : 0;
1627 have_bg = (high & BWN_TGSHIGH_HAVE_2GHZ) ? 1 : 0;
1614 bwn_reset_core(mac,
1615 (high & BWN_TGSHIGH_HAVE_2GHZ) ? BWN_TGSLOW_SUPPORT_G : 0);
1616 error = bwn_phy_getinfo(mac, high);
1617 if (error)
1618 goto fail;
1619
1620 have_a = (high & BWN_TGSHIGH_HAVE_5GHZ) ? 1 : 0;
1621 have_bg = (high & BWN_TGSHIGH_HAVE_2GHZ) ? 1 : 0;
1628 if (siba->siba_pci_did != 0x4312 && siba->siba_pci_did != 0x4319 &&
1629 siba->siba_pci_did != 0x4324) {
1622 if (siba_get_pci_device(sc->sc_dev) != 0x4312 &&
1623 siba_get_pci_device(sc->sc_dev) != 0x4319 &&
1624 siba_get_pci_device(sc->sc_dev) != 0x4324) {
1630 have_a = have_bg = 0;
1631 if (mac->mac_phy.type == BWN_PHYTYPE_A)
1632 have_a = 1;
1633 else if (mac->mac_phy.type == BWN_PHYTYPE_G ||
1634 mac->mac_phy.type == BWN_PHYTYPE_N ||
1635 mac->mac_phy.type == BWN_PHYTYPE_LP)
1636 have_bg = 1;
1637 else

--- 76 unchanged lines hidden (view full) ---

1714 error = bwn_dma_attach(mac);
1715 if (error != 0) {
1716 device_printf(sc->sc_dev, "failed to initialize DMA\n");
1717 goto fail;
1718 }
1719
1720 mac->mac_phy.switch_analog(mac, 0);
1721
1625 have_a = have_bg = 0;
1626 if (mac->mac_phy.type == BWN_PHYTYPE_A)
1627 have_a = 1;
1628 else if (mac->mac_phy.type == BWN_PHYTYPE_G ||
1629 mac->mac_phy.type == BWN_PHYTYPE_N ||
1630 mac->mac_phy.type == BWN_PHYTYPE_LP)
1631 have_bg = 1;
1632 else

--- 76 unchanged lines hidden (view full) ---

1709 error = bwn_dma_attach(mac);
1710 if (error != 0) {
1711 device_printf(sc->sc_dev, "failed to initialize DMA\n");
1712 goto fail;
1713 }
1714
1715 mac->mac_phy.switch_analog(mac, 0);
1716
1722 siba_dev_down(sd, 0);
1717 siba_dev_down(sc->sc_dev, 0);
1723fail:
1718fail:
1724 siba_powerdown(siba);
1719 siba_powerdown(sc->sc_dev);
1725 return (error);
1726}
1727
1728static void
1729bwn_reset_core(struct bwn_mac *mac, uint32_t flags)
1730{
1720 return (error);
1721}
1722
1723static void
1724bwn_reset_core(struct bwn_mac *mac, uint32_t flags)
1725{
1731 struct siba_dev_softc *sd = mac->mac_sd;
1726 struct bwn_softc *sc = mac->mac_sc;
1732 uint32_t low, ctl;
1733
1734 flags |= (BWN_TGSLOW_PHYCLOCK_ENABLE | BWN_TGSLOW_PHYRESET);
1735
1727 uint32_t low, ctl;
1728
1729 flags |= (BWN_TGSLOW_PHYCLOCK_ENABLE | BWN_TGSLOW_PHYRESET);
1730
1736 siba_dev_up(sd, flags);
1731 siba_dev_up(sc->sc_dev, flags);
1737 DELAY(2000);
1738
1732 DELAY(2000);
1733
1739 low = (siba_read_4(sd, SIBA_TGSLOW) | SIBA_TGSLOW_FGC) &
1734 low = (siba_read_4(sc->sc_dev, SIBA_TGSLOW) | SIBA_TGSLOW_FGC) &
1740 ~BWN_TGSLOW_PHYRESET;
1735 ~BWN_TGSLOW_PHYRESET;
1741 siba_write_4(sd, SIBA_TGSLOW, low);
1742 siba_read_4(sd, SIBA_TGSLOW);
1736 siba_write_4(sc->sc_dev, SIBA_TGSLOW, low);
1737 siba_read_4(sc->sc_dev, SIBA_TGSLOW);
1743 DELAY(1000);
1738 DELAY(1000);
1744 siba_write_4(sd, SIBA_TGSLOW, low & ~SIBA_TGSLOW_FGC);
1745 siba_read_4(sd, SIBA_TGSLOW);
1739 siba_write_4(sc->sc_dev, SIBA_TGSLOW, low & ~SIBA_TGSLOW_FGC);
1740 siba_read_4(sc->sc_dev, SIBA_TGSLOW);
1746 DELAY(1000);
1747
1748 if (mac->mac_phy.switch_analog != NULL)
1749 mac->mac_phy.switch_analog(mac, 1);
1750
1751 ctl = BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GMODE;
1752 if (flags & BWN_TGSLOW_SUPPORT_G)
1753 ctl |= BWN_MACCTL_GMODE;
1754 BWN_WRITE_4(mac, BWN_MACCTL, ctl | BWN_MACCTL_IHR_ON);
1755}
1756
1757static int
1758bwn_phy_getinfo(struct bwn_mac *mac, int tgshigh)
1759{
1760 struct bwn_phy *phy = &mac->mac_phy;
1761 struct bwn_softc *sc = mac->mac_sc;
1741 DELAY(1000);
1742
1743 if (mac->mac_phy.switch_analog != NULL)
1744 mac->mac_phy.switch_analog(mac, 1);
1745
1746 ctl = BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GMODE;
1747 if (flags & BWN_TGSLOW_SUPPORT_G)
1748 ctl |= BWN_MACCTL_GMODE;
1749 BWN_WRITE_4(mac, BWN_MACCTL, ctl | BWN_MACCTL_IHR_ON);
1750}
1751
1752static int
1753bwn_phy_getinfo(struct bwn_mac *mac, int tgshigh)
1754{
1755 struct bwn_phy *phy = &mac->mac_phy;
1756 struct bwn_softc *sc = mac->mac_sc;
1762 struct siba_dev_softc *sd = mac->mac_sd;
1763 struct siba_softc *siba = sd->sd_bus;
1764 uint32_t tmp;
1765
1766 /* PHY */
1767 tmp = BWN_READ_2(mac, BWN_PHYVER);
1768 phy->gmode = (tgshigh & BWN_TGSHIGH_HAVE_2GHZ) ? 1 : 0;
1769 phy->rf_on = 1;
1770 phy->analog = (tmp & BWN_PHYVER_ANALOG) >> 12;
1771 phy->type = (tmp & BWN_PHYVER_TYPE) >> 8;
1772 phy->rev = (tmp & BWN_PHYVER_VERSION);
1773 if ((phy->type == BWN_PHYTYPE_A && phy->rev >= 4) ||
1774 (phy->type == BWN_PHYTYPE_B && phy->rev != 2 &&
1775 phy->rev != 4 && phy->rev != 6 && phy->rev != 7) ||
1776 (phy->type == BWN_PHYTYPE_G && phy->rev > 9) ||
1777 (phy->type == BWN_PHYTYPE_N && phy->rev > 4) ||
1778 (phy->type == BWN_PHYTYPE_LP && phy->rev > 2))
1779 goto unsupphy;
1780
1781 /* RADIO */
1757 uint32_t tmp;
1758
1759 /* PHY */
1760 tmp = BWN_READ_2(mac, BWN_PHYVER);
1761 phy->gmode = (tgshigh & BWN_TGSHIGH_HAVE_2GHZ) ? 1 : 0;
1762 phy->rf_on = 1;
1763 phy->analog = (tmp & BWN_PHYVER_ANALOG) >> 12;
1764 phy->type = (tmp & BWN_PHYVER_TYPE) >> 8;
1765 phy->rev = (tmp & BWN_PHYVER_VERSION);
1766 if ((phy->type == BWN_PHYTYPE_A && phy->rev >= 4) ||
1767 (phy->type == BWN_PHYTYPE_B && phy->rev != 2 &&
1768 phy->rev != 4 && phy->rev != 6 && phy->rev != 7) ||
1769 (phy->type == BWN_PHYTYPE_G && phy->rev > 9) ||
1770 (phy->type == BWN_PHYTYPE_N && phy->rev > 4) ||
1771 (phy->type == BWN_PHYTYPE_LP && phy->rev > 2))
1772 goto unsupphy;
1773
1774 /* RADIO */
1782 if (siba->siba_chipid == 0x4317) {
1783 if (siba->siba_chiprev == 0)
1775 if (siba_get_chipid(sc->sc_dev) == 0x4317) {
1776 if (siba_get_chiprev(sc->sc_dev) == 0)
1784 tmp = 0x3205017f;
1777 tmp = 0x3205017f;
1785 else if (siba->siba_chiprev == 1)
1778 else if (siba_get_chiprev(sc->sc_dev) == 1)
1786 tmp = 0x4205017f;
1787 else
1788 tmp = 0x5205017f;
1789 } else {
1790 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
1791 tmp = BWN_READ_2(mac, BWN_RFDATALO);
1792 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
1793 tmp |= (uint32_t)BWN_READ_2(mac, BWN_RFDATAHI) << 16;

--- 27 unchanged lines hidden (view full) ---

1821}
1822
1823static int
1824bwn_chiptest(struct bwn_mac *mac)
1825{
1826#define TESTVAL0 0x55aaaa55
1827#define TESTVAL1 0xaa5555aa
1828 struct bwn_softc *sc = mac->mac_sc;
1779 tmp = 0x4205017f;
1780 else
1781 tmp = 0x5205017f;
1782 } else {
1783 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
1784 tmp = BWN_READ_2(mac, BWN_RFDATALO);
1785 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
1786 tmp |= (uint32_t)BWN_READ_2(mac, BWN_RFDATAHI) << 16;

--- 27 unchanged lines hidden (view full) ---

1814}
1815
1816static int
1817bwn_chiptest(struct bwn_mac *mac)
1818{
1819#define TESTVAL0 0x55aaaa55
1820#define TESTVAL1 0xaa5555aa
1821 struct bwn_softc *sc = mac->mac_sc;
1829 struct siba_dev_softc *sd = mac->mac_sd;
1830 uint32_t v, backup;
1831
1832 BWN_LOCK(sc);
1833
1834 backup = bwn_shm_read_4(mac, BWN_SHARED, 0);
1835
1836 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL0);
1837 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL0)
1838 goto error;
1839 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL1);
1840 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL1)
1841 goto error;
1842
1843 bwn_shm_write_4(mac, BWN_SHARED, 0, backup);
1844
1822 uint32_t v, backup;
1823
1824 BWN_LOCK(sc);
1825
1826 backup = bwn_shm_read_4(mac, BWN_SHARED, 0);
1827
1828 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL0);
1829 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL0)
1830 goto error;
1831 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL1);
1832 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL1)
1833 goto error;
1834
1835 bwn_shm_write_4(mac, BWN_SHARED, 0, backup);
1836
1845 if ((sd->sd_id.sd_rev >= 3) && (sd->sd_id.sd_rev <= 10)) {
1837 if ((siba_get_revid(sc->sc_dev) >= 3) &&
1838 (siba_get_revid(sc->sc_dev) <= 10)) {
1846 BWN_WRITE_2(mac, BWN_TSF_CFP_START, 0xaaaa);
1847 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0xccccbbbb);
1848 if (BWN_READ_2(mac, BWN_TSF_CFP_START_LOW) != 0xbbbb)
1849 goto error;
1850 if (BWN_READ_2(mac, BWN_TSF_CFP_START_HIGH) != 0xcccc)
1851 goto error;
1852 }
1853 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0);

--- 211 unchanged lines hidden (view full) ---

2065}
2066
2067static int
2068bwn_phy_g_attach(struct bwn_mac *mac)
2069{
2070 struct bwn_softc *sc = mac->mac_sc;
2071 struct bwn_phy *phy = &mac->mac_phy;
2072 struct bwn_phy_g *pg = &phy->phy_g;
1839 BWN_WRITE_2(mac, BWN_TSF_CFP_START, 0xaaaa);
1840 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0xccccbbbb);
1841 if (BWN_READ_2(mac, BWN_TSF_CFP_START_LOW) != 0xbbbb)
1842 goto error;
1843 if (BWN_READ_2(mac, BWN_TSF_CFP_START_HIGH) != 0xcccc)
1844 goto error;
1845 }
1846 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0);

--- 211 unchanged lines hidden (view full) ---

2058}
2059
2060static int
2061bwn_phy_g_attach(struct bwn_mac *mac)
2062{
2063 struct bwn_softc *sc = mac->mac_sc;
2064 struct bwn_phy *phy = &mac->mac_phy;
2065 struct bwn_phy_g *pg = &phy->phy_g;
2073 struct siba_dev_softc *sd = mac->mac_sd;
2074 struct siba_sprom *sprom = &sd->sd_bus->siba_sprom;
2075 unsigned int i;
2066 unsigned int i;
2076 int16_t pab0 = (int16_t)(sprom->pa0b0), pab1 = (int16_t)(sprom->pa0b1),
2077 pab2 = (int16_t)(sprom->pa0b2);
2067 int16_t pab0, pab1, pab2;
2078 static int8_t bwn_phy_g_tssi2dbm_table[] = BWN_PHY_G_TSSI2DBM_TABLE;
2068 static int8_t bwn_phy_g_tssi2dbm_table[] = BWN_PHY_G_TSSI2DBM_TABLE;
2079 int8_t bg = (int8_t)sprom->tssi_bg;
2069 int8_t bg;
2080
2070
2081 if ((sd->sd_bus->siba_chipid == 0x4301) && (phy->rf_ver != 0x2050))
2071 bg = (int8_t)siba_sprom_get_tssi_bg(sc->sc_dev);
2072 pab0 = (int16_t)siba_sprom_get_pa0b0(sc->sc_dev);
2073 pab1 = (int16_t)siba_sprom_get_pa0b1(sc->sc_dev);
2074 pab2 = (int16_t)siba_sprom_get_pa0b2(sc->sc_dev);
2075
2076 if ((siba_get_chipid(sc->sc_dev) == 0x4301) && (phy->rf_ver != 0x2050))
2082 device_printf(sc->sc_dev, "not supported anymore\n");
2083
2084 pg->pg_flags = 0;
2085 if (pab0 == 0 || pab1 == 0 || pab2 == 0 || pab0 == -1 || pab1 == -1 ||
2086 pab2 == -1) {
2087 pg->pg_idletssi = 52;
2088 pg->pg_tssi2dbm = bwn_phy_g_tssi2dbm_table;
2089 return (0);

--- 80 unchanged lines hidden (view full) ---

2170 TAILQ_INIT(&pg->pg_loctl.calib_list);
2171}
2172
2173static int
2174bwn_phy_g_prepare_hw(struct bwn_mac *mac)
2175{
2176 struct bwn_phy *phy = &mac->mac_phy;
2177 struct bwn_phy_g *pg = &phy->phy_g;
2077 device_printf(sc->sc_dev, "not supported anymore\n");
2078
2079 pg->pg_flags = 0;
2080 if (pab0 == 0 || pab1 == 0 || pab2 == 0 || pab0 == -1 || pab1 == -1 ||
2081 pab2 == -1) {
2082 pg->pg_idletssi = 52;
2083 pg->pg_tssi2dbm = bwn_phy_g_tssi2dbm_table;
2084 return (0);

--- 80 unchanged lines hidden (view full) ---

2165 TAILQ_INIT(&pg->pg_loctl.calib_list);
2166}
2167
2168static int
2169bwn_phy_g_prepare_hw(struct bwn_mac *mac)
2170{
2171 struct bwn_phy *phy = &mac->mac_phy;
2172 struct bwn_phy_g *pg = &phy->phy_g;
2173 struct bwn_softc *sc = mac->mac_sc;
2178 struct bwn_txpwr_loctl *lo = &pg->pg_loctl;
2174 struct bwn_txpwr_loctl *lo = &pg->pg_loctl;
2179 struct siba_softc *bus = mac->mac_sd->sd_bus;
2180 static const struct bwn_rfatt rfatt0[] = {
2181 { 3, 0 }, { 1, 0 }, { 5, 0 }, { 7, 0 }, { 9, 0 }, { 2, 0 },
2182 { 0, 0 }, { 4, 0 }, { 6, 0 }, { 8, 0 }, { 1, 1 }, { 2, 1 },
2183 { 3, 1 }, { 4, 1 }
2184 };
2185 static const struct bwn_rfatt rfatt1[] = {
2186 { 2, 1 }, { 4, 1 }, { 6, 1 }, { 8, 1 }, { 10, 1 }, { 12, 1 },
2187 { 14, 1 }

--- 11 unchanged lines hidden (view full) ---

2199 if (phy->rf_ver == 0x2050 && phy->rf_rev < 6)
2200 pg->pg_bbatt.att = 0;
2201 else
2202 pg->pg_bbatt.att = 2;
2203
2204 /* prepare Radio Attenuation */
2205 pg->pg_rfatt.padmix = 0;
2206
2175 static const struct bwn_rfatt rfatt0[] = {
2176 { 3, 0 }, { 1, 0 }, { 5, 0 }, { 7, 0 }, { 9, 0 }, { 2, 0 },
2177 { 0, 0 }, { 4, 0 }, { 6, 0 }, { 8, 0 }, { 1, 1 }, { 2, 1 },
2178 { 3, 1 }, { 4, 1 }
2179 };
2180 static const struct bwn_rfatt rfatt1[] = {
2181 { 2, 1 }, { 4, 1 }, { 6, 1 }, { 8, 1 }, { 10, 1 }, { 12, 1 },
2182 { 14, 1 }

--- 11 unchanged lines hidden (view full) ---

2194 if (phy->rf_ver == 0x2050 && phy->rf_rev < 6)
2195 pg->pg_bbatt.att = 0;
2196 else
2197 pg->pg_bbatt.att = 2;
2198
2199 /* prepare Radio Attenuation */
2200 pg->pg_rfatt.padmix = 0;
2201
2207 if (bus->siba_board_vendor == SIBA_BOARDVENDOR_BCM &&
2208 bus->siba_board_type == SIBA_BOARD_BCM4309G) {
2209 if (bus->siba_board_rev < 0x43) {
2202 if (siba_get_pci_subvendor(sc->sc_dev) == SIBA_BOARDVENDOR_BCM &&
2203 siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BCM4309G) {
2204 if (siba_get_pci_revid(sc->sc_dev) < 0x43) {
2210 pg->pg_rfatt.att = 2;
2211 goto done;
2205 pg->pg_rfatt.att = 2;
2206 goto done;
2212 } else if (bus->siba_board_rev < 0x51) {
2207 } else if (siba_get_pci_revid(sc->sc_dev) < 0x51) {
2213 pg->pg_rfatt.att = 3;
2214 goto done;
2215 }
2216 }
2217
2218 if (phy->type == BWN_PHYTYPE_A) {
2219 pg->pg_rfatt.att = 0x60;
2220 goto done;
2221 }
2222
2223 switch (phy->rf_ver) {
2224 case 0x2050:
2225 switch (phy->rf_rev) {
2226 case 0:
2227 pg->pg_rfatt.att = 5;
2228 goto done;
2229 case 1:
2230 if (phy->type == BWN_PHYTYPE_G) {
2208 pg->pg_rfatt.att = 3;
2209 goto done;
2210 }
2211 }
2212
2213 if (phy->type == BWN_PHYTYPE_A) {
2214 pg->pg_rfatt.att = 0x60;
2215 goto done;
2216 }
2217
2218 switch (phy->rf_ver) {
2219 case 0x2050:
2220 switch (phy->rf_rev) {
2221 case 0:
2222 pg->pg_rfatt.att = 5;
2223 goto done;
2224 case 1:
2225 if (phy->type == BWN_PHYTYPE_G) {
2231 if (bus->siba_board_vendor ==
2226 if (siba_get_pci_subvendor(sc->sc_dev) ==
2232 SIBA_BOARDVENDOR_BCM &&
2227 SIBA_BOARDVENDOR_BCM &&
2233 bus->siba_board_type ==
2228 siba_get_pci_subdevice(sc->sc_dev) ==
2234 SIBA_BOARD_BCM4309G &&
2229 SIBA_BOARD_BCM4309G &&
2235 bus->siba_board_rev >= 30)
2230 siba_get_pci_revid(sc->sc_dev) >= 30)
2236 pg->pg_rfatt.att = 3;
2231 pg->pg_rfatt.att = 3;
2237 else if (bus->siba_board_vendor ==
2232 else if (siba_get_pci_subvendor(sc->sc_dev) ==
2238 SIBA_BOARDVENDOR_BCM &&
2233 SIBA_BOARDVENDOR_BCM &&
2239 bus->siba_board_type == SIBA_BOARD_BU4306)
2234 siba_get_pci_subdevice(sc->sc_dev) ==
2235 SIBA_BOARD_BU4306)
2240 pg->pg_rfatt.att = 3;
2241 else
2242 pg->pg_rfatt.att = 1;
2243 } else {
2236 pg->pg_rfatt.att = 3;
2237 else
2238 pg->pg_rfatt.att = 1;
2239 } else {
2244 if (bus->siba_board_vendor ==
2240 if (siba_get_pci_subvendor(sc->sc_dev) ==
2245 SIBA_BOARDVENDOR_BCM &&
2241 SIBA_BOARDVENDOR_BCM &&
2246 bus->siba_board_type ==
2242 siba_get_pci_subdevice(sc->sc_dev) ==
2247 SIBA_BOARD_BCM4309G &&
2243 SIBA_BOARD_BCM4309G &&
2248 bus->siba_board_rev >= 30)
2244 siba_get_pci_revid(sc->sc_dev) >= 30)
2249 pg->pg_rfatt.att = 7;
2250 else
2251 pg->pg_rfatt.att = 6;
2252 }
2253 goto done;
2254 case 2:
2255 if (phy->type == BWN_PHYTYPE_G) {
2245 pg->pg_rfatt.att = 7;
2246 else
2247 pg->pg_rfatt.att = 6;
2248 }
2249 goto done;
2250 case 2:
2251 if (phy->type == BWN_PHYTYPE_G) {
2256 if (bus->siba_board_vendor ==
2252 if (siba_get_pci_subvendor(sc->sc_dev) ==
2257 SIBA_BOARDVENDOR_BCM &&
2253 SIBA_BOARDVENDOR_BCM &&
2258 bus->siba_board_type ==
2254 siba_get_pci_subdevice(sc->sc_dev) ==
2259 SIBA_BOARD_BCM4309G &&
2255 SIBA_BOARD_BCM4309G &&
2260 bus->siba_board_rev >= 30)
2256 siba_get_pci_revid(sc->sc_dev) >= 30)
2261 pg->pg_rfatt.att = 3;
2257 pg->pg_rfatt.att = 3;
2262 else if (bus->siba_board_vendor ==
2258 else if (siba_get_pci_subvendor(sc->sc_dev) ==
2263 SIBA_BOARDVENDOR_BCM &&
2259 SIBA_BOARDVENDOR_BCM &&
2264 bus->siba_board_type == SIBA_BOARD_BU4306)
2260 siba_get_pci_subdevice(sc->sc_dev) ==
2261 SIBA_BOARD_BU4306)
2265 pg->pg_rfatt.att = 5;
2262 pg->pg_rfatt.att = 5;
2266 else if (bus->siba_chipid == 0x4320)
2263 else if (siba_get_chipid(sc->sc_dev) == 0x4320)
2267 pg->pg_rfatt.att = 4;
2268 else
2269 pg->pg_rfatt.att = 3;
2270 } else
2271 pg->pg_rfatt.att = 6;
2272 goto done;
2273 case 3:
2274 pg->pg_rfatt.att = 5;

--- 267 unchanged lines hidden (view full) ---

2542}
2543
2544static int
2545bwn_phy_g_recalc_txpwr(struct bwn_mac *mac, int ignore_tssi)
2546{
2547 struct bwn_phy *phy = &mac->mac_phy;
2548 struct bwn_phy_g *pg = &phy->phy_g;
2549 struct bwn_softc *sc = mac->mac_sc;
2264 pg->pg_rfatt.att = 4;
2265 else
2266 pg->pg_rfatt.att = 3;
2267 } else
2268 pg->pg_rfatt.att = 6;
2269 goto done;
2270 case 3:
2271 pg->pg_rfatt.att = 5;

--- 267 unchanged lines hidden (view full) ---

2539}
2540
2541static int
2542bwn_phy_g_recalc_txpwr(struct bwn_mac *mac, int ignore_tssi)
2543{
2544 struct bwn_phy *phy = &mac->mac_phy;
2545 struct bwn_phy_g *pg = &phy->phy_g;
2546 struct bwn_softc *sc = mac->mac_sc;
2550 struct siba_softc *siba = mac->mac_sd->sd_bus;
2551 unsigned int tssi;
2552 int cck, ofdm;
2553 int power;
2554 int rfatt, bbatt;
2555 unsigned int max;
2556
2557 KASSERT(phy->type == BWN_PHYTYPE_G, ("%s: fail", __func__));
2558

--- 6 unchanged lines hidden (view full) ---

2565 ofdm = 0;
2566 }
2567 tssi = (cck < 0) ? ofdm : ((ofdm < 0) ? cck : (cck + ofdm) / 2);
2568 if (pg->pg_avgtssi != 0xff)
2569 tssi = (tssi + pg->pg_avgtssi) / 2;
2570 pg->pg_avgtssi = tssi;
2571 KASSERT(tssi < BWN_TSSI_MAX, ("%s:%d: fail", __func__, __LINE__));
2572
2547 unsigned int tssi;
2548 int cck, ofdm;
2549 int power;
2550 int rfatt, bbatt;
2551 unsigned int max;
2552
2553 KASSERT(phy->type == BWN_PHYTYPE_G, ("%s: fail", __func__));
2554

--- 6 unchanged lines hidden (view full) ---

2561 ofdm = 0;
2562 }
2563 tssi = (cck < 0) ? ofdm : ((ofdm < 0) ? cck : (cck + ofdm) / 2);
2564 if (pg->pg_avgtssi != 0xff)
2565 tssi = (tssi + pg->pg_avgtssi) / 2;
2566 pg->pg_avgtssi = tssi;
2567 KASSERT(tssi < BWN_TSSI_MAX, ("%s:%d: fail", __func__, __LINE__));
2568
2573 max = siba->siba_sprom.maxpwr_bg;
2574 if (siba->siba_sprom.bf_lo & BWN_BFL_PACTRL)
2569 max = siba_sprom_get_maxpwr_bg(sc->sc_dev);
2570 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL)
2575 max -= 3;
2576 if (max >= 120) {
2577 device_printf(sc->sc_dev, "invalid max TX-power value\n");
2571 max -= 3;
2572 if (max >= 120) {
2573 device_printf(sc->sc_dev, "invalid max TX-power value\n");
2578 siba->siba_sprom.maxpwr_bg = max = 80;
2574 max = 80;
2575 siba_sprom_set_maxpwr_bg(sc->sc_dev, max);
2579 }
2580
2581 power = MIN(MAX((phy->txpower < 0) ? 0 : (phy->txpower << 2), 0), max) -
2582 (pg->pg_tssi2dbm[MIN(MAX(pg->pg_idletssi - pg->pg_curtssi +
2583 tssi, 0x00), 0x3f)]);
2584 if (power == 0)
2585 return (BWN_TXPWR_RES_DONE);
2586

--- 27 unchanged lines hidden (view full) ---

2614 bwn_phy_g_setatt(mac, &bbatt, &rfatt);
2615 txctl = pg->pg_txctl;
2616 if ((phy->rf_ver == 0x2050) && (phy->rf_rev == 2)) {
2617 if (rfatt <= 1) {
2618 if (txctl == 0) {
2619 txctl = BWN_TXCTL_PA2DB | BWN_TXCTL_TXMIX;
2620 rfatt += 2;
2621 bbatt += 2;
2576 }
2577
2578 power = MIN(MAX((phy->txpower < 0) ? 0 : (phy->txpower << 2), 0), max) -
2579 (pg->pg_tssi2dbm[MIN(MAX(pg->pg_idletssi - pg->pg_curtssi +
2580 tssi, 0x00), 0x3f)]);
2581 if (power == 0)
2582 return (BWN_TXPWR_RES_DONE);
2583

--- 27 unchanged lines hidden (view full) ---

2611 bwn_phy_g_setatt(mac, &bbatt, &rfatt);
2612 txctl = pg->pg_txctl;
2613 if ((phy->rf_ver == 0x2050) && (phy->rf_rev == 2)) {
2614 if (rfatt <= 1) {
2615 if (txctl == 0) {
2616 txctl = BWN_TXCTL_PA2DB | BWN_TXCTL_TXMIX;
2617 rfatt += 2;
2618 bbatt += 2;
2622 } else if (mac->mac_sd->sd_bus->siba_sprom.
2623 bf_lo &
2624 BWN_BFL_PACTRL) {
2619 } else if (siba_sprom_get_bf_lo(sc->sc_dev) &
2620 BWN_BFL_PACTRL) {
2625 bbatt += 4 * (rfatt - 2);
2626 rfatt = 2;
2627 }
2628 } else if (rfatt > 4 && txctl) {
2629 txctl = 0;
2630 if (bbatt < 3) {
2631 rfatt -= 3;
2632 bbatt += 2;

--- 78 unchanged lines hidden (view full) ---

2711fail:
2712 bwn_mac_enable(mac);
2713}
2714
2715static void
2716bwn_phy_g_task_60s(struct bwn_mac *mac)
2717{
2718 struct bwn_phy *phy = &mac->mac_phy;
2621 bbatt += 4 * (rfatt - 2);
2622 rfatt = 2;
2623 }
2624 } else if (rfatt > 4 && txctl) {
2625 txctl = 0;
2626 if (bbatt < 3) {
2627 rfatt -= 3;
2628 bbatt += 2;

--- 78 unchanged lines hidden (view full) ---

2707fail:
2708 bwn_mac_enable(mac);
2709}
2710
2711static void
2712bwn_phy_g_task_60s(struct bwn_mac *mac)
2713{
2714 struct bwn_phy *phy = &mac->mac_phy;
2715 struct bwn_softc *sc = mac->mac_sc;
2719 uint8_t old = phy->chan;
2720
2716 uint8_t old = phy->chan;
2717
2721 if (!(mac->mac_sd->sd_bus->siba_sprom.bf_lo & BWN_BFL_RSSI))
2718 if (!(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_RSSI))
2722 return;
2723
2724 bwn_mac_suspend(mac);
2725 bwn_nrssi_slope_11g(mac);
2726 if ((phy->rf_ver == 0x2050) && (phy->rf_rev == 8)) {
2727 bwn_switch_channel(mac, (old >= 8) ? 1 : 13);
2728 bwn_switch_channel(mac, old);
2729 }

--- 447 unchanged lines hidden (view full) ---

3177 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
3178 }
3179 }
3180}
3181
3182static int
3183bwn_core_init(struct bwn_mac *mac)
3184{
2719 return;
2720
2721 bwn_mac_suspend(mac);
2722 bwn_nrssi_slope_11g(mac);
2723 if ((phy->rf_ver == 0x2050) && (phy->rf_rev == 8)) {
2724 bwn_switch_channel(mac, (old >= 8) ? 1 : 13);
2725 bwn_switch_channel(mac, old);
2726 }

--- 447 unchanged lines hidden (view full) ---

3174 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
3175 }
3176 }
3177}
3178
3179static int
3180bwn_core_init(struct bwn_mac *mac)
3181{
3185#ifdef BWN_DEBUG
3186 struct bwn_softc *sc = mac->mac_sc;
3182 struct bwn_softc *sc = mac->mac_sc;
3187#endif
3188 struct siba_dev_softc *sd = mac->mac_sd;
3189 struct siba_softc *siba = sd->sd_bus;
3190 struct siba_sprom *sprom = &siba->siba_sprom;
3191 uint64_t hf;
3192 int error;
3193
3194 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT,
3195 ("%s:%d: fail", __func__, __LINE__));
3196
3183 uint64_t hf;
3184 int error;
3185
3186 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT,
3187 ("%s:%d: fail", __func__, __LINE__));
3188
3197 siba_powerup(siba, 0);
3198 if (!siba_dev_isup(sd))
3189 siba_powerup(sc->sc_dev, 0);
3190 if (!siba_dev_isup(sc->sc_dev))
3199 bwn_reset_core(mac,
3200 mac->mac_phy.gmode ? BWN_TGSLOW_SUPPORT_G : 0);
3201
3202 mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID;
3203 mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON;
3204 mac->mac_phy.hwpctl = (bwn_hwpctl) ? 1 : 0;
3205 BWN_GETTIME(mac->mac_phy.nexttime);
3206 mac->mac_phy.txerrors = BWN_TXERROR_MAX;

--- 7 unchanged lines hidden (view full) ---

3214 mac->mac_intr_mask &= ~BWN_INTR_PHY_TXERR;
3215#endif
3216 mac->mac_suspended = 1;
3217 mac->mac_task_state = 0;
3218 memset(&mac->mac_noise, 0, sizeof(mac->mac_noise));
3219
3220 mac->mac_phy.init_pre(mac);
3221
3191 bwn_reset_core(mac,
3192 mac->mac_phy.gmode ? BWN_TGSLOW_SUPPORT_G : 0);
3193
3194 mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID;
3195 mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON;
3196 mac->mac_phy.hwpctl = (bwn_hwpctl) ? 1 : 0;
3197 BWN_GETTIME(mac->mac_phy.nexttime);
3198 mac->mac_phy.txerrors = BWN_TXERROR_MAX;

--- 7 unchanged lines hidden (view full) ---

3206 mac->mac_intr_mask &= ~BWN_INTR_PHY_TXERR;
3207#endif
3208 mac->mac_suspended = 1;
3209 mac->mac_task_state = 0;
3210 memset(&mac->mac_noise, 0, sizeof(mac->mac_noise));
3211
3212 mac->mac_phy.init_pre(mac);
3213
3222 siba_pcicore_intr(&siba->siba_pci, sd);
3214 siba_pcicore_intr(sc->sc_dev);
3223
3215
3224 bwn_fix_imcfglobug(mac);
3216 siba_fix_imcfglobug(sc->sc_dev);
3225 bwn_bt_disable(mac);
3226 if (mac->mac_phy.prepare_hw) {
3227 error = mac->mac_phy.prepare_hw(mac);
3228 if (error)
3229 goto fail0;
3230 }
3231 error = bwn_chip_init(mac);
3232 if (error)
3233 goto fail0;
3234 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_COREREV,
3217 bwn_bt_disable(mac);
3218 if (mac->mac_phy.prepare_hw) {
3219 error = mac->mac_phy.prepare_hw(mac);
3220 if (error)
3221 goto fail0;
3222 }
3223 error = bwn_chip_init(mac);
3224 if (error)
3225 goto fail0;
3226 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_COREREV,
3235 mac->mac_sd->sd_id.sd_rev);
3227 siba_get_revid(sc->sc_dev));
3236 hf = bwn_hf_read(mac);
3237 if (mac->mac_phy.type == BWN_PHYTYPE_G) {
3238 hf |= BWN_HF_GPHY_SYM_WORKAROUND;
3228 hf = bwn_hf_read(mac);
3229 if (mac->mac_phy.type == BWN_PHYTYPE_G) {
3230 hf |= BWN_HF_GPHY_SYM_WORKAROUND;
3239 if (sprom->bf_lo & BWN_BFL_PACTRL)
3231 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL)
3240 hf |= BWN_HF_PAGAINBOOST_OFDM_ON;
3241 if (mac->mac_phy.rev == 1)
3242 hf |= BWN_HF_GPHY_DC_CANCELFILTER;
3243 }
3244 if (mac->mac_phy.rf_ver == 0x2050) {
3245 if (mac->mac_phy.rf_rev < 6)
3246 hf |= BWN_HF_FORCE_VCO_RECALC;
3247 if (mac->mac_phy.rf_rev == 6)
3248 hf |= BWN_HF_4318_TSSI;
3249 }
3232 hf |= BWN_HF_PAGAINBOOST_OFDM_ON;
3233 if (mac->mac_phy.rev == 1)
3234 hf |= BWN_HF_GPHY_DC_CANCELFILTER;
3235 }
3236 if (mac->mac_phy.rf_ver == 0x2050) {
3237 if (mac->mac_phy.rf_rev < 6)
3238 hf |= BWN_HF_FORCE_VCO_RECALC;
3239 if (mac->mac_phy.rf_rev == 6)
3240 hf |= BWN_HF_4318_TSSI;
3241 }
3250 if (sprom->bf_lo & BWN_BFL_CRYSTAL_NOSLOW)
3242 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW)
3251 hf |= BWN_HF_SLOWCLOCK_REQ_OFF;
3243 hf |= BWN_HF_SLOWCLOCK_REQ_OFF;
3252 if ((siba->siba_type == SIBA_TYPE_PCI) &&
3253 (siba->siba_pci.spc_dev->sd_id.sd_rev <= 10))
3244 if ((siba_get_type(sc->sc_dev) == SIBA_TYPE_PCI) &&
3245 (siba_get_pcicore_revid(sc->sc_dev) <= 10))
3254 hf |= BWN_HF_PCI_SLOWCLOCK_WORKAROUND;
3255 hf &= ~BWN_HF_SKIP_CFP_UPDATE;
3256 bwn_hf_write(mac, hf);
3257
3258 bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG);
3259 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SHORT_RETRY_FALLBACK, 3);
3260 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_LONG_RETRY_FALLBACK, 2);
3261 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_MAXTIME, 1);
3262
3263 bwn_rate_init(mac);
3264 bwn_set_phytxctl(mac);
3265
3266 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MIN,
3267 (mac->mac_phy.type == BWN_PHYTYPE_B) ? 0x1f : 0xf);
3268 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MAX, 0x3ff);
3269
3246 hf |= BWN_HF_PCI_SLOWCLOCK_WORKAROUND;
3247 hf &= ~BWN_HF_SKIP_CFP_UPDATE;
3248 bwn_hf_write(mac, hf);
3249
3250 bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG);
3251 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SHORT_RETRY_FALLBACK, 3);
3252 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_LONG_RETRY_FALLBACK, 2);
3253 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_MAXTIME, 1);
3254
3255 bwn_rate_init(mac);
3256 bwn_set_phytxctl(mac);
3257
3258 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MIN,
3259 (mac->mac_phy.type == BWN_PHYTYPE_B) ? 0x1f : 0xf);
3260 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MAX, 0x3ff);
3261
3270 if (siba->siba_type == SIBA_TYPE_PCMCIA || bwn_usedma == 0)
3262 if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0)
3271 bwn_pio_init(mac);
3272 else
3273 bwn_dma_init(mac);
3274 if (error)
3275 goto fail1;
3276 bwn_wme_init(mac);
3277 bwn_spu_setdelay(mac, 1);
3278 bwn_bt_enable(mac);
3279
3263 bwn_pio_init(mac);
3264 else
3265 bwn_dma_init(mac);
3266 if (error)
3267 goto fail1;
3268 bwn_wme_init(mac);
3269 bwn_spu_setdelay(mac, 1);
3270 bwn_bt_enable(mac);
3271
3280 siba_powerup(siba, !(sprom->bf_lo & BWN_BFL_CRYSTAL_NOSLOW));
3272 siba_powerup(sc->sc_dev,
3273 !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW));
3281 bwn_set_macaddr(mac);
3282 bwn_crypt_init(mac);
3283
3284 /* XXX LED initializatin */
3285
3286 mac->mac_status = BWN_MAC_STATUS_INITED;
3287
3288 return (error);
3289
3290fail1:
3291 bwn_chip_exit(mac);
3292fail0:
3274 bwn_set_macaddr(mac);
3275 bwn_crypt_init(mac);
3276
3277 /* XXX LED initializatin */
3278
3279 mac->mac_status = BWN_MAC_STATUS_INITED;
3280
3281 return (error);
3282
3283fail1:
3284 bwn_chip_exit(mac);
3285fail0:
3293 siba_powerdown(siba);
3286 siba_powerdown(sc->sc_dev);
3294 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT,
3295 ("%s:%d: fail", __func__, __LINE__));
3296 return (error);
3297}
3298
3299static void
3300bwn_core_start(struct bwn_mac *mac)
3301{
3302 struct bwn_softc *sc = mac->mac_sc;
3303 uint32_t tmp;
3304
3305 KASSERT(mac->mac_status == BWN_MAC_STATUS_INITED,
3306 ("%s:%d: fail", __func__, __LINE__));
3307
3287 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT,
3288 ("%s:%d: fail", __func__, __LINE__));
3289 return (error);
3290}
3291
3292static void
3293bwn_core_start(struct bwn_mac *mac)
3294{
3295 struct bwn_softc *sc = mac->mac_sc;
3296 uint32_t tmp;
3297
3298 KASSERT(mac->mac_status == BWN_MAC_STATUS_INITED,
3299 ("%s:%d: fail", __func__, __LINE__));
3300
3308 if (mac->mac_sd->sd_id.sd_rev < 5)
3301 if (siba_get_revid(sc->sc_dev) < 5)
3309 return;
3310
3311 while (1) {
3312 tmp = BWN_READ_4(mac, BWN_XMITSTAT_0);
3313 if (!(tmp & 0x00000001))
3314 break;
3315 tmp = BWN_READ_4(mac, BWN_XMITSTAT_1);
3316 }
3317
3318 bwn_mac_enable(mac);
3319 BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask);
3320 callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac);
3321
3322 mac->mac_status = BWN_MAC_STATUS_STARTED;
3323}
3324
3325static void
3326bwn_core_exit(struct bwn_mac *mac)
3327{
3302 return;
3303
3304 while (1) {
3305 tmp = BWN_READ_4(mac, BWN_XMITSTAT_0);
3306 if (!(tmp & 0x00000001))
3307 break;
3308 tmp = BWN_READ_4(mac, BWN_XMITSTAT_1);
3309 }
3310
3311 bwn_mac_enable(mac);
3312 BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask);
3313 callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac);
3314
3315 mac->mac_status = BWN_MAC_STATUS_STARTED;
3316}
3317
3318static void
3319bwn_core_exit(struct bwn_mac *mac)
3320{
3321 struct bwn_softc *sc = mac->mac_sc;
3328 uint32_t macctl;
3329
3330 BWN_ASSERT_LOCKED(mac->mac_sc);
3331
3332 KASSERT(mac->mac_status <= BWN_MAC_STATUS_INITED,
3333 ("%s:%d: fail", __func__, __LINE__));
3334
3335 if (mac->mac_status != BWN_MAC_STATUS_INITED)

--- 4 unchanged lines hidden (view full) ---

3340 macctl &= ~BWN_MACCTL_MCODE_RUN;
3341 macctl |= BWN_MACCTL_MCODE_JMP0;
3342 BWN_WRITE_4(mac, BWN_MACCTL, macctl);
3343
3344 bwn_dma_stop(mac);
3345 bwn_pio_stop(mac);
3346 bwn_chip_exit(mac);
3347 mac->mac_phy.switch_analog(mac, 0);
3322 uint32_t macctl;
3323
3324 BWN_ASSERT_LOCKED(mac->mac_sc);
3325
3326 KASSERT(mac->mac_status <= BWN_MAC_STATUS_INITED,
3327 ("%s:%d: fail", __func__, __LINE__));
3328
3329 if (mac->mac_status != BWN_MAC_STATUS_INITED)

--- 4 unchanged lines hidden (view full) ---

3334 macctl &= ~BWN_MACCTL_MCODE_RUN;
3335 macctl |= BWN_MACCTL_MCODE_JMP0;
3336 BWN_WRITE_4(mac, BWN_MACCTL, macctl);
3337
3338 bwn_dma_stop(mac);
3339 bwn_pio_stop(mac);
3340 bwn_chip_exit(mac);
3341 mac->mac_phy.switch_analog(mac, 0);
3348 siba_dev_down(mac->mac_sd, 0);
3349 siba_powerdown(mac->mac_sd->sd_bus);
3342 siba_dev_down(sc->sc_dev, 0);
3343 siba_powerdown(sc->sc_dev);
3350}
3351
3352static void
3344}
3345
3346static void
3353bwn_fix_imcfglobug(struct bwn_mac *mac)
3354{
3355 struct siba_dev_softc *sd = mac->mac_sd;
3356 struct siba_softc *siba = sd->sd_bus;
3357 uint32_t tmp;
3358
3359 if (siba->siba_pci.spc_dev == NULL)
3360 return;
3361 if (siba->siba_pci.spc_dev->sd_id.sd_device != SIBA_DEVID_PCI ||
3362 siba->siba_pci.spc_dev->sd_id.sd_rev > 5)
3363 return;
3364
3365 tmp = siba_read_4(sd, SIBA_IMCFGLO) &
3366 ~(SIBA_IMCFGLO_REQTO | SIBA_IMCFGLO_SERTO);
3367 switch (siba->siba_type) {
3368 case SIBA_TYPE_PCI:
3369 case SIBA_TYPE_PCMCIA:
3370 tmp |= 0x32;
3371 break;
3372 case SIBA_TYPE_SSB:
3373 tmp |= 0x53;
3374 break;
3375 }
3376 siba_write_4(sd, SIBA_IMCFGLO, tmp);
3377}
3378
3379static void
3380bwn_bt_disable(struct bwn_mac *mac)
3381{
3382 struct bwn_softc *sc = mac->mac_sc;
3383
3384 (void)sc;
3385 /* XXX do nothing yet */
3386}
3387
3388static int
3389bwn_chip_init(struct bwn_mac *mac)
3390{
3347bwn_bt_disable(struct bwn_mac *mac)
3348{
3349 struct bwn_softc *sc = mac->mac_sc;
3350
3351 (void)sc;
3352 /* XXX do nothing yet */
3353}
3354
3355static int
3356bwn_chip_init(struct bwn_mac *mac)
3357{
3358 struct bwn_softc *sc = mac->mac_sc;
3391 struct bwn_phy *phy = &mac->mac_phy;
3392 uint32_t macctl;
3393 int error;
3394
3395 macctl = BWN_MACCTL_IHR_ON | BWN_MACCTL_SHM_ON | BWN_MACCTL_STA;
3396 if (phy->gmode)
3397 macctl |= BWN_MACCTL_GMODE;
3398 BWN_WRITE_4(mac, BWN_MACCTL, macctl);

--- 6 unchanged lines hidden (view full) ---

3405 return (error);
3406
3407 error = bwn_gpio_init(mac);
3408 if (error)
3409 return (error);
3410
3411 error = bwn_fw_loadinitvals(mac);
3412 if (error) {
3359 struct bwn_phy *phy = &mac->mac_phy;
3360 uint32_t macctl;
3361 int error;
3362
3363 macctl = BWN_MACCTL_IHR_ON | BWN_MACCTL_SHM_ON | BWN_MACCTL_STA;
3364 if (phy->gmode)
3365 macctl |= BWN_MACCTL_GMODE;
3366 BWN_WRITE_4(mac, BWN_MACCTL, macctl);

--- 6 unchanged lines hidden (view full) ---

3373 return (error);
3374
3375 error = bwn_gpio_init(mac);
3376 if (error)
3377 return (error);
3378
3379 error = bwn_fw_loadinitvals(mac);
3380 if (error) {
3413 bwn_gpio_cleanup(mac);
3381 siba_gpio_set(sc->sc_dev, 0);
3414 return (error);
3415 }
3416 phy->switch_analog(mac, 1);
3417 error = bwn_phy_init(mac);
3418 if (error) {
3382 return (error);
3383 }
3384 phy->switch_analog(mac, 1);
3385 error = bwn_phy_init(mac);
3386 if (error) {
3419 bwn_gpio_cleanup(mac);
3387 siba_gpio_set(sc->sc_dev, 0);
3420 return (error);
3421 }
3422 if (phy->set_im)
3423 phy->set_im(mac, BWN_IMMODE_NONE);
3424 if (phy->set_antenna)
3425 phy->set_antenna(mac, BWN_ANT_DEFAULT);
3426 bwn_set_txantenna(mac, BWN_ANT_DEFAULT);
3427
3428 if (phy->type == BWN_PHYTYPE_B)
3429 BWN_WRITE_2(mac, 0x005e, BWN_READ_2(mac, 0x005e) | 0x0004);
3430 BWN_WRITE_4(mac, 0x0100, 0x01000000);
3388 return (error);
3389 }
3390 if (phy->set_im)
3391 phy->set_im(mac, BWN_IMMODE_NONE);
3392 if (phy->set_antenna)
3393 phy->set_antenna(mac, BWN_ANT_DEFAULT);
3394 bwn_set_txantenna(mac, BWN_ANT_DEFAULT);
3395
3396 if (phy->type == BWN_PHYTYPE_B)
3397 BWN_WRITE_2(mac, 0x005e, BWN_READ_2(mac, 0x005e) | 0x0004);
3398 BWN_WRITE_4(mac, 0x0100, 0x01000000);
3431 if (mac->mac_sd->sd_id.sd_rev < 5)
3399 if (siba_get_revid(sc->sc_dev) < 5)
3432 BWN_WRITE_4(mac, 0x010c, 0x01000000);
3433
3434 BWN_WRITE_4(mac, BWN_MACCTL,
3435 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_STA);
3436 BWN_WRITE_4(mac, BWN_MACCTL,
3437 BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_STA);
3438 bwn_shm_write_2(mac, BWN_SHARED, 0x0074, 0x0000);
3439
3440 bwn_set_opmode(mac);
3400 BWN_WRITE_4(mac, 0x010c, 0x01000000);
3401
3402 BWN_WRITE_4(mac, BWN_MACCTL,
3403 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_STA);
3404 BWN_WRITE_4(mac, BWN_MACCTL,
3405 BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_STA);
3406 bwn_shm_write_2(mac, BWN_SHARED, 0x0074, 0x0000);
3407
3408 bwn_set_opmode(mac);
3441 if (mac->mac_sd->sd_id.sd_rev < 3) {
3409 if (siba_get_revid(sc->sc_dev) < 3) {
3442 BWN_WRITE_2(mac, 0x060e, 0x0000);
3443 BWN_WRITE_2(mac, 0x0610, 0x8000);
3444 BWN_WRITE_2(mac, 0x0604, 0x0000);
3445 BWN_WRITE_2(mac, 0x0606, 0x0200);
3446 } else {
3447 BWN_WRITE_4(mac, 0x0188, 0x80000000);
3448 BWN_WRITE_4(mac, 0x018c, 0x02000000);
3449 }
3450 BWN_WRITE_4(mac, BWN_INTR_REASON, 0x00004000);
3451 BWN_WRITE_4(mac, BWN_DMA0_INTR_MASK, 0x0001dc00);
3452 BWN_WRITE_4(mac, BWN_DMA1_INTR_MASK, 0x0000dc00);
3453 BWN_WRITE_4(mac, BWN_DMA2_INTR_MASK, 0x0000dc00);
3454 BWN_WRITE_4(mac, BWN_DMA3_INTR_MASK, 0x0001dc00);
3455 BWN_WRITE_4(mac, BWN_DMA4_INTR_MASK, 0x0000dc00);
3456 BWN_WRITE_4(mac, BWN_DMA5_INTR_MASK, 0x0000dc00);
3410 BWN_WRITE_2(mac, 0x060e, 0x0000);
3411 BWN_WRITE_2(mac, 0x0610, 0x8000);
3412 BWN_WRITE_2(mac, 0x0604, 0x0000);
3413 BWN_WRITE_2(mac, 0x0606, 0x0200);
3414 } else {
3415 BWN_WRITE_4(mac, 0x0188, 0x80000000);
3416 BWN_WRITE_4(mac, 0x018c, 0x02000000);
3417 }
3418 BWN_WRITE_4(mac, BWN_INTR_REASON, 0x00004000);
3419 BWN_WRITE_4(mac, BWN_DMA0_INTR_MASK, 0x0001dc00);
3420 BWN_WRITE_4(mac, BWN_DMA1_INTR_MASK, 0x0000dc00);
3421 BWN_WRITE_4(mac, BWN_DMA2_INTR_MASK, 0x0000dc00);
3422 BWN_WRITE_4(mac, BWN_DMA3_INTR_MASK, 0x0001dc00);
3423 BWN_WRITE_4(mac, BWN_DMA4_INTR_MASK, 0x0000dc00);
3424 BWN_WRITE_4(mac, BWN_DMA5_INTR_MASK, 0x0000dc00);
3457 siba_write_4(mac->mac_sd, SIBA_TGSLOW,
3458 siba_read_4(mac->mac_sd, SIBA_TGSLOW) | 0x00100000);
3459 BWN_WRITE_2(mac, BWN_POWERUP_DELAY,
3460 mac->mac_sd->sd_bus->siba_cc.scc_powerup_delay);
3425 siba_write_4(sc->sc_dev, SIBA_TGSLOW,
3426 siba_read_4(sc->sc_dev, SIBA_TGSLOW) | 0x00100000);
3427 BWN_WRITE_2(mac, BWN_POWERUP_DELAY, siba_get_cc_powerdelay(sc->sc_dev));
3461 return (error);
3462}
3463
3464/* read hostflags */
3465static uint64_t
3466bwn_hf_read(struct bwn_mac *mac)
3467{
3468 uint64_t ret;

--- 145 unchanged lines hidden (view full) ---

3614 bwn_pio_setupqueue_rx(mac, &pio->rx, 0);
3615}
3616
3617static void
3618bwn_pio_set_txqueue(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
3619 int index)
3620{
3621 struct bwn_pio_txpkt *tp;
3428 return (error);
3429}
3430
3431/* read hostflags */
3432static uint64_t
3433bwn_hf_read(struct bwn_mac *mac)
3434{
3435 uint64_t ret;

--- 145 unchanged lines hidden (view full) ---

3581 bwn_pio_setupqueue_rx(mac, &pio->rx, 0);
3582}
3583
3584static void
3585bwn_pio_set_txqueue(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
3586 int index)
3587{
3588 struct bwn_pio_txpkt *tp;
3589 struct bwn_softc *sc = mac->mac_sc;
3622 unsigned int i;
3623
3624 tq->tq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_TXQOFFSET(mac);
3625 tq->tq_index = index;
3626
3627 tq->tq_free = BWN_PIO_MAX_TXPACKETS;
3590 unsigned int i;
3591
3592 tq->tq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_TXQOFFSET(mac);
3593 tq->tq_index = index;
3594
3595 tq->tq_free = BWN_PIO_MAX_TXPACKETS;
3628 if (mac->mac_sd->sd_id.sd_rev >= 8)
3596 if (siba_get_revid(sc->sc_dev) >= 8)
3629 tq->tq_size = 1920;
3630 else {
3631 tq->tq_size = bwn_pio_read_2(mac, tq, BWN_PIO_TXQBUFSIZE);
3632 tq->tq_size -= 80;
3633 }
3634
3635 TAILQ_INIT(&tq->tq_pktlist);
3636 for (i = 0; i < N(tq->tq_pkts); i++) {

--- 22 unchanged lines hidden (view full) ---

3659 BWN_PIO11_BASE0,
3660 BWN_PIO11_BASE1,
3661 BWN_PIO11_BASE2,
3662 BWN_PIO11_BASE3,
3663 BWN_PIO11_BASE4,
3664 BWN_PIO11_BASE5,
3665 };
3666
3597 tq->tq_size = 1920;
3598 else {
3599 tq->tq_size = bwn_pio_read_2(mac, tq, BWN_PIO_TXQBUFSIZE);
3600 tq->tq_size -= 80;
3601 }
3602
3603 TAILQ_INIT(&tq->tq_pktlist);
3604 for (i = 0; i < N(tq->tq_pkts); i++) {

--- 22 unchanged lines hidden (view full) ---

3627 BWN_PIO11_BASE0,
3628 BWN_PIO11_BASE1,
3629 BWN_PIO11_BASE2,
3630 BWN_PIO11_BASE3,
3631 BWN_PIO11_BASE4,
3632 BWN_PIO11_BASE5,
3633 };
3634
3667 if (mac->mac_sd->sd_id.sd_rev >= 11) {
3635 if (siba_get_revid(sc->sc_dev) >= 11) {
3668 if (index >= N(bases_rev11))
3669 device_printf(sc->sc_dev, "%s: warning\n", __func__);
3670 return (bases_rev11[index]);
3671 }
3672 if (index >= N(bases))
3673 device_printf(sc->sc_dev, "%s: warning\n", __func__);
3674 return (bases[index]);
3675}
3676
3677static void
3678bwn_pio_setupqueue_rx(struct bwn_mac *mac, struct bwn_pio_rxqueue *prq,
3679 int index)
3680{
3636 if (index >= N(bases_rev11))
3637 device_printf(sc->sc_dev, "%s: warning\n", __func__);
3638 return (bases_rev11[index]);
3639 }
3640 if (index >= N(bases))
3641 device_printf(sc->sc_dev, "%s: warning\n", __func__);
3642 return (bases[index]);
3643}
3644
3645static void
3646bwn_pio_setupqueue_rx(struct bwn_mac *mac, struct bwn_pio_rxqueue *prq,
3647 int index)
3648{
3649 struct bwn_softc *sc = mac->mac_sc;
3681
3682 prq->prq_mac = mac;
3650
3651 prq->prq_mac = mac;
3683 prq->prq_rev = mac->mac_sd->sd_id.sd_rev;
3652 prq->prq_rev = siba_get_revid(sc->sc_dev);
3684 prq->prq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_RXQOFFSET(mac);
3685 bwn_dma_rxdirectfifo(mac, index, 1);
3686}
3687
3688static void
3689bwn_destroy_pioqueue_tx(struct bwn_pio_txqueue *tq)
3690{
3691 if (tq == NULL)

--- 330 unchanged lines hidden (view full) ---

4022}
4023
4024static void
4025bwn_dma_32_setdesc(struct bwn_dma_ring *dr,
4026 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize,
4027 int start, int end, int irq)
4028{
4029 struct bwn_dmadesc32 *descbase = dr->dr_ring_descbase;
3653 prq->prq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_RXQOFFSET(mac);
3654 bwn_dma_rxdirectfifo(mac, index, 1);
3655}
3656
3657static void
3658bwn_destroy_pioqueue_tx(struct bwn_pio_txqueue *tq)
3659{
3660 if (tq == NULL)

--- 330 unchanged lines hidden (view full) ---

3991}
3992
3993static void
3994bwn_dma_32_setdesc(struct bwn_dma_ring *dr,
3995 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize,
3996 int start, int end, int irq)
3997{
3998 struct bwn_dmadesc32 *descbase = dr->dr_ring_descbase;
3999 struct bwn_softc *sc = dr->dr_mac->mac_sc;
4030 uint32_t addr, addrext, ctl;
4031 int slot;
4032
4033 slot = (int)(&(desc->dma.dma32) - descbase);
4034 KASSERT(slot >= 0 && slot < dr->dr_numslots,
4035 ("%s:%d: fail", __func__, __LINE__));
4036
4037 addr = (uint32_t) (dmaaddr & ~SIBA_DMA_TRANSLATION_MASK);
4038 addrext = (uint32_t) (dmaaddr & SIBA_DMA_TRANSLATION_MASK) >> 30;
4000 uint32_t addr, addrext, ctl;
4001 int slot;
4002
4003 slot = (int)(&(desc->dma.dma32) - descbase);
4004 KASSERT(slot >= 0 && slot < dr->dr_numslots,
4005 ("%s:%d: fail", __func__, __LINE__));
4006
4007 addr = (uint32_t) (dmaaddr & ~SIBA_DMA_TRANSLATION_MASK);
4008 addrext = (uint32_t) (dmaaddr & SIBA_DMA_TRANSLATION_MASK) >> 30;
4039 addr |= siba_dma_translation(dr->dr_mac->mac_sd);
4009 addr |= siba_dma_translation(sc->sc_dev);
4040 ctl = bufsize & BWN_DMA32_DCTL_BYTECNT;
4041 if (slot == dr->dr_numslots - 1)
4042 ctl |= BWN_DMA32_DCTL_DTABLEEND;
4043 if (start)
4044 ctl |= BWN_DMA32_DCTL_FRAMESTART;
4045 if (end)
4046 ctl |= BWN_DMA32_DCTL_FRAMEEND;
4047 if (irq)

--- 62 unchanged lines hidden (view full) ---

4110}
4111
4112static void
4113bwn_dma_64_setdesc(struct bwn_dma_ring *dr,
4114 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize,
4115 int start, int end, int irq)
4116{
4117 struct bwn_dmadesc64 *descbase = dr->dr_ring_descbase;
4010 ctl = bufsize & BWN_DMA32_DCTL_BYTECNT;
4011 if (slot == dr->dr_numslots - 1)
4012 ctl |= BWN_DMA32_DCTL_DTABLEEND;
4013 if (start)
4014 ctl |= BWN_DMA32_DCTL_FRAMESTART;
4015 if (end)
4016 ctl |= BWN_DMA32_DCTL_FRAMEEND;
4017 if (irq)

--- 62 unchanged lines hidden (view full) ---

4080}
4081
4082static void
4083bwn_dma_64_setdesc(struct bwn_dma_ring *dr,
4084 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize,
4085 int start, int end, int irq)
4086{
4087 struct bwn_dmadesc64 *descbase = dr->dr_ring_descbase;
4088 struct bwn_softc *sc = dr->dr_mac->mac_sc;
4118 int slot;
4119 uint32_t ctl0 = 0, ctl1 = 0;
4120 uint32_t addrlo, addrhi;
4121 uint32_t addrext;
4122
4123 slot = (int)(&(desc->dma.dma64) - descbase);
4124 KASSERT(slot >= 0 && slot < dr->dr_numslots,
4125 ("%s:%d: fail", __func__, __LINE__));
4126
4127 addrlo = (uint32_t) (dmaaddr & 0xffffffff);
4128 addrhi = (((uint64_t) dmaaddr >> 32) & ~SIBA_DMA_TRANSLATION_MASK);
4129 addrext = (((uint64_t) dmaaddr >> 32) & SIBA_DMA_TRANSLATION_MASK) >>
4130 30;
4089 int slot;
4090 uint32_t ctl0 = 0, ctl1 = 0;
4091 uint32_t addrlo, addrhi;
4092 uint32_t addrext;
4093
4094 slot = (int)(&(desc->dma.dma64) - descbase);
4095 KASSERT(slot >= 0 && slot < dr->dr_numslots,
4096 ("%s:%d: fail", __func__, __LINE__));
4097
4098 addrlo = (uint32_t) (dmaaddr & 0xffffffff);
4099 addrhi = (((uint64_t) dmaaddr >> 32) & ~SIBA_DMA_TRANSLATION_MASK);
4100 addrext = (((uint64_t) dmaaddr >> 32) & SIBA_DMA_TRANSLATION_MASK) >>
4101 30;
4131 addrhi |= (siba_dma_translation(dr->dr_mac->mac_sd) << 1);
4102 addrhi |= (siba_dma_translation(sc->sc_dev) << 1);
4132 if (slot == dr->dr_numslots - 1)
4133 ctl0 |= BWN_DMA64_DCTL0_DTABLEEND;
4134 if (start)
4135 ctl0 |= BWN_DMA64_DCTL0_FRAMESTART;
4136 if (end)
4137 ctl0 |= BWN_DMA64_DCTL0_FRAMEEND;
4138 if (irq)
4139 ctl0 |= BWN_DMA64_DCTL0_IRQ;

--- 93 unchanged lines hidden (view full) ---

4233 }
4234
4235 return (0);
4236}
4237
4238static void
4239bwn_dma_setup(struct bwn_dma_ring *dr)
4240{
4103 if (slot == dr->dr_numslots - 1)
4104 ctl0 |= BWN_DMA64_DCTL0_DTABLEEND;
4105 if (start)
4106 ctl0 |= BWN_DMA64_DCTL0_FRAMESTART;
4107 if (end)
4108 ctl0 |= BWN_DMA64_DCTL0_FRAMEEND;
4109 if (irq)
4110 ctl0 |= BWN_DMA64_DCTL0_IRQ;

--- 93 unchanged lines hidden (view full) ---

4204 }
4205
4206 return (0);
4207}
4208
4209static void
4210bwn_dma_setup(struct bwn_dma_ring *dr)
4211{
4212 struct bwn_softc *sc = dr->dr_mac->mac_sc;
4241 uint64_t ring64;
4242 uint32_t addrext, ring32, value;
4213 uint64_t ring64;
4214 uint32_t addrext, ring32, value;
4243 uint32_t trans = siba_dma_translation(dr->dr_mac->mac_sd);
4215 uint32_t trans = siba_dma_translation(sc->sc_dev);
4244
4245 if (dr->dr_tx) {
4246 dr->dr_curslot = -1;
4247
4248 if (dr->dr_type == BWN_DMA_64BIT) {
4249 ring64 = (uint64_t)(dr->dr_ring_dmabase);
4250 addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK)
4251 >> 30;

--- 279 unchanged lines hidden (view full) ---

4531 delay = max(delay, (uint16_t)2400);
4532
4533 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SPU_WAKEUP, delay);
4534}
4535
4536static void
4537bwn_bt_enable(struct bwn_mac *mac)
4538{
4216
4217 if (dr->dr_tx) {
4218 dr->dr_curslot = -1;
4219
4220 if (dr->dr_type == BWN_DMA_64BIT) {
4221 ring64 = (uint64_t)(dr->dr_ring_dmabase);
4222 addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK)
4223 >> 30;

--- 279 unchanged lines hidden (view full) ---

4503 delay = max(delay, (uint16_t)2400);
4504
4505 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SPU_WAKEUP, delay);
4506}
4507
4508static void
4509bwn_bt_enable(struct bwn_mac *mac)
4510{
4539 struct siba_sprom *sprom = &mac->mac_sd->sd_bus->siba_sprom;
4511 struct bwn_softc *sc = mac->mac_sc;
4540 uint64_t hf;
4541
4542 if (bwn_bluetooth == 0)
4543 return;
4512 uint64_t hf;
4513
4514 if (bwn_bluetooth == 0)
4515 return;
4544 if ((sprom->bf_lo & BWN_BFL_BTCOEXIST) == 0)
4516 if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCOEXIST) == 0)
4545 return;
4546 if (mac->mac_phy.type != BWN_PHYTYPE_B && !mac->mac_phy.gmode)
4547 return;
4548
4549 hf = bwn_hf_read(mac);
4517 return;
4518 if (mac->mac_phy.type != BWN_PHYTYPE_B && !mac->mac_phy.gmode)
4519 return;
4520
4521 hf = bwn_hf_read(mac);
4550 if (sprom->bf_lo & BWN_BFL_BTCMOD)
4522 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCMOD)
4551 hf |= BWN_HF_BT_COEXISTALT;
4552 else
4553 hf |= BWN_HF_BT_COEXIST;
4554 bwn_hf_write(mac, hf);
4555}
4556
4557static void
4558bwn_set_macaddr(struct bwn_mac *mac)

--- 20 unchanged lines hidden (view full) ---

4579 }
4580 mac->mac_key[i].keyconf = NULL;
4581 }
4582}
4583
4584static void
4585bwn_crypt_init(struct bwn_mac *mac)
4586{
4523 hf |= BWN_HF_BT_COEXISTALT;
4524 else
4525 hf |= BWN_HF_BT_COEXIST;
4526 bwn_hf_write(mac, hf);
4527}
4528
4529static void
4530bwn_set_macaddr(struct bwn_mac *mac)

--- 20 unchanged lines hidden (view full) ---

4551 }
4552 mac->mac_key[i].keyconf = NULL;
4553 }
4554}
4555
4556static void
4557bwn_crypt_init(struct bwn_mac *mac)
4558{
4559 struct bwn_softc *sc = mac->mac_sc;
4587
4560
4588 mac->mac_max_nr_keys = (mac->mac_sd->sd_id.sd_rev >= 5) ? 58 : 20;
4561 mac->mac_max_nr_keys = (siba_get_revid(sc->sc_dev) >= 5) ? 58 : 20;
4589 KASSERT(mac->mac_max_nr_keys <= N(mac->mac_key),
4590 ("%s:%d: fail", __func__, __LINE__));
4591 mac->mac_ktp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_KEY_TABLEP);
4592 mac->mac_ktp *= 2;
4562 KASSERT(mac->mac_max_nr_keys <= N(mac->mac_key),
4563 ("%s:%d: fail", __func__, __LINE__));
4564 mac->mac_ktp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_KEY_TABLEP);
4565 mac->mac_ktp *= 2;
4593 if (mac->mac_sd->sd_id.sd_rev >= 5) {
4594 BWN_WRITE_2(mac, BWN_RCMTA_COUNT,
4595 mac->mac_max_nr_keys - 8);
4596 }
4566 if (siba_get_revid(sc->sc_dev) >= 5)
4567 BWN_WRITE_2(mac, BWN_RCMTA_COUNT, mac->mac_max_nr_keys - 8);
4597 bwn_clear_keys(mac);
4598}
4599
4600static void
4601bwn_chip_exit(struct bwn_mac *mac)
4602{
4568 bwn_clear_keys(mac);
4569}
4570
4571static void
4572bwn_chip_exit(struct bwn_mac *mac)
4573{
4574 struct bwn_softc *sc = mac->mac_sc;
4603
4604 bwn_phy_exit(mac);
4575
4576 bwn_phy_exit(mac);
4605 bwn_gpio_cleanup(mac);
4577 siba_gpio_set(sc->sc_dev, 0);
4606}
4607
4608static int
4609bwn_fw_fillinfo(struct bwn_mac *mac)
4610{
4611 int error;
4612
4613 error = bwn_fw_gets(mac, BWN_FWTYPE_DEFAULT);
4614 if (error == 0)
4615 return (0);
4616 error = bwn_fw_gets(mac, BWN_FWTYPE_OPENSOURCE);
4617 if (error == 0)
4618 return (0);
4619 return (error);
4620}
4621
4622static int
4623bwn_gpio_init(struct bwn_mac *mac)
4624{
4578}
4579
4580static int
4581bwn_fw_fillinfo(struct bwn_mac *mac)
4582{
4583 int error;
4584
4585 error = bwn_fw_gets(mac, BWN_FWTYPE_DEFAULT);
4586 if (error == 0)
4587 return (0);
4588 error = bwn_fw_gets(mac, BWN_FWTYPE_OPENSOURCE);
4589 if (error == 0)
4590 return (0);
4591 return (error);
4592}
4593
4594static int
4595bwn_gpio_init(struct bwn_mac *mac)
4596{
4625 struct siba_softc *bus = mac->mac_sd->sd_bus;
4626 struct siba_dev_softc *sd;
4627 uint32_t mask = 0x0000001f, set = 0x0000000f;
4597 struct bwn_softc *sc = mac->mac_sc;
4598 uint32_t mask = 0x1f, set = 0xf, value;
4628
4629 BWN_WRITE_4(mac, BWN_MACCTL,
4630 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GPOUT_MASK);
4631 BWN_WRITE_2(mac, BWN_GPIO_MASK,
4632 BWN_READ_2(mac, BWN_GPIO_MASK) | 0x000f);
4633
4599
4600 BWN_WRITE_4(mac, BWN_MACCTL,
4601 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GPOUT_MASK);
4602 BWN_WRITE_2(mac, BWN_GPIO_MASK,
4603 BWN_READ_2(mac, BWN_GPIO_MASK) | 0x000f);
4604
4634 if (bus->siba_chipid == 0x4301) {
4605 if (siba_get_chipid(sc->sc_dev) == 0x4301) {
4635 mask |= 0x0060;
4636 set |= 0x0060;
4637 }
4606 mask |= 0x0060;
4607 set |= 0x0060;
4608 }
4638 if (bus->siba_sprom.bf_lo & BWN_BFL_PACTRL) {
4609 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL) {
4639 BWN_WRITE_2(mac, BWN_GPIO_MASK,
4640 BWN_READ_2(mac, BWN_GPIO_MASK) | 0x0200);
4641 mask |= 0x0200;
4642 set |= 0x0200;
4643 }
4610 BWN_WRITE_2(mac, BWN_GPIO_MASK,
4611 BWN_READ_2(mac, BWN_GPIO_MASK) | 0x0200);
4612 mask |= 0x0200;
4613 set |= 0x0200;
4614 }
4644 if (mac->mac_sd->sd_id.sd_rev >= 2)
4615 if (siba_get_revid(sc->sc_dev) >= 2)
4645 mask |= 0x0010;
4616 mask |= 0x0010;
4646 sd = (bus->siba_cc.scc_dev != NULL) ? bus->siba_cc.scc_dev :
4647 bus->siba_pci.spc_dev;
4648 if (sd == NULL)
4617
4618 value = siba_gpio_get(sc->sc_dev);
4619 if (value == -1)
4649 return (0);
4620 return (0);
4650 siba_write_4(sd, BWN_GPIOCTL,
4651 (siba_read_4(sd, BWN_GPIOCTL) & mask) | set);
4621 siba_gpio_set(sc->sc_dev, (value & mask) | set);
4652
4653 return (0);
4654}
4655
4656static int
4657bwn_fw_loadinitvals(struct bwn_mac *mac)
4658{
4659#define GETFWOFFSET(fwp, offset) \

--- 84 unchanged lines hidden (view full) ---

4744
4745 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
4746 ic->ic_opmode == IEEE80211_M_MBSS)
4747 ctl |= BWN_MACCTL_HOSTAP;
4748 else if (ic->ic_opmode == IEEE80211_M_IBSS)
4749 ctl &= ~BWN_MACCTL_STA;
4750 ctl |= sc->sc_filters;
4751
4622
4623 return (0);
4624}
4625
4626static int
4627bwn_fw_loadinitvals(struct bwn_mac *mac)
4628{
4629#define GETFWOFFSET(fwp, offset) \

--- 84 unchanged lines hidden (view full) ---

4714
4715 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
4716 ic->ic_opmode == IEEE80211_M_MBSS)
4717 ctl |= BWN_MACCTL_HOSTAP;
4718 else if (ic->ic_opmode == IEEE80211_M_IBSS)
4719 ctl &= ~BWN_MACCTL_STA;
4720 ctl |= sc->sc_filters;
4721
4752 if (mac->mac_sd->sd_id.sd_rev <= 4)
4722 if (siba_get_revid(sc->sc_dev) <= 4)
4753 ctl |= BWN_MACCTL_PROMISC;
4754
4755 BWN_WRITE_4(mac, BWN_MACCTL, ctl);
4756
4757 cfp_pretbtt = 2;
4758 if ((ctl & BWN_MACCTL_STA) && !(ctl & BWN_MACCTL_HOSTAP)) {
4723 ctl |= BWN_MACCTL_PROMISC;
4724
4725 BWN_WRITE_4(mac, BWN_MACCTL, ctl);
4726
4727 cfp_pretbtt = 2;
4728 if ((ctl & BWN_MACCTL_STA) && !(ctl & BWN_MACCTL_HOSTAP)) {
4759 if (mac->mac_sd->sd_bus->siba_chipid == 0x4306 &&
4760 mac->mac_sd->sd_bus->siba_chiprev == 3)
4729 if (siba_get_chipid(sc->sc_dev) == 0x4306 &&
4730 siba_get_chiprev(sc->sc_dev) == 3)
4761 cfp_pretbtt = 100;
4762 else
4763 cfp_pretbtt = 50;
4764 }
4765 BWN_WRITE_2(mac, 0x612, cfp_pretbtt);
4766}
4767
4731 cfp_pretbtt = 100;
4732 else
4733 cfp_pretbtt = 50;
4734 }
4735 BWN_WRITE_2(mac, 0x612, cfp_pretbtt);
4736}
4737
4768static void
4769bwn_gpio_cleanup(struct bwn_mac *mac)
4770{
4771 struct siba_softc *bus = mac->mac_sd->sd_bus;
4772 struct siba_dev_softc *gpiodev, *pcidev = NULL;
4773
4774 pcidev = bus->siba_pci.spc_dev;
4775 gpiodev = bus->siba_cc.scc_dev ? bus->siba_cc.scc_dev : pcidev;
4776 if (!gpiodev)
4777 return;
4778 siba_write_4(gpiodev, BWN_GPIOCTL, 0);
4779}
4780
4781static int
4782bwn_dma_gettype(struct bwn_mac *mac)
4783{
4784 uint32_t tmp;
4785 uint16_t base;
4786
4787 tmp = BWN_READ_4(mac, SIBA_TGSHIGH);
4788 if (tmp & SIBA_TGSHIGH_DMA64)

--- 16 unchanged lines hidden (view full) ---

4805 }
4806}
4807
4808static void
4809bwn_phy_g_init_sub(struct bwn_mac *mac)
4810{
4811 struct bwn_phy *phy = &mac->mac_phy;
4812 struct bwn_phy_g *pg = &phy->phy_g;
4738static int
4739bwn_dma_gettype(struct bwn_mac *mac)
4740{
4741 uint32_t tmp;
4742 uint16_t base;
4743
4744 tmp = BWN_READ_4(mac, SIBA_TGSHIGH);
4745 if (tmp & SIBA_TGSHIGH_DMA64)

--- 16 unchanged lines hidden (view full) ---

4762 }
4763}
4764
4765static void
4766bwn_phy_g_init_sub(struct bwn_mac *mac)
4767{
4768 struct bwn_phy *phy = &mac->mac_phy;
4769 struct bwn_phy_g *pg = &phy->phy_g;
4770 struct bwn_softc *sc = mac->mac_sc;
4813 uint16_t i, tmp;
4814
4815 if (phy->rev == 1)
4816 bwn_phy_init_b5(mac);
4817 else
4818 bwn_phy_init_b6(mac);
4819
4820 if (phy->rev >= 2 || phy->gmode)

--- 46 unchanged lines hidden (view full) ---

4867 pg->pg_loctl.tx_magn);
4868 } else {
4869 BWN_RF_SETMASK(mac, 0x52, 0xfff0, pg->pg_loctl.tx_bias);
4870 }
4871 if (phy->rev >= 6) {
4872 BWN_PHY_SETMASK(mac, BWN_PHY_CCK(0x36), 0x0fff,
4873 (pg->pg_loctl.tx_bias << 12));
4874 }
4771 uint16_t i, tmp;
4772
4773 if (phy->rev == 1)
4774 bwn_phy_init_b5(mac);
4775 else
4776 bwn_phy_init_b6(mac);
4777
4778 if (phy->rev >= 2 || phy->gmode)

--- 46 unchanged lines hidden (view full) ---

4825 pg->pg_loctl.tx_magn);
4826 } else {
4827 BWN_RF_SETMASK(mac, 0x52, 0xfff0, pg->pg_loctl.tx_bias);
4828 }
4829 if (phy->rev >= 6) {
4830 BWN_PHY_SETMASK(mac, BWN_PHY_CCK(0x36), 0x0fff,
4831 (pg->pg_loctl.tx_bias << 12));
4832 }
4875 if (mac->mac_sd->sd_bus->siba_sprom.bf_lo & BWN_BFL_PACTRL)
4833 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL)
4876 BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2e), 0x8075);
4877 else
4878 BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2e), 0x807f);
4879 if (phy->rev < 2)
4880 BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2f), 0x101);
4881 else
4882 BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2f), 0x202);
4883 if (phy->gmode || phy->rev >= 2) {
4884 bwn_lo_g_adjust(mac);
4885 BWN_PHY_WRITE(mac, BWN_PHY_LO_MASK, 0x8078);
4886 }
4887
4834 BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2e), 0x8075);
4835 else
4836 BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2e), 0x807f);
4837 if (phy->rev < 2)
4838 BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2f), 0x101);
4839 else
4840 BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2f), 0x202);
4841 if (phy->gmode || phy->rev >= 2) {
4842 bwn_lo_g_adjust(mac);
4843 BWN_PHY_WRITE(mac, BWN_PHY_LO_MASK, 0x8078);
4844 }
4845
4888 if (!(mac->mac_sd->sd_bus->siba_sprom.bf_lo & BWN_BFL_RSSI)) {
4846 if (!(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_RSSI)) {
4889 for (i = 0; i < 64; i++) {
4890 BWN_PHY_WRITE(mac, BWN_PHY_NRSSI_CTRL, i);
4891 BWN_PHY_WRITE(mac, BWN_PHY_NRSSI_DATA,
4892 (uint16_t)MIN(MAX(bwn_nrssi_read(mac, i) - 0xffff,
4893 -32), 31));
4894 }
4895 bwn_nrssi_threshold(mac);
4896 } else if (phy->gmode || phy->rev >= 2) {
4897 if (pg->pg_nrssi[0] == -1000) {
4898 KASSERT(pg->pg_nrssi[1] == -1000,
4899 ("%s:%d: fail", __func__, __LINE__));
4900 bwn_nrssi_slope_11g(mac);
4901 } else
4902 bwn_nrssi_threshold(mac);
4903 }
4904 if (phy->rf_rev == 8)
4905 BWN_PHY_WRITE(mac, BWN_PHY_EXTG(0x05), 0x3230);
4906 bwn_phy_hwpctl_init(mac);
4847 for (i = 0; i < 64; i++) {
4848 BWN_PHY_WRITE(mac, BWN_PHY_NRSSI_CTRL, i);
4849 BWN_PHY_WRITE(mac, BWN_PHY_NRSSI_DATA,
4850 (uint16_t)MIN(MAX(bwn_nrssi_read(mac, i) - 0xffff,
4851 -32), 31));
4852 }
4853 bwn_nrssi_threshold(mac);
4854 } else if (phy->gmode || phy->rev >= 2) {
4855 if (pg->pg_nrssi[0] == -1000) {
4856 KASSERT(pg->pg_nrssi[1] == -1000,
4857 ("%s:%d: fail", __func__, __LINE__));
4858 bwn_nrssi_slope_11g(mac);
4859 } else
4860 bwn_nrssi_threshold(mac);
4861 }
4862 if (phy->rf_rev == 8)
4863 BWN_PHY_WRITE(mac, BWN_PHY_EXTG(0x05), 0x3230);
4864 bwn_phy_hwpctl_init(mac);
4907 if ((mac->mac_sd->sd_bus->siba_chipid == 0x4306
4908 && mac->mac_sd->sd_bus->siba_chippkg == 2) || 0) {
4865 if ((siba_get_chipid(sc->sc_dev) == 0x4306
4866 && siba_get_chippkg(sc->sc_dev) == 2) || 0) {
4909 BWN_PHY_MASK(mac, BWN_PHY_CRS0, 0xbfff);
4910 BWN_PHY_MASK(mac, BWN_PHY_OFDM(0xc3), 0x7fff);
4911 }
4912}
4913
4914static uint8_t
4915bwn_has_hwpctl(struct bwn_mac *mac)
4916{
4917
4918 if (mac->mac_phy.hwpctl == 0 || mac->mac_phy.use_hwpctl == NULL)
4919 return (0);
4920 return (mac->mac_phy.use_hwpctl(mac));
4921}
4922
4923static void
4924bwn_phy_init_b5(struct bwn_mac *mac)
4925{
4867 BWN_PHY_MASK(mac, BWN_PHY_CRS0, 0xbfff);
4868 BWN_PHY_MASK(mac, BWN_PHY_OFDM(0xc3), 0x7fff);
4869 }
4870}
4871
4872static uint8_t
4873bwn_has_hwpctl(struct bwn_mac *mac)
4874{
4875
4876 if (mac->mac_phy.hwpctl == 0 || mac->mac_phy.use_hwpctl == NULL)
4877 return (0);
4878 return (mac->mac_phy.use_hwpctl(mac));
4879}
4880
4881static void
4882bwn_phy_init_b5(struct bwn_mac *mac)
4883{
4926 struct siba_softc *bus = mac->mac_sd->sd_bus;
4927 struct bwn_phy *phy = &mac->mac_phy;
4928 struct bwn_phy_g *pg = &phy->phy_g;
4884 struct bwn_phy *phy = &mac->mac_phy;
4885 struct bwn_phy_g *pg = &phy->phy_g;
4886 struct bwn_softc *sc = mac->mac_sc;
4929 uint16_t offset, value;
4930 uint8_t old_channel;
4931
4932 if (phy->analog == 1)
4933 BWN_RF_SET(mac, 0x007a, 0x0050);
4887 uint16_t offset, value;
4888 uint8_t old_channel;
4889
4890 if (phy->analog == 1)
4891 BWN_RF_SET(mac, 0x007a, 0x0050);
4934 if ((bus->siba_board_vendor != SIBA_BOARDVENDOR_BCM) &&
4935 (bus->siba_board_type != SIBA_BOARD_BU4306)) {
4892 if ((siba_get_pci_subvendor(sc->sc_dev) != SIBA_BOARDVENDOR_BCM) &&
4893 (siba_get_pci_subdevice(sc->sc_dev) != SIBA_BOARD_BU4306)) {
4936 value = 0x2120;
4937 for (offset = 0x00a8; offset < 0x00c7; offset++) {
4938 BWN_PHY_WRITE(mac, offset, value);
4939 value += 0x202;
4940 }
4941 }
4942 BWN_PHY_SETMASK(mac, 0x0035, 0xf0ff, 0x0700);
4943 if (phy->rf_ver == 0x2050)

--- 72 unchanged lines hidden (view full) ---

5016 BWN_WRITE_2(mac, 0x03e4, (BWN_READ_2(mac, 0x03e4) & 0xffc0) | 0x0004);
5017}
5018
5019static void
5020bwn_loopback_calcgain(struct bwn_mac *mac)
5021{
5022 struct bwn_phy *phy = &mac->mac_phy;
5023 struct bwn_phy_g *pg = &phy->phy_g;
4894 value = 0x2120;
4895 for (offset = 0x00a8; offset < 0x00c7; offset++) {
4896 BWN_PHY_WRITE(mac, offset, value);
4897 value += 0x202;
4898 }
4899 }
4900 BWN_PHY_SETMASK(mac, 0x0035, 0xf0ff, 0x0700);
4901 if (phy->rf_ver == 0x2050)

--- 72 unchanged lines hidden (view full) ---

4974 BWN_WRITE_2(mac, 0x03e4, (BWN_READ_2(mac, 0x03e4) & 0xffc0) | 0x0004);
4975}
4976
4977static void
4978bwn_loopback_calcgain(struct bwn_mac *mac)
4979{
4980 struct bwn_phy *phy = &mac->mac_phy;
4981 struct bwn_phy_g *pg = &phy->phy_g;
4982 struct bwn_softc *sc = mac->mac_sc;
5024 uint16_t backup_phy[16] = { 0 };
5025 uint16_t backup_radio[3];
5026 uint16_t backup_bband;
5027 uint16_t i, j, loop_i_max;
5028 uint16_t trsw_rx;
5029 uint16_t loop1_outer_done, loop1_inner_done;
5030
5031 backup_phy[0] = BWN_PHY_READ(mac, BWN_PHY_CRS0);

--- 62 unchanged lines hidden (view full) ---

5094 BWN_PHY_WRITE(mac, BWN_PHY_LO_CTL, 0);
5095
5096 BWN_PHY_SETMASK(mac, BWN_PHY_CCK(0x2b), 0xffc0, 0x01);
5097 BWN_PHY_SETMASK(mac, BWN_PHY_CCK(0x2b), 0xc0ff, 0x800);
5098
5099 BWN_PHY_SET(mac, BWN_PHY_RFOVER, 0x0100);
5100 BWN_PHY_MASK(mac, BWN_PHY_RFOVERVAL, 0xcfff);
5101
4983 uint16_t backup_phy[16] = { 0 };
4984 uint16_t backup_radio[3];
4985 uint16_t backup_bband;
4986 uint16_t i, j, loop_i_max;
4987 uint16_t trsw_rx;
4988 uint16_t loop1_outer_done, loop1_inner_done;
4989
4990 backup_phy[0] = BWN_PHY_READ(mac, BWN_PHY_CRS0);

--- 62 unchanged lines hidden (view full) ---

5053 BWN_PHY_WRITE(mac, BWN_PHY_LO_CTL, 0);
5054
5055 BWN_PHY_SETMASK(mac, BWN_PHY_CCK(0x2b), 0xffc0, 0x01);
5056 BWN_PHY_SETMASK(mac, BWN_PHY_CCK(0x2b), 0xc0ff, 0x800);
5057
5058 BWN_PHY_SET(mac, BWN_PHY_RFOVER, 0x0100);
5059 BWN_PHY_MASK(mac, BWN_PHY_RFOVERVAL, 0xcfff);
5060
5102 if (mac->mac_sd->sd_bus->siba_sprom.bf_lo & BWN_BFL_EXTLNA) {
5061 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA) {
5103 if (phy->rev >= 7) {
5104 BWN_PHY_SET(mac, BWN_PHY_RFOVER, 0x0800);
5105 BWN_PHY_SET(mac, BWN_PHY_RFOVERVAL, 0x8000);
5106 }
5107 }
5108 BWN_RF_MASK(mac, 0x7a, 0x00f7);
5109
5110 j = 0;

--- 283 unchanged lines hidden (view full) ---

5394 return ((i > 15) ? radio78 : rcc);
5395}
5396
5397static void
5398bwn_phy_init_b6(struct bwn_mac *mac)
5399{
5400 struct bwn_phy *phy = &mac->mac_phy;
5401 struct bwn_phy_g *pg = &phy->phy_g;
5062 if (phy->rev >= 7) {
5063 BWN_PHY_SET(mac, BWN_PHY_RFOVER, 0x0800);
5064 BWN_PHY_SET(mac, BWN_PHY_RFOVERVAL, 0x8000);
5065 }
5066 }
5067 BWN_RF_MASK(mac, 0x7a, 0x00f7);
5068
5069 j = 0;

--- 283 unchanged lines hidden (view full) ---

5353 return ((i > 15) ? radio78 : rcc);
5354}
5355
5356static void
5357bwn_phy_init_b6(struct bwn_mac *mac)
5358{
5359 struct bwn_phy *phy = &mac->mac_phy;
5360 struct bwn_phy_g *pg = &phy->phy_g;
5361 struct bwn_softc *sc = mac->mac_sc;
5402 uint16_t offset, val;
5403 uint8_t old_channel;
5404
5405 KASSERT(!(phy->rf_rev == 6 || phy->rf_rev == 7),
5406 ("%s:%d: fail", __func__, __LINE__));
5407
5408 BWN_PHY_WRITE(mac, 0x003e, 0x817a);
5409 BWN_RF_WRITE(mac, 0x007a, BWN_RF_READ(mac, 0x007a) | 0x0058);

--- 13 unchanged lines hidden (view full) ---

5423 if (phy->rf_rev == 8) {
5424 BWN_RF_WRITE(mac, 0x51, 0);
5425 BWN_RF_WRITE(mac, 0x52, 0x40);
5426 BWN_RF_WRITE(mac, 0x53, 0xb7);
5427 BWN_RF_WRITE(mac, 0x54, 0x98);
5428 BWN_RF_WRITE(mac, 0x5a, 0x88);
5429 BWN_RF_WRITE(mac, 0x5b, 0x6b);
5430 BWN_RF_WRITE(mac, 0x5c, 0x0f);
5362 uint16_t offset, val;
5363 uint8_t old_channel;
5364
5365 KASSERT(!(phy->rf_rev == 6 || phy->rf_rev == 7),
5366 ("%s:%d: fail", __func__, __LINE__));
5367
5368 BWN_PHY_WRITE(mac, 0x003e, 0x817a);
5369 BWN_RF_WRITE(mac, 0x007a, BWN_RF_READ(mac, 0x007a) | 0x0058);

--- 13 unchanged lines hidden (view full) ---

5383 if (phy->rf_rev == 8) {
5384 BWN_RF_WRITE(mac, 0x51, 0);
5385 BWN_RF_WRITE(mac, 0x52, 0x40);
5386 BWN_RF_WRITE(mac, 0x53, 0xb7);
5387 BWN_RF_WRITE(mac, 0x54, 0x98);
5388 BWN_RF_WRITE(mac, 0x5a, 0x88);
5389 BWN_RF_WRITE(mac, 0x5b, 0x6b);
5390 BWN_RF_WRITE(mac, 0x5c, 0x0f);
5431 if (mac->mac_sd->sd_bus->siba_sprom.bf_lo & BWN_BFL_ALTIQ) {
5391 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_ALTIQ) {
5432 BWN_RF_WRITE(mac, 0x5d, 0xfa);
5433 BWN_RF_WRITE(mac, 0x5e, 0xd8);
5434 } else {
5435 BWN_RF_WRITE(mac, 0x5d, 0xf5);
5436 BWN_RF_WRITE(mac, 0x5e, 0xb8);
5437 }
5438 BWN_RF_WRITE(mac, 0x0073, 0x0003);
5439 BWN_RF_WRITE(mac, 0x007d, 0x00a8);

--- 64 unchanged lines hidden (view full) ---

5504 else if (phy->type == BWN_PHYTYPE_G)
5505 BWN_WRITE_2(mac, 0x03e6, 0x0);
5506}
5507
5508static void
5509bwn_phy_init_a(struct bwn_mac *mac)
5510{
5511 struct bwn_phy *phy = &mac->mac_phy;
5392 BWN_RF_WRITE(mac, 0x5d, 0xfa);
5393 BWN_RF_WRITE(mac, 0x5e, 0xd8);
5394 } else {
5395 BWN_RF_WRITE(mac, 0x5d, 0xf5);
5396 BWN_RF_WRITE(mac, 0x5e, 0xb8);
5397 }
5398 BWN_RF_WRITE(mac, 0x0073, 0x0003);
5399 BWN_RF_WRITE(mac, 0x007d, 0x00a8);

--- 64 unchanged lines hidden (view full) ---

5464 else if (phy->type == BWN_PHYTYPE_G)
5465 BWN_WRITE_2(mac, 0x03e6, 0x0);
5466}
5467
5468static void
5469bwn_phy_init_a(struct bwn_mac *mac)
5470{
5471 struct bwn_phy *phy = &mac->mac_phy;
5472 struct bwn_softc *sc = mac->mac_sc;
5512
5513 KASSERT(phy->type == BWN_PHYTYPE_A || phy->type == BWN_PHYTYPE_G,
5514 ("%s:%d: fail", __func__, __LINE__));
5515
5516 if (phy->rev >= 6) {
5517 if (phy->type == BWN_PHYTYPE_A)
5518 BWN_PHY_MASK(mac, BWN_PHY_OFDM(0x1b), ~0x1000);
5519 if (BWN_PHY_READ(mac, BWN_PHY_ENCORE) & BWN_PHY_ENCORE_EN)
5520 BWN_PHY_SET(mac, BWN_PHY_ENCORE, 0x0010);
5521 else
5522 BWN_PHY_MASK(mac, BWN_PHY_ENCORE, ~0x1010);
5523 }
5524
5525 bwn_wa_init(mac);
5526
5527 if (phy->type == BWN_PHYTYPE_G &&
5473
5474 KASSERT(phy->type == BWN_PHYTYPE_A || phy->type == BWN_PHYTYPE_G,
5475 ("%s:%d: fail", __func__, __LINE__));
5476
5477 if (phy->rev >= 6) {
5478 if (phy->type == BWN_PHYTYPE_A)
5479 BWN_PHY_MASK(mac, BWN_PHY_OFDM(0x1b), ~0x1000);
5480 if (BWN_PHY_READ(mac, BWN_PHY_ENCORE) & BWN_PHY_ENCORE_EN)
5481 BWN_PHY_SET(mac, BWN_PHY_ENCORE, 0x0010);
5482 else
5483 BWN_PHY_MASK(mac, BWN_PHY_ENCORE, ~0x1010);
5484 }
5485
5486 bwn_wa_init(mac);
5487
5488 if (phy->type == BWN_PHYTYPE_G &&
5528 (mac->mac_sd->sd_bus->siba_sprom.bf_lo & BWN_BFL_PACTRL))
5489 (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL))
5529 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x6e), 0xe000, 0x3cf);
5530}
5531
5532static void
5533bwn_wa_write_noisescale(struct bwn_mac *mac, const uint16_t *nst)
5534{
5535 int i;
5536

--- 234 unchanged lines hidden (view full) ---

5771 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_UNKNOWN_0F, 2, 15);
5772 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_UNKNOWN_0F, 3, 20);
5773}
5774
5775static void
5776bwn_wa_init(struct bwn_mac *mac)
5777{
5778 struct bwn_phy *phy = &mac->mac_phy;
5490 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x6e), 0xe000, 0x3cf);
5491}
5492
5493static void
5494bwn_wa_write_noisescale(struct bwn_mac *mac, const uint16_t *nst)
5495{
5496 int i;
5497

--- 234 unchanged lines hidden (view full) ---

5732 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_UNKNOWN_0F, 2, 15);
5733 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_UNKNOWN_0F, 3, 20);
5734}
5735
5736static void
5737bwn_wa_init(struct bwn_mac *mac)
5738{
5739 struct bwn_phy *phy = &mac->mac_phy;
5779 struct siba_softc *bus = mac->mac_sd->sd_bus;
5740 struct bwn_softc *sc = mac->mac_sc;
5780
5781 KASSERT(phy->type == BWN_PHYTYPE_G, ("%s fail", __func__));
5782
5783 switch (phy->rev) {
5784 case 1:
5785 bwn_wa_grev1(mac);
5786 break;
5787 case 2:
5788 case 6:
5789 case 7:
5790 case 8:
5791 case 9:
5792 bwn_wa_grev26789(mac);
5793 break;
5794 default:
5795 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
5796 }
5797
5741
5742 KASSERT(phy->type == BWN_PHYTYPE_G, ("%s fail", __func__));
5743
5744 switch (phy->rev) {
5745 case 1:
5746 bwn_wa_grev1(mac);
5747 break;
5748 case 2:
5749 case 6:
5750 case 7:
5751 case 8:
5752 case 9:
5753 bwn_wa_grev26789(mac);
5754 break;
5755 default:
5756 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
5757 }
5758
5798 if (bus->siba_board_vendor != SIBA_BOARDVENDOR_BCM ||
5799 bus->siba_board_type != SIBA_BOARD_BU4306 ||
5800 bus->siba_board_rev != 0x17) {
5759 if (siba_get_pci_subvendor(sc->sc_dev) != SIBA_BOARDVENDOR_BCM ||
5760 siba_get_pci_subdevice(sc->sc_dev) != SIBA_BOARD_BU4306 ||
5761 siba_get_pci_revid(sc->sc_dev) != 0x17) {
5801 if (phy->rev < 2) {
5802 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX_R1, 1,
5803 0x0002);
5804 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX_R1, 2,
5805 0x0001);
5806 } else {
5807 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX, 1, 0x0002);
5808 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX, 2, 0x0001);
5762 if (phy->rev < 2) {
5763 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX_R1, 1,
5764 0x0002);
5765 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX_R1, 2,
5766 0x0001);
5767 } else {
5768 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX, 1, 0x0002);
5769 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX, 2, 0x0001);
5809 if ((bus->siba_sprom.bf_lo & BWN_BFL_EXTLNA) &&
5770 if ((siba_sprom_get_bf_lo(sc->sc_dev) &
5771 BWN_BFL_EXTLNA) &&
5810 (phy->rev >= 7)) {
5811 BWN_PHY_MASK(mac, BWN_PHY_EXTG(0x11), 0xf7ff);
5812 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX,
5813 0x0020, 0x0001);
5814 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX,
5815 0x0021, 0x0001);
5816 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX,
5817 0x0022, 0x0001);
5818 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX,
5819 0x0023, 0x0000);
5820 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX,
5821 0x0000, 0x0000);
5822 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX,
5823 0x0003, 0x0002);
5824 }
5825 }
5826 }
5772 (phy->rev >= 7)) {
5773 BWN_PHY_MASK(mac, BWN_PHY_EXTG(0x11), 0xf7ff);
5774 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX,
5775 0x0020, 0x0001);
5776 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX,
5777 0x0021, 0x0001);
5778 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX,
5779 0x0022, 0x0001);
5780 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX,
5781 0x0023, 0x0000);
5782 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX,
5783 0x0000, 0x0000);
5784 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX,
5785 0x0003, 0x0002);
5786 }
5787 }
5788 }
5827 if (bus->siba_sprom.bf_lo & BWN_BFL_FEM) {
5789 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM) {
5828 BWN_PHY_WRITE(mac, BWN_PHY_GTABCTL, 0x3120);
5829 BWN_PHY_WRITE(mac, BWN_PHY_GTABDATA, 0xc480);
5830 }
5831
5832 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_UNKNOWN_11, 0, 0);
5833 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_UNKNOWN_11, 1, 0);
5834}
5835

--- 41 unchanged lines hidden (view full) ---

5877 BWN_PHY_WRITE(mac, BWN_PHY_GTABCTL, table + offset);
5878 BWN_PHY_WRITE(mac, BWN_PHY_GTABDATA, value);
5879}
5880
5881static void
5882bwn_dummy_transmission(struct bwn_mac *mac, int ofdm, int paon)
5883{
5884 struct bwn_phy *phy = &mac->mac_phy;
5790 BWN_PHY_WRITE(mac, BWN_PHY_GTABCTL, 0x3120);
5791 BWN_PHY_WRITE(mac, BWN_PHY_GTABDATA, 0xc480);
5792 }
5793
5794 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_UNKNOWN_11, 0, 0);
5795 bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_UNKNOWN_11, 1, 0);
5796}
5797

--- 41 unchanged lines hidden (view full) ---

5839 BWN_PHY_WRITE(mac, BWN_PHY_GTABCTL, table + offset);
5840 BWN_PHY_WRITE(mac, BWN_PHY_GTABDATA, value);
5841}
5842
5843static void
5844bwn_dummy_transmission(struct bwn_mac *mac, int ofdm, int paon)
5845{
5846 struct bwn_phy *phy = &mac->mac_phy;
5847 struct bwn_softc *sc = mac->mac_sc;
5885 unsigned int i, max_loop;
5886 uint16_t value;
5887 uint32_t buffer[5] = {
5888 0x00000000, 0x00d40000, 0x00000000, 0x01000000, 0x00000000
5889 };
5890
5891 if (ofdm) {
5892 max_loop = 0x1e;

--- 5 unchanged lines hidden (view full) ---

5898
5899 BWN_ASSERT_LOCKED(mac->mac_sc);
5900
5901 for (i = 0; i < 5; i++)
5902 bwn_ram_write(mac, i * 4, buffer[i]);
5903
5904 BWN_WRITE_2(mac, 0x0568, 0x0000);
5905 BWN_WRITE_2(mac, 0x07c0,
5848 unsigned int i, max_loop;
5849 uint16_t value;
5850 uint32_t buffer[5] = {
5851 0x00000000, 0x00d40000, 0x00000000, 0x01000000, 0x00000000
5852 };
5853
5854 if (ofdm) {
5855 max_loop = 0x1e;

--- 5 unchanged lines hidden (view full) ---

5861
5862 BWN_ASSERT_LOCKED(mac->mac_sc);
5863
5864 for (i = 0; i < 5; i++)
5865 bwn_ram_write(mac, i * 4, buffer[i]);
5866
5867 BWN_WRITE_2(mac, 0x0568, 0x0000);
5868 BWN_WRITE_2(mac, 0x07c0,
5906 (mac->mac_sd->sd_id.sd_rev < 11) ? 0x0000 : 0x0100);
5869 (siba_get_revid(sc->sc_dev) < 11) ? 0x0000 : 0x0100);
5907 value = ((phy->type == BWN_PHYTYPE_A) ? 0x41 : 0x40);
5908 BWN_WRITE_2(mac, 0x050c, value);
5909 if (phy->type == BWN_PHYTYPE_LP)
5910 BWN_WRITE_2(mac, 0x0514, 0x1a02);
5911 BWN_WRITE_2(mac, 0x0508, 0x0000);
5912 BWN_WRITE_2(mac, 0x050a, 0x0000);
5913 BWN_WRITE_2(mac, 0x054c, 0x0000);
5914 BWN_WRITE_2(mac, 0x056a, 0x0014);

--- 57 unchanged lines hidden (view full) ---

5972 BWN_PHY_WRITE(mac, BWN_PHY_LO_CTL, value);
5973}
5974
5975static uint16_t
5976bwn_lo_calcfeed(struct bwn_mac *mac,
5977 uint16_t lna, uint16_t pga, uint16_t trsw_rx)
5978{
5979 struct bwn_phy *phy = &mac->mac_phy;
5870 value = ((phy->type == BWN_PHYTYPE_A) ? 0x41 : 0x40);
5871 BWN_WRITE_2(mac, 0x050c, value);
5872 if (phy->type == BWN_PHYTYPE_LP)
5873 BWN_WRITE_2(mac, 0x0514, 0x1a02);
5874 BWN_WRITE_2(mac, 0x0508, 0x0000);
5875 BWN_WRITE_2(mac, 0x050a, 0x0000);
5876 BWN_WRITE_2(mac, 0x054c, 0x0000);
5877 BWN_WRITE_2(mac, 0x056a, 0x0014);

--- 57 unchanged lines hidden (view full) ---

5935 BWN_PHY_WRITE(mac, BWN_PHY_LO_CTL, value);
5936}
5937
5938static uint16_t
5939bwn_lo_calcfeed(struct bwn_mac *mac,
5940 uint16_t lna, uint16_t pga, uint16_t trsw_rx)
5941{
5942 struct bwn_phy *phy = &mac->mac_phy;
5943 struct bwn_softc *sc = mac->mac_sc;
5980 uint16_t rfover;
5981 uint16_t feedthrough;
5982
5983 if (phy->gmode) {
5984 lna <<= BWN_PHY_RFOVERVAL_LNA_SHIFT;
5985 pga <<= BWN_PHY_RFOVERVAL_PGA_SHIFT;
5986
5987 KASSERT((lna & ~BWN_PHY_RFOVERVAL_LNA) == 0,
5988 ("%s:%d: fail", __func__, __LINE__));
5989 KASSERT((pga & ~BWN_PHY_RFOVERVAL_PGA) == 0,
5990 ("%s:%d: fail", __func__, __LINE__));
5991
5992 trsw_rx &= (BWN_PHY_RFOVERVAL_TRSWRX | BWN_PHY_RFOVERVAL_BW);
5993
5994 rfover = BWN_PHY_RFOVERVAL_UNK | pga | lna | trsw_rx;
5944 uint16_t rfover;
5945 uint16_t feedthrough;
5946
5947 if (phy->gmode) {
5948 lna <<= BWN_PHY_RFOVERVAL_LNA_SHIFT;
5949 pga <<= BWN_PHY_RFOVERVAL_PGA_SHIFT;
5950
5951 KASSERT((lna & ~BWN_PHY_RFOVERVAL_LNA) == 0,
5952 ("%s:%d: fail", __func__, __LINE__));
5953 KASSERT((pga & ~BWN_PHY_RFOVERVAL_PGA) == 0,
5954 ("%s:%d: fail", __func__, __LINE__));
5955
5956 trsw_rx &= (BWN_PHY_RFOVERVAL_TRSWRX | BWN_PHY_RFOVERVAL_BW);
5957
5958 rfover = BWN_PHY_RFOVERVAL_UNK | pga | lna | trsw_rx;
5995 if ((mac->mac_sd->sd_bus->siba_sprom.bf_lo & BWN_BFL_EXTLNA)
5996 && phy->rev > 6)
5959 if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA) &&
5960 phy->rev > 6)
5997 rfover |= BWN_PHY_RFOVERVAL_EXTLNA;
5998
5999 BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, 0xe300);
6000 BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, rfover);
6001 DELAY(10);
6002 rfover |= BWN_PHY_RFOVERVAL_BW_LBW;
6003 BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, rfover);
6004 DELAY(10);

--- 231 unchanged lines hidden (view full) ---

6236 else
6237 tmp |= 0x0008;
6238 BWN_RF_WRITE(mac, 0x7a, tmp);
6239}
6240
6241static void
6242bwn_lo_save(struct bwn_mac *mac, struct bwn_lo_g_value *sav)
6243{
5961 rfover |= BWN_PHY_RFOVERVAL_EXTLNA;
5962
5963 BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, 0xe300);
5964 BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, rfover);
5965 DELAY(10);
5966 rfover |= BWN_PHY_RFOVERVAL_BW_LBW;
5967 BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, rfover);
5968 DELAY(10);

--- 231 unchanged lines hidden (view full) ---

6200 else
6201 tmp |= 0x0008;
6202 BWN_RF_WRITE(mac, 0x7a, tmp);
6203}
6204
6205static void
6206bwn_lo_save(struct bwn_mac *mac, struct bwn_lo_g_value *sav)
6207{
6244 struct siba_sprom *sprom = &mac->mac_sd->sd_bus->siba_sprom;
6245 struct bwn_phy *phy = &mac->mac_phy;
6246 struct bwn_phy_g *pg = &phy->phy_g;
6208 struct bwn_phy *phy = &mac->mac_phy;
6209 struct bwn_phy_g *pg = &phy->phy_g;
6210 struct bwn_softc *sc = mac->mac_sc;
6247 struct bwn_txpwr_loctl *lo = &pg->pg_loctl;
6248 struct timespec ts;
6249 uint16_t tmp;
6250
6251 if (bwn_has_hwpctl(mac)) {
6252 sav->phy_lomask = BWN_PHY_READ(mac, BWN_PHY_LO_MASK);
6253 sav->phy_extg = BWN_PHY_READ(mac, BWN_PHY_EXTG(0x01));
6254 sav->phy_dacctl_hwpctl = BWN_PHY_READ(mac, BWN_PHY_DACCTL);

--- 21 unchanged lines hidden (view full) ---

6276 sav->phy_crs0 = BWN_PHY_READ(mac, BWN_PHY_CRS0);
6277
6278 BWN_PHY_MASK(mac, BWN_PHY_CLASSCTL, 0xfffc);
6279 BWN_PHY_MASK(mac, BWN_PHY_CRS0, 0x7fff);
6280 BWN_PHY_SET(mac, BWN_PHY_ANALOGOVER, 0x0003);
6281 BWN_PHY_MASK(mac, BWN_PHY_ANALOGOVERVAL, 0xfffc);
6282 if (phy->type == BWN_PHYTYPE_G) {
6283 if ((phy->rev >= 7) &&
6211 struct bwn_txpwr_loctl *lo = &pg->pg_loctl;
6212 struct timespec ts;
6213 uint16_t tmp;
6214
6215 if (bwn_has_hwpctl(mac)) {
6216 sav->phy_lomask = BWN_PHY_READ(mac, BWN_PHY_LO_MASK);
6217 sav->phy_extg = BWN_PHY_READ(mac, BWN_PHY_EXTG(0x01));
6218 sav->phy_dacctl_hwpctl = BWN_PHY_READ(mac, BWN_PHY_DACCTL);

--- 21 unchanged lines hidden (view full) ---

6240 sav->phy_crs0 = BWN_PHY_READ(mac, BWN_PHY_CRS0);
6241
6242 BWN_PHY_MASK(mac, BWN_PHY_CLASSCTL, 0xfffc);
6243 BWN_PHY_MASK(mac, BWN_PHY_CRS0, 0x7fff);
6244 BWN_PHY_SET(mac, BWN_PHY_ANALOGOVER, 0x0003);
6245 BWN_PHY_MASK(mac, BWN_PHY_ANALOGOVERVAL, 0xfffc);
6246 if (phy->type == BWN_PHYTYPE_G) {
6247 if ((phy->rev >= 7) &&
6284 (sprom->bf_lo & BWN_BFL_EXTLNA)) {
6248 (siba_sprom_get_bf_lo(sc->sc_dev) &
6249 BWN_BFL_EXTLNA)) {
6285 BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, 0x933);
6286 } else {
6287 BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, 0x133);
6288 }
6289 } else {
6290 BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, 0);
6291 }
6292 BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x3e), 0);

--- 483 unchanged lines hidden (view full) ---

6776 BWN_READ_4(mac, BWN_INTR_REASON);
6777 bwn_psctl(mac, 0);
6778 }
6779}
6780
6781static void
6782bwn_psctl(struct bwn_mac *mac, uint32_t flags)
6783{
6250 BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, 0x933);
6251 } else {
6252 BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, 0x133);
6253 }
6254 } else {
6255 BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, 0);
6256 }
6257 BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x3e), 0);

--- 483 unchanged lines hidden (view full) ---

6741 BWN_READ_4(mac, BWN_INTR_REASON);
6742 bwn_psctl(mac, 0);
6743 }
6744}
6745
6746static void
6747bwn_psctl(struct bwn_mac *mac, uint32_t flags)
6748{
6749 struct bwn_softc *sc = mac->mac_sc;
6784 int i;
6785 uint16_t ucstat;
6786
6787 KASSERT(!((flags & BWN_PS_ON) && (flags & BWN_PS_OFF)),
6788 ("%s:%d: fail", __func__, __LINE__));
6789 KASSERT(!((flags & BWN_PS_AWAKE) && (flags & BWN_PS_ASLEEP)),
6790 ("%s:%d: fail", __func__, __LINE__));
6791
6792 /* XXX forcibly awake and hwps-off */
6793
6794 BWN_WRITE_4(mac, BWN_MACCTL,
6795 (BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_AWAKE) &
6796 ~BWN_MACCTL_HWPS);
6797 BWN_READ_4(mac, BWN_MACCTL);
6750 int i;
6751 uint16_t ucstat;
6752
6753 KASSERT(!((flags & BWN_PS_ON) && (flags & BWN_PS_OFF)),
6754 ("%s:%d: fail", __func__, __LINE__));
6755 KASSERT(!((flags & BWN_PS_AWAKE) && (flags & BWN_PS_ASLEEP)),
6756 ("%s:%d: fail", __func__, __LINE__));
6757
6758 /* XXX forcibly awake and hwps-off */
6759
6760 BWN_WRITE_4(mac, BWN_MACCTL,
6761 (BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_AWAKE) &
6762 ~BWN_MACCTL_HWPS);
6763 BWN_READ_4(mac, BWN_MACCTL);
6798 if (mac->mac_sd->sd_id.sd_rev >= 5) {
6764 if (siba_get_revid(sc->sc_dev) >= 5) {
6799 for (i = 0; i < 100; i++) {
6800 ucstat = bwn_shm_read_2(mac, BWN_SHARED,
6801 BWN_SHARED_UCODESTAT);
6802 if (ucstat != BWN_SHARED_UCODESTAT_SLEEP)
6803 break;
6804 DELAY(10);
6805 }
6806 }

--- 7 unchanged lines hidden (view full) ---

6814 return ((int16_t)BWN_PHY_READ(mac, BWN_PHY_NRSSI_DATA));
6815}
6816
6817static void
6818bwn_nrssi_threshold(struct bwn_mac *mac)
6819{
6820 struct bwn_phy *phy = &mac->mac_phy;
6821 struct bwn_phy_g *pg = &phy->phy_g;
6765 for (i = 0; i < 100; i++) {
6766 ucstat = bwn_shm_read_2(mac, BWN_SHARED,
6767 BWN_SHARED_UCODESTAT);
6768 if (ucstat != BWN_SHARED_UCODESTAT_SLEEP)
6769 break;
6770 DELAY(10);
6771 }
6772 }

--- 7 unchanged lines hidden (view full) ---

6780 return ((int16_t)BWN_PHY_READ(mac, BWN_PHY_NRSSI_DATA));
6781}
6782
6783static void
6784bwn_nrssi_threshold(struct bwn_mac *mac)
6785{
6786 struct bwn_phy *phy = &mac->mac_phy;
6787 struct bwn_phy_g *pg = &phy->phy_g;
6822 struct siba_softc *siba = mac->mac_sd->sd_bus;
6788 struct bwn_softc *sc = mac->mac_sc;
6823 int32_t a, b;
6824 int16_t tmp16;
6825 uint16_t tmpu16;
6826
6827 KASSERT(phy->type == BWN_PHYTYPE_G, ("%s: fail", __func__));
6828
6789 int32_t a, b;
6790 int16_t tmp16;
6791 uint16_t tmpu16;
6792
6793 KASSERT(phy->type == BWN_PHYTYPE_G, ("%s: fail", __func__));
6794
6829 if (phy->gmode && (siba->siba_sprom.bf_lo & BWN_BFL_RSSI)) {
6795 if (phy->gmode && (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_RSSI)) {
6830 if (!pg->pg_aci_wlan_automatic && pg->pg_aci_enable) {
6831 a = 0x13;
6832 b = 0x12;
6833 } else {
6834 a = 0xe;
6835 b = 0x11;
6836 }
6837

--- 416 unchanged lines hidden (view full) ---

7254 BWN_PHY_SETMASK(mac, 0x04a1, 0xbfbf, 0x4040);
7255 BWN_PHY_SETMASK(mac, 0x04a2, 0xbfbf, 0x4000);
7256 bwn_dummy_transmission(mac, 0, 1);
7257}
7258
7259static void
7260bwn_phy_hwpctl_init(struct bwn_mac *mac)
7261{
6796 if (!pg->pg_aci_wlan_automatic && pg->pg_aci_enable) {
6797 a = 0x13;
6798 b = 0x12;
6799 } else {
6800 a = 0xe;
6801 b = 0x11;
6802 }
6803

--- 416 unchanged lines hidden (view full) ---

7220 BWN_PHY_SETMASK(mac, 0x04a1, 0xbfbf, 0x4040);
7221 BWN_PHY_SETMASK(mac, 0x04a2, 0xbfbf, 0x4000);
7222 bwn_dummy_transmission(mac, 0, 1);
7223}
7224
7225static void
7226bwn_phy_hwpctl_init(struct bwn_mac *mac)
7227{
7262 struct siba_softc *bus = mac->mac_sd->sd_bus;
7263 struct bwn_phy *phy = &mac->mac_phy;
7264 struct bwn_phy_g *pg = &phy->phy_g;
7265 struct bwn_rfatt old_rfatt, rfatt;
7266 struct bwn_bbatt old_bbatt, bbatt;
7228 struct bwn_phy *phy = &mac->mac_phy;
7229 struct bwn_phy_g *pg = &phy->phy_g;
7230 struct bwn_rfatt old_rfatt, rfatt;
7231 struct bwn_bbatt old_bbatt, bbatt;
7232 struct bwn_softc *sc = mac->mac_sc;
7267 uint8_t old_txctl = 0;
7268
7269 KASSERT(phy->type == BWN_PHYTYPE_G,
7270 ("%s:%d: fail", __func__, __LINE__));
7271
7233 uint8_t old_txctl = 0;
7234
7235 KASSERT(phy->type == BWN_PHYTYPE_G,
7236 ("%s:%d: fail", __func__, __LINE__));
7237
7272 if ((bus->siba_board_vendor == SIBA_BOARDVENDOR_BCM) &&
7273 (bus->siba_board_type == SIBA_BOARD_BU4306))
7238 if ((siba_get_pci_subvendor(sc->sc_dev) == SIBA_BOARDVENDOR_BCM) &&
7239 (siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BU4306))
7274 return;
7275
7276 BWN_PHY_WRITE(mac, 0x0028, 0x8018);
7277
7278 BWN_WRITE_2(mac, BWN_PHY0, BWN_READ_2(mac, BWN_PHY0) & 0xffdf);
7279
7280 if (!phy->gmode)
7281 return;

--- 120 unchanged lines hidden (view full) ---

7402
7403 bwn_phy_g_dc_lookup_init(mac, 1);
7404 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_HW_POWERCTL);
7405}
7406
7407static void
7408bwn_phy_g_switch_chan(struct bwn_mac *mac, int channel, uint8_t spu)
7409{
7240 return;
7241
7242 BWN_PHY_WRITE(mac, 0x0028, 0x8018);
7243
7244 BWN_WRITE_2(mac, BWN_PHY0, BWN_READ_2(mac, BWN_PHY0) & 0xffdf);
7245
7246 if (!phy->gmode)
7247 return;

--- 120 unchanged lines hidden (view full) ---

7368
7369 bwn_phy_g_dc_lookup_init(mac, 1);
7370 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_HW_POWERCTL);
7371}
7372
7373static void
7374bwn_phy_g_switch_chan(struct bwn_mac *mac, int channel, uint8_t spu)
7375{
7410 struct siba_softc *siba = mac->mac_sd->sd_bus;
7376 struct bwn_softc *sc = mac->mac_sc;
7411
7412 if (spu != 0)
7413 bwn_spu_workaround(mac, channel);
7414
7415 BWN_WRITE_2(mac, BWN_CHANNEL, bwn_phy_g_chan2freq(channel));
7416
7417 if (channel == 14) {
7377
7378 if (spu != 0)
7379 bwn_spu_workaround(mac, channel);
7380
7381 BWN_WRITE_2(mac, BWN_CHANNEL, bwn_phy_g_chan2freq(channel));
7382
7383 if (channel == 14) {
7418 if (siba->siba_sprom.ccode == SIBA_CCODE_JAPAN)
7384 if (siba_sprom_get_ccode(sc->sc_dev) == SIBA_CCODE_JAPAN)
7419 bwn_hf_write(mac,
7420 bwn_hf_read(mac) & ~BWN_HF_JAPAN_CHAN14_OFF);
7421 else
7422 bwn_hf_write(mac,
7423 bwn_hf_read(mac) | BWN_HF_JAPAN_CHAN14_OFF);
7424 BWN_WRITE_2(mac, BWN_CHANNEL_EXT,
7425 BWN_READ_2(mac, BWN_CHANNEL_EXT) | (1 << 11));
7426 return;

--- 68 unchanged lines hidden (view full) ---

7495 BWN_PHY_SETMASK(mac, BWN_PHY_DACCTL, 0xff87, bbatt << 3);
7496}
7497
7498static uint16_t
7499bwn_rf_2050_rfoverval(struct bwn_mac *mac, uint16_t reg, uint32_t lpd)
7500{
7501 struct bwn_phy *phy = &mac->mac_phy;
7502 struct bwn_phy_g *pg = &phy->phy_g;
7385 bwn_hf_write(mac,
7386 bwn_hf_read(mac) & ~BWN_HF_JAPAN_CHAN14_OFF);
7387 else
7388 bwn_hf_write(mac,
7389 bwn_hf_read(mac) | BWN_HF_JAPAN_CHAN14_OFF);
7390 BWN_WRITE_2(mac, BWN_CHANNEL_EXT,
7391 BWN_READ_2(mac, BWN_CHANNEL_EXT) | (1 << 11));
7392 return;

--- 68 unchanged lines hidden (view full) ---

7461 BWN_PHY_SETMASK(mac, BWN_PHY_DACCTL, 0xff87, bbatt << 3);
7462}
7463
7464static uint16_t
7465bwn_rf_2050_rfoverval(struct bwn_mac *mac, uint16_t reg, uint32_t lpd)
7466{
7467 struct bwn_phy *phy = &mac->mac_phy;
7468 struct bwn_phy_g *pg = &phy->phy_g;
7503 struct siba_sprom *sprom = &(mac->mac_sd->sd_bus->siba_sprom);
7469 struct bwn_softc *sc = mac->mac_sc;
7504 int max_lb_gain;
7505 uint16_t extlna;
7506 uint16_t i;
7507
7508 if (phy->gmode == 0)
7509 return (0);
7510
7511 if (BWN_HAS_LOOPBACK(phy)) {

--- 14 unchanged lines hidden (view full) ---

7526 }
7527
7528 for (i = 0; i < 16; i++) {
7529 max_lb_gain -= (i * 6);
7530 if (max_lb_gain < 6)
7531 break;
7532 }
7533
7470 int max_lb_gain;
7471 uint16_t extlna;
7472 uint16_t i;
7473
7474 if (phy->gmode == 0)
7475 return (0);
7476
7477 if (BWN_HAS_LOOPBACK(phy)) {

--- 14 unchanged lines hidden (view full) ---

7492 }
7493
7494 for (i = 0; i < 16; i++) {
7495 max_lb_gain -= (i * 6);
7496 if (max_lb_gain < 6)
7497 break;
7498 }
7499
7534 if ((phy->rev < 7) || !(sprom->bf_lo & BWN_BFL_EXTLNA)) {
7500 if ((phy->rev < 7) ||
7501 !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA)) {
7535 if (reg == BWN_PHY_RFOVER) {
7536 return (0x1b3);
7537 } else if (reg == BWN_PHY_RFOVERVAL) {
7538 extlna |= (i << 8);
7539 switch (lpd) {
7540 case BWN_LPD(0, 1, 1):
7541 return (0x0f92);
7542 case BWN_LPD(0, 0, 1):

--- 27 unchanged lines hidden (view full) ---

7570 ("%s:%d: fail", __func__, __LINE__));
7571 }
7572 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
7573 }
7574 return (0);
7575 }
7576
7577 if ((phy->rev < 7) ||
7502 if (reg == BWN_PHY_RFOVER) {
7503 return (0x1b3);
7504 } else if (reg == BWN_PHY_RFOVERVAL) {
7505 extlna |= (i << 8);
7506 switch (lpd) {
7507 case BWN_LPD(0, 1, 1):
7508 return (0x0f92);
7509 case BWN_LPD(0, 0, 1):

--- 27 unchanged lines hidden (view full) ---

7537 ("%s:%d: fail", __func__, __LINE__));
7538 }
7539 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
7540 }
7541 return (0);
7542 }
7543
7544 if ((phy->rev < 7) ||
7578 !(sprom->bf_lo & BWN_BFL_EXTLNA)) {
7545 !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA)) {
7579 if (reg == BWN_PHY_RFOVER) {
7580 return (0x1b3);
7581 } else if (reg == BWN_PHY_RFOVERVAL) {
7582 switch (lpd) {
7583 case BWN_LPD(0, 1, 1):
7584 return (0x0fb2);
7585 case BWN_LPD(0, 0, 1):
7586 return (0x00b2);

--- 40 unchanged lines hidden (view full) ---

7627 BWN_WRITE_2(mac, BWN_CHANNEL, bwn_phy_g_chan2freq(channel));
7628}
7629
7630static int
7631bwn_fw_gets(struct bwn_mac *mac, enum bwn_fwtype type)
7632{
7633 struct bwn_softc *sc = mac->mac_sc;
7634 struct bwn_fw *fw = &mac->mac_fw;
7546 if (reg == BWN_PHY_RFOVER) {
7547 return (0x1b3);
7548 } else if (reg == BWN_PHY_RFOVERVAL) {
7549 switch (lpd) {
7550 case BWN_LPD(0, 1, 1):
7551 return (0x0fb2);
7552 case BWN_LPD(0, 0, 1):
7553 return (0x00b2);

--- 40 unchanged lines hidden (view full) ---

7594 BWN_WRITE_2(mac, BWN_CHANNEL, bwn_phy_g_chan2freq(channel));
7595}
7596
7597static int
7598bwn_fw_gets(struct bwn_mac *mac, enum bwn_fwtype type)
7599{
7600 struct bwn_softc *sc = mac->mac_sc;
7601 struct bwn_fw *fw = &mac->mac_fw;
7635 const uint8_t rev = mac->mac_sd->sd_id.sd_rev;
7602 const uint8_t rev = siba_get_revid(sc->sc_dev);
7636 const char *filename;
7637 uint32_t high;
7638 int error;
7639
7640 /* microcode */
7641 if (rev >= 5 && rev <= 10)
7642 filename = "ucode5";
7643 else if (rev >= 11 && rev <= 12)

--- 26 unchanged lines hidden (view full) ---

7670 return (error);
7671 }
7672 } else if (rev < 11) {
7673 device_printf(sc->sc_dev, "no PCM for rev %d\n", rev);
7674 return (EOPNOTSUPP);
7675 }
7676
7677 /* initvals */
7603 const char *filename;
7604 uint32_t high;
7605 int error;
7606
7607 /* microcode */
7608 if (rev >= 5 && rev <= 10)
7609 filename = "ucode5";
7610 else if (rev >= 11 && rev <= 12)

--- 26 unchanged lines hidden (view full) ---

7637 return (error);
7638 }
7639 } else if (rev < 11) {
7640 device_printf(sc->sc_dev, "no PCM for rev %d\n", rev);
7641 return (EOPNOTSUPP);
7642 }
7643
7644 /* initvals */
7678 high = siba_read_4(mac->mac_sd, SIBA_TGSHIGH);
7645 high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH);
7679 switch (mac->mac_phy.type) {
7680 case BWN_PHYTYPE_A:
7681 if (rev < 5 || rev > 10)
7682 goto fail1;
7683 if (high & BWN_TGSHIGH_HAVE_2GHZ)
7684 filename = "a0g1initvals5";
7685 else
7686 filename = "a0g0initvals5";

--- 514 unchanged lines hidden (view full) ---

8201 bwn_key_macwrite(mac, index, mac_addr);
8202
8203 mac->mac_key[index].algorithm = algorithm;
8204}
8205
8206static void
8207bwn_key_macwrite(struct bwn_mac *mac, uint8_t index, const uint8_t *addr)
8208{
7646 switch (mac->mac_phy.type) {
7647 case BWN_PHYTYPE_A:
7648 if (rev < 5 || rev > 10)
7649 goto fail1;
7650 if (high & BWN_TGSHIGH_HAVE_2GHZ)
7651 filename = "a0g1initvals5";
7652 else
7653 filename = "a0g0initvals5";

--- 514 unchanged lines hidden (view full) ---

8168 bwn_key_macwrite(mac, index, mac_addr);
8169
8170 mac->mac_key[index].algorithm = algorithm;
8171}
8172
8173static void
8174bwn_key_macwrite(struct bwn_mac *mac, uint8_t index, const uint8_t *addr)
8175{
8176 struct bwn_softc *sc = mac->mac_sc;
8209 uint32_t addrtmp[2] = { 0, 0 };
8210 uint8_t start = 8;
8211
8212 if (BWN_SEC_NEWAPI(mac))
8213 start = 4;
8214
8215 KASSERT(index >= start,
8216 ("%s:%d: fail", __func__, __LINE__));
8217 index -= start;
8218
8219 if (addr) {
8220 addrtmp[0] = addr[0];
8221 addrtmp[0] |= ((uint32_t) (addr[1]) << 8);
8222 addrtmp[0] |= ((uint32_t) (addr[2]) << 16);
8223 addrtmp[0] |= ((uint32_t) (addr[3]) << 24);
8224 addrtmp[1] = addr[4];
8225 addrtmp[1] |= ((uint32_t) (addr[5]) << 8);
8226 }
8227
8177 uint32_t addrtmp[2] = { 0, 0 };
8178 uint8_t start = 8;
8179
8180 if (BWN_SEC_NEWAPI(mac))
8181 start = 4;
8182
8183 KASSERT(index >= start,
8184 ("%s:%d: fail", __func__, __LINE__));
8185 index -= start;
8186
8187 if (addr) {
8188 addrtmp[0] = addr[0];
8189 addrtmp[0] |= ((uint32_t) (addr[1]) << 8);
8190 addrtmp[0] |= ((uint32_t) (addr[2]) << 16);
8191 addrtmp[0] |= ((uint32_t) (addr[3]) << 24);
8192 addrtmp[1] = addr[4];
8193 addrtmp[1] |= ((uint32_t) (addr[5]) << 8);
8194 }
8195
8228 if (mac->mac_sd->sd_id.sd_rev >= 5) {
8196 if (siba_get_revid(sc->sc_dev) >= 5) {
8229 bwn_shm_write_4(mac, BWN_RCMTA, (index * 2) + 0, addrtmp[0]);
8230 bwn_shm_write_2(mac, BWN_RCMTA, (index * 2) + 1, addrtmp[1]);
8231 } else {
8232 if (index >= 8) {
8233 bwn_shm_write_4(mac, BWN_SHARED,
8234 BWN_SHARED_PSM + (index * 6) + 0, addrtmp[0]);
8235 bwn_shm_write_2(mac, BWN_SHARED,
8236 BWN_SHARED_PSM + (index * 6) + 4, addrtmp[1]);

--- 154 unchanged lines hidden (view full) ---

8391 mac->mac_phy.rf_onoff(mac, 0);
8392 mac->mac_phy.rf_on = 0;
8393 bwn_mac_enable(mac);
8394}
8395
8396static void
8397bwn_phy_reset(struct bwn_mac *mac)
8398{
8197 bwn_shm_write_4(mac, BWN_RCMTA, (index * 2) + 0, addrtmp[0]);
8198 bwn_shm_write_2(mac, BWN_RCMTA, (index * 2) + 1, addrtmp[1]);
8199 } else {
8200 if (index >= 8) {
8201 bwn_shm_write_4(mac, BWN_SHARED,
8202 BWN_SHARED_PSM + (index * 6) + 0, addrtmp[0]);
8203 bwn_shm_write_2(mac, BWN_SHARED,
8204 BWN_SHARED_PSM + (index * 6) + 4, addrtmp[1]);

--- 154 unchanged lines hidden (view full) ---

8359 mac->mac_phy.rf_onoff(mac, 0);
8360 mac->mac_phy.rf_on = 0;
8361 bwn_mac_enable(mac);
8362}
8363
8364static void
8365bwn_phy_reset(struct bwn_mac *mac)
8366{
8399 struct siba_dev_softc *sd = mac->mac_sd;
8367 struct bwn_softc *sc = mac->mac_sc;
8400
8368
8401 siba_write_4(sd, SIBA_TGSLOW,
8402 ((siba_read_4(sd, SIBA_TGSLOW) & ~BWN_TGSLOW_SUPPORT_G) |
8369 siba_write_4(sc->sc_dev, SIBA_TGSLOW,
8370 ((siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~BWN_TGSLOW_SUPPORT_G) |
8403 BWN_TGSLOW_PHYRESET) | SIBA_TGSLOW_FGC);
8404 DELAY(1000);
8371 BWN_TGSLOW_PHYRESET) | SIBA_TGSLOW_FGC);
8372 DELAY(1000);
8405 siba_write_4(sd, SIBA_TGSLOW,
8406 (siba_read_4(sd, SIBA_TGSLOW) & ~SIBA_TGSLOW_FGC) |
8373 siba_write_4(sc->sc_dev, SIBA_TGSLOW,
8374 (siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~SIBA_TGSLOW_FGC) |
8407 BWN_TGSLOW_PHYRESET);
8408 DELAY(1000);
8409}
8410
8411static int
8412bwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
8413{
8414 struct bwn_vap *bvp = BWN_VAP(vap);

--- 66 unchanged lines hidden (view full) ---

8481 BWN_WRITE_2(mac, BWN_TSF_CFP_PRETBTT, pretbtt);
8482}
8483
8484static int
8485bwn_intr(void *arg)
8486{
8487 struct bwn_mac *mac = arg;
8488 struct bwn_softc *sc = mac->mac_sc;
8375 BWN_TGSLOW_PHYRESET);
8376 DELAY(1000);
8377}
8378
8379static int
8380bwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
8381{
8382 struct bwn_vap *bvp = BWN_VAP(vap);

--- 66 unchanged lines hidden (view full) ---

8449 BWN_WRITE_2(mac, BWN_TSF_CFP_PRETBTT, pretbtt);
8450}
8451
8452static int
8453bwn_intr(void *arg)
8454{
8455 struct bwn_mac *mac = arg;
8456 struct bwn_softc *sc = mac->mac_sc;
8489 struct siba_softc *siba = mac->mac_sd->sd_bus;
8490 uint32_t reason;
8491
8457 uint32_t reason;
8458
8492 if (mac->mac_status < BWN_MAC_STATUS_STARTED || siba->siba_invalid)
8459 if (mac->mac_status < BWN_MAC_STATUS_STARTED ||
8460 (sc->sc_flags & BWN_FLAG_INVALID))
8493 return (FILTER_STRAY);
8494
8495 reason = BWN_READ_4(mac, BWN_INTR_REASON);
8496 if (reason == 0xffffffff) /* shared IRQ */
8497 return (FILTER_STRAY);
8498 reason &= mac->mac_intr_mask;
8499 if (reason == 0)
8500 return (FILTER_HANDLED);

--- 23 unchanged lines hidden (view full) ---

8524}
8525
8526static void
8527bwn_intrtask(void *arg, int npending)
8528{
8529 struct bwn_mac *mac = arg;
8530 struct bwn_softc *sc = mac->mac_sc;
8531 struct ifnet *ifp = sc->sc_ifp;
8461 return (FILTER_STRAY);
8462
8463 reason = BWN_READ_4(mac, BWN_INTR_REASON);
8464 if (reason == 0xffffffff) /* shared IRQ */
8465 return (FILTER_STRAY);
8466 reason &= mac->mac_intr_mask;
8467 if (reason == 0)
8468 return (FILTER_HANDLED);

--- 23 unchanged lines hidden (view full) ---

8492}
8493
8494static void
8495bwn_intrtask(void *arg, int npending)
8496{
8497 struct bwn_mac *mac = arg;
8498 struct bwn_softc *sc = mac->mac_sc;
8499 struct ifnet *ifp = sc->sc_ifp;
8532 struct siba_softc *siba = mac->mac_sd->sd_bus;
8533 uint32_t merged = 0;
8534 int i, tx = 0, rx = 0;
8535
8536 BWN_LOCK(sc);
8500 uint32_t merged = 0;
8501 int i, tx = 0, rx = 0;
8502
8503 BWN_LOCK(sc);
8537 if (mac->mac_status < BWN_MAC_STATUS_STARTED || siba->siba_invalid) {
8504 if (mac->mac_status < BWN_MAC_STATUS_STARTED ||
8505 (sc->sc_flags & BWN_FLAG_INVALID)) {
8538 BWN_UNLOCK(sc);
8539 return;
8540 }
8541
8542 for (i = 0; i < N(mac->mac_reason); i++)
8543 merged |= mac->mac_reason[i];
8544
8545 if (mac->mac_reason_intr & BWN_INTR_MAC_TXERR)

--- 625 unchanged lines hidden (view full) ---

9171 goto ready;
9172 DELAY(10);
9173 }
9174 }
9175 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
9176 return (1);
9177ready:
9178 if (prq->prq_rev >= 8)
8506 BWN_UNLOCK(sc);
8507 return;
8508 }
8509
8510 for (i = 0; i < N(mac->mac_reason); i++)
8511 merged |= mac->mac_reason[i];
8512
8513 if (mac->mac_reason_intr & BWN_INTR_MAC_TXERR)

--- 625 unchanged lines hidden (view full) ---

9139 goto ready;
9140 DELAY(10);
9141 }
9142 }
9143 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
9144 return (1);
9145ready:
9146 if (prq->prq_rev >= 8)
9179 siba_read_multi_4(mac->mac_sd, &rxhdr, sizeof(rxhdr),
9147 siba_read_multi_4(sc->sc_dev, &rxhdr, sizeof(rxhdr),
9180 prq->prq_base + BWN_PIO8_RXDATA);
9181 else
9148 prq->prq_base + BWN_PIO8_RXDATA);
9149 else
9182 siba_read_multi_2(mac->mac_sd, &rxhdr, sizeof(rxhdr),
9150 siba_read_multi_2(sc->sc_dev, &rxhdr, sizeof(rxhdr),
9183 prq->prq_base + BWN_PIO_RXDATA);
9184 len = le16toh(rxhdr.frame_len);
9185 if (len > 0x700) {
9186 device_printf(sc->sc_dev, "%s: len is too big\n", __func__);
9187 goto error;
9188 }
9189 if (len == 0) {
9190 device_printf(sc->sc_dev, "%s: len is 0\n", __func__);

--- 12 unchanged lines hidden (view full) ---

9203 KASSERT(len + padding <= MCLBYTES, ("too big..\n"));
9204 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
9205 if (m == NULL) {
9206 device_printf(sc->sc_dev, "%s: out of memory", __func__);
9207 goto error;
9208 }
9209 mp = mtod(m, unsigned char *);
9210 if (prq->prq_rev >= 8) {
9151 prq->prq_base + BWN_PIO_RXDATA);
9152 len = le16toh(rxhdr.frame_len);
9153 if (len > 0x700) {
9154 device_printf(sc->sc_dev, "%s: len is too big\n", __func__);
9155 goto error;
9156 }
9157 if (len == 0) {
9158 device_printf(sc->sc_dev, "%s: len is 0\n", __func__);

--- 12 unchanged lines hidden (view full) ---

9171 KASSERT(len + padding <= MCLBYTES, ("too big..\n"));
9172 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
9173 if (m == NULL) {
9174 device_printf(sc->sc_dev, "%s: out of memory", __func__);
9175 goto error;
9176 }
9177 mp = mtod(m, unsigned char *);
9178 if (prq->prq_rev >= 8) {
9211 siba_read_multi_4(mac->mac_sd, mp + padding, (len & ~3),
9179 siba_read_multi_4(sc->sc_dev, mp + padding, (len & ~3),
9212 prq->prq_base + BWN_PIO8_RXDATA);
9213 if (len & 3) {
9214 v32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXDATA);
9215 data = &(mp[len + padding - 1]);
9216 switch (len & 3) {
9217 case 3:
9218 *data = (v32 >> 16);
9219 data--;
9220 case 2:
9221 *data = (v32 >> 8);
9222 data--;
9223 case 1:
9224 *data = v32;
9225 }
9226 }
9227 } else {
9180 prq->prq_base + BWN_PIO8_RXDATA);
9181 if (len & 3) {
9182 v32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXDATA);
9183 data = &(mp[len + padding - 1]);
9184 switch (len & 3) {
9185 case 3:
9186 *data = (v32 >> 16);
9187 data--;
9188 case 2:
9189 *data = (v32 >> 8);
9190 data--;
9191 case 1:
9192 *data = v32;
9193 }
9194 }
9195 } else {
9228 siba_read_multi_2(mac->mac_sd, mp + padding, (len & ~1),
9196 siba_read_multi_2(sc->sc_dev, mp + padding, (len & ~1),
9229 prq->prq_base + BWN_PIO_RXDATA);
9230 if (len & 1) {
9231 v16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXDATA);
9232 mp[len + padding - 1] = v16;
9233 }
9234 }
9235
9236 m->m_pkthdr.rcvif = ifp;

--- 336 unchanged lines hidden (view full) ---

9573
9574static void
9575bwn_phy_txpower_check(struct bwn_mac *mac, uint32_t flags)
9576{
9577 struct bwn_softc *sc = mac->mac_sc;
9578 struct bwn_phy *phy = &mac->mac_phy;
9579 struct ifnet *ifp = sc->sc_ifp;
9580 struct ieee80211com *ic = ifp->if_l2com;
9197 prq->prq_base + BWN_PIO_RXDATA);
9198 if (len & 1) {
9199 v16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXDATA);
9200 mp[len + padding - 1] = v16;
9201 }
9202 }
9203
9204 m->m_pkthdr.rcvif = ifp;

--- 336 unchanged lines hidden (view full) ---

9541
9542static void
9543bwn_phy_txpower_check(struct bwn_mac *mac, uint32_t flags)
9544{
9545 struct bwn_softc *sc = mac->mac_sc;
9546 struct bwn_phy *phy = &mac->mac_phy;
9547 struct ifnet *ifp = sc->sc_ifp;
9548 struct ieee80211com *ic = ifp->if_l2com;
9581 struct siba_softc *siba = mac->mac_sd->sd_bus;
9582 unsigned long now;
9583 int result;
9584
9585 BWN_GETTIME(now);
9586
9587 if (!(flags & BWN_TXPWR_IGNORE_TIME) && time_before(now, phy->nexttime))
9588 return;
9589 phy->nexttime = now + 2 * 1000;
9590
9549 unsigned long now;
9550 int result;
9551
9552 BWN_GETTIME(now);
9553
9554 if (!(flags & BWN_TXPWR_IGNORE_TIME) && time_before(now, phy->nexttime))
9555 return;
9556 phy->nexttime = now + 2 * 1000;
9557
9591 if (siba->siba_board_vendor == SIBA_BOARDVENDOR_BCM &&
9592 siba->siba_board_type == SIBA_BOARD_BU4306)
9558 if (siba_get_pci_subvendor(sc->sc_dev) == SIBA_BOARDVENDOR_BCM &&
9559 siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BU4306)
9593 return;
9594
9595 if (phy->recalc_txpwr != NULL) {
9596 result = phy->recalc_txpwr(mac,
9597 (flags & BWN_TXPWR_IGNORE_TSSI) ? 1 : 0);
9598 if (result == BWN_TXPWR_RES_DONE)
9599 return;
9600 KASSERT(result == BWN_TXPWR_RES_NEED_ADJUST,

--- 296 unchanged lines hidden (view full) ---

9897 plcp->o.data |= htole32(plen << 16);
9898 raw[0] = bwn_plcp_getcck(rate);
9899 }
9900}
9901
9902static uint8_t
9903bwn_antenna_sanitize(struct bwn_mac *mac, uint8_t n)
9904{
9560 return;
9561
9562 if (phy->recalc_txpwr != NULL) {
9563 result = phy->recalc_txpwr(mac,
9564 (flags & BWN_TXPWR_IGNORE_TSSI) ? 1 : 0);
9565 if (result == BWN_TXPWR_RES_DONE)
9566 return;
9567 KASSERT(result == BWN_TXPWR_RES_NEED_ADJUST,

--- 296 unchanged lines hidden (view full) ---

9864 plcp->o.data |= htole32(plen << 16);
9865 raw[0] = bwn_plcp_getcck(rate);
9866 }
9867}
9868
9869static uint8_t
9870bwn_antenna_sanitize(struct bwn_mac *mac, uint8_t n)
9871{
9872 struct bwn_softc *sc = mac->mac_sc;
9905 uint8_t mask;
9906
9907 if (n == 0)
9908 return (0);
9909 if (mac->mac_phy.gmode)
9873 uint8_t mask;
9874
9875 if (n == 0)
9876 return (0);
9877 if (mac->mac_phy.gmode)
9910 mask = mac->mac_sd->sd_bus->siba_sprom.ant_bg;
9878 mask = siba_sprom_get_ant_bg(sc->sc_dev);
9911 else
9879 else
9912 mask = mac->mac_sd->sd_bus->siba_sprom.ant_a;
9880 mask = siba_sprom_get_ant_a(sc->sc_dev);
9913 if (!(mask & (1 << (n - 1))))
9914 return (0);
9915 return (n);
9916}
9917
9918static uint8_t
9919bwn_get_fbrate(uint8_t bitrate)
9920{

--- 26 unchanged lines hidden (view full) ---

9947 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
9948 return (0);
9949}
9950
9951static uint32_t
9952bwn_pio_write_multi_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
9953 uint32_t ctl, const void *_data, int len)
9954{
9881 if (!(mask & (1 << (n - 1))))
9882 return (0);
9883 return (n);
9884}
9885
9886static uint8_t
9887bwn_get_fbrate(uint8_t bitrate)
9888{

--- 26 unchanged lines hidden (view full) ---

9915 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
9916 return (0);
9917}
9918
9919static uint32_t
9920bwn_pio_write_multi_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
9921 uint32_t ctl, const void *_data, int len)
9922{
9923 struct bwn_softc *sc = mac->mac_sc;
9955 uint32_t value = 0;
9956 const uint8_t *data = _data;
9957
9958 ctl |= BWN_PIO8_TXCTL_0_7 | BWN_PIO8_TXCTL_8_15 |
9959 BWN_PIO8_TXCTL_16_23 | BWN_PIO8_TXCTL_24_31;
9960 bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl);
9961
9924 uint32_t value = 0;
9925 const uint8_t *data = _data;
9926
9927 ctl |= BWN_PIO8_TXCTL_0_7 | BWN_PIO8_TXCTL_8_15 |
9928 BWN_PIO8_TXCTL_16_23 | BWN_PIO8_TXCTL_24_31;
9929 bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl);
9930
9962 siba_write_multi_4(mac->mac_sd, data, (len & ~3),
9931 siba_write_multi_4(sc->sc_dev, data, (len & ~3),
9963 tq->tq_base + BWN_PIO8_TXDATA);
9964 if (len & 3) {
9965 ctl &= ~(BWN_PIO8_TXCTL_8_15 | BWN_PIO8_TXCTL_16_23 |
9966 BWN_PIO8_TXCTL_24_31);
9967 data = &(data[len - 1]);
9968 switch (len & 3) {
9969 case 3:
9970 ctl |= BWN_PIO8_TXCTL_16_23;

--- 20 unchanged lines hidden (view full) ---

9991
9992 BWN_WRITE_4(mac, tq->tq_base + offset, value);
9993}
9994
9995static uint16_t
9996bwn_pio_write_multi_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
9997 uint16_t ctl, const void *_data, int len)
9998{
9932 tq->tq_base + BWN_PIO8_TXDATA);
9933 if (len & 3) {
9934 ctl &= ~(BWN_PIO8_TXCTL_8_15 | BWN_PIO8_TXCTL_16_23 |
9935 BWN_PIO8_TXCTL_24_31);
9936 data = &(data[len - 1]);
9937 switch (len & 3) {
9938 case 3:
9939 ctl |= BWN_PIO8_TXCTL_16_23;

--- 20 unchanged lines hidden (view full) ---

9960
9961 BWN_WRITE_4(mac, tq->tq_base + offset, value);
9962}
9963
9964static uint16_t
9965bwn_pio_write_multi_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
9966 uint16_t ctl, const void *_data, int len)
9967{
9968 struct bwn_softc *sc = mac->mac_sc;
9999 const uint8_t *data = _data;
10000
10001 ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI;
10002 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
10003
9969 const uint8_t *data = _data;
9970
9971 ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI;
9972 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
9973
10004 siba_write_multi_2(mac->mac_sd, data, (len & ~1),
9974 siba_write_multi_2(sc->sc_dev, data, (len & ~1),
10005 tq->tq_base + BWN_PIO_TXDATA);
10006 if (len & 1) {
10007 ctl &= ~BWN_PIO_TXCTL_WRITEHI;
10008 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
10009 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data[len - 1]);
10010 }
10011
10012 return (ctl);

--- 162 unchanged lines hidden (view full) ---

10175}
10176
10177static void
10178bwn_phy_lock(struct bwn_mac *mac)
10179{
10180 struct bwn_softc *sc = mac->mac_sc;
10181 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
10182
9975 tq->tq_base + BWN_PIO_TXDATA);
9976 if (len & 1) {
9977 ctl &= ~BWN_PIO_TXCTL_WRITEHI;
9978 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
9979 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data[len - 1]);
9980 }
9981
9982 return (ctl);

--- 162 unchanged lines hidden (view full) ---

10145}
10146
10147static void
10148bwn_phy_lock(struct bwn_mac *mac)
10149{
10150 struct bwn_softc *sc = mac->mac_sc;
10151 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
10152
10183 KASSERT(mac->mac_sd->sd_id.sd_rev >= 3,
10184 ("%s: unsupported rev %d", __func__, mac->mac_sd->sd_id.sd_rev));
10153 KASSERT(siba_get_revid(sc->sc_dev) >= 3,
10154 ("%s: unsupported rev %d", __func__, siba_get_revid(sc->sc_dev)));
10185
10186 if (ic->ic_opmode != IEEE80211_M_HOSTAP)
10187 bwn_psctl(mac, BWN_PS_AWAKE);
10188}
10189
10190static void
10191bwn_phy_unlock(struct bwn_mac *mac)
10192{
10193 struct bwn_softc *sc = mac->mac_sc;
10194 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
10195
10155
10156 if (ic->ic_opmode != IEEE80211_M_HOSTAP)
10157 bwn_psctl(mac, BWN_PS_AWAKE);
10158}
10159
10160static void
10161bwn_phy_unlock(struct bwn_mac *mac)
10162{
10163 struct bwn_softc *sc = mac->mac_sc;
10164 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
10165
10196 KASSERT(mac->mac_sd->sd_id.sd_rev >= 3,
10197 ("%s: unsupported rev %d", __func__, mac->mac_sd->sd_id.sd_rev));
10166 KASSERT(siba_get_revid(sc->sc_dev) >= 3,
10167 ("%s: unsupported rev %d", __func__, siba_get_revid(sc->sc_dev)));
10198
10199 if (ic->ic_opmode != IEEE80211_M_HOSTAP)
10200 bwn_psctl(mac, 0);
10201}
10202
10203static void
10204bwn_rf_lock(struct bwn_mac *mac)
10205{

--- 200 unchanged lines hidden (view full) ---

10406 sc->sc_rx_th.wr_rate = rate;
10407 sc->sc_rx_th.wr_antsignal = rssi;
10408 sc->sc_rx_th.wr_antnoise = noise;
10409}
10410
10411static void
10412bwn_tsf_read(struct bwn_mac *mac, uint64_t *tsf)
10413{
10168
10169 if (ic->ic_opmode != IEEE80211_M_HOSTAP)
10170 bwn_psctl(mac, 0);
10171}
10172
10173static void
10174bwn_rf_lock(struct bwn_mac *mac)
10175{

--- 200 unchanged lines hidden (view full) ---

10376 sc->sc_rx_th.wr_rate = rate;
10377 sc->sc_rx_th.wr_antsignal = rssi;
10378 sc->sc_rx_th.wr_antnoise = noise;
10379}
10380
10381static void
10382bwn_tsf_read(struct bwn_mac *mac, uint64_t *tsf)
10383{
10384 struct bwn_softc *sc = mac->mac_sc;
10414 uint32_t low, high;
10415
10385 uint32_t low, high;
10386
10416 KASSERT(mac->mac_sd->sd_id.sd_rev >= 3,
10387 KASSERT(siba_get_revid(sc->sc_dev) >= 3,
10417 ("%s:%d: fail", __func__, __LINE__));
10418
10419 low = BWN_READ_4(mac, BWN_REV3PLUS_TSF_LOW);
10420 high = BWN_READ_4(mac, BWN_REV3PLUS_TSF_HIGH);
10421 *tsf = high;
10422 *tsf <<= 32;
10423 *tsf |= low;
10424}
10425
10426static int
10427bwn_dma_attach(struct bwn_mac *mac)
10428{
10429 struct bwn_dma *dma = &mac->mac_method.dma;
10430 struct bwn_softc *sc = mac->mac_sc;
10388 ("%s:%d: fail", __func__, __LINE__));
10389
10390 low = BWN_READ_4(mac, BWN_REV3PLUS_TSF_LOW);
10391 high = BWN_READ_4(mac, BWN_REV3PLUS_TSF_HIGH);
10392 *tsf = high;
10393 *tsf <<= 32;
10394 *tsf |= low;
10395}
10396
10397static int
10398bwn_dma_attach(struct bwn_mac *mac)
10399{
10400 struct bwn_dma *dma = &mac->mac_method.dma;
10401 struct bwn_softc *sc = mac->mac_sc;
10431 struct siba_dev_softc *sd = mac->mac_sd;
10432 struct siba_softc *siba = sd->sd_bus;
10433 bus_addr_t lowaddr = 0;
10434 int error;
10435
10402 bus_addr_t lowaddr = 0;
10403 int error;
10404
10436 if (siba->siba_type == SIBA_TYPE_PCMCIA || bwn_usedma == 0)
10405 if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0)
10437 return (0);
10438
10406 return (0);
10407
10439 KASSERT(mac->mac_sd->sd_id.sd_rev >= 5, ("%s: fail", __func__));
10408 KASSERT(siba_get_revid(sc->sc_dev) >= 5, ("%s: fail", __func__));
10440
10441 mac->mac_flags |= BWN_MAC_FLAG_DMA;
10442
10443 dma->dmatype = bwn_dma_gettype(mac);
10444 if (dma->dmatype == BWN_DMA_30BIT)
10445 lowaddr = BWN_BUS_SPACE_MAXADDR_30BIT;
10446 else if (dma->dmatype == BWN_DMA_32BIT)
10447 lowaddr = BUS_SPACE_MAXADDR_32BIT;

--- 182 unchanged lines hidden (view full) ---

10630 bwn_destroy_queue_tx(&pio->wme[WME_AC_BE]);
10631 bwn_destroy_queue_tx(&pio->wme[WME_AC_BK]);
10632}
10633
10634static void
10635bwn_led_attach(struct bwn_mac *mac)
10636{
10637 struct bwn_softc *sc = mac->mac_sc;
10409
10410 mac->mac_flags |= BWN_MAC_FLAG_DMA;
10411
10412 dma->dmatype = bwn_dma_gettype(mac);
10413 if (dma->dmatype == BWN_DMA_30BIT)
10414 lowaddr = BWN_BUS_SPACE_MAXADDR_30BIT;
10415 else if (dma->dmatype == BWN_DMA_32BIT)
10416 lowaddr = BUS_SPACE_MAXADDR_32BIT;

--- 182 unchanged lines hidden (view full) ---

10599 bwn_destroy_queue_tx(&pio->wme[WME_AC_BE]);
10600 bwn_destroy_queue_tx(&pio->wme[WME_AC_BK]);
10601}
10602
10603static void
10604bwn_led_attach(struct bwn_mac *mac)
10605{
10606 struct bwn_softc *sc = mac->mac_sc;
10638 struct siba_softc *siba = mac->mac_sd->sd_bus;
10639 const uint8_t *led_act = NULL;
10640 uint16_t val[BWN_LED_MAX];
10641 int i;
10642
10643 sc->sc_led_idle = (2350 * hz) / 1000;
10644 sc->sc_led_blink = 1;
10645
10646 for (i = 0; i < N(bwn_vendor_led_act); ++i) {
10607 const uint8_t *led_act = NULL;
10608 uint16_t val[BWN_LED_MAX];
10609 int i;
10610
10611 sc->sc_led_idle = (2350 * hz) / 1000;
10612 sc->sc_led_blink = 1;
10613
10614 for (i = 0; i < N(bwn_vendor_led_act); ++i) {
10647 if (siba->siba_pci_subvid == bwn_vendor_led_act[i].vid) {
10615 if (siba_get_pci_subvendor(sc->sc_dev) ==
10616 bwn_vendor_led_act[i].vid) {
10648 led_act = bwn_vendor_led_act[i].led_act;
10649 break;
10650 }
10651 }
10652 if (led_act == NULL)
10653 led_act = bwn_default_led_act;
10654
10617 led_act = bwn_vendor_led_act[i].led_act;
10618 break;
10619 }
10620 }
10621 if (led_act == NULL)
10622 led_act = bwn_default_led_act;
10623
10655 val[0] = siba->siba_sprom.gpio0;
10656 val[1] = siba->siba_sprom.gpio1;
10657 val[2] = siba->siba_sprom.gpio2;
10658 val[3] = siba->siba_sprom.gpio3;
10624 val[0] = siba_sprom_get_gpio0(sc->sc_dev);
10625 val[1] = siba_sprom_get_gpio1(sc->sc_dev);
10626 val[2] = siba_sprom_get_gpio2(sc->sc_dev);
10627 val[3] = siba_sprom_get_gpio3(sc->sc_dev);
10659
10660 for (i = 0; i < BWN_LED_MAX; ++i) {
10661 struct bwn_led *led = &sc->sc_leds[i];
10662
10663 if (val[i] == 0xff) {
10664 led->led_act = led_act[i];
10665 } else {
10666 if (val[i] & BWN_LED_ACT_LOW)

--- 99 unchanged lines hidden (view full) ---

10766 }
10767 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
10768}
10769
10770static void
10771bwn_led_event(struct bwn_mac *mac, int event)
10772{
10773 struct bwn_softc *sc = mac->mac_sc;
10628
10629 for (i = 0; i < BWN_LED_MAX; ++i) {
10630 struct bwn_led *led = &sc->sc_leds[i];
10631
10632 if (val[i] == 0xff) {
10633 led->led_act = led_act[i];
10634 } else {
10635 if (val[i] & BWN_LED_ACT_LOW)

--- 99 unchanged lines hidden (view full) ---

10735 }
10736 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
10737}
10738
10739static void
10740bwn_led_event(struct bwn_mac *mac, int event)
10741{
10742 struct bwn_softc *sc = mac->mac_sc;
10774 struct bwn_led *led = sc->sc_blink_led;
10775 int rate;
10743 struct bwn_led *led = sc->sc_blink_led;
10744 int rate;
10776
10745
10777 if (event == BWN_LED_EVENT_POLL) {
10778 if ((led->led_flags & BWN_LED_F_POLLABLE) == 0)
10779 return;
10780 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
10781 return;
10782 }
10746 if (event == BWN_LED_EVENT_POLL) {
10747 if ((led->led_flags & BWN_LED_F_POLLABLE) == 0)
10748 return;
10749 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
10750 return;
10751 }
10783
10752
10784 sc->sc_led_ticks = ticks;
10785 if (sc->sc_led_blinking)
10786 return;
10753 sc->sc_led_ticks = ticks;
10754 if (sc->sc_led_blinking)
10755 return;
10787
10756
10788 switch (event) {
10789 case BWN_LED_EVENT_RX:
10790 rate = sc->sc_rx_rate;
10791 break;
10792 case BWN_LED_EVENT_TX:
10793 rate = sc->sc_tx_rate;
10794 break;
10795 case BWN_LED_EVENT_POLL:
10796 rate = 0;
10797 break;
10798 default:
10799 panic("unknown LED event %d\n", event);
10800 break;
10801 }
10802 bwn_led_blink_start(mac, bwn_led_duration[rate].on_dur,
10803 bwn_led_duration[rate].off_dur);
10757 switch (event) {
10758 case BWN_LED_EVENT_RX:
10759 rate = sc->sc_rx_rate;
10760 break;
10761 case BWN_LED_EVENT_TX:
10762 rate = sc->sc_tx_rate;
10763 break;
10764 case BWN_LED_EVENT_POLL:
10765 rate = 0;
10766 break;
10767 default:
10768 panic("unknown LED event %d\n", event);
10769 break;
10770 }
10771 bwn_led_blink_start(mac, bwn_led_duration[rate].on_dur,
10772 bwn_led_duration[rate].off_dur);
10804}
10805
10806static void
10807bwn_led_blink_start(struct bwn_mac *mac, int on_dur, int off_dur)
10808{
10809 struct bwn_softc *sc = mac->mac_sc;
10773}
10774
10775static void
10776bwn_led_blink_start(struct bwn_mac *mac, int on_dur, int off_dur)
10777{
10778 struct bwn_softc *sc = mac->mac_sc;
10810 struct bwn_led *led = sc->sc_blink_led;
10811 uint16_t val;
10779 struct bwn_led *led = sc->sc_blink_led;
10780 uint16_t val;
10812
10781
10813 val = BWN_READ_2(mac, BWN_GPIO_CONTROL);
10814 val = bwn_led_onoff(led, val, 1);
10815 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
10782 val = BWN_READ_2(mac, BWN_GPIO_CONTROL);
10783 val = bwn_led_onoff(led, val, 1);
10784 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
10816
10785
10817 if (led->led_flags & BWN_LED_F_SLOW) {
10818 BWN_LED_SLOWDOWN(on_dur);
10819 BWN_LED_SLOWDOWN(off_dur);
10820 }
10786 if (led->led_flags & BWN_LED_F_SLOW) {
10787 BWN_LED_SLOWDOWN(on_dur);
10788 BWN_LED_SLOWDOWN(off_dur);
10789 }
10821
10790
10822 sc->sc_led_blinking = 1;
10823 sc->sc_led_blink_offdur = off_dur;
10791 sc->sc_led_blinking = 1;
10792 sc->sc_led_blink_offdur = off_dur;
10824
10793
10825 callout_reset(&sc->sc_led_blink_ch, on_dur, bwn_led_blink_next, mac);
10794 callout_reset(&sc->sc_led_blink_ch, on_dur, bwn_led_blink_next, mac);
10826}
10827
10828static void
10829bwn_led_blink_next(void *arg)
10830{
10831 struct bwn_mac *mac = arg;
10795}
10796
10797static void
10798bwn_led_blink_next(void *arg)
10799{
10800 struct bwn_mac *mac = arg;
10832 struct bwn_softc *sc = mac->mac_sc;
10833 uint16_t val;
10801 struct bwn_softc *sc = mac->mac_sc;
10802 uint16_t val;
10834
10803
10835 val = BWN_READ_2(mac, BWN_GPIO_CONTROL);
10836 val = bwn_led_onoff(sc->sc_blink_led, val, 0);
10837 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
10804 val = BWN_READ_2(mac, BWN_GPIO_CONTROL);
10805 val = bwn_led_onoff(sc->sc_blink_led, val, 0);
10806 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
10838
10807
10839 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
10840 bwn_led_blink_end, mac);
10808 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
10809 bwn_led_blink_end, mac);
10841}
10842
10843static void
10844bwn_led_blink_end(void *arg)
10845{
10846 struct bwn_mac *mac = arg;
10810}
10811
10812static void
10813bwn_led_blink_end(void *arg)
10814{
10815 struct bwn_mac *mac = arg;
10847 struct bwn_softc *sc = mac->mac_sc;
10816 struct bwn_softc *sc = mac->mac_sc;
10848
10817
10849 sc->sc_led_blinking = 0;
10818 sc->sc_led_blinking = 0;
10850}
10851
10852static int
10853bwn_suspend(device_t dev)
10854{
10855 struct bwn_softc *sc = device_get_softc(dev);
10856
10857 bwn_stop(sc, 1);

--- 238 unchanged lines hidden (view full) ---

11096
11097static uint32_t
11098bwn_phy_lp_get_default_chan(struct bwn_mac *mac)
11099{
11100 struct bwn_softc *sc = mac->mac_sc;
11101 struct ifnet *ifp = sc->sc_ifp;
11102 struct ieee80211com *ic = ifp->if_l2com;
11103
10819}
10820
10821static int
10822bwn_suspend(device_t dev)
10823{
10824 struct bwn_softc *sc = device_get_softc(dev);
10825
10826 bwn_stop(sc, 1);

--- 238 unchanged lines hidden (view full) ---

11065
11066static uint32_t
11067bwn_phy_lp_get_default_chan(struct bwn_mac *mac)
11068{
11069 struct bwn_softc *sc = mac->mac_sc;
11070 struct ifnet *ifp = sc->sc_ifp;
11071 struct ieee80211com *ic = ifp->if_l2com;
11072
11104 device_printf(sc->sc_dev, "correct?\n");
11105
11106 return (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? 1 : 36);
11107}
11108
11109static void
11110bwn_phy_lp_set_antenna(struct bwn_mac *mac, int antenna)
11111{
11112 struct bwn_phy *phy = &mac->mac_phy;
11113 struct bwn_phy_lp *plp = &phy->phy_lp;

--- 17 unchanged lines hidden (view full) ---

11131
11132static void
11133bwn_phy_lp_readsprom(struct bwn_mac *mac)
11134{
11135 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
11136 struct bwn_softc *sc = mac->mac_sc;
11137 struct ifnet *ifp = sc->sc_ifp;
11138 struct ieee80211com *ic = ifp->if_l2com;
11073 return (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? 1 : 36);
11074}
11075
11076static void
11077bwn_phy_lp_set_antenna(struct bwn_mac *mac, int antenna)
11078{
11079 struct bwn_phy *phy = &mac->mac_phy;
11080 struct bwn_phy_lp *plp = &phy->phy_lp;

--- 17 unchanged lines hidden (view full) ---

11098
11099static void
11100bwn_phy_lp_readsprom(struct bwn_mac *mac)
11101{
11102 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
11103 struct bwn_softc *sc = mac->mac_sc;
11104 struct ifnet *ifp = sc->sc_ifp;
11105 struct ieee80211com *ic = ifp->if_l2com;
11139 struct siba_dev_softc *sd = mac->mac_sd;
11140 struct siba_softc *siba = sd->sd_bus;
11141 struct siba_sprom *sprom = &siba->siba_sprom;
11142
11106
11143 device_printf(sc->sc_dev, "XXX using %dghz\n",
11144 IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? 2 : 5);
11145
11146 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) {
11107 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) {
11147 plp->plp_txisoband_m = sprom->tri2g;
11148 plp->plp_bxarch = sprom->bxa2g;
11149 plp->plp_rxpwroffset = sprom->rxpo2g;
11150 plp->plp_rssivf = sprom->rssismf2g;
11151 plp->plp_rssivc = sprom->rssismc2g;
11152 plp->plp_rssigs = sprom->rssisav2g;
11108 plp->plp_txisoband_m = siba_sprom_get_tri2g(sc->sc_dev);
11109 plp->plp_bxarch = siba_sprom_get_bxa2g(sc->sc_dev);
11110 plp->plp_rxpwroffset = siba_sprom_get_rxpo2g(sc->sc_dev);
11111 plp->plp_rssivf = siba_sprom_get_rssismf2g(sc->sc_dev);
11112 plp->plp_rssivc = siba_sprom_get_rssismc2g(sc->sc_dev);
11113 plp->plp_rssigs = siba_sprom_get_rssisav2g(sc->sc_dev);
11153 return;
11154 }
11155
11114 return;
11115 }
11116
11156 plp->plp_txisoband_l = sprom->tri5gl;
11157 plp->plp_txisoband_m = sprom->tri5g;
11158 plp->plp_txisoband_h = sprom->tri5gh;
11159 plp->plp_bxarch = sprom->bxa5g;
11160 plp->plp_rxpwroffset = sprom->rxpo5g;
11161 plp->plp_rssivf = sprom->rssismf5g;
11162 plp->plp_rssivc = sprom->rssismc5g;
11163 plp->plp_rssigs = sprom->rssisav5g;
11117 plp->plp_txisoband_l = siba_sprom_get_tri5gl(sc->sc_dev);
11118 plp->plp_txisoband_m = siba_sprom_get_tri5g(sc->sc_dev);
11119 plp->plp_txisoband_h = siba_sprom_get_tri5gh(sc->sc_dev);
11120 plp->plp_bxarch = siba_sprom_get_bxa5g(sc->sc_dev);
11121 plp->plp_rxpwroffset = siba_sprom_get_rxpo5g(sc->sc_dev);
11122 plp->plp_rssivf = siba_sprom_get_rssismf5g(sc->sc_dev);
11123 plp->plp_rssivc = siba_sprom_get_rssismc5g(sc->sc_dev);
11124 plp->plp_rssigs = siba_sprom_get_rssisav5g(sc->sc_dev);
11164}
11165
11166static void
11167bwn_phy_lp_bbinit(struct bwn_mac *mac)
11168{
11169
11170 bwn_phy_lp_tblinit(mac);
11171 if (mac->mac_phy.rev >= 2)

--- 15 unchanged lines hidden (view full) ---

11187 IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? &gain_2ghz : &gain_5ghz);
11188 bwn_phy_lp_set_bbmult(mac, 150);
11189}
11190
11191static void
11192bwn_phy_lp_calib(struct bwn_mac *mac)
11193{
11194 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
11125}
11126
11127static void
11128bwn_phy_lp_bbinit(struct bwn_mac *mac)
11129{
11130
11131 bwn_phy_lp_tblinit(mac);
11132 if (mac->mac_phy.rev >= 2)

--- 15 unchanged lines hidden (view full) ---

11148 IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? &gain_2ghz : &gain_5ghz);
11149 bwn_phy_lp_set_bbmult(mac, 150);
11150}
11151
11152static void
11153bwn_phy_lp_calib(struct bwn_mac *mac)
11154{
11155 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
11195 struct siba_dev_softc *sd = mac->mac_sd;
11196 struct siba_softc *siba = sd->sd_bus;
11197 struct bwn_softc *sc = mac->mac_sc;
11198 struct ifnet *ifp = sc->sc_ifp;
11199 struct ieee80211com *ic = ifp->if_l2com;
11200 const struct bwn_rxcompco *rc = NULL;
11201 struct bwn_txgain ogain;
11202 int i, omode, oafeovr, orf, obbmult;
11203 uint8_t mode, fc = 0;
11204

--- 30 unchanged lines hidden (view full) ---

11235 bwn_phy_lp_set_txpctlmode(mac, omode);
11236 BWN_PHY_SETMASK(mac, BWN_PHY_RF_PWR_OVERRIDE, 0xff00, orf);
11237 }
11238 bwn_phy_lp_set_txpctlmode(mac, mode);
11239 if (mac->mac_phy.rev >= 2)
11240 bwn_phy_lp_digflt_restore(mac);
11241
11242 /* do RX IQ Calculation; assumes that noise is true. */
11156 struct bwn_softc *sc = mac->mac_sc;
11157 struct ifnet *ifp = sc->sc_ifp;
11158 struct ieee80211com *ic = ifp->if_l2com;
11159 const struct bwn_rxcompco *rc = NULL;
11160 struct bwn_txgain ogain;
11161 int i, omode, oafeovr, orf, obbmult;
11162 uint8_t mode, fc = 0;
11163

--- 30 unchanged lines hidden (view full) ---

11194 bwn_phy_lp_set_txpctlmode(mac, omode);
11195 BWN_PHY_SETMASK(mac, BWN_PHY_RF_PWR_OVERRIDE, 0xff00, orf);
11196 }
11197 bwn_phy_lp_set_txpctlmode(mac, mode);
11198 if (mac->mac_phy.rev >= 2)
11199 bwn_phy_lp_digflt_restore(mac);
11200
11201 /* do RX IQ Calculation; assumes that noise is true. */
11243 if (siba->siba_chipid == 0x5354) {
11202 if (siba_get_chipid(sc->sc_dev) == 0x5354) {
11244 for (i = 0; i < N(bwn_rxcompco_5354); i++) {
11245 if (bwn_rxcompco_5354[i].rc_chan == plp->plp_chan)
11246 rc = &bwn_rxcompco_5354[i];
11247 }
11248 } else if (mac->mac_phy.rev >= 2)
11249 rc = &bwn_rxcompco_r2;
11250 else {
11251 for (i = 0; i < N(bwn_rxcompco_r12); i++) {

--- 49 unchanged lines hidden (view full) ---

11301fail:
11302 bwn_mac_enable(mac);
11303}
11304
11305static void
11306bwn_phy_lp_switch_analog(struct bwn_mac *mac, int on)
11307{
11308
11203 for (i = 0; i < N(bwn_rxcompco_5354); i++) {
11204 if (bwn_rxcompco_5354[i].rc_chan == plp->plp_chan)
11205 rc = &bwn_rxcompco_5354[i];
11206 }
11207 } else if (mac->mac_phy.rev >= 2)
11208 rc = &bwn_rxcompco_r2;
11209 else {
11210 for (i = 0; i < N(bwn_rxcompco_r12); i++) {

--- 49 unchanged lines hidden (view full) ---

11260fail:
11261 bwn_mac_enable(mac);
11262}
11263
11264static void
11265bwn_phy_lp_switch_analog(struct bwn_mac *mac, int on)
11266{
11267
11309 if (on) {
11310 BWN_PHY_MASK(mac, BWN_PHY_AFE_CTL_OVR, 0xfff8);
11311 return;
11312 }
11268 if (on) {
11269 BWN_PHY_MASK(mac, BWN_PHY_AFE_CTL_OVR, 0xfff8);
11270 return;
11271 }
11313
11272
11314 BWN_PHY_SET(mac, BWN_PHY_AFE_CTL_OVRVAL, 0x0007);
11315 BWN_PHY_SET(mac, BWN_PHY_AFE_CTL_OVR, 0x0007);
11273 BWN_PHY_SET(mac, BWN_PHY_AFE_CTL_OVRVAL, 0x0007);
11274 BWN_PHY_SET(mac, BWN_PHY_AFE_CTL_OVR, 0x0007);
11316}
11317
11318static int
11319bwn_phy_lp_b2063_switch_channel(struct bwn_mac *mac, uint8_t chan)
11320{
11275}
11276
11277static int
11278bwn_phy_lp_b2063_switch_channel(struct bwn_mac *mac, uint8_t chan)
11279{
11321 struct siba_dev_softc *sd = mac->mac_sd;
11322 struct siba_softc *siba = sd->sd_bus;
11323 static const struct bwn_b206x_chan *bc = NULL;
11280 static const struct bwn_b206x_chan *bc = NULL;
11281 struct bwn_softc *sc = mac->mac_sc;
11324 uint32_t count, freqref, freqvco, freqxtal, val[3], timeout, timeoutref,
11325 tmp[6];
11326 uint16_t old, scale, tmp16;
11327 int i, div;
11328
11329 for (i = 0; i < N(bwn_b2063_chantable); i++) {
11330 if (bwn_b2063_chantable[i].bc_chan == chan) {
11331 bc = &bwn_b2063_chantable[i];

--- 14 unchanged lines hidden (view full) ---

11346 BWN_RF_WRITE(mac, BWN_B2063_A_RX_PS6, bc->bc_data[8]);
11347 BWN_RF_WRITE(mac, BWN_B2063_TX_RF_CTL2, bc->bc_data[9]);
11348 BWN_RF_WRITE(mac, BWN_B2063_TX_RF_CTL5, bc->bc_data[10]);
11349 BWN_RF_WRITE(mac, BWN_B2063_PA_CTL11, bc->bc_data[11]);
11350
11351 old = BWN_RF_READ(mac, BWN_B2063_COM15);
11352 BWN_RF_SET(mac, BWN_B2063_COM15, 0x1e);
11353
11282 uint32_t count, freqref, freqvco, freqxtal, val[3], timeout, timeoutref,
11283 tmp[6];
11284 uint16_t old, scale, tmp16;
11285 int i, div;
11286
11287 for (i = 0; i < N(bwn_b2063_chantable); i++) {
11288 if (bwn_b2063_chantable[i].bc_chan == chan) {
11289 bc = &bwn_b2063_chantable[i];

--- 14 unchanged lines hidden (view full) ---

11304 BWN_RF_WRITE(mac, BWN_B2063_A_RX_PS6, bc->bc_data[8]);
11305 BWN_RF_WRITE(mac, BWN_B2063_TX_RF_CTL2, bc->bc_data[9]);
11306 BWN_RF_WRITE(mac, BWN_B2063_TX_RF_CTL5, bc->bc_data[10]);
11307 BWN_RF_WRITE(mac, BWN_B2063_PA_CTL11, bc->bc_data[11]);
11308
11309 old = BWN_RF_READ(mac, BWN_B2063_COM15);
11310 BWN_RF_SET(mac, BWN_B2063_COM15, 0x1e);
11311
11354 freqxtal = siba->siba_cc.scc_pmu.freq * 1000;
11312 freqxtal = siba_get_cc_pmufreq(sc->sc_dev) * 1000;
11355 freqvco = bc->bc_freq << ((bc->bc_freq > 4000) ? 1 : 2);
11356 freqref = freqxtal * 3;
11357 div = (freqxtal <= 26000000 ? 1 : 2);
11358 timeout = ((((8 * freqxtal) / (div * 5000000)) + 1) >> 1) - 1;
11359 timeoutref = ((((8 * freqxtal) / (div * (timeout + 1))) +
11360 999999) / 1000000) + 1;
11361
11362 BWN_RF_WRITE(mac, BWN_B2063_JTAG_VCO_CALIB3, 0x2);

--- 81 unchanged lines hidden (view full) ---

11444
11445 BWN_RF_WRITE(mac, BWN_B2063_COM15, old);
11446 return (0);
11447}
11448
11449static int
11450bwn_phy_lp_b2062_switch_channel(struct bwn_mac *mac, uint8_t chan)
11451{
11313 freqvco = bc->bc_freq << ((bc->bc_freq > 4000) ? 1 : 2);
11314 freqref = freqxtal * 3;
11315 div = (freqxtal <= 26000000 ? 1 : 2);
11316 timeout = ((((8 * freqxtal) / (div * 5000000)) + 1) >> 1) - 1;
11317 timeoutref = ((((8 * freqxtal) / (div * (timeout + 1))) +
11318 999999) / 1000000) + 1;
11319
11320 BWN_RF_WRITE(mac, BWN_B2063_JTAG_VCO_CALIB3, 0x2);

--- 81 unchanged lines hidden (view full) ---

11402
11403 BWN_RF_WRITE(mac, BWN_B2063_COM15, old);
11404 return (0);
11405}
11406
11407static int
11408bwn_phy_lp_b2062_switch_channel(struct bwn_mac *mac, uint8_t chan)
11409{
11410 struct bwn_softc *sc = mac->mac_sc;
11452 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
11411 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
11453 struct siba_dev_softc *sd = mac->mac_sd;
11454 struct siba_softc *siba = sd->sd_bus;
11455 const struct bwn_b206x_chan *bc = NULL;
11412 const struct bwn_b206x_chan *bc = NULL;
11456 uint32_t freqxtal = siba->siba_cc.scc_pmu.freq * 1000;
11413 uint32_t freqxtal = siba_get_cc_pmufreq(sc->sc_dev) * 1000;
11457 uint32_t tmp[9];
11458 int i;
11459
11460 for (i = 0; i < N(bwn_b2062_chantable); i++) {
11461 if (bwn_b2062_chantable[i].bc_chan == chan) {
11462 bc = &bwn_b2062_chantable[i];
11463 break;
11464 }

--- 345 unchanged lines hidden (view full) ---

11810 uint16_t mask;
11811 uint16_t set;
11812};
11813
11814static void
11815bwn_phy_lp_bbinit_r2(struct bwn_mac *mac)
11816{
11817 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
11414 uint32_t tmp[9];
11415 int i;
11416
11417 for (i = 0; i < N(bwn_b2062_chantable); i++) {
11418 if (bwn_b2062_chantable[i].bc_chan == chan) {
11419 bc = &bwn_b2062_chantable[i];
11420 break;
11421 }

--- 345 unchanged lines hidden (view full) ---

11767 uint16_t mask;
11768 uint16_t set;
11769};
11770
11771static void
11772bwn_phy_lp_bbinit_r2(struct bwn_mac *mac)
11773{
11774 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
11818 struct siba_dev_softc *sd = mac->mac_sd;
11819 struct siba_softc *siba = sd->sd_bus;
11820 struct bwn_softc *sc = mac->mac_sc;
11821 struct ifnet *ifp = sc->sc_ifp;
11822 struct ieee80211com *ic = ifp->if_l2com;
11823 static const struct bwn_wpair v1[] = {
11824 { BWN_PHY_AFE_DAC_CTL, 0x50 },
11825 { BWN_PHY_AFE_CTL, 0x8800 },
11826 { BWN_PHY_AFE_CTL_OVR, 0 },
11827 { BWN_PHY_AFE_CTL_OVRVAL, 0 },

--- 15 unchanged lines hidden (view full) ---

11843 { BWN_PHY_OFDM(0x100), 0xff00, 0x19 },
11844 { BWN_PHY_OFDM(0xff), 0x03ff, 0x3c00 },
11845 { BWN_PHY_OFDM(0xfe), 0xfc1f, 0x3e0 },
11846 { BWN_PHY_OFDM(0xff), 0xffe0, 0xc },
11847 { BWN_PHY_OFDM(0x100), 0x00ff, 0x1900 },
11848 { BWN_PHY_CLIPCTRTHRESH, 0x83ff, 0x5800 },
11849 { BWN_PHY_CLIPCTRTHRESH, 0xffe0, 0x12 },
11850 { BWN_PHY_GAINMISMATCH, 0x0fff, 0x9000 },
11775 struct bwn_softc *sc = mac->mac_sc;
11776 struct ifnet *ifp = sc->sc_ifp;
11777 struct ieee80211com *ic = ifp->if_l2com;
11778 static const struct bwn_wpair v1[] = {
11779 { BWN_PHY_AFE_DAC_CTL, 0x50 },
11780 { BWN_PHY_AFE_CTL, 0x8800 },
11781 { BWN_PHY_AFE_CTL_OVR, 0 },
11782 { BWN_PHY_AFE_CTL_OVRVAL, 0 },

--- 15 unchanged lines hidden (view full) ---

11798 { BWN_PHY_OFDM(0x100), 0xff00, 0x19 },
11799 { BWN_PHY_OFDM(0xff), 0x03ff, 0x3c00 },
11800 { BWN_PHY_OFDM(0xfe), 0xfc1f, 0x3e0 },
11801 { BWN_PHY_OFDM(0xff), 0xffe0, 0xc },
11802 { BWN_PHY_OFDM(0x100), 0x00ff, 0x1900 },
11803 { BWN_PHY_CLIPCTRTHRESH, 0x83ff, 0x5800 },
11804 { BWN_PHY_CLIPCTRTHRESH, 0xffe0, 0x12 },
11805 { BWN_PHY_GAINMISMATCH, 0x0fff, 0x9000 },
11851
11806
11852 };
11853 int i;
11854
11855 for (i = 0; i < N(v1); i++)
11856 BWN_PHY_WRITE(mac, v1[i].reg, v1[i].value);
11857 BWN_PHY_SET(mac, BWN_PHY_ADC_COMPENSATION_CTL, 0x10);
11858 for (i = 0; i < N(v2); i++)
11859 BWN_PHY_SETMASK(mac, v2[i].offset, v2[i].mask, v2[i].set);
11860
11861 BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x4000);
11862 BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x2000);
11863 BWN_PHY_SET(mac, BWN_PHY_OFDM(0x10a), 0x1);
11807 };
11808 int i;
11809
11810 for (i = 0; i < N(v1); i++)
11811 BWN_PHY_WRITE(mac, v1[i].reg, v1[i].value);
11812 BWN_PHY_SET(mac, BWN_PHY_ADC_COMPENSATION_CTL, 0x10);
11813 for (i = 0; i < N(v2); i++)
11814 BWN_PHY_SETMASK(mac, v2[i].offset, v2[i].mask, v2[i].set);
11815
11816 BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x4000);
11817 BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x2000);
11818 BWN_PHY_SET(mac, BWN_PHY_OFDM(0x10a), 0x1);
11864 if (siba->siba_board_rev >= 0x18) {
11819 if (siba_get_pci_revid(sc->sc_dev) >= 0x18) {
11865 bwn_tab_write(mac, BWN_TAB_4(17, 65), 0xec);
11866 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x10a), 0xff01, 0x14);
11867 } else {
11868 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x10a), 0xff01, 0x10);
11869 }
11870 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xdf), 0xff00, 0xf4);
11871 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xdf), 0x00ff, 0xf100);
11872 BWN_PHY_WRITE(mac, BWN_PHY_CLIPTHRESH, 0x48);
11873 BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0xff00, 0x46);
11874 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xe4), 0xff00, 0x10);
11875 BWN_PHY_SETMASK(mac, BWN_PHY_PWR_THRESH1, 0xfff0, 0x9);
11876 BWN_PHY_MASK(mac, BWN_PHY_GAINDIRECTMISMATCH, ~0xf);
11877 BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0x00ff, 0x5500);
11878 BWN_PHY_SETMASK(mac, BWN_PHY_CLIPCTRTHRESH, 0xfc1f, 0xa0);
11879 BWN_PHY_SETMASK(mac, BWN_PHY_GAINDIRECTMISMATCH, 0xe0ff, 0x300);
11880 BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0x00ff, 0x2a00);
11820 bwn_tab_write(mac, BWN_TAB_4(17, 65), 0xec);
11821 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x10a), 0xff01, 0x14);
11822 } else {
11823 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x10a), 0xff01, 0x10);
11824 }
11825 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xdf), 0xff00, 0xf4);
11826 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xdf), 0x00ff, 0xf100);
11827 BWN_PHY_WRITE(mac, BWN_PHY_CLIPTHRESH, 0x48);
11828 BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0xff00, 0x46);
11829 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xe4), 0xff00, 0x10);
11830 BWN_PHY_SETMASK(mac, BWN_PHY_PWR_THRESH1, 0xfff0, 0x9);
11831 BWN_PHY_MASK(mac, BWN_PHY_GAINDIRECTMISMATCH, ~0xf);
11832 BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0x00ff, 0x5500);
11833 BWN_PHY_SETMASK(mac, BWN_PHY_CLIPCTRTHRESH, 0xfc1f, 0xa0);
11834 BWN_PHY_SETMASK(mac, BWN_PHY_GAINDIRECTMISMATCH, 0xe0ff, 0x300);
11835 BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0x00ff, 0x2a00);
11881 if ((siba->siba_chipid == 0x4325) && (siba->siba_chiprev == 0)) {
11836 if ((siba_get_chipid(sc->sc_dev) == 0x4325) &&
11837 (siba_get_chiprev(sc->sc_dev) == 0)) {
11882 BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x2100);
11883 BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0xa);
11884 } else {
11885 BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x1e00);
11886 BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0xd);
11887 }
11888 for (i = 0; i < N(v3); i++)
11889 BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask, v3[i].set);
11838 BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x2100);
11839 BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0xa);
11840 } else {
11841 BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x1e00);
11842 BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0xd);
11843 }
11844 for (i = 0; i < N(v3); i++)
11845 BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask, v3[i].set);
11890 if ((siba->siba_chipid == 0x4325) && (siba->siba_chiprev == 0)) {
11846 if ((siba_get_chipid(sc->sc_dev) == 0x4325) &&
11847 (siba_get_chiprev(sc->sc_dev) == 0)) {
11891 bwn_tab_write(mac, BWN_TAB_2(0x08, 0x14), 0);
11892 bwn_tab_write(mac, BWN_TAB_2(0x08, 0x12), 0x40);
11893 }
11894
11895 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) {
11896 BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x40);
11897 BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xf0ff, 0xb00);
11898 BWN_PHY_SETMASK(mac, BWN_PHY_SYNCPEAKCNT, 0xfff8, 0x6);

--- 8 unchanged lines hidden (view full) ---

11907 BWN_PHY_SETMASK(mac, BWN_PHY_INPUT_PWRDB, 0xff00, plp->plp_rxpwroffset);
11908 BWN_PHY_SET(mac, BWN_PHY_RESET_CTL, 0x44);
11909 BWN_PHY_WRITE(mac, BWN_PHY_RESET_CTL, 0x80);
11910 BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_0, 0xa954);
11911 BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_1,
11912 0x2000 | ((uint16_t)plp->plp_rssigs << 10) |
11913 ((uint16_t)plp->plp_rssivc << 4) | plp->plp_rssivf);
11914
11848 bwn_tab_write(mac, BWN_TAB_2(0x08, 0x14), 0);
11849 bwn_tab_write(mac, BWN_TAB_2(0x08, 0x12), 0x40);
11850 }
11851
11852 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) {
11853 BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x40);
11854 BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xf0ff, 0xb00);
11855 BWN_PHY_SETMASK(mac, BWN_PHY_SYNCPEAKCNT, 0xfff8, 0x6);

--- 8 unchanged lines hidden (view full) ---

11864 BWN_PHY_SETMASK(mac, BWN_PHY_INPUT_PWRDB, 0xff00, plp->plp_rxpwroffset);
11865 BWN_PHY_SET(mac, BWN_PHY_RESET_CTL, 0x44);
11866 BWN_PHY_WRITE(mac, BWN_PHY_RESET_CTL, 0x80);
11867 BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_0, 0xa954);
11868 BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_1,
11869 0x2000 | ((uint16_t)plp->plp_rssigs << 10) |
11870 ((uint16_t)plp->plp_rssivc << 4) | plp->plp_rssivf);
11871
11915 if ((siba->siba_chipid == 0x4325) && (siba->siba_chiprev == 0)) {
11872 if ((siba_get_chipid(sc->sc_dev) == 0x4325) &&
11873 (siba_get_chiprev(sc->sc_dev) == 0)) {
11916 BWN_PHY_SET(mac, BWN_PHY_AFE_ADC_CTL_0, 0x1c);
11917 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_CTL, 0x00ff, 0x8800);
11918 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_ADC_CTL_1, 0xfc3c, 0x0400);
11919 }
11920
11921 bwn_phy_lp_digflt_save(mac);
11922}
11923
11924static void
11925bwn_phy_lp_bbinit_r01(struct bwn_mac *mac)
11926{
11927 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
11874 BWN_PHY_SET(mac, BWN_PHY_AFE_ADC_CTL_0, 0x1c);
11875 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_CTL, 0x00ff, 0x8800);
11876 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_ADC_CTL_1, 0xfc3c, 0x0400);
11877 }
11878
11879 bwn_phy_lp_digflt_save(mac);
11880}
11881
11882static void
11883bwn_phy_lp_bbinit_r01(struct bwn_mac *mac)
11884{
11885 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
11928 struct siba_dev_softc *sd = mac->mac_sd;
11929 struct siba_softc *siba = sd->sd_bus;
11930 struct bwn_softc *sc = mac->mac_sc;
11931 struct ifnet *ifp = sc->sc_ifp;
11932 struct ieee80211com *ic = ifp->if_l2com;
11933 static const struct bwn_smpair v1[] = {
11934 { BWN_PHY_CLIPCTRTHRESH, 0xffe0, 0x0005 },
11935 { BWN_PHY_CLIPCTRTHRESH, 0xfc1f, 0x0180 },
11936 { BWN_PHY_CLIPCTRTHRESH, 0x83ff, 0x3c00 },
11937 { BWN_PHY_GAINDIRECTMISMATCH, 0xfff0, 0x0005 },

--- 66 unchanged lines hidden (view full) ---

12004 BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0x00ff, 0x2400);
12005 BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x2100);
12006 BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0x0006);
12007 BWN_PHY_MASK(mac, BWN_PHY_RX_RADIO_CTL, 0xfffe);
12008 for (i = 0; i < N(v1); i++)
12009 BWN_PHY_SETMASK(mac, v1[i].offset, v1[i].mask, v1[i].set);
12010 BWN_PHY_SETMASK(mac, BWN_PHY_INPUT_PWRDB,
12011 0xff00, plp->plp_rxpwroffset);
11886 struct bwn_softc *sc = mac->mac_sc;
11887 struct ifnet *ifp = sc->sc_ifp;
11888 struct ieee80211com *ic = ifp->if_l2com;
11889 static const struct bwn_smpair v1[] = {
11890 { BWN_PHY_CLIPCTRTHRESH, 0xffe0, 0x0005 },
11891 { BWN_PHY_CLIPCTRTHRESH, 0xfc1f, 0x0180 },
11892 { BWN_PHY_CLIPCTRTHRESH, 0x83ff, 0x3c00 },
11893 { BWN_PHY_GAINDIRECTMISMATCH, 0xfff0, 0x0005 },

--- 66 unchanged lines hidden (view full) ---

11960 BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0x00ff, 0x2400);
11961 BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x2100);
11962 BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0x0006);
11963 BWN_PHY_MASK(mac, BWN_PHY_RX_RADIO_CTL, 0xfffe);
11964 for (i = 0; i < N(v1); i++)
11965 BWN_PHY_SETMASK(mac, v1[i].offset, v1[i].mask, v1[i].set);
11966 BWN_PHY_SETMASK(mac, BWN_PHY_INPUT_PWRDB,
11967 0xff00, plp->plp_rxpwroffset);
12012 if ((siba->siba_sprom.bf_lo & BWN_BFL_FEM) &&
11968 if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM) &&
12013 ((IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) ||
11969 ((IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) ||
12014 (siba->siba_sprom.bf_hi & BWN_BFH_LDO_PAREF))) {
12015 siba_cc_pmu_set_ldovolt(&siba->siba_cc, SIBA_LDO_PAREF, 0x28);
12016 siba_cc_pmu_set_ldoparef(&siba->siba_cc, 1);
11970 (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_LDO_PAREF))) {
11971 siba_cc_pmu_set_ldovolt(sc->sc_dev, SIBA_LDO_PAREF, 0x28);
11972 siba_cc_pmu_set_ldoparef(sc->sc_dev, 1);
12017 if (mac->mac_phy.rev == 0)
12018 BWN_PHY_SETMASK(mac, BWN_PHY_LP_RF_SIGNAL_LUT,
12019 0xffcf, 0x0010);
12020 bwn_tab_write(mac, BWN_TAB_2(11, 7), 60);
12021 } else {
11973 if (mac->mac_phy.rev == 0)
11974 BWN_PHY_SETMASK(mac, BWN_PHY_LP_RF_SIGNAL_LUT,
11975 0xffcf, 0x0010);
11976 bwn_tab_write(mac, BWN_TAB_2(11, 7), 60);
11977 } else {
12022 siba_cc_pmu_set_ldoparef(&siba->siba_cc, 0);
11978 siba_cc_pmu_set_ldoparef(sc->sc_dev, 0);
12023 BWN_PHY_SETMASK(mac, BWN_PHY_LP_RF_SIGNAL_LUT, 0xffcf, 0x0020);
12024 bwn_tab_write(mac, BWN_TAB_2(11, 7), 100);
12025 }
12026 tmp = plp->plp_rssivf | plp->plp_rssivc << 4 | 0xa000;
12027 BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_0, tmp);
11979 BWN_PHY_SETMASK(mac, BWN_PHY_LP_RF_SIGNAL_LUT, 0xffcf, 0x0020);
11980 bwn_tab_write(mac, BWN_TAB_2(11, 7), 100);
11981 }
11982 tmp = plp->plp_rssivf | plp->plp_rssivc << 4 | 0xa000;
11983 BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_0, tmp);
12028 if (siba->siba_sprom.bf_hi & BWN_BFH_RSSIINV)
11984 if (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_RSSIINV)
12029 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_RSSI_CTL_1, 0xf000, 0x0aaa);
12030 else
12031 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_RSSI_CTL_1, 0xf000, 0x02aa);
12032 bwn_tab_write(mac, BWN_TAB_2(11, 1), 24);
12033 BWN_PHY_SETMASK(mac, BWN_PHY_RX_RADIO_CTL,
12034 0xfff9, (plp->plp_bxarch << 1));
12035 if (mac->mac_phy.rev == 1 &&
11985 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_RSSI_CTL_1, 0xf000, 0x0aaa);
11986 else
11987 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_RSSI_CTL_1, 0xf000, 0x02aa);
11988 bwn_tab_write(mac, BWN_TAB_2(11, 1), 24);
11989 BWN_PHY_SETMASK(mac, BWN_PHY_RX_RADIO_CTL,
11990 0xfff9, (plp->plp_bxarch << 1));
11991 if (mac->mac_phy.rev == 1 &&
12036 (siba->siba_sprom.bf_hi & BWN_BFH_FEM_BT)) {
11992 (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_FEM_BT)) {
12037 for (i = 0; i < N(v2); i++)
12038 BWN_PHY_SETMASK(mac, v2[i].offset, v2[i].mask,
12039 v2[i].set);
12040 } else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ||
11993 for (i = 0; i < N(v2); i++)
11994 BWN_PHY_SETMASK(mac, v2[i].offset, v2[i].mask,
11995 v2[i].set);
11996 } else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ||
12041 (siba->siba_board_type == 0x048a) || ((mac->mac_phy.rev == 0) &&
12042 (siba->siba_sprom.bf_lo & BWN_BFL_FEM))) {
11997 (siba_get_pci_subdevice(sc->sc_dev) == 0x048a) ||
11998 ((mac->mac_phy.rev == 0) &&
11999 (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM))) {
12043 for (i = 0; i < N(v3); i++)
12044 BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask,
12045 v3[i].set);
12046 } else if (mac->mac_phy.rev == 1 ||
12000 for (i = 0; i < N(v3); i++)
12001 BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask,
12002 v3[i].set);
12003 } else if (mac->mac_phy.rev == 1 ||
12047 (siba->siba_sprom.bf_lo & BWN_BFL_FEM)) {
12004 (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM)) {
12048 for (i = 0; i < N(v4); i++)
12049 BWN_PHY_SETMASK(mac, v4[i].offset, v4[i].mask,
12050 v4[i].set);
12051 } else {
12052 for (i = 0; i < N(v5); i++)
12053 BWN_PHY_SETMASK(mac, v5[i].offset, v5[i].mask,
12054 v5[i].set);
12055 }
12056 if (mac->mac_phy.rev == 1 &&
12005 for (i = 0; i < N(v4); i++)
12006 BWN_PHY_SETMASK(mac, v4[i].offset, v4[i].mask,
12007 v4[i].set);
12008 } else {
12009 for (i = 0; i < N(v5); i++)
12010 BWN_PHY_SETMASK(mac, v5[i].offset, v5[i].mask,
12011 v5[i].set);
12012 }
12013 if (mac->mac_phy.rev == 1 &&
12057 (siba->siba_sprom.bf_hi & BWN_BFH_LDO_PAREF)) {
12014 (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_LDO_PAREF)) {
12058 BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_5, BWN_PHY_TR_LOOKUP_1);
12059 BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_6, BWN_PHY_TR_LOOKUP_2);
12060 BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_7, BWN_PHY_TR_LOOKUP_3);
12061 BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_8, BWN_PHY_TR_LOOKUP_4);
12062 }
12015 BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_5, BWN_PHY_TR_LOOKUP_1);
12016 BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_6, BWN_PHY_TR_LOOKUP_2);
12017 BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_7, BWN_PHY_TR_LOOKUP_3);
12018 BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_8, BWN_PHY_TR_LOOKUP_4);
12019 }
12063 if ((siba->siba_sprom.bf_hi & BWN_BFH_FEM_BT) &&
12064 (siba->siba_chipid == 0x5354) &&
12065 (siba->siba_chippkg == SIBA_CHIPPACK_BCM4712S)) {
12020 if ((siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_FEM_BT) &&
12021 (siba_get_chipid(sc->sc_dev) == 0x5354) &&
12022 (siba_get_chippkg(sc->sc_dev) == SIBA_CHIPPACK_BCM4712S)) {
12066 BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x0006);
12067 BWN_PHY_WRITE(mac, BWN_PHY_GPIO_SELECT, 0x0005);
12068 BWN_PHY_WRITE(mac, BWN_PHY_GPIO_OUTEN, 0xffff);
12069 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_PR45960W);
12070 }
12071 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) {
12072 BWN_PHY_SET(mac, BWN_PHY_LP_PHY_CTL, 0x8000);
12073 BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x0040);

--- 33 unchanged lines hidden (view full) ---

12107{
12108#define CALC_CTL7(freq, div) \
12109 (((800000000 * (div) + (freq)) / (2 * (freq)) - 8) & 0xff)
12110#define CALC_CTL18(freq, div) \
12111 ((((100 * (freq) + 16000000 * (div)) / (32000000 * (div))) - 1) & 0xff)
12112#define CALC_CTL19(freq, div) \
12113 ((((2 * (freq) + 1000000 * (div)) / (2000000 * (div))) - 1) & 0xff)
12114 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
12023 BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x0006);
12024 BWN_PHY_WRITE(mac, BWN_PHY_GPIO_SELECT, 0x0005);
12025 BWN_PHY_WRITE(mac, BWN_PHY_GPIO_OUTEN, 0xffff);
12026 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_PR45960W);
12027 }
12028 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) {
12029 BWN_PHY_SET(mac, BWN_PHY_LP_PHY_CTL, 0x8000);
12030 BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x0040);

--- 33 unchanged lines hidden (view full) ---

12064{
12065#define CALC_CTL7(freq, div) \
12066 (((800000000 * (div) + (freq)) / (2 * (freq)) - 8) & 0xff)
12067#define CALC_CTL18(freq, div) \
12068 ((((100 * (freq) + 16000000 * (div)) / (32000000 * (div))) - 1) & 0xff)
12069#define CALC_CTL19(freq, div) \
12070 ((((2 * (freq) + 1000000 * (div)) / (2000000 * (div))) - 1) & 0xff)
12071 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
12115 struct siba_dev_softc *sd = mac->mac_sd;
12116 struct siba_softc *siba = sd->sd_bus;
12117 struct bwn_softc *sc = mac->mac_sc;
12118 struct ifnet *ifp = sc->sc_ifp;
12119 struct ieee80211com *ic = ifp->if_l2com;
12120 static const struct bwn_b2062_freq freqdata_tab[] = {
12121 { 12000, { 6, 6, 6, 6, 10, 6 } },
12122 { 13000, { 4, 4, 4, 4, 11, 7 } },
12123 { 14400, { 3, 3, 3, 3, 12, 7 } },
12124 { 16200, { 3, 3, 3, 3, 13, 8 } },

--- 21 unchanged lines hidden (view full) ---

12146 if (mac->mac_phy.rev > 0)
12147 BWN_RF_WRITE(mac, BWN_B2062_S_BG_CTL1,
12148 (BWN_RF_READ(mac, BWN_B2062_N_COM2) >> 1) | 0x80);
12149 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
12150 BWN_RF_SET(mac, BWN_B2062_N_TSSI_CTL0, 0x1);
12151 else
12152 BWN_RF_MASK(mac, BWN_B2062_N_TSSI_CTL0, ~0x1);
12153
12072 struct bwn_softc *sc = mac->mac_sc;
12073 struct ifnet *ifp = sc->sc_ifp;
12074 struct ieee80211com *ic = ifp->if_l2com;
12075 static const struct bwn_b2062_freq freqdata_tab[] = {
12076 { 12000, { 6, 6, 6, 6, 10, 6 } },
12077 { 13000, { 4, 4, 4, 4, 11, 7 } },
12078 { 14400, { 3, 3, 3, 3, 12, 7 } },
12079 { 16200, { 3, 3, 3, 3, 13, 8 } },

--- 21 unchanged lines hidden (view full) ---

12101 if (mac->mac_phy.rev > 0)
12102 BWN_RF_WRITE(mac, BWN_B2062_S_BG_CTL1,
12103 (BWN_RF_READ(mac, BWN_B2062_N_COM2) >> 1) | 0x80);
12104 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
12105 BWN_RF_SET(mac, BWN_B2062_N_TSSI_CTL0, 0x1);
12106 else
12107 BWN_RF_MASK(mac, BWN_B2062_N_TSSI_CTL0, ~0x1);
12108
12154 KASSERT(siba->siba_cc.scc_caps & SIBA_CC_CAPS_PMU,
12109 KASSERT(siba_get_cc_caps(sc->sc_dev) & SIBA_CC_CAPS_PMU,
12155 ("%s:%d: fail", __func__, __LINE__));
12110 ("%s:%d: fail", __func__, __LINE__));
12156 xtalfreq = siba->siba_cc.scc_pmu.freq * 1000;
12111 xtalfreq = siba_get_cc_pmufreq(sc->sc_dev) * 1000;
12157 KASSERT(xtalfreq != 0, ("%s:%d: fail", __func__, __LINE__));
12158
12159 if (xtalfreq <= 30000000) {
12160 plp->plp_div = 1;
12161 BWN_RF_MASK(mac, BWN_B2062_S_RFPLLCTL1, 0xfffb);
12162 } else {
12163 plp->plp_div = 2;
12164 BWN_RF_SET(mac, BWN_B2062_S_RFPLLCTL1, 0x4);

--- 47 unchanged lines hidden (view full) ---

12212 BWN_RF_WRITE(mac, BWN_B2063_PA_SP3, 0x20);
12213 BWN_RF_WRITE(mac, BWN_B2063_PA_SP2, 0x20);
12214 }
12215}
12216
12217static void
12218bwn_phy_lp_rxcal_r2(struct bwn_mac *mac)
12219{
12112 KASSERT(xtalfreq != 0, ("%s:%d: fail", __func__, __LINE__));
12113
12114 if (xtalfreq <= 30000000) {
12115 plp->plp_div = 1;
12116 BWN_RF_MASK(mac, BWN_B2062_S_RFPLLCTL1, 0xfffb);
12117 } else {
12118 plp->plp_div = 2;
12119 BWN_RF_SET(mac, BWN_B2062_S_RFPLLCTL1, 0x4);

--- 47 unchanged lines hidden (view full) ---

12167 BWN_RF_WRITE(mac, BWN_B2063_PA_SP3, 0x20);
12168 BWN_RF_WRITE(mac, BWN_B2063_PA_SP2, 0x20);
12169 }
12170}
12171
12172static void
12173bwn_phy_lp_rxcal_r2(struct bwn_mac *mac)
12174{
12220 struct siba_dev_softc *sd = mac->mac_sd;
12221 struct siba_softc *siba = sd->sd_bus;
12175 struct bwn_softc *sc = mac->mac_sc;
12222 static const struct bwn_wpair v1[] = {
12223 { BWN_B2063_RX_BB_SP8, 0x0 },
12224 { BWN_B2063_RC_CALIB_CTL1, 0x7e },
12225 { BWN_B2063_RC_CALIB_CTL1, 0x7c },
12226 { BWN_B2063_RC_CALIB_CTL2, 0x15 },
12227 { BWN_B2063_RC_CALIB_CTL3, 0x70 },
12228 { BWN_B2063_RC_CALIB_CTL4, 0x52 },
12229 { BWN_B2063_RC_CALIB_CTL5, 0x1 },
12230 { BWN_B2063_RC_CALIB_CTL1, 0x7d }
12231 };
12232 static const struct bwn_wpair v2[] = {
12233 { BWN_B2063_TX_BB_SP3, 0x0 },
12234 { BWN_B2063_RC_CALIB_CTL1, 0x7e },
12235 { BWN_B2063_RC_CALIB_CTL1, 0x7c },
12236 { BWN_B2063_RC_CALIB_CTL2, 0x55 },
12237 { BWN_B2063_RC_CALIB_CTL3, 0x76 }
12238 };
12176 static const struct bwn_wpair v1[] = {
12177 { BWN_B2063_RX_BB_SP8, 0x0 },
12178 { BWN_B2063_RC_CALIB_CTL1, 0x7e },
12179 { BWN_B2063_RC_CALIB_CTL1, 0x7c },
12180 { BWN_B2063_RC_CALIB_CTL2, 0x15 },
12181 { BWN_B2063_RC_CALIB_CTL3, 0x70 },
12182 { BWN_B2063_RC_CALIB_CTL4, 0x52 },
12183 { BWN_B2063_RC_CALIB_CTL5, 0x1 },
12184 { BWN_B2063_RC_CALIB_CTL1, 0x7d }
12185 };
12186 static const struct bwn_wpair v2[] = {
12187 { BWN_B2063_TX_BB_SP3, 0x0 },
12188 { BWN_B2063_RC_CALIB_CTL1, 0x7e },
12189 { BWN_B2063_RC_CALIB_CTL1, 0x7c },
12190 { BWN_B2063_RC_CALIB_CTL2, 0x55 },
12191 { BWN_B2063_RC_CALIB_CTL3, 0x76 }
12192 };
12239 uint32_t freqxtal = siba->siba_cc.scc_pmu.freq * 1000;
12193 uint32_t freqxtal = siba_get_cc_pmufreq(sc->sc_dev) * 1000;
12240 int i;
12241 uint8_t tmp;
12242
12243 tmp = BWN_RF_READ(mac, BWN_B2063_RX_BB_SP8) & 0xff;
12244
12245 for (i = 0; i < 2; i++)
12246 BWN_RF_WRITE(mac, v1[i].reg, v1[i].value);
12247 BWN_RF_MASK(mac, BWN_B2063_PLL_SP1, 0xf7);

--- 182 unchanged lines hidden (view full) ---

12430 if (r << 1 >= div)
12431 q++;
12432 return (q);
12433}
12434
12435static void
12436bwn_phy_lp_b2062_reset_pllbias(struct bwn_mac *mac)
12437{
12194 int i;
12195 uint8_t tmp;
12196
12197 tmp = BWN_RF_READ(mac, BWN_B2063_RX_BB_SP8) & 0xff;
12198
12199 for (i = 0; i < 2; i++)
12200 BWN_RF_WRITE(mac, v1[i].reg, v1[i].value);
12201 BWN_RF_MASK(mac, BWN_B2063_PLL_SP1, 0xf7);

--- 182 unchanged lines hidden (view full) ---

12384 if (r << 1 >= div)
12385 q++;
12386 return (q);
12387}
12388
12389static void
12390bwn_phy_lp_b2062_reset_pllbias(struct bwn_mac *mac)
12391{
12438 struct siba_dev_softc *sd = mac->mac_sd;
12439 struct siba_softc *siba = sd->sd_bus;
12392 struct bwn_softc *sc = mac->mac_sc;
12440
12441 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 0xff);
12442 DELAY(20);
12393
12394 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 0xff);
12395 DELAY(20);
12443 if (siba->siba_chipid == 0x5354) {
12396 if (siba_get_chipid(sc->sc_dev) == 0x5354) {
12444 BWN_RF_WRITE(mac, BWN_B2062_N_COM1, 4);
12445 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 4);
12446 } else {
12447 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 0);
12448 }
12449 DELAY(5);
12450}
12451

--- 689 unchanged lines hidden (view full) ---

13141 }
13142 bwn_tab_write_multi(mac, BWN_TAB_2(15, 0), N(gaindelta), gaindelta);
13143 bwn_tab_write_multi(mac, BWN_TAB_4(10, 0), N(txpwrctl), txpwrctl);
13144}
13145
13146static void
13147bwn_phy_lp_tblinit_r2(struct bwn_mac *mac)
13148{
12397 BWN_RF_WRITE(mac, BWN_B2062_N_COM1, 4);
12398 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 4);
12399 } else {
12400 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 0);
12401 }
12402 DELAY(5);
12403}
12404

--- 689 unchanged lines hidden (view full) ---

13094 }
13095 bwn_tab_write_multi(mac, BWN_TAB_2(15, 0), N(gaindelta), gaindelta);
13096 bwn_tab_write_multi(mac, BWN_TAB_4(10, 0), N(txpwrctl), txpwrctl);
13097}
13098
13099static void
13100bwn_phy_lp_tblinit_r2(struct bwn_mac *mac)
13101{
13149 struct siba_dev_softc *sd = mac->mac_sd;
13150 struct siba_softc *siba = sd->sd_bus;
13102 struct bwn_softc *sc = mac->mac_sc;
13151 int i;
13152 static const uint16_t noisescale[] = {
13153 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4,
13154 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4,
13155 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4,
13156 0x00a4, 0x00a4, 0x0000, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4,
13157 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4,
13158 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4,

--- 191 unchanged lines hidden (view full) ---

13350 bwn_tab_write_multi(mac, BWN_TAB_2(18, 0), N(gain), gain);
13351 bwn_tab_write_multi(mac, BWN_TAB_1(6, 0), N(bwn_tab_pllfrac_tbl),
13352 bwn_tab_pllfrac_tbl);
13353 bwn_tab_write_multi(mac, BWN_TAB_2(0, 0), N(bwn_tabl_iqlocal_tbl),
13354 bwn_tabl_iqlocal_tbl);
13355 bwn_tab_write_multi(mac, BWN_TAB_4(9, 0), N(papdeps), papdeps);
13356 bwn_tab_write_multi(mac, BWN_TAB_4(10, 0), N(papdmult), papdmult);
13357
13103 int i;
13104 static const uint16_t noisescale[] = {
13105 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4,
13106 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4,
13107 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4,
13108 0x00a4, 0x00a4, 0x0000, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4,
13109 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4,
13110 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4,

--- 191 unchanged lines hidden (view full) ---

13302 bwn_tab_write_multi(mac, BWN_TAB_2(18, 0), N(gain), gain);
13303 bwn_tab_write_multi(mac, BWN_TAB_1(6, 0), N(bwn_tab_pllfrac_tbl),
13304 bwn_tab_pllfrac_tbl);
13305 bwn_tab_write_multi(mac, BWN_TAB_2(0, 0), N(bwn_tabl_iqlocal_tbl),
13306 bwn_tabl_iqlocal_tbl);
13307 bwn_tab_write_multi(mac, BWN_TAB_4(9, 0), N(papdeps), papdeps);
13308 bwn_tab_write_multi(mac, BWN_TAB_4(10, 0), N(papdmult), papdmult);
13309
13358 if ((siba->siba_chipid == 0x4325) && (siba->siba_chiprev == 0)) {
13310 if ((siba_get_chipid(sc->sc_dev) == 0x4325) &&
13311 (siba_get_chiprev(sc->sc_dev) == 0)) {
13359 bwn_tab_write_multi(mac, BWN_TAB_4(13, 0), N(gainidx_a0),
13360 gainidx_a0);
13361 bwn_tab_write_multi(mac, BWN_TAB_2(14, 0), N(auxgainidx_a0),
13362 auxgainidx_a0);
13363 bwn_tab_write_multi(mac, BWN_TAB_4(17, 0), N(gainval_a0),
13364 gainval_a0);
13365 bwn_tab_write_multi(mac, BWN_TAB_2(18, 0), N(gain_a0), gain_a0);
13366 }
13367}
13368
13369static void
13370bwn_phy_lp_tblinit_txgain(struct bwn_mac *mac)
13371{
13312 bwn_tab_write_multi(mac, BWN_TAB_4(13, 0), N(gainidx_a0),
13313 gainidx_a0);
13314 bwn_tab_write_multi(mac, BWN_TAB_2(14, 0), N(auxgainidx_a0),
13315 auxgainidx_a0);
13316 bwn_tab_write_multi(mac, BWN_TAB_4(17, 0), N(gainval_a0),
13317 gainval_a0);
13318 bwn_tab_write_multi(mac, BWN_TAB_2(18, 0), N(gain_a0), gain_a0);
13319 }
13320}
13321
13322static void
13323bwn_phy_lp_tblinit_txgain(struct bwn_mac *mac)
13324{
13372 struct siba_dev_softc *sd = mac->mac_sd;
13373 struct siba_softc *siba = sd->sd_bus;
13374 struct bwn_softc *sc = mac->mac_sc;
13375 struct ifnet *ifp = sc->sc_ifp;
13376 struct ieee80211com *ic = ifp->if_l2com;
13377 static struct bwn_txgain_entry txgain_r2[] = {
13378 { 255, 255, 203, 0, 152 }, { 255, 255, 203, 0, 147 },
13379 { 255, 255, 203, 0, 143 }, { 255, 255, 203, 0, 139 },
13380 { 255, 255, 203, 0, 135 }, { 255, 255, 203, 0, 131 },
13381 { 255, 255, 203, 0, 128 }, { 255, 255, 203, 0, 124 },

--- 588 unchanged lines hidden (view full) ---

13970 { 7, 11, 7, 0, 62 }, { 7, 11, 7, 0, 61 },
13971 { 7, 11, 7, 0, 59 }, { 7, 11, 7, 0, 57 },
13972 { 7, 11, 6, 0, 69 }, { 7, 11, 6, 0, 67 },
13973 { 7, 11, 6, 0, 65 }, { 7, 11, 6, 0, 63 },
13974 { 7, 11, 6, 0, 62 }, { 7, 11, 6, 0, 60 }
13975 };
13976
13977 if (mac->mac_phy.rev != 0 && mac->mac_phy.rev != 1) {
13325 struct bwn_softc *sc = mac->mac_sc;
13326 struct ifnet *ifp = sc->sc_ifp;
13327 struct ieee80211com *ic = ifp->if_l2com;
13328 static struct bwn_txgain_entry txgain_r2[] = {
13329 { 255, 255, 203, 0, 152 }, { 255, 255, 203, 0, 147 },
13330 { 255, 255, 203, 0, 143 }, { 255, 255, 203, 0, 139 },
13331 { 255, 255, 203, 0, 135 }, { 255, 255, 203, 0, 131 },
13332 { 255, 255, 203, 0, 128 }, { 255, 255, 203, 0, 124 },

--- 588 unchanged lines hidden (view full) ---

13921 { 7, 11, 7, 0, 62 }, { 7, 11, 7, 0, 61 },
13922 { 7, 11, 7, 0, 59 }, { 7, 11, 7, 0, 57 },
13923 { 7, 11, 6, 0, 69 }, { 7, 11, 6, 0, 67 },
13924 { 7, 11, 6, 0, 65 }, { 7, 11, 6, 0, 63 },
13925 { 7, 11, 6, 0, 62 }, { 7, 11, 6, 0, 60 }
13926 };
13927
13928 if (mac->mac_phy.rev != 0 && mac->mac_phy.rev != 1) {
13978 if (siba->siba_sprom.bf_hi & BWN_BFH_NOPA)
13929 if (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_NOPA)
13979 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r2);
13980 else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
13981 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128,
13982 txgain_2ghz_r2);
13983 else
13984 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128,
13985 txgain_5ghz_r2);
13986 return;
13987 }
13988
13989 if (mac->mac_phy.rev == 0) {
13930 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r2);
13931 else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
13932 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128,
13933 txgain_2ghz_r2);
13934 else
13935 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128,
13936 txgain_5ghz_r2);
13937 return;
13938 }
13939
13940 if (mac->mac_phy.rev == 0) {
13990 if ((siba->siba_sprom.bf_hi & BWN_BFH_NOPA) ||
13991 (siba->siba_sprom.bf_lo & BWN_BFL_HGPA))
13941 if ((siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_NOPA) ||
13942 (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_HGPA))
13992 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r0);
13993 else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
13994 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128,
13995 txgain_2ghz_r0);
13996 else
13997 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128,
13998 txgain_5ghz_r0);
13999 return;
14000 }
14001
13943 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r0);
13944 else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
13945 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128,
13946 txgain_2ghz_r0);
13947 else
13948 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128,
13949 txgain_5ghz_r0);
13950 return;
13951 }
13952
14002 if ((siba->siba_sprom.bf_hi & BWN_BFH_NOPA) ||
14003 (siba->siba_sprom.bf_lo & BWN_BFL_HGPA))
13953 if ((siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_NOPA) ||
13954 (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_HGPA))
14004 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r1);
14005 else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
14006 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_2ghz_r1);
14007 else
14008 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_5ghz_r1);
14009}
14010
14011static void

--- 323 unchanged lines hidden --- 		13955 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r1);
13956 else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
13957 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_2ghz_r1);
13958 else
13959 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_5ghz_r1);
13960}
13961
13962static void

--- 323 unchanged lines hidden ---