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if_ath.c (164598) if_ath.c (165185)
1/*-
2 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 21 unchanged lines hidden (view full) ---

30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 */
36
37#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 21 unchanged lines hidden (view full) ---

30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 */
36
37#include <sys/cdefs.h>
38__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 164598 2006-11-24 22:45:26Z sam $");
38__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 165185 2006-12-13 19:34:35Z sam $");
39
40/*
41 * Driver for the Atheros Wireless LAN controller.
42 *
43 * This software is derived from work of Atsushi Onoe; his contribution
44 * is greatly appreciated.
45 */
46

--- 206 unchanged lines hidden (view full) ---

253#define DPRINTF(sc, m, fmt, ...) do { \
254 if (sc->sc_debug & (m)) \
255 printf(fmt, __VA_ARGS__); \
256} while (0)
257#define KEYPRINTF(sc, ix, hk, mac) do { \
258 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \
259 ath_keyprint(sc, __func__, ix, hk, mac); \
260} while (0)
39
40/*
41 * Driver for the Atheros Wireless LAN controller.
42 *
43 * This software is derived from work of Atsushi Onoe; his contribution
44 * is greatly appreciated.
45 */
46

--- 206 unchanged lines hidden (view full) ---

253#define DPRINTF(sc, m, fmt, ...) do { \
254 if (sc->sc_debug & (m)) \
255 printf(fmt, __VA_ARGS__); \
256} while (0)
257#define KEYPRINTF(sc, ix, hk, mac) do { \
258 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \
259 ath_keyprint(sc, __func__, ix, hk, mac); \
260} while (0)
261static void ath_printrxbuf(struct ath_buf *bf, u_int ix, int);
262static void ath_printtxbuf(struct ath_buf *bf, u_int qnum, u_int ix, int done);
261static void ath_printrxbuf(const struct ath_buf *bf, u_int ix, int);
262static void ath_printtxbuf(const struct ath_buf *bf, u_int qnum, u_int ix, int done);
263#else
264#define IFF_DUMPPKTS(sc, m) \
265 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
266#define DPRINTF(sc, m, fmt, ...) do { \
267 (void) sc; \
268} while (0)
269#define KEYPRINTF(sc, k, ix, mac) do { \
270 (void) sc; \

--- 2482 unchanged lines hidden (view full) ---

2753 * if DMA is happening. When processing RX interrupts we
2754 * never remove/process the last, self-linked, entry on the
2755 * descriptor list. This insures the hardware always has
2756 * someplace to write a new frame.
2757 */
2758 ds = bf->bf_desc;
2759 ds->ds_link = bf->bf_daddr; /* link to self */
2760 ds->ds_data = bf->bf_segs[0].ds_addr;
263#else
264#define IFF_DUMPPKTS(sc, m) \
265 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
266#define DPRINTF(sc, m, fmt, ...) do { \
267 (void) sc; \
268} while (0)
269#define KEYPRINTF(sc, k, ix, mac) do { \
270 (void) sc; \

--- 2482 unchanged lines hidden (view full) ---

2753 * if DMA is happening. When processing RX interrupts we
2754 * never remove/process the last, self-linked, entry on the
2755 * descriptor list. This insures the hardware always has
2756 * someplace to write a new frame.
2757 */
2758 ds = bf->bf_desc;
2759 ds->ds_link = bf->bf_daddr; /* link to self */
2760 ds->ds_data = bf->bf_segs[0].ds_addr;
2761 ds->ds_vdata = mtod(m, void *); /* for radar */
2762 ath_hal_setuprxdesc(ah, ds
2763 , m->m_len /* buffer size */
2764 , 0
2765 );
2766
2767 if (sc->sc_rxlink != NULL)
2768 *sc->sc_rxlink = bf->bf_daddr;
2769 sc->sc_rxlink = &ds->ds_link;

--- 81 unchanged lines hidden (view full) ---

2851 if (sc->sc_defant != antenna)
2852 sc->sc_stats.ast_ant_defswitch++;
2853 sc->sc_defant = antenna;
2854 sc->sc_rxotherant = 0;
2855}
2856
2857static int
2858ath_rx_tap(struct ath_softc *sc, struct mbuf *m,
2761 ath_hal_setuprxdesc(ah, ds
2762 , m->m_len /* buffer size */
2763 , 0
2764 );
2765
2766 if (sc->sc_rxlink != NULL)
2767 *sc->sc_rxlink = bf->bf_daddr;
2768 sc->sc_rxlink = &ds->ds_link;

--- 81 unchanged lines hidden (view full) ---

2850 if (sc->sc_defant != antenna)
2851 sc->sc_stats.ast_ant_defswitch++;
2852 sc->sc_defant = antenna;
2853 sc->sc_rxotherant = 0;
2854}
2855
2856static int
2857ath_rx_tap(struct ath_softc *sc, struct mbuf *m,
2859 const struct ath_desc *ds, u_int64_t tsf, int16_t nf)
2858 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
2860{
2861 u_int8_t rix;
2862
2863 KASSERT(sc->sc_drvbpf != NULL, ("no tap"));
2864
2865 /*
2866 * Discard anything shorter than an ack or cts.
2867 */
2868 if (m->m_pkthdr.len < IEEE80211_ACK_LEN) {
2869 DPRINTF(sc, ATH_DEBUG_RECV, "%s: runt packet %d\n",
2870 __func__, m->m_pkthdr.len);
2871 sc->sc_stats.ast_rx_tooshort++;
2872 return 0;
2873 }
2859{
2860 u_int8_t rix;
2861
2862 KASSERT(sc->sc_drvbpf != NULL, ("no tap"));
2863
2864 /*
2865 * Discard anything shorter than an ack or cts.
2866 */
2867 if (m->m_pkthdr.len < IEEE80211_ACK_LEN) {
2868 DPRINTF(sc, ATH_DEBUG_RECV, "%s: runt packet %d\n",
2869 __func__, m->m_pkthdr.len);
2870 sc->sc_stats.ast_rx_tooshort++;
2871 return 0;
2872 }
2874 sc->sc_rx_th.wr_tsf = htole64(
2875 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf));
2876 rix = ds->ds_rxstat.rs_rate;
2873 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(rs->rs_tstamp, tsf));
2874 rix = rs->rs_rate;
2877 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
2875 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
2878 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC)
2876 if (rs->rs_status & HAL_RXERR_CRC)
2879 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
2880 /* XXX propagate other error flags from descriptor */
2881 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
2877 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
2878 /* XXX propagate other error flags from descriptor */
2879 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
2882 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf;
2880 sc->sc_rx_th.wr_antsignal = rs->rs_rssi + nf;
2883 sc->sc_rx_th.wr_antnoise = nf;
2881 sc->sc_rx_th.wr_antnoise = nf;
2884 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna;
2882 sc->sc_rx_th.wr_antenna = rs->rs_antenna;
2885
2886 bpf_mtap2(sc->sc_drvbpf, &sc->sc_rx_th, sc->sc_rx_th_len, m);
2887
2888 return 1;
2889}
2890
2891static void
2892ath_rx_proc(void *arg, int npending)
2893{
2894#define PA2DESC(_sc, _pa) \
2895 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
2896 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
2897 struct ath_softc *sc = arg;
2898 struct ath_buf *bf;
2899 struct ieee80211com *ic = &sc->sc_ic;
2900 struct ifnet *ifp = sc->sc_ifp;
2901 struct ath_hal *ah = sc->sc_ah;
2902 struct ath_desc *ds;
2883
2884 bpf_mtap2(sc->sc_drvbpf, &sc->sc_rx_th, sc->sc_rx_th_len, m);
2885
2886 return 1;
2887}
2888
2889static void
2890ath_rx_proc(void *arg, int npending)
2891{
2892#define PA2DESC(_sc, _pa) \
2893 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
2894 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
2895 struct ath_softc *sc = arg;
2896 struct ath_buf *bf;
2897 struct ieee80211com *ic = &sc->sc_ic;
2898 struct ifnet *ifp = sc->sc_ifp;
2899 struct ath_hal *ah = sc->sc_ah;
2900 struct ath_desc *ds;
2901 struct ath_rx_status *rs;
2903 struct mbuf *m;
2904 struct ieee80211_node *ni;
2905 struct ath_node *an;
2906 int len, type, ngood;
2907 u_int phyerr;
2908 HAL_STATUS status;
2909 int16_t nf;
2910 u_int64_t tsf;

--- 33 unchanged lines hidden (view full) ---

2944 * address of the next descriptor in the h/w chain.
2945 * This allows the HAL to look ahead to see if the
2946 * hardware is done with a descriptor by checking the
2947 * done bit in the following descriptor and the address
2948 * of the current descriptor the DMA engine is working
2949 * on. All this is necessary because of our use of
2950 * a self-linked list to avoid rx overruns.
2951 */
2902 struct mbuf *m;
2903 struct ieee80211_node *ni;
2904 struct ath_node *an;
2905 int len, type, ngood;
2906 u_int phyerr;
2907 HAL_STATUS status;
2908 int16_t nf;
2909 u_int64_t tsf;

--- 33 unchanged lines hidden (view full) ---

2943 * address of the next descriptor in the h/w chain.
2944 * This allows the HAL to look ahead to see if the
2945 * hardware is done with a descriptor by checking the
2946 * done bit in the following descriptor and the address
2947 * of the current descriptor the DMA engine is working
2948 * on. All this is necessary because of our use of
2949 * a self-linked list to avoid rx overruns.
2950 */
2951 rs = &bf->bf_status.ds_rxstat;
2952 status = ath_hal_rxprocdesc(ah, ds,
2952 status = ath_hal_rxprocdesc(ah, ds,
2953 bf->bf_daddr, PA2DESC(sc, ds->ds_link));
2953 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
2954#ifdef ATH_DEBUG
2955 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
2956 ath_printrxbuf(bf, 0, status == HAL_OK);
2957#endif
2958 if (status == HAL_EINPROGRESS)
2959 break;
2960 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
2954#ifdef ATH_DEBUG
2955 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
2956 ath_printrxbuf(bf, 0, status == HAL_OK);
2957#endif
2958 if (status == HAL_EINPROGRESS)
2959 break;
2960 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
2961 if (ds->ds_rxstat.rs_more) {
2961 if (rs->rs_more) {
2962 /*
2963 * Frame spans multiple descriptors; this
2964 * cannot happen yet as we don't support
2965 * jumbograms. If not in monitor mode,
2966 * discard the frame.
2967 */
2968 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2969 sc->sc_stats.ast_rx_toobig++;
2970 goto rx_next;
2971 }
2972 /* fall thru for monitor mode handling... */
2962 /*
2963 * Frame spans multiple descriptors; this
2964 * cannot happen yet as we don't support
2965 * jumbograms. If not in monitor mode,
2966 * discard the frame.
2967 */
2968 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2969 sc->sc_stats.ast_rx_toobig++;
2970 goto rx_next;
2971 }
2972 /* fall thru for monitor mode handling... */
2973 } else if (ds->ds_rxstat.rs_status != 0) {
2974 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC)
2973 } else if (rs->rs_status != 0) {
2974 if (rs->rs_status & HAL_RXERR_CRC)
2975 sc->sc_stats.ast_rx_crcerr++;
2975 sc->sc_stats.ast_rx_crcerr++;
2976 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO)
2976 if (rs->rs_status & HAL_RXERR_FIFO)
2977 sc->sc_stats.ast_rx_fifoerr++;
2977 sc->sc_stats.ast_rx_fifoerr++;
2978 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) {
2978 if (rs->rs_status & HAL_RXERR_PHY) {
2979 sc->sc_stats.ast_rx_phyerr++;
2979 sc->sc_stats.ast_rx_phyerr++;
2980 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f;
2980 phyerr = rs->rs_phyerr & 0x1f;
2981 sc->sc_stats.ast_rx_phy[phyerr]++;
2982 goto rx_next;
2983 }
2981 sc->sc_stats.ast_rx_phy[phyerr]++;
2982 goto rx_next;
2983 }
2984 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) {
2984 if (rs->rs_status & HAL_RXERR_DECRYPT) {
2985 /*
2986 * Decrypt error. If the error occurred
2987 * because there was no hardware key, then
2988 * let the frame through so the upper layers
2989 * can process it. This is necessary for 5210
2990 * parts which have no way to setup a ``clear''
2991 * key cache entry.
2992 *
2993 * XXX do key cache faulting
2994 */
2985 /*
2986 * Decrypt error. If the error occurred
2987 * because there was no hardware key, then
2988 * let the frame through so the upper layers
2989 * can process it. This is necessary for 5210
2990 * parts which have no way to setup a ``clear''
2991 * key cache entry.
2992 *
2993 * XXX do key cache faulting
2994 */
2995 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID)
2995 if (rs->rs_keyix == HAL_RXKEYIX_INVALID)
2996 goto rx_accept;
2997 sc->sc_stats.ast_rx_badcrypt++;
2998 }
2996 goto rx_accept;
2997 sc->sc_stats.ast_rx_badcrypt++;
2998 }
2999 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) {
2999 if (rs->rs_status & HAL_RXERR_MIC) {
3000 sc->sc_stats.ast_rx_badmic++;
3001 /*
3002 * Do minimal work required to hand off
3003 * the 802.11 header for notifcation.
3004 */
3005 /* XXX frag's and qos frames */
3000 sc->sc_stats.ast_rx_badmic++;
3001 /*
3002 * Do minimal work required to hand off
3003 * the 802.11 header for notifcation.
3004 */
3005 /* XXX frag's and qos frames */
3006 len = ds->ds_rxstat.rs_datalen;
3006 len = rs->rs_datalen;
3007 if (len >= sizeof (struct ieee80211_frame)) {
3008 bus_dmamap_sync(sc->sc_dmat,
3009 bf->bf_dmamap,
3010 BUS_DMASYNC_POSTREAD);
3011 ieee80211_notify_michael_failure(ic,
3012 mtod(m, struct ieee80211_frame *),
3013 sc->sc_splitmic ?
3007 if (len >= sizeof (struct ieee80211_frame)) {
3008 bus_dmamap_sync(sc->sc_dmat,
3009 bf->bf_dmamap,
3010 BUS_DMASYNC_POSTREAD);
3011 ieee80211_notify_michael_failure(ic,
3012 mtod(m, struct ieee80211_frame *),
3013 sc->sc_splitmic ?
3014 ds->ds_rxstat.rs_keyix-32 :
3015 ds->ds_rxstat.rs_keyix
3014 rs->rs_keyix-32 : rs->rs_keyix
3016 );
3017 }
3018 }
3019 ifp->if_ierrors++;
3020 /*
3021 * When a tap is present pass error frames
3022 * that have been requested. By default we
3023 * pass decrypt+mic errors but others may be
3024 * interesting (e.g. crc).
3025 */
3026 if (bpf_peers_present(sc->sc_drvbpf) &&
3015 );
3016 }
3017 }
3018 ifp->if_ierrors++;
3019 /*
3020 * When a tap is present pass error frames
3021 * that have been requested. By default we
3022 * pass decrypt+mic errors but others may be
3023 * interesting (e.g. crc).
3024 */
3025 if (bpf_peers_present(sc->sc_drvbpf) &&
3027 (ds->ds_rxstat.rs_status & sc->sc_monpass)) {
3026 (rs->rs_status & sc->sc_monpass)) {
3028 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3029 BUS_DMASYNC_POSTREAD);
3030 /* NB: bpf needs the mbuf length setup */
3027 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3028 BUS_DMASYNC_POSTREAD);
3029 /* NB: bpf needs the mbuf length setup */
3031 len = ds->ds_rxstat.rs_datalen;
3030 len = rs->rs_datalen;
3032 m->m_pkthdr.len = m->m_len = len;
3031 m->m_pkthdr.len = m->m_len = len;
3033 (void) ath_rx_tap(sc, m, ds, tsf, nf);
3032 (void) ath_rx_tap(sc, m, rs, tsf, nf);
3034 }
3035 /* XXX pass MIC errors up for s/w reclaculation */
3036 goto rx_next;
3037 }
3038rx_accept:
3039 /*
3040 * Sync and unmap the frame. At this point we're
3041 * committed to passing the mbuf somewhere so clear
3042 * bf_m; this means a new mbuf must be allocated
3043 * when the rx descriptor is setup again to receive
3044 * another frame.
3045 */
3046 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3047 BUS_DMASYNC_POSTREAD);
3048 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3049 bf->bf_m = NULL;
3050
3051 m->m_pkthdr.rcvif = ifp;
3033 }
3034 /* XXX pass MIC errors up for s/w reclaculation */
3035 goto rx_next;
3036 }
3037rx_accept:
3038 /*
3039 * Sync and unmap the frame. At this point we're
3040 * committed to passing the mbuf somewhere so clear
3041 * bf_m; this means a new mbuf must be allocated
3042 * when the rx descriptor is setup again to receive
3043 * another frame.
3044 */
3045 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3046 BUS_DMASYNC_POSTREAD);
3047 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3048 bf->bf_m = NULL;
3049
3050 m->m_pkthdr.rcvif = ifp;
3052 len = ds->ds_rxstat.rs_datalen;
3051 len = rs->rs_datalen;
3053 m->m_pkthdr.len = m->m_len = len;
3054
3052 m->m_pkthdr.len = m->m_len = len;
3053
3055 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++;
3054 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++;
3056
3057 if (bpf_peers_present(sc->sc_drvbpf) &&
3055
3056 if (bpf_peers_present(sc->sc_drvbpf) &&
3058 !ath_rx_tap(sc, m, ds, tsf, nf)) {
3057 !ath_rx_tap(sc, m, rs, tsf, nf)) {
3059 m_freem(m); /* XXX reclaim */
3060 goto rx_next;
3061 }
3062
3063 /*
3064 * From this point on we assume the frame is at least
3065 * as large as ieee80211_frame_min; verify that.
3066 */
3067 if (len < IEEE80211_MIN_LEN) {
3068 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n",
3069 __func__, len);
3070 sc->sc_stats.ast_rx_tooshort++;
3071 m_freem(m);
3072 goto rx_next;
3073 }
3074
3075 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
3076 ieee80211_dump_pkt(mtod(m, caddr_t), len,
3058 m_freem(m); /* XXX reclaim */
3059 goto rx_next;
3060 }
3061
3062 /*
3063 * From this point on we assume the frame is at least
3064 * as large as ieee80211_frame_min; verify that.
3065 */
3066 if (len < IEEE80211_MIN_LEN) {
3067 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n",
3068 __func__, len);
3069 sc->sc_stats.ast_rx_tooshort++;
3070 m_freem(m);
3071 goto rx_next;
3072 }
3073
3074 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
3075 ieee80211_dump_pkt(mtod(m, caddr_t), len,
3077 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate,
3078 ds->ds_rxstat.rs_rssi);
3076 sc->sc_hwmap[rs->rs_rate].ieeerate,
3077 rs->rs_rssi);
3079 }
3080
3081 m_adj(m, -IEEE80211_CRC_LEN);
3082
3083 /*
3084 * Locate the node for sender, track state, and then
3085 * pass the (referenced) node up to the 802.11 layer
3086 * for its use.
3087 */
3088 ni = ieee80211_find_rxnode_withkey(ic,
3089 mtod(m, const struct ieee80211_frame_min *),
3078 }
3079
3080 m_adj(m, -IEEE80211_CRC_LEN);
3081
3082 /*
3083 * Locate the node for sender, track state, and then
3084 * pass the (referenced) node up to the 802.11 layer
3085 * for its use.
3086 */
3087 ni = ieee80211_find_rxnode_withkey(ic,
3088 mtod(m, const struct ieee80211_frame_min *),
3090 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ?
3091 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix);
3089 rs->rs_keyix == HAL_RXKEYIX_INVALID ?
3090 IEEE80211_KEYIX_NONE : rs->rs_keyix);
3092 /*
3093 * Track rx rssi and do any rx antenna management.
3094 */
3095 an = ATH_NODE(ni);
3091 /*
3092 * Track rx rssi and do any rx antenna management.
3093 */
3094 an = ATH_NODE(ni);
3096 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi);
3097 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi);
3095 ATH_RSSI_LPF(an->an_avgrssi, rs->rs_rssi);
3096 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi);
3098 /*
3099 * Send frame up for processing.
3100 */
3097 /*
3098 * Send frame up for processing.
3099 */
3101 type = ieee80211_input(ic, m, ni,
3102 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp);
3100 type = ieee80211_input(ic, m, ni, rs->rs_rssi, rs->rs_tstamp);
3103 ieee80211_free_node(ni);
3104 if (sc->sc_diversity) {
3105 /*
3106 * When using fast diversity, change the default rx
3107 * antenna if diversity chooses the other antenna 3
3108 * times in a row.
3109 */
3101 ieee80211_free_node(ni);
3102 if (sc->sc_diversity) {
3103 /*
3104 * When using fast diversity, change the default rx
3105 * antenna if diversity chooses the other antenna 3
3106 * times in a row.
3107 */
3110 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) {
3108 if (sc->sc_defant != rs->rs_antenna) {
3111 if (++sc->sc_rxotherant >= 3)
3109 if (++sc->sc_rxotherant >= 3)
3112 ath_setdefantenna(sc,
3113 ds->ds_rxstat.rs_antenna);
3110 ath_setdefantenna(sc, rs->rs_antenna);
3114 } else
3115 sc->sc_rxotherant = 0;
3116 }
3117 if (sc->sc_softled) {
3118 /*
3119 * Blink for any data frame. Otherwise do a
3120 * heartbeat-style blink when idle. The latter
3121 * is mainly for station mode where we depend on
3122 * periodic beacon frames to trigger the poll event.
3123 */
3124 if (type == IEEE80211_FC0_TYPE_DATA) {
3111 } else
3112 sc->sc_rxotherant = 0;
3113 }
3114 if (sc->sc_softled) {
3115 /*
3116 * Blink for any data frame. Otherwise do a
3117 * heartbeat-style blink when idle. The latter
3118 * is mainly for station mode where we depend on
3119 * periodic beacon frames to trigger the poll event.
3120 */
3121 if (type == IEEE80211_FC0_TYPE_DATA) {
3125 sc->sc_rxrate = ds->ds_rxstat.rs_rate;
3122 sc->sc_rxrate = rs->rs_rate;
3126 ath_led_event(sc, ATH_LED_RX);
3127 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
3128 ath_led_event(sc, ATH_LED_POLL);
3129 }
3130 /*
3131 * Arrange to update the last rx timestamp only for
3132 * frames from our ap when operating in station mode.
3133 * This assumes the rx key is always setup when associated.
3134 */
3135 if (ic->ic_opmode == IEEE80211_M_STA &&
3123 ath_led_event(sc, ATH_LED_RX);
3124 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
3125 ath_led_event(sc, ATH_LED_POLL);
3126 }
3127 /*
3128 * Arrange to update the last rx timestamp only for
3129 * frames from our ap when operating in station mode.
3130 * This assumes the rx key is always setup when associated.
3131 */
3132 if (ic->ic_opmode == IEEE80211_M_STA &&
3136 ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID)
3133 rs->rs_keyix != HAL_RXKEYIX_INVALID)
3137 ngood++;
3138rx_next:
3139 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
3140 } while (ath_rxbuf_init(sc, bf) == 0);
3141
3142 /* rx signal state monitoring */
3143 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan);
3144 if (ngood)

--- 768 unchanged lines hidden (view full) ---

3913 */
3914static int
3915ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
3916{
3917 struct ath_hal *ah = sc->sc_ah;
3918 struct ieee80211com *ic = &sc->sc_ic;
3919 struct ath_buf *bf;
3920 struct ath_desc *ds, *ds0;
3134 ngood++;
3135rx_next:
3136 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
3137 } while (ath_rxbuf_init(sc, bf) == 0);
3138
3139 /* rx signal state monitoring */
3140 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan);
3141 if (ngood)

--- 768 unchanged lines hidden (view full) ---

3910 */
3911static int
3912ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
3913{
3914 struct ath_hal *ah = sc->sc_ah;
3915 struct ieee80211com *ic = &sc->sc_ic;
3916 struct ath_buf *bf;
3917 struct ath_desc *ds, *ds0;
3918 struct ath_tx_status *ts;
3921 struct ieee80211_node *ni;
3922 struct ath_node *an;
3923 int sr, lr, pri, nacked;
3924 HAL_STATUS status;
3925
3926 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
3927 __func__, txq->axq_qnum,
3928 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),

--- 4 unchanged lines hidden (view full) ---

3933 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
3934 bf = STAILQ_FIRST(&txq->axq_q);
3935 if (bf == NULL) {
3936 ATH_TXQ_UNLOCK(txq);
3937 break;
3938 }
3939 ds0 = &bf->bf_desc[0];
3940 ds = &bf->bf_desc[bf->bf_nseg - 1];
3919 struct ieee80211_node *ni;
3920 struct ath_node *an;
3921 int sr, lr, pri, nacked;
3922 HAL_STATUS status;
3923
3924 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
3925 __func__, txq->axq_qnum,
3926 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),

--- 4 unchanged lines hidden (view full) ---

3931 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
3932 bf = STAILQ_FIRST(&txq->axq_q);
3933 if (bf == NULL) {
3934 ATH_TXQ_UNLOCK(txq);
3935 break;
3936 }
3937 ds0 = &bf->bf_desc[0];
3938 ds = &bf->bf_desc[bf->bf_nseg - 1];
3941 status = ath_hal_txprocdesc(ah, ds);
3939 ts = &bf->bf_status.ds_txstat;
3940 status = ath_hal_txprocdesc(ah, ds, ts);
3942#ifdef ATH_DEBUG
3943 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
3944 ath_printtxbuf(bf, txq->axq_qnum, 0, status == HAL_OK);
3945#endif
3946 if (status == HAL_EINPROGRESS) {
3947 ATH_TXQ_UNLOCK(txq);
3948 break;
3949 }
3950 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3951 if (txq->axq_depth == 0)
3952 txq->axq_link = NULL;
3953 ATH_TXQ_UNLOCK(txq);
3954
3955 ni = bf->bf_node;
3956 if (ni != NULL) {
3957 an = ATH_NODE(ni);
3941#ifdef ATH_DEBUG
3942 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
3943 ath_printtxbuf(bf, txq->axq_qnum, 0, status == HAL_OK);
3944#endif
3945 if (status == HAL_EINPROGRESS) {
3946 ATH_TXQ_UNLOCK(txq);
3947 break;
3948 }
3949 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3950 if (txq->axq_depth == 0)
3951 txq->axq_link = NULL;
3952 ATH_TXQ_UNLOCK(txq);
3953
3954 ni = bf->bf_node;
3955 if (ni != NULL) {
3956 an = ATH_NODE(ni);
3958 if (ds->ds_txstat.ts_status == 0) {
3959 u_int8_t txant = ds->ds_txstat.ts_antenna;
3957 if (ts->ts_status == 0) {
3958 u_int8_t txant = ts->ts_antenna;
3960 sc->sc_stats.ast_ant_tx[txant]++;
3961 sc->sc_ant_tx[txant]++;
3959 sc->sc_stats.ast_ant_tx[txant]++;
3960 sc->sc_ant_tx[txant]++;
3962 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
3961 if (ts->ts_rate & HAL_TXSTAT_ALTRATE)
3963 sc->sc_stats.ast_tx_altrate++;
3962 sc->sc_stats.ast_tx_altrate++;
3964 sc->sc_stats.ast_tx_rssi =
3965 ds->ds_txstat.ts_rssi;
3963 sc->sc_stats.ast_tx_rssi = ts->ts_rssi;
3966 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
3964 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
3967 ds->ds_txstat.ts_rssi);
3965 ts->ts_rssi);
3968 pri = M_WME_GETAC(bf->bf_m);
3969 if (pri >= WME_AC_VO)
3970 ic->ic_wme.wme_hipri_traffic++;
3971 ni->ni_inact = ni->ni_inact_reload;
3972 } else {
3966 pri = M_WME_GETAC(bf->bf_m);
3967 if (pri >= WME_AC_VO)
3968 ic->ic_wme.wme_hipri_traffic++;
3969 ni->ni_inact = ni->ni_inact_reload;
3970 } else {
3973 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
3971 if (ts->ts_status & HAL_TXERR_XRETRY)
3974 sc->sc_stats.ast_tx_xretries++;
3972 sc->sc_stats.ast_tx_xretries++;
3975 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO)
3973 if (ts->ts_status & HAL_TXERR_FIFO)
3976 sc->sc_stats.ast_tx_fifoerr++;
3974 sc->sc_stats.ast_tx_fifoerr++;
3977 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
3975 if (ts->ts_status & HAL_TXERR_FILT)
3978 sc->sc_stats.ast_tx_filtered++;
3979 }
3976 sc->sc_stats.ast_tx_filtered++;
3977 }
3980 sr = ds->ds_txstat.ts_shortretry;
3981 lr = ds->ds_txstat.ts_longretry;
3978 sr = ts->ts_shortretry;
3979 lr = ts->ts_longretry;
3982 sc->sc_stats.ast_tx_shortretry += sr;
3983 sc->sc_stats.ast_tx_longretry += lr;
3984 /*
3985 * Hand the descriptor to the rate control algorithm.
3986 */
3980 sc->sc_stats.ast_tx_shortretry += sr;
3981 sc->sc_stats.ast_tx_longretry += lr;
3982 /*
3983 * Hand the descriptor to the rate control algorithm.
3984 */
3987 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 &&
3985 if ((ts->ts_status & HAL_TXERR_FILT) == 0 &&
3988 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
3989 /*
3990 * If frame was ack'd update the last rx time
3991 * used to workaround phantom bmiss interrupts.
3992 */
3986 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
3987 /*
3988 * If frame was ack'd update the last rx time
3989 * used to workaround phantom bmiss interrupts.
3990 */
3993 if (ds->ds_txstat.ts_status == 0)
3991 if (ts->ts_status == 0)
3994 nacked++;
3992 nacked++;
3995 ath_rate_tx_complete(sc, an, ds, ds0);
3993 ath_rate_tx_complete(sc, an, bf);
3996 }
3997 /*
3998 * Reclaim reference to node.
3999 *
4000 * NB: the node may be reclaimed here if, for example
4001 * this is a DEAUTH message that was sent and the
4002 * node was timed out due to inactivity.
4003 */

--- 132 unchanged lines hidden (view full) ---

4136 ATH_TXQ_UNLOCK(txq);
4137 break;
4138 }
4139 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
4140 ATH_TXQ_UNLOCK(txq);
4141#ifdef ATH_DEBUG
4142 if (sc->sc_debug & ATH_DEBUG_RESET) {
4143 ath_printtxbuf(bf, txq->axq_qnum, ix,
3994 }
3995 /*
3996 * Reclaim reference to node.
3997 *
3998 * NB: the node may be reclaimed here if, for example
3999 * this is a DEAUTH message that was sent and the
4000 * node was timed out due to inactivity.
4001 */

--- 132 unchanged lines hidden (view full) ---

4134 ATH_TXQ_UNLOCK(txq);
4135 break;
4136 }
4137 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
4138 ATH_TXQ_UNLOCK(txq);
4139#ifdef ATH_DEBUG
4140 if (sc->sc_debug & ATH_DEBUG_RESET) {
4141 ath_printtxbuf(bf, txq->axq_qnum, ix,
4144 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK);
4142 ath_hal_txprocdesc(ah, bf->bf_desc,
4143 &bf->bf_status.ds_txstat) == HAL_OK);
4145 ieee80211_dump_pkt(mtod(bf->bf_m, caddr_t),
4146 bf->bf_m->m_len, 0, -1);
4147 }
4148#endif /* ATH_DEBUG */
4149 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4150 m_freem(bf->bf_m);
4151 bf->bf_m = NULL;
4152 ni = bf->bf_node;

--- 48 unchanged lines hidden (view full) ---

4201 if (ATH_TXQ_SETUP(sc, i))
4202 ath_tx_draintxq(sc, &sc->sc_txq[i]);
4203 ath_tx_draintxq(sc, &sc->sc_mcastq);
4204#ifdef ATH_DEBUG
4205 if (sc->sc_debug & ATH_DEBUG_RESET) {
4206 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf);
4207 if (bf != NULL && bf->bf_m != NULL) {
4208 ath_printtxbuf(bf, sc->sc_bhalq, 0,
4144 ieee80211_dump_pkt(mtod(bf->bf_m, caddr_t),
4145 bf->bf_m->m_len, 0, -1);
4146 }
4147#endif /* ATH_DEBUG */
4148 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4149 m_freem(bf->bf_m);
4150 bf->bf_m = NULL;
4151 ni = bf->bf_node;

--- 48 unchanged lines hidden (view full) ---

4200 if (ATH_TXQ_SETUP(sc, i))
4201 ath_tx_draintxq(sc, &sc->sc_txq[i]);
4202 ath_tx_draintxq(sc, &sc->sc_mcastq);
4203#ifdef ATH_DEBUG
4204 if (sc->sc_debug & ATH_DEBUG_RESET) {
4205 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf);
4206 if (bf != NULL && bf->bf_m != NULL) {
4207 ath_printtxbuf(bf, sc->sc_bhalq, 0,
4209 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK);
4208 ath_hal_txprocdesc(ah, bf->bf_desc,
4209 &bf->bf_status.ds_txstat) == HAL_OK);
4210 ieee80211_dump_pkt(mtod(bf->bf_m, caddr_t),
4211 bf->bf_m->m_len, 0, -1);
4212 }
4213 }
4214#endif /* ATH_DEBUG */
4215 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4216 sc->sc_tx_timer = 0;
4217}

--- 18 unchanged lines hidden (view full) ---

4236 struct ath_buf *bf;
4237 u_int ix;
4238
4239 printf("%s: rx queue %p, link %p\n", __func__,
4240 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink);
4241 ix = 0;
4242 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
4243 struct ath_desc *ds = bf->bf_desc;
4210 ieee80211_dump_pkt(mtod(bf->bf_m, caddr_t),
4211 bf->bf_m->m_len, 0, -1);
4212 }
4213 }
4214#endif /* ATH_DEBUG */
4215 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4216 sc->sc_tx_timer = 0;
4217}

--- 18 unchanged lines hidden (view full) ---

4236 struct ath_buf *bf;
4237 u_int ix;
4238
4239 printf("%s: rx queue %p, link %p\n", __func__,
4240 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink);
4241 ix = 0;
4242 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
4243 struct ath_desc *ds = bf->bf_desc;
4244 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
4244 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
4245 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
4245 bf->bf_daddr, PA2DESC(sc, ds->ds_link));
4246 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
4246 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
4247 ath_printrxbuf(bf, ix, status == HAL_OK);
4248 ix++;
4249 }
4250 }
4251#endif
4252 sc->sc_rxlink = NULL; /* just in case */
4253#undef PA2DESC

--- 781 unchanged lines hidden (view full) ---

5035 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate);
5036 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate;
5037 /* NB: caller is responsible for reseting rate control state */
5038#undef N
5039}
5040
5041#ifdef ATH_DEBUG
5042static void
4247 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
4248 ath_printrxbuf(bf, ix, status == HAL_OK);
4249 ix++;
4250 }
4251 }
4252#endif
4253 sc->sc_rxlink = NULL; /* just in case */
4254#undef PA2DESC

--- 781 unchanged lines hidden (view full) ---

5036 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate);
5037 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate;
5038 /* NB: caller is responsible for reseting rate control state */
5039#undef N
5040}
5041
5042#ifdef ATH_DEBUG
5043static void
5043ath_printrxbuf(struct ath_buf *bf, u_int ix, int done)
5044ath_printrxbuf(const struct ath_buf *bf, u_int ix, int done)
5044{
5045{
5045 struct ath_desc *ds;
5046 const struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
5047 const struct ath_desc *ds;
5046 int i;
5047
5048 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
5049 printf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n"
5050 " %08x %08x %08x %08x\n",
5048 int i;
5049
5050 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
5051 printf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n"
5052 " %08x %08x %08x %08x\n",
5051 ix, ds, (struct ath_desc *)bf->bf_daddr + i,
5053 ix, ds, (const struct ath_desc *)bf->bf_daddr + i,
5052 ds->ds_link, ds->ds_data,
5054 ds->ds_link, ds->ds_data,
5053 !done ? "" : (ds->ds_rxstat.rs_status == 0) ? " *" : " !",
5055 !done ? "" : (rs->rs_status == 0) ? " *" : " !",
5054 ds->ds_ctl0, ds->ds_ctl1,
5055 ds->ds_hw[0], ds->ds_hw[1]);
5056 }
5057}
5058
5059static void
5056 ds->ds_ctl0, ds->ds_ctl1,
5057 ds->ds_hw[0], ds->ds_hw[1]);
5058 }
5059}
5060
5061static void
5060ath_printtxbuf(struct ath_buf *bf, u_int qnum, u_int ix, int done)
5062ath_printtxbuf(const struct ath_buf *bf, u_int qnum, u_int ix, int done)
5061{
5063{
5062 struct ath_desc *ds;
5064 const struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
5065 const struct ath_desc *ds;
5063 int i;
5064
5065 printf("Q%u[%3u]", qnum, ix);
5066 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
5067 printf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n"
5068 " %08x %08x %08x %08x %08x %08x\n",
5066 int i;
5067
5068 printf("Q%u[%3u]", qnum, ix);
5069 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
5070 printf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n"
5071 " %08x %08x %08x %08x %08x %08x\n",
5069 ds, (struct ath_desc *)bf->bf_daddr + i,
5072 ds, (const struct ath_desc *)bf->bf_daddr + i,
5070 ds->ds_link, ds->ds_data, bf->bf_flags,
5073 ds->ds_link, ds->ds_data, bf->bf_flags,
5071 !done ? "" : (ds->ds_txstat.ts_status == 0) ? " *" : " !",
5074 !done ? "" : (ts->ts_status == 0) ? " *" : " !",
5072 ds->ds_ctl0, ds->ds_ctl1,
5073 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]);
5074 }
5075}
5076#endif /* ATH_DEBUG */
5077
5078static void
5079ath_watchdog(struct ifnet *ifp)

--- 773 unchanged lines hidden --- 		5075 ds->ds_ctl0, ds->ds_ctl1,
5076 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]);
5077 }
5078}
5079#endif /* ATH_DEBUG */
5080
5081static void
5082ath_watchdog(struct ifnet *ifp)

--- 773 unchanged lines hidden ---