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if_ath.c (155991) if_ath.c (156073)
1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 21 unchanged lines hidden (view full) ---

30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 */
36
37#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 21 unchanged lines hidden (view full) ---

30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 */
36
37#include <sys/cdefs.h>
38__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 155991 2006-02-24 23:10:08Z sam $");
38__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 156073 2006-02-27 17:20:23Z sam $");
39
40/*
41 * Driver for the Atheros Wireless LAN controller.
42 *
43 * This software is derived from work of Atsushi Onoe; his contribution
44 * is greatly appreciated.
45 */
46

--- 1103 unchanged lines hidden (view full) ---

1150 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid)
1151 return;
1152 for (;;) {
1153 /*
1154 * Grab a TX buffer and associated resources.
1155 */
1156 ATH_TXBUF_LOCK(sc);
1157 bf = STAILQ_FIRST(&sc->sc_txbuf);
39
40/*
41 * Driver for the Atheros Wireless LAN controller.
42 *
43 * This software is derived from work of Atsushi Onoe; his contribution
44 * is greatly appreciated.
45 */
46

--- 1103 unchanged lines hidden (view full) ---

1150 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid)
1151 return;
1152 for (;;) {
1153 /*
1154 * Grab a TX buffer and associated resources.
1155 */
1156 ATH_TXBUF_LOCK(sc);
1157 bf = STAILQ_FIRST(&sc->sc_txbuf);
1158 if (bf != NULL) {
1159 if (bf->bf_flags & ATH_FLAG_BUSY)
1160 bf = NULL;
1161 else
1162 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list);
1163 }
1158 if (bf != NULL)
1159 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list);
1164 ATH_TXBUF_UNLOCK(sc);
1165 if (bf == NULL) {
1160 ATH_TXBUF_UNLOCK(sc);
1161 if (bf == NULL) {
1166 DPRINTF(sc, ATH_DEBUG_XMIT,
1167 "%s: no available xmit buffers\n", __func__);
1162 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n",
1163 __func__);
1168 sc->sc_stats.ast_tx_qstop++;
1169 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1170 break;
1171 }
1172 /*
1173 * Poll the management queue for frames; they
1174 * have priority over normal data frames.
1175 */

--- 4 unchanged lines hidden (view full) ---

1180 */
1181 if (ic->ic_state != IEEE80211_S_RUN) {
1182 DPRINTF(sc, ATH_DEBUG_XMIT,
1183 "%s: discard data packet, state %s\n",
1184 __func__,
1185 ieee80211_state_name[ic->ic_state]);
1186 sc->sc_stats.ast_tx_discard++;
1187 ATH_TXBUF_LOCK(sc);
1164 sc->sc_stats.ast_tx_qstop++;
1165 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1166 break;
1167 }
1168 /*
1169 * Poll the management queue for frames; they
1170 * have priority over normal data frames.
1171 */

--- 4 unchanged lines hidden (view full) ---

1176 */
1177 if (ic->ic_state != IEEE80211_S_RUN) {
1178 DPRINTF(sc, ATH_DEBUG_XMIT,
1179 "%s: discard data packet, state %s\n",
1180 __func__,
1181 ieee80211_state_name[ic->ic_state]);
1182 sc->sc_stats.ast_tx_discard++;
1183 ATH_TXBUF_LOCK(sc);
1188 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
1184 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1189 ATH_TXBUF_UNLOCK(sc);
1190 break;
1191 }
1192 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */
1193 if (m == NULL) {
1194 ATH_TXBUF_LOCK(sc);
1185 ATH_TXBUF_UNLOCK(sc);
1186 break;
1187 }
1188 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */
1189 if (m == NULL) {
1190 ATH_TXBUF_LOCK(sc);
1195 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
1191 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1196 ATH_TXBUF_UNLOCK(sc);
1197 break;
1198 }
1199 /*
1200 * Find the node for the destination so we can do
1201 * things like power save and fast frames aggregation.
1202 */
1203 if (m->m_len < sizeof(struct ether_header) &&

--- 70 unchanged lines hidden (view full) ---

1274 sc->sc_stats.ast_tx_mgmt++;
1275 }
1276
1277 if (ath_tx_start(sc, ni, bf, m)) {
1278 bad:
1279 ifp->if_oerrors++;
1280 reclaim:
1281 ATH_TXBUF_LOCK(sc);
1192 ATH_TXBUF_UNLOCK(sc);
1193 break;
1194 }
1195 /*
1196 * Find the node for the destination so we can do
1197 * things like power save and fast frames aggregation.
1198 */
1199 if (m->m_len < sizeof(struct ether_header) &&

--- 70 unchanged lines hidden (view full) ---

1270 sc->sc_stats.ast_tx_mgmt++;
1271 }
1272
1273 if (ath_tx_start(sc, ni, bf, m)) {
1274 bad:
1275 ifp->if_oerrors++;
1276 reclaim:
1277 ATH_TXBUF_LOCK(sc);
1282 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
1278 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1283 ATH_TXBUF_UNLOCK(sc);
1284 if (ni != NULL)
1285 ieee80211_free_node(ni);
1286 continue;
1287 }
1288
1289 sc->sc_tx_timer = 5;
1290 ifp->if_timer = 1;

--- 1119 unchanged lines hidden (view full) ---

2410 goto fail2;
2411 }
2412
2413 ds = dd->dd_desc;
2414 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
2415 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len,
2416 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len);
2417
1279 ATH_TXBUF_UNLOCK(sc);
1280 if (ni != NULL)
1281 ieee80211_free_node(ni);
1282 continue;
1283 }
1284
1285 sc->sc_tx_timer = 5;
1286 ifp->if_timer = 1;

--- 1119 unchanged lines hidden (view full) ---

2406 goto fail2;
2407 }
2408
2409 ds = dd->dd_desc;
2410 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
2411 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len,
2412 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len);
2413
2418 /* allocate buffers */
2414 /* allocate rx buffers */
2419 bsize = sizeof(struct ath_buf) * nbuf;
2420 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
2421 if (bf == NULL) {
2422 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
2423 dd->dd_name, bsize);
2424 goto fail3;
2425 }
2426 dd->dd_bufptr = bf;

--- 1259 unchanged lines hidden (view full) ---

3686 , ni->ni_txpower /* txpower */
3687 , txrate, try0 /* series 0 rate/tries */
3688 , keyix /* key cache index */
3689 , sc->sc_txantenna /* antenna mode */
3690 , flags /* flags */
3691 , ctsrate /* rts/cts rate */
3692 , ctsduration /* rts/cts duration */
3693 );
2415 bsize = sizeof(struct ath_buf) * nbuf;
2416 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
2417 if (bf == NULL) {
2418 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
2419 dd->dd_name, bsize);
2420 goto fail3;
2421 }
2422 dd->dd_bufptr = bf;

--- 1259 unchanged lines hidden (view full) ---

3682 , ni->ni_txpower /* txpower */
3683 , txrate, try0 /* series 0 rate/tries */
3684 , keyix /* key cache index */
3685 , sc->sc_txantenna /* antenna mode */
3686 , flags /* flags */
3687 , ctsrate /* rts/cts rate */
3688 , ctsduration /* rts/cts duration */
3689 );
3694 bf->bf_txflags = flags;
3690 bf->bf_flags = flags;
3695 /*
3696 * Setup the multi-rate retry state only when we're
3697 * going to use it. This assumes ath_hal_setuptxdesc
3698 * initializes the descriptors (so we don't have to)
3699 * when the hardware supports multi-rate retry and
3700 * we don't use it.
3701 */
3702 if (ismrr)

--- 54 unchanged lines hidden (view full) ---

3757/*
3758 * Process completed xmit descriptors from the specified queue.
3759 */
3760static int
3761ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
3762{
3763 struct ath_hal *ah = sc->sc_ah;
3764 struct ieee80211com *ic = &sc->sc_ic;
3691 /*
3692 * Setup the multi-rate retry state only when we're
3693 * going to use it. This assumes ath_hal_setuptxdesc
3694 * initializes the descriptors (so we don't have to)
3695 * when the hardware supports multi-rate retry and
3696 * we don't use it.
3697 */
3698 if (ismrr)

--- 54 unchanged lines hidden (view full) ---

3753/*
3754 * Process completed xmit descriptors from the specified queue.
3755 */
3756static int
3757ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
3758{
3759 struct ath_hal *ah = sc->sc_ah;
3760 struct ieee80211com *ic = &sc->sc_ic;
3765 struct ath_buf *bf, *last;
3761 struct ath_buf *bf;
3766 struct ath_desc *ds, *ds0;
3767 struct ieee80211_node *ni;
3768 struct ath_node *an;
3769 int sr, lr, pri, nacked;
3770 HAL_STATUS status;
3771
3772 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
3773 __func__, txq->axq_qnum,

--- 15 unchanged lines hidden (view full) ---

3789 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
3790 ath_printtxbuf(bf, txq->axq_qnum, 0, status == HAL_OK);
3791#endif
3792 if (status == HAL_EINPROGRESS) {
3793 ATH_TXQ_UNLOCK(txq);
3794 break;
3795 }
3796 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3762 struct ath_desc *ds, *ds0;
3763 struct ieee80211_node *ni;
3764 struct ath_node *an;
3765 int sr, lr, pri, nacked;
3766 HAL_STATUS status;
3767
3768 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
3769 __func__, txq->axq_qnum,

--- 15 unchanged lines hidden (view full) ---

3785 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
3786 ath_printtxbuf(bf, txq->axq_qnum, 0, status == HAL_OK);
3787#endif
3788 if (status == HAL_EINPROGRESS) {
3789 ATH_TXQ_UNLOCK(txq);
3790 break;
3791 }
3792 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3797 if (txq->axq_depth > 0) {
3798 /*
3799 * More frames follow. Mark the buffer busy
3800 * so it's not re-used while the hardware may
3801 * still re-read the link field.
3802 */
3803 bf->bf_flags |= ATH_FLAG_BUSY;
3804 } else
3793 if (txq->axq_depth == 0)
3805 txq->axq_link = NULL;
3806 ATH_TXQ_UNLOCK(txq);
3807
3808 ni = bf->bf_node;
3809 if (ni != NULL) {
3810 an = ATH_NODE(ni);
3811 if (ds->ds_txstat.ts_status == 0) {
3812 u_int8_t txant = ds->ds_txstat.ts_antenna;

--- 20 unchanged lines hidden (view full) ---

3833 sr = ds->ds_txstat.ts_shortretry;
3834 lr = ds->ds_txstat.ts_longretry;
3835 sc->sc_stats.ast_tx_shortretry += sr;
3836 sc->sc_stats.ast_tx_longretry += lr;
3837 /*
3838 * Hand the descriptor to the rate control algorithm.
3839 */
3840 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 &&
3794 txq->axq_link = NULL;
3795 ATH_TXQ_UNLOCK(txq);
3796
3797 ni = bf->bf_node;
3798 if (ni != NULL) {
3799 an = ATH_NODE(ni);
3800 if (ds->ds_txstat.ts_status == 0) {
3801 u_int8_t txant = ds->ds_txstat.ts_antenna;

--- 20 unchanged lines hidden (view full) ---

3822 sr = ds->ds_txstat.ts_shortretry;
3823 lr = ds->ds_txstat.ts_longretry;
3824 sc->sc_stats.ast_tx_shortretry += sr;
3825 sc->sc_stats.ast_tx_longretry += lr;
3826 /*
3827 * Hand the descriptor to the rate control algorithm.
3828 */
3829 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 &&
3841 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0) {
3830 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
3842 /*
3843 * If frame was ack'd update the last rx time
3844 * used to workaround phantom bmiss interrupts.
3845 */
3846 if (ds->ds_txstat.ts_status == 0)
3847 nacked++;
3848 ath_rate_tx_complete(sc, an, ds, ds0);
3849 }

--- 9 unchanged lines hidden (view full) ---

3859 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3860 BUS_DMASYNC_POSTWRITE);
3861 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3862 m_freem(bf->bf_m);
3863 bf->bf_m = NULL;
3864 bf->bf_node = NULL;
3865
3866 ATH_TXBUF_LOCK(sc);
3831 /*
3832 * If frame was ack'd update the last rx time
3833 * used to workaround phantom bmiss interrupts.
3834 */
3835 if (ds->ds_txstat.ts_status == 0)
3836 nacked++;
3837 ath_rate_tx_complete(sc, an, ds, ds0);
3838 }

--- 9 unchanged lines hidden (view full) ---

3848 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3849 BUS_DMASYNC_POSTWRITE);
3850 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3851 m_freem(bf->bf_m);
3852 bf->bf_m = NULL;
3853 bf->bf_node = NULL;
3854
3855 ATH_TXBUF_LOCK(sc);
3867 last = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list);
3868 if (last != NULL)
3869 last->bf_flags &= ~ATH_FLAG_BUSY;
3870 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
3871 ATH_TXBUF_UNLOCK(sc);
3872 }
3873 return nacked;
3874}
3875
3876static __inline int
3877txqactive(struct ath_hal *ah, int qnum)

--- 99 unchanged lines hidden (view full) ---

3977 struct ath_hal *ah = sc->sc_ah;
3978#endif
3979 struct ieee80211_node *ni;
3980 struct ath_buf *bf;
3981 u_int ix;
3982
3983 /*
3984 * NB: this assumes output has been stopped and
3856 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
3857 ATH_TXBUF_UNLOCK(sc);
3858 }
3859 return nacked;
3860}
3861
3862static __inline int
3863txqactive(struct ath_hal *ah, int qnum)

--- 99 unchanged lines hidden (view full) ---

3963 struct ath_hal *ah = sc->sc_ah;
3964#endif
3965 struct ieee80211_node *ni;
3966 struct ath_buf *bf;
3967 u_int ix;
3968
3969 /*
3970 * NB: this assumes output has been stopped and
3985 * we do not need to block ath_tx_proc
3971 * we do not need to block ath_tx_tasklet
3986 */
3987 for (ix = 0;; ix++) {
3988 ATH_TXQ_LOCK(txq);
3989 bf = STAILQ_FIRST(&txq->axq_q);
3990 if (bf == NULL) {
3972 */
3973 for (ix = 0;; ix++) {
3974 ATH_TXQ_LOCK(txq);
3975 bf = STAILQ_FIRST(&txq->axq_q);
3976 if (bf == NULL) {
3977 txq->axq_link = NULL;
3991 ATH_TXQ_UNLOCK(txq);
3992 break;
3993 }
3994 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3978 ATH_TXQ_UNLOCK(txq);
3979 break;
3980 }
3981 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3995 if (txq->axq_depth == 0)
3996 txq->axq_link = NULL;
3997 ATH_TXQ_UNLOCK(txq);
3998#ifdef AR_DEBUG
3999 if (sc->sc_debug & ATH_DEBUG_RESET)
4000 ath_printtxbuf(bf, txq->axq_qnum, ix,
4001 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK);
4002#endif /* AR_DEBUG */
4003 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4004 m_freem(bf->bf_m);
4005 bf->bf_m = NULL;
4006 ni = bf->bf_node;
4007 bf->bf_node = NULL;
4008 if (ni != NULL) {
4009 /*
4010 * Reclaim node reference.
4011 */
4012 ieee80211_free_node(ni);
4013 }
3982 ATH_TXQ_UNLOCK(txq);
3983#ifdef AR_DEBUG
3984 if (sc->sc_debug & ATH_DEBUG_RESET)
3985 ath_printtxbuf(bf, txq->axq_qnum, ix,
3986 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK);
3987#endif /* AR_DEBUG */
3988 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3989 m_freem(bf->bf_m);
3990 bf->bf_m = NULL;
3991 ni = bf->bf_node;
3992 bf->bf_node = NULL;
3993 if (ni != NULL) {
3994 /*
3995 * Reclaim node reference.
3996 */
3997 ieee80211_free_node(ni);
3998 }
4014 bf->bf_flags &= ~ATH_FLAG_BUSY;
4015 ATH_TXBUF_LOCK(sc);
4016 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
4017 ATH_TXBUF_UNLOCK(sc);
4018 }
3999 ATH_TXBUF_LOCK(sc);
4000 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
4001 ATH_TXBUF_UNLOCK(sc);
4002 }
4019 ATH_TXBUF_LOCK(sc);
4020 bf = STAILQ_FIRST(&sc->sc_txbuf);
4021 if (bf != NULL)
4022 bf->bf_flags &= ~ATH_FLAG_BUSY;
4023 ATH_TXBUF_UNLOCK(sc);
4024}
4025
4026static void
4027ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
4028{
4029 struct ath_hal *ah = sc->sc_ah;
4030
4031 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);

--- 861 unchanged lines hidden (view full) ---

4893static void
4894ath_printtxbuf(struct ath_buf *bf, u_int qnum, u_int ix, int done)
4895{
4896 struct ath_desc *ds;
4897 int i;
4898
4899 printf("Q%u[%3u]", qnum, ix);
4900 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
4003}
4004
4005static void
4006ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
4007{
4008 struct ath_hal *ah = sc->sc_ah;
4009
4010 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);

--- 861 unchanged lines hidden (view full) ---

4872static void
4873ath_printtxbuf(struct ath_buf *bf, u_int qnum, u_int ix, int done)
4874{
4875 struct ath_desc *ds;
4876 int i;
4877
4878 printf("Q%u[%3u]", qnum, ix);
4879 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
4901 printf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:%x TF:%04x%s\n"
4880 printf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n"
4902 " %08x %08x %08x %08x %08x %08x\n",
4903 ds, (struct ath_desc *)bf->bf_daddr + i,
4881 " %08x %08x %08x %08x %08x %08x\n",
4882 ds, (struct ath_desc *)bf->bf_daddr + i,
4904 ds->ds_link, ds->ds_data, bf->bf_flags, bf->bf_txflags,
4883 ds->ds_link, ds->ds_data, bf->bf_flags,
4905 !done ? "" : (ds->ds_txstat.ts_status == 0) ? " *" : " !",
4906 ds->ds_ctl0, ds->ds_ctl1,
4907 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]);
4908 }
4909}
4910#endif /* AR_DEBUG */
4911
4912static void

--- 540 unchanged lines hidden --- 		4884 !done ? "" : (ds->ds_txstat.ts_status == 0) ? " *" : " !",
4885 ds->ds_ctl0, ds->ds_ctl1,
4886 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]);
4887 }
4888}
4889#endif /* AR_DEBUG */
4890
4891static void

--- 540 unchanged lines hidden ---