843 sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW;
844 sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH;
845 sc->sc_aggr_limit = ATH_AGGR_MAXSIZE;
846 sc->sc_delim_min_pad = 0;
847
848 /*
849 * Check if the hardware requires PCI register serialisation.
850 * Some of the Owl based MACs require this.
851 */
852 if (mp_ncpus > 1 &&
853 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR,
854 0, NULL) == HAL_OK) {
855 sc->sc_ah->ah_config.ah_serialise_reg_war = 1;
856 device_printf(sc->sc_dev,
857 "Enabling register serialisation\n");
858 }
859
860 /*
861 * Initialise the deferred completed RX buffer list.
862 */
863 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP]);
864 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP]);
865
866 /*
867 * Indicate we need the 802.11 header padded to a
868 * 32-bit boundary for 4-address and QoS frames.
869 */
870 ic->ic_flags |= IEEE80211_F_DATAPAD;
871
872 /*
873 * Query the hal about antenna support.
874 */
875 sc->sc_defant = ath_hal_getdefantenna(ah);
876
877 /*
878 * Not all chips have the VEOL support we want to
879 * use with IBSS beacons; check here for it.
880 */
881 sc->sc_hasveol = ath_hal_hasveol(ah);
882
883 /* get mac address from hardware */
884 ath_hal_getmac(ah, macaddr);
885 if (sc->sc_hasbmask)
886 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask);
887
888 /* NB: used to size node table key mapping array */
889 ic->ic_max_keyix = sc->sc_keymax;
890 /* call MI attach routine. */
891 ieee80211_ifattach(ic, macaddr);
892 ic->ic_setregdomain = ath_setregdomain;
893 ic->ic_getradiocaps = ath_getradiocaps;
894 sc->sc_opmode = HAL_M_STA;
895
896 /* override default methods */
897 ic->ic_newassoc = ath_newassoc;
898 ic->ic_updateslot = ath_updateslot;
899 ic->ic_wme.wme_update = ath_wme_update;
900 ic->ic_vap_create = ath_vap_create;
901 ic->ic_vap_delete = ath_vap_delete;
902 ic->ic_raw_xmit = ath_raw_xmit;
903 ic->ic_update_mcast = ath_update_mcast;
904 ic->ic_update_promisc = ath_update_promisc;
905 ic->ic_node_alloc = ath_node_alloc;
906 sc->sc_node_free = ic->ic_node_free;
907 ic->ic_node_free = ath_node_free;
908 sc->sc_node_cleanup = ic->ic_node_cleanup;
909 ic->ic_node_cleanup = ath_node_cleanup;
910 ic->ic_node_getsignal = ath_node_getsignal;
911 ic->ic_scan_start = ath_scan_start;
912 ic->ic_scan_end = ath_scan_end;
913 ic->ic_set_channel = ath_set_channel;
914#ifdef ATH_ENABLE_11N
915 /* 802.11n specific - but just override anyway */
916 sc->sc_addba_request = ic->ic_addba_request;
917 sc->sc_addba_response = ic->ic_addba_response;
918 sc->sc_addba_stop = ic->ic_addba_stop;
919 sc->sc_bar_response = ic->ic_bar_response;
920 sc->sc_addba_response_timeout = ic->ic_addba_response_timeout;
921
922 ic->ic_addba_request = ath_addba_request;
923 ic->ic_addba_response = ath_addba_response;
924 ic->ic_addba_response_timeout = ath_addba_response_timeout;
925 ic->ic_addba_stop = ath_addba_stop;
926 ic->ic_bar_response = ath_bar_response;
927
928 ic->ic_update_chw = ath_update_chw;
929#endif /* ATH_ENABLE_11N */
930
931#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
932 /*
933 * There's one vendor bitmap entry in the RX radiotap
934 * header; make sure that's taken into account.
935 */
936 ieee80211_radiotap_attachv(ic,
937 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 0,
938 ATH_TX_RADIOTAP_PRESENT,
939 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 1,
940 ATH_RX_RADIOTAP_PRESENT);
941#else
942 /*
943 * No vendor bitmap/extensions are present.
944 */
945 ieee80211_radiotap_attach(ic,
946 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
947 ATH_TX_RADIOTAP_PRESENT,
948 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
949 ATH_RX_RADIOTAP_PRESENT);
950#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
951
952 /*
953 * Setup the ALQ logging if required
954 */
955#ifdef ATH_DEBUG_ALQ
956 if_ath_alq_init(&sc->sc_alq, device_get_nameunit(sc->sc_dev));
957 if_ath_alq_setcfg(&sc->sc_alq,
958 sc->sc_ah->ah_macVersion,
959 sc->sc_ah->ah_macRev,
960 sc->sc_ah->ah_phyRev,
961 sc->sc_ah->ah_magic);
962#endif
963
964 /*
965 * Setup dynamic sysctl's now that country code and
966 * regdomain are available from the hal.
967 */
968 ath_sysctlattach(sc);
969 ath_sysctl_stats_attach(sc);
970 ath_sysctl_hal_attach(sc);
971
972 if (bootverbose)
973 ieee80211_announce(ic);
974 ath_announce(sc);
975 return 0;
976bad2:
977 ath_tx_cleanup(sc);
978 ath_desc_free(sc);
979 ath_txdma_teardown(sc);
980 ath_rxdma_teardown(sc);
981bad:
982 if (ah)
983 ath_hal_detach(ah);
984
985 /*
986 * To work around scoping issues with CURVNET_SET/CURVNET_RESTORE..
987 */
988 if (ifp != NULL && ifp->if_vnet) {
989 CURVNET_SET(ifp->if_vnet);
990 if_free(ifp);
991 CURVNET_RESTORE();
992 } else if (ifp != NULL)
993 if_free(ifp);
994 sc->sc_invalid = 1;
995 return error;
996}
997
998int
999ath_detach(struct ath_softc *sc)
1000{
1001 struct ifnet *ifp = sc->sc_ifp;
1002
1003 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1004 __func__, ifp->if_flags);
1005
1006 /*
1007 * NB: the order of these is important:
1008 * o stop the chip so no more interrupts will fire
1009 * o call the 802.11 layer before detaching the hal to
1010 * insure callbacks into the driver to delete global
1011 * key cache entries can be handled
1012 * o free the taskqueue which drains any pending tasks
1013 * o reclaim the tx queue data structures after calling
1014 * the 802.11 layer as we'll get called back to reclaim
1015 * node state and potentially want to use them
1016 * o to cleanup the tx queues the hal is called, so detach
1017 * it last
1018 * Other than that, it's straightforward...
1019 */
1020 ath_stop(ifp);
1021 ieee80211_ifdetach(ifp->if_l2com);
1022 taskqueue_free(sc->sc_tq);
1023#ifdef ATH_TX99_DIAG
1024 if (sc->sc_tx99 != NULL)
1025 sc->sc_tx99->detach(sc->sc_tx99);
1026#endif
1027 ath_rate_detach(sc->sc_rc);
1028#ifdef ATH_DEBUG_ALQ
1029 if_ath_alq_tidyup(&sc->sc_alq);
1030#endif
1031 ath_spectral_detach(sc);
1032 ath_dfs_detach(sc);
1033 ath_desc_free(sc);
1034 ath_txdma_teardown(sc);
1035 ath_rxdma_teardown(sc);
1036 ath_tx_cleanup(sc);
1037 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */
1038
1039 CURVNET_SET(ifp->if_vnet);
1040 if_free(ifp);
1041 CURVNET_RESTORE();
1042
1043 return 0;
1044}
1045
1046/*
1047 * MAC address handling for multiple BSS on the same radio.
1048 * The first vap uses the MAC address from the EEPROM. For
1049 * subsequent vap's we set the U/L bit (bit 1) in the MAC
1050 * address and use the next six bits as an index.
1051 */
1052static void
1053assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone)
1054{
1055 int i;
1056
1057 if (clone && sc->sc_hasbmask) {
1058 /* NB: we only do this if h/w supports multiple bssid */
1059 for (i = 0; i < 8; i++)
1060 if ((sc->sc_bssidmask & (1<<i)) == 0)
1061 break;
1062 if (i != 0)
1063 mac[0] |= (i << 2)|0x2;
1064 } else
1065 i = 0;
1066 sc->sc_bssidmask |= 1<<i;
1067 sc->sc_hwbssidmask[0] &= ~mac[0];
1068 if (i == 0)
1069 sc->sc_nbssid0++;
1070}
1071
1072static void
1073reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN])
1074{
1075 int i = mac[0] >> 2;
1076 uint8_t mask;
1077
1078 if (i != 0 || --sc->sc_nbssid0 == 0) {
1079 sc->sc_bssidmask &= ~(1<<i);
1080 /* recalculate bssid mask from remaining addresses */
1081 mask = 0xff;
1082 for (i = 1; i < 8; i++)
1083 if (sc->sc_bssidmask & (1<<i))
1084 mask &= ~((i<<2)|0x2);
1085 sc->sc_hwbssidmask[0] |= mask;
1086 }
1087}
1088
1089/*
1090 * Assign a beacon xmit slot. We try to space out
1091 * assignments so when beacons are staggered the
1092 * traffic coming out of the cab q has maximal time
1093 * to go out before the next beacon is scheduled.
1094 */
1095static int
1096assign_bslot(struct ath_softc *sc)
1097{
1098 u_int slot, free;
1099
1100 free = 0;
1101 for (slot = 0; slot < ATH_BCBUF; slot++)
1102 if (sc->sc_bslot[slot] == NULL) {
1103 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL &&
1104 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL)
1105 return slot;
1106 free = slot;
1107 /* NB: keep looking for a double slot */
1108 }
1109 return free;
1110}
1111
1112static struct ieee80211vap *
1113ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
1114 enum ieee80211_opmode opmode, int flags,
1115 const uint8_t bssid[IEEE80211_ADDR_LEN],
1116 const uint8_t mac0[IEEE80211_ADDR_LEN])
1117{
1118 struct ath_softc *sc = ic->ic_ifp->if_softc;
1119 struct ath_vap *avp;
1120 struct ieee80211vap *vap;
1121 uint8_t mac[IEEE80211_ADDR_LEN];
1122 int needbeacon, error;
1123 enum ieee80211_opmode ic_opmode;
1124
1125 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap),
1126 M_80211_VAP, M_WAITOK | M_ZERO);
1127 needbeacon = 0;
1128 IEEE80211_ADDR_COPY(mac, mac0);
1129
1130 ATH_LOCK(sc);
1131 ic_opmode = opmode; /* default to opmode of new vap */
1132 switch (opmode) {
1133 case IEEE80211_M_STA:
1134 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */
1135 device_printf(sc->sc_dev, "only 1 sta vap supported\n");
1136 goto bad;
1137 }
1138 if (sc->sc_nvaps) {
1139 /*
1140 * With multiple vaps we must fall back
1141 * to s/w beacon miss handling.
1142 */
1143 flags |= IEEE80211_CLONE_NOBEACONS;
1144 }
1145 if (flags & IEEE80211_CLONE_NOBEACONS) {
1146 /*
1147 * Station mode w/o beacons are implemented w/ AP mode.
1148 */
1149 ic_opmode = IEEE80211_M_HOSTAP;
1150 }
1151 break;
1152 case IEEE80211_M_IBSS:
1153 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */
1154 device_printf(sc->sc_dev,
1155 "only 1 ibss vap supported\n");
1156 goto bad;
1157 }
1158 needbeacon = 1;
1159 break;
1160 case IEEE80211_M_AHDEMO:
1161#ifdef IEEE80211_SUPPORT_TDMA
1162 if (flags & IEEE80211_CLONE_TDMA) {
1163 if (sc->sc_nvaps != 0) {
1164 device_printf(sc->sc_dev,
1165 "only 1 tdma vap supported\n");
1166 goto bad;
1167 }
1168 needbeacon = 1;
1169 flags |= IEEE80211_CLONE_NOBEACONS;
1170 }
1171 /* fall thru... */
1172#endif
1173 case IEEE80211_M_MONITOR:
1174 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) {
1175 /*
1176 * Adopt existing mode. Adding a monitor or ahdemo
1177 * vap to an existing configuration is of dubious
1178 * value but should be ok.
1179 */
1180 /* XXX not right for monitor mode */
1181 ic_opmode = ic->ic_opmode;
1182 }
1183 break;
1184 case IEEE80211_M_HOSTAP:
1185 case IEEE80211_M_MBSS:
1186 needbeacon = 1;
1187 break;
1188 case IEEE80211_M_WDS:
1189 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) {
1190 device_printf(sc->sc_dev,
1191 "wds not supported in sta mode\n");
1192 goto bad;
1193 }
1194 /*
1195 * Silently remove any request for a unique
1196 * bssid; WDS vap's always share the local
1197 * mac address.
1198 */
1199 flags &= ~IEEE80211_CLONE_BSSID;
1200 if (sc->sc_nvaps == 0)
1201 ic_opmode = IEEE80211_M_HOSTAP;
1202 else
1203 ic_opmode = ic->ic_opmode;
1204 break;
1205 default:
1206 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
1207 goto bad;
1208 }
1209 /*
1210 * Check that a beacon buffer is available; the code below assumes it.
1211 */
1212 if (needbeacon & TAILQ_EMPTY(&sc->sc_bbuf)) {
1213 device_printf(sc->sc_dev, "no beacon buffer available\n");
1214 goto bad;
1215 }
1216
1217 /* STA, AHDEMO? */
1218 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) {
1219 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID);
1220 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1221 }
1222
1223 vap = &avp->av_vap;
1224 /* XXX can't hold mutex across if_alloc */
1225 ATH_UNLOCK(sc);
1226 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags,
1227 bssid, mac);
1228 ATH_LOCK(sc);
1229 if (error != 0) {
1230 device_printf(sc->sc_dev, "%s: error %d creating vap\n",
1231 __func__, error);
1232 goto bad2;
1233 }
1234
1235 /* h/w crypto support */
1236 vap->iv_key_alloc = ath_key_alloc;
1237 vap->iv_key_delete = ath_key_delete;
1238 vap->iv_key_set = ath_key_set;
1239 vap->iv_key_update_begin = ath_key_update_begin;
1240 vap->iv_key_update_end = ath_key_update_end;
1241
1242 /* override various methods */
1243 avp->av_recv_mgmt = vap->iv_recv_mgmt;
1244 vap->iv_recv_mgmt = ath_recv_mgmt;
1245 vap->iv_reset = ath_reset_vap;
1246 vap->iv_update_beacon = ath_beacon_update;
1247 avp->av_newstate = vap->iv_newstate;
1248 vap->iv_newstate = ath_newstate;
1249 avp->av_bmiss = vap->iv_bmiss;
1250 vap->iv_bmiss = ath_bmiss_vap;
1251
1252 avp->av_node_ps = vap->iv_node_ps;
1253 vap->iv_node_ps = ath_node_powersave;
1254
1255 avp->av_set_tim = vap->iv_set_tim;
1256 vap->iv_set_tim = ath_node_set_tim;
1257
1258 avp->av_recv_pspoll = vap->iv_recv_pspoll;
1259 vap->iv_recv_pspoll = ath_node_recv_pspoll;
1260
1261 /* Set default parameters */
1262
1263 /*
1264 * Anything earlier than some AR9300 series MACs don't
1265 * support a smaller MPDU density.
1266 */
1267 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8;
1268 /*
1269 * All NICs can handle the maximum size, however
1270 * AR5416 based MACs can only TX aggregates w/ RTS
1271 * protection when the total aggregate size is <= 8k.
1272 * However, for now that's enforced by the TX path.
1273 */
1274 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K;
1275
1276 avp->av_bslot = -1;
1277 if (needbeacon) {
1278 /*
1279 * Allocate beacon state and setup the q for buffered
1280 * multicast frames. We know a beacon buffer is
1281 * available because we checked above.
1282 */
1283 avp->av_bcbuf = TAILQ_FIRST(&sc->sc_bbuf);
1284 TAILQ_REMOVE(&sc->sc_bbuf, avp->av_bcbuf, bf_list);
1285 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) {
1286 /*
1287 * Assign the vap to a beacon xmit slot. As above
1288 * this cannot fail to find a free one.
1289 */
1290 avp->av_bslot = assign_bslot(sc);
1291 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL,
1292 ("beacon slot %u not empty", avp->av_bslot));
1293 sc->sc_bslot[avp->av_bslot] = vap;
1294 sc->sc_nbcnvaps++;
1295 }
1296 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) {
1297 /*
1298 * Multple vaps are to transmit beacons and we
1299 * have h/w support for TSF adjusting; enable
1300 * use of staggered beacons.
1301 */
1302 sc->sc_stagbeacons = 1;
1303 }
1304 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ);
1305 }
1306
1307 ic->ic_opmode = ic_opmode;
1308 if (opmode != IEEE80211_M_WDS) {
1309 sc->sc_nvaps++;
1310 if (opmode == IEEE80211_M_STA)
1311 sc->sc_nstavaps++;
1312 if (opmode == IEEE80211_M_MBSS)
1313 sc->sc_nmeshvaps++;
1314 }
1315 switch (ic_opmode) {
1316 case IEEE80211_M_IBSS:
1317 sc->sc_opmode = HAL_M_IBSS;
1318 break;
1319 case IEEE80211_M_STA:
1320 sc->sc_opmode = HAL_M_STA;
1321 break;
1322 case IEEE80211_M_AHDEMO:
1323#ifdef IEEE80211_SUPPORT_TDMA
1324 if (vap->iv_caps & IEEE80211_C_TDMA) {
1325 sc->sc_tdma = 1;
1326 /* NB: disable tsf adjust */
1327 sc->sc_stagbeacons = 0;
1328 }
1329 /*
1330 * NB: adhoc demo mode is a pseudo mode; to the hal it's
1331 * just ap mode.
1332 */
1333 /* fall thru... */
1334#endif
1335 case IEEE80211_M_HOSTAP:
1336 case IEEE80211_M_MBSS:
1337 sc->sc_opmode = HAL_M_HOSTAP;
1338 break;
1339 case IEEE80211_M_MONITOR:
1340 sc->sc_opmode = HAL_M_MONITOR;
1341 break;
1342 default:
1343 /* XXX should not happen */
1344 break;
1345 }
1346 if (sc->sc_hastsfadd) {
1347 /*
1348 * Configure whether or not TSF adjust should be done.
1349 */
1350 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons);
1351 }
1352 if (flags & IEEE80211_CLONE_NOBEACONS) {
1353 /*
1354 * Enable s/w beacon miss handling.
1355 */
1356 sc->sc_swbmiss = 1;
1357 }
1358 ATH_UNLOCK(sc);
1359
1360 /* complete setup */
1361 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status);
1362 return vap;
1363bad2:
1364 reclaim_address(sc, mac);
1365 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1366bad:
1367 free(avp, M_80211_VAP);
1368 ATH_UNLOCK(sc);
1369 return NULL;
1370}
1371
1372static void
1373ath_vap_delete(struct ieee80211vap *vap)
1374{
1375 struct ieee80211com *ic = vap->iv_ic;
1376 struct ifnet *ifp = ic->ic_ifp;
1377 struct ath_softc *sc = ifp->if_softc;
1378 struct ath_hal *ah = sc->sc_ah;
1379 struct ath_vap *avp = ATH_VAP(vap);
1380
1381 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
1382 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1383 /*
1384 * Quiesce the hardware while we remove the vap. In
1385 * particular we need to reclaim all references to
1386 * the vap state by any frames pending on the tx queues.
1387 */
1388 ath_hal_intrset(ah, 0); /* disable interrupts */
1389 ath_draintxq(sc, ATH_RESET_DEFAULT); /* stop hw xmit side */
1390 /* XXX Do all frames from all vaps/nodes need draining here? */
1391 ath_stoprecv(sc, 1); /* stop recv side */
1392 }
1393
1394 ieee80211_vap_detach(vap);
1395
1396 /*
1397 * XXX Danger Will Robinson! Danger!
1398 *
1399 * Because ieee80211_vap_detach() can queue a frame (the station
1400 * diassociate message?) after we've drained the TXQ and
1401 * flushed the software TXQ, we will end up with a frame queued
1402 * to a node whose vap is about to be freed.
1403 *
1404 * To work around this, flush the hardware/software again.
1405 * This may be racy - the ath task may be running and the packet
1406 * may be being scheduled between sw->hw txq. Tsk.
1407 *
1408 * TODO: figure out why a new node gets allocated somewhere around
1409 * here (after the ath_tx_swq() call; and after an ath_stop_locked()
1410 * call!)
1411 */
1412
1413 ath_draintxq(sc, ATH_RESET_DEFAULT);
1414
1415 ATH_LOCK(sc);
1416 /*
1417 * Reclaim beacon state. Note this must be done before
1418 * the vap instance is reclaimed as we may have a reference
1419 * to it in the buffer for the beacon frame.
1420 */
1421 if (avp->av_bcbuf != NULL) {
1422 if (avp->av_bslot != -1) {
1423 sc->sc_bslot[avp->av_bslot] = NULL;
1424 sc->sc_nbcnvaps--;
1425 }
1426 ath_beacon_return(sc, avp->av_bcbuf);
1427 avp->av_bcbuf = NULL;
1428 if (sc->sc_nbcnvaps == 0) {
1429 sc->sc_stagbeacons = 0;
1430 if (sc->sc_hastsfadd)
1431 ath_hal_settsfadjust(sc->sc_ah, 0);
1432 }
1433 /*
1434 * Reclaim any pending mcast frames for the vap.
1435 */
1436 ath_tx_draintxq(sc, &avp->av_mcastq);
1437 }
1438 /*
1439 * Update bookkeeping.
1440 */
1441 if (vap->iv_opmode == IEEE80211_M_STA) {
1442 sc->sc_nstavaps--;
1443 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss)
1444 sc->sc_swbmiss = 0;
1445 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
1446 vap->iv_opmode == IEEE80211_M_MBSS) {
1447 reclaim_address(sc, vap->iv_myaddr);
1448 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask);
1449 if (vap->iv_opmode == IEEE80211_M_MBSS)
1450 sc->sc_nmeshvaps--;
1451 }
1452 if (vap->iv_opmode != IEEE80211_M_WDS)
1453 sc->sc_nvaps--;
1454#ifdef IEEE80211_SUPPORT_TDMA
1455 /* TDMA operation ceases when the last vap is destroyed */
1456 if (sc->sc_tdma && sc->sc_nvaps == 0) {
1457 sc->sc_tdma = 0;
1458 sc->sc_swbmiss = 0;
1459 }
1460#endif
1461 free(avp, M_80211_VAP);
1462
1463 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1464 /*
1465 * Restart rx+tx machines if still running (RUNNING will
1466 * be reset if we just destroyed the last vap).
1467 */
1468 if (ath_startrecv(sc) != 0)
1469 if_printf(ifp, "%s: unable to restart recv logic\n",
1470 __func__);
1471 if (sc->sc_beacons) { /* restart beacons */
1472#ifdef IEEE80211_SUPPORT_TDMA
1473 if (sc->sc_tdma)
1474 ath_tdma_config(sc, NULL);
1475 else
1476#endif
1477 ath_beacon_config(sc, NULL);
1478 }
1479 ath_hal_intrset(ah, sc->sc_imask);
1480 }
1481 ATH_UNLOCK(sc);
1482}
1483
1484void
1485ath_suspend(struct ath_softc *sc)
1486{
1487 struct ifnet *ifp = sc->sc_ifp;
1488 struct ieee80211com *ic = ifp->if_l2com;
1489
1490 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1491 __func__, ifp->if_flags);
1492
1493 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0;
1494
1495 ieee80211_suspend_all(ic);
1496 /*
1497 * NB: don't worry about putting the chip in low power
1498 * mode; pci will power off our socket on suspend and
1499 * CardBus detaches the device.
1500 */
1501
1502 /*
1503 * XXX ensure none of the taskqueues are running
1504 * XXX ensure sc_invalid is 1
1505 * XXX ensure the calibration callout is disabled
1506 */
1507
1508 /* Disable the PCIe PHY, complete with workarounds */
1509 ath_hal_enablepcie(sc->sc_ah, 1, 1);
1510}
1511
1512/*
1513 * Reset the key cache since some parts do not reset the
1514 * contents on resume. First we clear all entries, then
1515 * re-load keys that the 802.11 layer assumes are setup
1516 * in h/w.
1517 */
1518static void
1519ath_reset_keycache(struct ath_softc *sc)
1520{
1521 struct ifnet *ifp = sc->sc_ifp;
1522 struct ieee80211com *ic = ifp->if_l2com;
1523 struct ath_hal *ah = sc->sc_ah;
1524 int i;
1525
1526 for (i = 0; i < sc->sc_keymax; i++)
1527 ath_hal_keyreset(ah, i);
1528 ieee80211_crypto_reload_keys(ic);
1529}
1530
1531/*
1532 * Fetch the current chainmask configuration based on the current
1533 * operating channel and options.
1534 */
1535static void
1536ath_update_chainmasks(struct ath_softc *sc, struct ieee80211_channel *chan)
1537{
1538
1539 /*
1540 * Set TX chainmask to the currently configured chainmask;
1541 * the TX chainmask depends upon the current operating mode.
1542 */
1543 sc->sc_cur_rxchainmask = sc->sc_rxchainmask;
1544 if (IEEE80211_IS_CHAN_HT(chan)) {
1545 sc->sc_cur_txchainmask = sc->sc_txchainmask;
1546 } else {
1547 sc->sc_cur_txchainmask = 1;
1548 }
1549
1550 DPRINTF(sc, ATH_DEBUG_RESET,
1551 "%s: TX chainmask is now 0x%x, RX is now 0x%x\n",
1552 __func__,
1553 sc->sc_cur_txchainmask,
1554 sc->sc_cur_rxchainmask);
1555}
1556
1557void
1558ath_resume(struct ath_softc *sc)
1559{
1560 struct ifnet *ifp = sc->sc_ifp;
1561 struct ieee80211com *ic = ifp->if_l2com;
1562 struct ath_hal *ah = sc->sc_ah;
1563 HAL_STATUS status;
1564
1565 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1566 __func__, ifp->if_flags);
1567
1568 /* Re-enable PCIe, re-enable the PCIe bus */
1569 ath_hal_enablepcie(ah, 0, 0);
1570
1571 /*
1572 * Must reset the chip before we reload the
1573 * keycache as we were powered down on suspend.
1574 */
1575 ath_update_chainmasks(sc,
1576 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan);
1577 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
1578 sc->sc_cur_rxchainmask);
1579 ath_hal_reset(ah, sc->sc_opmode,
1580 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan,
1581 AH_FALSE, &status);
1582 ath_reset_keycache(sc);
1583
1584 /* Let DFS at it in case it's a DFS channel */
1585 ath_dfs_radar_enable(sc, ic->ic_curchan);
1586
1587 /* Let spectral at in case spectral is enabled */
1588 ath_spectral_enable(sc, ic->ic_curchan);
1589
1590 /*
1591 * If we're doing TDMA, enforce the TXOP limitation for chips that
1592 * support it.
1593 */
1594 if (sc->sc_hasenforcetxop && sc->sc_tdma)
1595 ath_hal_setenforcetxop(sc->sc_ah, 1);
1596 else
1597 ath_hal_setenforcetxop(sc->sc_ah, 0);
1598
1599 /* Restore the LED configuration */
1600 ath_led_config(sc);
1601 ath_hal_setledstate(ah, HAL_LED_INIT);
1602
1603 if (sc->sc_resume_up)
1604 ieee80211_resume_all(ic);
1605
1606 /* XXX beacons ? */
1607}
1608
1609void
1610ath_shutdown(struct ath_softc *sc)
1611{
1612 struct ifnet *ifp = sc->sc_ifp;
1613
1614 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1615 __func__, ifp->if_flags);
1616
1617 ath_stop(ifp);
1618 /* NB: no point powering down chip as we're about to reboot */
1619}
1620
1621/*
1622 * Interrupt handler. Most of the actual processing is deferred.
1623 */
1624void
1625ath_intr(void *arg)
1626{
1627 struct ath_softc *sc = arg;
1628 struct ifnet *ifp = sc->sc_ifp;
1629 struct ath_hal *ah = sc->sc_ah;
1630 HAL_INT status = 0;
1631 uint32_t txqs;
1632
1633 /*
1634 * If we're inside a reset path, just print a warning and
1635 * clear the ISR. The reset routine will finish it for us.
1636 */
1637 ATH_PCU_LOCK(sc);
1638 if (sc->sc_inreset_cnt) {
1639 HAL_INT status;
1640 ath_hal_getisr(ah, &status); /* clear ISR */
1641 ath_hal_intrset(ah, 0); /* disable further intr's */
1642 DPRINTF(sc, ATH_DEBUG_ANY,
1643 "%s: in reset, ignoring: status=0x%x\n",
1644 __func__, status);
1645 ATH_PCU_UNLOCK(sc);
1646 return;
1647 }
1648
1649 if (sc->sc_invalid) {
1650 /*
1651 * The hardware is not ready/present, don't touch anything.
1652 * Note this can happen early on if the IRQ is shared.
1653 */
1654 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
1655 ATH_PCU_UNLOCK(sc);
1656 return;
1657 }
1658 if (!ath_hal_intrpend(ah)) { /* shared irq, not for us */
1659 ATH_PCU_UNLOCK(sc);
1660 return;
1661 }
1662
1663 if ((ifp->if_flags & IFF_UP) == 0 ||
1664 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1665 HAL_INT status;
1666
1667 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
1668 __func__, ifp->if_flags);
1669 ath_hal_getisr(ah, &status); /* clear ISR */
1670 ath_hal_intrset(ah, 0); /* disable further intr's */
1671 ATH_PCU_UNLOCK(sc);
1672 return;
1673 }
1674
1675 /*
1676 * Figure out the reason(s) for the interrupt. Note
1677 * that the hal returns a pseudo-ISR that may include
1678 * bits we haven't explicitly enabled so we mask the
1679 * value to insure we only process bits we requested.
1680 */
1681 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
1682 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
1683 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1, "ath_intr: mask=0x%.8x", status);
1684#ifdef ATH_DEBUG_ALQ
1685 if_ath_alq_post_intr(&sc->sc_alq, status, ah->ah_intrstate,
1686 ah->ah_syncstate);
1687#endif /* ATH_DEBUG_ALQ */
1688#ifdef ATH_KTR_INTR_DEBUG
1689 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 5,
1690 "ath_intr: ISR=0x%.8x, ISR_S0=0x%.8x, ISR_S1=0x%.8x, ISR_S2=0x%.8x, ISR_S5=0x%.8x",
1691 ah->ah_intrstate[0],
1692 ah->ah_intrstate[1],
1693 ah->ah_intrstate[2],
1694 ah->ah_intrstate[3],
1695 ah->ah_intrstate[6]);
1696#endif
1697
1698 /* Squirrel away SYNC interrupt debugging */
1699 if (ah->ah_syncstate != 0) {
1700 int i;
1701 for (i = 0; i < 32; i++)
1702 if (ah->ah_syncstate & (i << i))
1703 sc->sc_intr_stats.sync_intr[i]++;
1704 }
1705
1706 status &= sc->sc_imask; /* discard unasked for bits */
1707
1708 /* Short-circuit un-handled interrupts */
1709 if (status == 0x0) {
1710 ATH_PCU_UNLOCK(sc);
1711 return;
1712 }
1713
1714 /*
1715 * Take a note that we're inside the interrupt handler, so
1716 * the reset routines know to wait.
1717 */
1718 sc->sc_intr_cnt++;
1719 ATH_PCU_UNLOCK(sc);
1720
1721 /*
1722 * Handle the interrupt. We won't run concurrent with the reset
1723 * or channel change routines as they'll wait for sc_intr_cnt
1724 * to be 0 before continuing.
1725 */
1726 if (status & HAL_INT_FATAL) {
1727 sc->sc_stats.ast_hardware++;
1728 ath_hal_intrset(ah, 0); /* disable intr's until reset */
1729 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask);
1730 } else {
1731 if (status & HAL_INT_SWBA) {
1732 /*
1733 * Software beacon alert--time to send a beacon.
1734 * Handle beacon transmission directly; deferring
1735 * this is too slow to meet timing constraints
1736 * under load.
1737 */
1738#ifdef IEEE80211_SUPPORT_TDMA
1739 if (sc->sc_tdma) {
1740 if (sc->sc_tdmaswba == 0) {
1741 struct ieee80211com *ic = ifp->if_l2com;
1742 struct ieee80211vap *vap =
1743 TAILQ_FIRST(&ic->ic_vaps);
1744 ath_tdma_beacon_send(sc, vap);
1745 sc->sc_tdmaswba =
1746 vap->iv_tdma->tdma_bintval;
1747 } else
1748 sc->sc_tdmaswba--;
1749 } else
1750#endif
1751 {
1752 ath_beacon_proc(sc, 0);
1753#ifdef IEEE80211_SUPPORT_SUPERG
1754 /*
1755 * Schedule the rx taskq in case there's no
1756 * traffic so any frames held on the staging
1757 * queue are aged and potentially flushed.
1758 */
1759 sc->sc_rx.recv_sched(sc, 1);
1760#endif
1761 }
1762 }
1763 if (status & HAL_INT_RXEOL) {
1764 int imask;
1765 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXEOL");
1766 ATH_PCU_LOCK(sc);
1767 /*
1768 * NB: the hardware should re-read the link when
1769 * RXE bit is written, but it doesn't work at
1770 * least on older hardware revs.
1771 */
1772 sc->sc_stats.ast_rxeol++;
1773 /*
1774 * Disable RXEOL/RXORN - prevent an interrupt
1775 * storm until the PCU logic can be reset.
1776 * In case the interface is reset some other
1777 * way before "sc_kickpcu" is called, don't
1778 * modify sc_imask - that way if it is reset
1779 * by a call to ath_reset() somehow, the
1780 * interrupt mask will be correctly reprogrammed.
1781 */
1782 imask = sc->sc_imask;
1783 imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN);
1784 ath_hal_intrset(ah, imask);
1785 /*
1786 * Only blank sc_rxlink if we've not yet kicked
1787 * the PCU.
1788 *
1789 * This isn't entirely correct - the correct solution
1790 * would be to have a PCU lock and engage that for
1791 * the duration of the PCU fiddling; which would include
1792 * running the RX process. Otherwise we could end up
1793 * messing up the RX descriptor chain and making the
1794 * RX desc list much shorter.
1795 */
1796 if (! sc->sc_kickpcu)
1797 sc->sc_rxlink = NULL;
1798 sc->sc_kickpcu = 1;
1799 ATH_PCU_UNLOCK(sc);
1800 /*
1801 * Enqueue an RX proc, to handled whatever
1802 * is in the RX queue.
1803 * This will then kick the PCU.
1804 */
1805 sc->sc_rx.recv_sched(sc, 1);
1806 }
1807 if (status & HAL_INT_TXURN) {
1808 sc->sc_stats.ast_txurn++;
1809 /* bump tx trigger level */
1810 ath_hal_updatetxtriglevel(ah, AH_TRUE);
1811 }
1812 /*
1813 * Handle both the legacy and RX EDMA interrupt bits.
1814 * Note that HAL_INT_RXLP is also HAL_INT_RXDESC.
1815 */
1816 if (status & (HAL_INT_RX | HAL_INT_RXHP | HAL_INT_RXLP)) {
1817 sc->sc_stats.ast_rx_intr++;
1818 sc->sc_rx.recv_sched(sc, 1);
1819 }
1820 if (status & HAL_INT_TX) {
1821 sc->sc_stats.ast_tx_intr++;
1822 /*
1823 * Grab all the currently set bits in the HAL txq bitmap
1824 * and blank them. This is the only place we should be
1825 * doing this.
1826 */
1827 if (! sc->sc_isedma) {
1828 ATH_PCU_LOCK(sc);
1829 txqs = 0xffffffff;
1830 ath_hal_gettxintrtxqs(sc->sc_ah, &txqs);
1831 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 3,
1832 "ath_intr: TX; txqs=0x%08x, txq_active was 0x%08x, now 0x%08x",
1833 txqs,
1834 sc->sc_txq_active,
1835 sc->sc_txq_active | txqs);
1836 sc->sc_txq_active |= txqs;
1837 ATH_PCU_UNLOCK(sc);
1838 }
1839 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask);
1840 }
1841 if (status & HAL_INT_BMISS) {
1842 sc->sc_stats.ast_bmiss++;
1843 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask);
1844 }
1845 if (status & HAL_INT_GTT)
1846 sc->sc_stats.ast_tx_timeout++;
1847 if (status & HAL_INT_CST)
1848 sc->sc_stats.ast_tx_cst++;
1849 if (status & HAL_INT_MIB) {
1850 sc->sc_stats.ast_mib++;
1851 ATH_PCU_LOCK(sc);
1852 /*
1853 * Disable interrupts until we service the MIB
1854 * interrupt; otherwise it will continue to fire.
1855 */
1856 ath_hal_intrset(ah, 0);
1857 /*
1858 * Let the hal handle the event. We assume it will
1859 * clear whatever condition caused the interrupt.
1860 */
1861 ath_hal_mibevent(ah, &sc->sc_halstats);
1862 /*
1863 * Don't reset the interrupt if we've just
1864 * kicked the PCU, or we may get a nested
1865 * RXEOL before the rxproc has had a chance
1866 * to run.
1867 */
1868 if (sc->sc_kickpcu == 0)
1869 ath_hal_intrset(ah, sc->sc_imask);
1870 ATH_PCU_UNLOCK(sc);
1871 }
1872 if (status & HAL_INT_RXORN) {
1873 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */
1874 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXORN");
1875 sc->sc_stats.ast_rxorn++;
1876 }
1877 }
1878 ATH_PCU_LOCK(sc);
1879 sc->sc_intr_cnt--;
1880 ATH_PCU_UNLOCK(sc);
1881}
1882
1883static void
1884ath_fatal_proc(void *arg, int pending)
1885{
1886 struct ath_softc *sc = arg;
1887 struct ifnet *ifp = sc->sc_ifp;
1888 u_int32_t *state;
1889 u_int32_t len;
1890 void *sp;
1891
1892 if_printf(ifp, "hardware error; resetting\n");
1893 /*
1894 * Fatal errors are unrecoverable. Typically these
1895 * are caused by DMA errors. Collect h/w state from
1896 * the hal so we can diagnose what's going on.
1897 */
1898 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) {
1899 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len));
1900 state = sp;
1901 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n",
1902 state[0], state[1] , state[2], state[3],
1903 state[4], state[5]);
1904 }
1905 ath_reset(ifp, ATH_RESET_NOLOSS);
1906}
1907
1908static void
1909ath_bmiss_vap(struct ieee80211vap *vap)
1910{
1911 /*
1912 * Workaround phantom bmiss interrupts by sanity-checking
1913 * the time of our last rx'd frame. If it is within the
1914 * beacon miss interval then ignore the interrupt. If it's
1915 * truly a bmiss we'll get another interrupt soon and that'll
1916 * be dispatched up for processing. Note this applies only
1917 * for h/w beacon miss events.
1918 */
1919 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) {
1920 struct ifnet *ifp = vap->iv_ic->ic_ifp;
1921 struct ath_softc *sc = ifp->if_softc;
1922 u_int64_t lastrx = sc->sc_lastrx;
1923 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah);
1924 /* XXX should take a locked ref to iv_bss */
1925 u_int bmisstimeout =
1926 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024;
1927
1928 DPRINTF(sc, ATH_DEBUG_BEACON,
1929 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
1930 __func__, (unsigned long long) tsf,
1931 (unsigned long long)(tsf - lastrx),
1932 (unsigned long long) lastrx, bmisstimeout);
1933
1934 if (tsf - lastrx <= bmisstimeout) {
1935 sc->sc_stats.ast_bmiss_phantom++;
1936 return;
1937 }
1938 }
1939 ATH_VAP(vap)->av_bmiss(vap);
1940}
1941
1942int
1943ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs)
1944{
1945 uint32_t rsize;
1946 void *sp;
1947
1948 if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize))
1949 return 0;
1950 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize));
1951 *hangs = *(uint32_t *)sp;
1952 return 1;
1953}
1954
1955static void
1956ath_bmiss_proc(void *arg, int pending)
1957{
1958 struct ath_softc *sc = arg;
1959 struct ifnet *ifp = sc->sc_ifp;
1960 uint32_t hangs;
1961
1962 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
1963
1964 /*
1965 * Do a reset upon any becaon miss event.
1966 *
1967 * It may be a non-recognised RX clear hang which needs a reset
1968 * to clear.
1969 */
1970 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) {
1971 ath_reset(ifp, ATH_RESET_NOLOSS);
1972 if_printf(ifp, "bb hang detected (0x%x), resetting\n", hangs);
1973 } else {
1974 ath_reset(ifp, ATH_RESET_NOLOSS);
1975 ieee80211_beacon_miss(ifp->if_l2com);
1976 }
1977}
1978
1979/*
1980 * Handle TKIP MIC setup to deal hardware that doesn't do MIC
1981 * calcs together with WME. If necessary disable the crypto
1982 * hardware and mark the 802.11 state so keys will be setup
1983 * with the MIC work done in software.
1984 */
1985static void
1986ath_settkipmic(struct ath_softc *sc)
1987{
1988 struct ifnet *ifp = sc->sc_ifp;
1989 struct ieee80211com *ic = ifp->if_l2com;
1990
1991 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) {
1992 if (ic->ic_flags & IEEE80211_F_WME) {
1993 ath_hal_settkipmic(sc->sc_ah, AH_FALSE);
1994 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC;
1995 } else {
1996 ath_hal_settkipmic(sc->sc_ah, AH_TRUE);
1997 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
1998 }
1999 }
2000}
2001
2002static void
2003ath_init(void *arg)
2004{
2005 struct ath_softc *sc = (struct ath_softc *) arg;
2006 struct ifnet *ifp = sc->sc_ifp;
2007 struct ieee80211com *ic = ifp->if_l2com;
2008 struct ath_hal *ah = sc->sc_ah;
2009 HAL_STATUS status;
2010
2011 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
2012 __func__, ifp->if_flags);
2013
2014 ATH_LOCK(sc);
2015 /*
2016 * Stop anything previously setup. This is safe
2017 * whether this is the first time through or not.
2018 */
2019 ath_stop_locked(ifp);
2020
2021 /*
2022 * The basic interface to setting the hardware in a good
2023 * state is ``reset''. On return the hardware is known to
2024 * be powered up and with interrupts disabled. This must
2025 * be followed by initialization of the appropriate bits
2026 * and then setup of the interrupt mask.
2027 */
2028 ath_settkipmic(sc);
2029 ath_update_chainmasks(sc, ic->ic_curchan);
2030 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2031 sc->sc_cur_rxchainmask);
2032 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) {
2033 if_printf(ifp, "unable to reset hardware; hal status %u\n",
2034 status);
2035 ATH_UNLOCK(sc);
2036 return;
2037 }
2038 ath_chan_change(sc, ic->ic_curchan);
2039
2040 /* Let DFS at it in case it's a DFS channel */
2041 ath_dfs_radar_enable(sc, ic->ic_curchan);
2042
2043 /* Let spectral at in case spectral is enabled */
2044 ath_spectral_enable(sc, ic->ic_curchan);
2045
2046 /*
2047 * If we're doing TDMA, enforce the TXOP limitation for chips that
2048 * support it.
2049 */
2050 if (sc->sc_hasenforcetxop && sc->sc_tdma)
2051 ath_hal_setenforcetxop(sc->sc_ah, 1);
2052 else
2053 ath_hal_setenforcetxop(sc->sc_ah, 0);
2054
2055 /*
2056 * Likewise this is set during reset so update
2057 * state cached in the driver.
2058 */
2059 sc->sc_diversity = ath_hal_getdiversity(ah);
2060 sc->sc_lastlongcal = 0;
2061 sc->sc_resetcal = 1;
2062 sc->sc_lastcalreset = 0;
2063 sc->sc_lastani = 0;
2064 sc->sc_lastshortcal = 0;
2065 sc->sc_doresetcal = AH_FALSE;
2066 /*
2067 * Beacon timers were cleared here; give ath_newstate()
2068 * a hint that the beacon timers should be poked when
2069 * things transition to the RUN state.
2070 */
2071 sc->sc_beacons = 0;
2072
2073 /*
2074 * Setup the hardware after reset: the key cache
2075 * is filled as needed and the receive engine is
2076 * set going. Frame transmit is handled entirely
2077 * in the frame output path; there's nothing to do
2078 * here except setup the interrupt mask.
2079 */
2080 if (ath_startrecv(sc) != 0) {
2081 if_printf(ifp, "unable to start recv logic\n");
2082 ATH_UNLOCK(sc);
2083 return;
2084 }
2085
2086 /*
2087 * Enable interrupts.
2088 */
2089 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
2090 | HAL_INT_RXEOL | HAL_INT_RXORN
2091 | HAL_INT_TXURN
2092 | HAL_INT_FATAL | HAL_INT_GLOBAL;
2093
2094 /*
2095 * Enable RX EDMA bits. Note these overlap with
2096 * HAL_INT_RX and HAL_INT_RXDESC respectively.
2097 */
2098 if (sc->sc_isedma)
2099 sc->sc_imask |= (HAL_INT_RXHP | HAL_INT_RXLP);
2100
2101 /*
2102 * Enable MIB interrupts when there are hardware phy counters.
2103 * Note we only do this (at the moment) for station mode.
2104 */
2105 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
2106 sc->sc_imask |= HAL_INT_MIB;
2107
2108 /* Enable global TX timeout and carrier sense timeout if available */
2109 if (ath_hal_gtxto_supported(ah))
2110 sc->sc_imask |= HAL_INT_GTT;
2111
2112 DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n",
2113 __func__, sc->sc_imask);
2114
2115 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2116 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc);
2117 ath_hal_intrset(ah, sc->sc_imask);
2118
2119 ATH_UNLOCK(sc);
2120
2121#ifdef ATH_TX99_DIAG
2122 if (sc->sc_tx99 != NULL)
2123 sc->sc_tx99->start(sc->sc_tx99);
2124 else
2125#endif
2126 ieee80211_start_all(ic); /* start all vap's */
2127}
2128
2129static void
2130ath_stop_locked(struct ifnet *ifp)
2131{
2132 struct ath_softc *sc = ifp->if_softc;
2133 struct ath_hal *ah = sc->sc_ah;
2134
2135 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
2136 __func__, sc->sc_invalid, ifp->if_flags);
2137
2138 ATH_LOCK_ASSERT(sc);
2139 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2140 /*
2141 * Shutdown the hardware and driver:
2142 * reset 802.11 state machine
2143 * turn off timers
2144 * disable interrupts
2145 * turn off the radio
2146 * clear transmit machinery
2147 * clear receive machinery
2148 * drain and release tx queues
2149 * reclaim beacon resources
2150 * power down hardware
2151 *
2152 * Note that some of this work is not possible if the
2153 * hardware is gone (invalid).
2154 */
2155#ifdef ATH_TX99_DIAG
2156 if (sc->sc_tx99 != NULL)
2157 sc->sc_tx99->stop(sc->sc_tx99);
2158#endif
2159 callout_stop(&sc->sc_wd_ch);
2160 sc->sc_wd_timer = 0;
2161 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2162 if (!sc->sc_invalid) {
2163 if (sc->sc_softled) {
2164 callout_stop(&sc->sc_ledtimer);
2165 ath_hal_gpioset(ah, sc->sc_ledpin,
2166 !sc->sc_ledon);
2167 sc->sc_blinking = 0;
2168 }
2169 ath_hal_intrset(ah, 0);
2170 }
2171 ath_draintxq(sc, ATH_RESET_DEFAULT);
2172 if (!sc->sc_invalid) {
2173 ath_stoprecv(sc, 1);
2174 ath_hal_phydisable(ah);
2175 } else
2176 sc->sc_rxlink = NULL;
2177 ath_beacon_free(sc); /* XXX not needed */
2178 }
2179}
2180
2181#define MAX_TXRX_ITERATIONS 1000
2182static void
2183ath_txrx_stop_locked(struct ath_softc *sc)
2184{
2185 int i = MAX_TXRX_ITERATIONS;
2186
2187 ATH_UNLOCK_ASSERT(sc);
2188 ATH_PCU_LOCK_ASSERT(sc);
2189
2190 /*
2191 * Sleep until all the pending operations have completed.
2192 *
2193 * The caller must ensure that reset has been incremented
2194 * or the pending operations may continue being queued.
2195 */
2196 while (sc->sc_rxproc_cnt || sc->sc_txproc_cnt ||
2197 sc->sc_txstart_cnt || sc->sc_intr_cnt) {
2198 if (i <= 0)
2199 break;
2200 msleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop", 1);
2201 i--;
2202 }
2203
2204 if (i <= 0)
2205 device_printf(sc->sc_dev,
2206 "%s: didn't finish after %d iterations\n",
2207 __func__, MAX_TXRX_ITERATIONS);
2208}
2209#undef MAX_TXRX_ITERATIONS
2210
2211#if 0
2212static void
2213ath_txrx_stop(struct ath_softc *sc)
2214{
2215 ATH_UNLOCK_ASSERT(sc);
2216 ATH_PCU_UNLOCK_ASSERT(sc);
2217
2218 ATH_PCU_LOCK(sc);
2219 ath_txrx_stop_locked(sc);
2220 ATH_PCU_UNLOCK(sc);
2221}
2222#endif
2223
2224static void
2225ath_txrx_start(struct ath_softc *sc)
2226{
2227
2228 taskqueue_unblock(sc->sc_tq);
2229}
2230
2231/*
2232 * Grab the reset lock, and wait around until noone else
2233 * is trying to do anything with it.
2234 *
2235 * This is totally horrible but we can't hold this lock for
2236 * long enough to do TX/RX or we end up with net80211/ip stack
2237 * LORs and eventual deadlock.
2238 *
2239 * "dowait" signals whether to spin, waiting for the reset
2240 * lock count to reach 0. This should (for now) only be used
2241 * during the reset path, as the rest of the code may not
2242 * be locking-reentrant enough to behave correctly.
2243 *
2244 * Another, cleaner way should be found to serialise all of
2245 * these operations.
2246 */
2247#define MAX_RESET_ITERATIONS 10
2248static int
2249ath_reset_grablock(struct ath_softc *sc, int dowait)
2250{
2251 int w = 0;
2252 int i = MAX_RESET_ITERATIONS;
2253
2254 ATH_PCU_LOCK_ASSERT(sc);
2255 do {
2256 if (sc->sc_inreset_cnt == 0) {
2257 w = 1;
2258 break;
2259 }
2260 if (dowait == 0) {
2261 w = 0;
2262 break;
2263 }
2264 ATH_PCU_UNLOCK(sc);
2265 pause("ath_reset_grablock", 1);
2266 i--;
2267 ATH_PCU_LOCK(sc);
2268 } while (i > 0);
2269
2270 /*
2271 * We always increment the refcounter, regardless
2272 * of whether we succeeded to get it in an exclusive
2273 * way.
2274 */
2275 sc->sc_inreset_cnt++;
2276
2277 if (i <= 0)
2278 device_printf(sc->sc_dev,
2279 "%s: didn't finish after %d iterations\n",
2280 __func__, MAX_RESET_ITERATIONS);
2281
2282 if (w == 0)
2283 device_printf(sc->sc_dev,
2284 "%s: warning, recursive reset path!\n",
2285 __func__);
2286
2287 return w;
2288}
2289#undef MAX_RESET_ITERATIONS
2290
2291/*
2292 * XXX TODO: write ath_reset_releaselock
2293 */
2294
2295static void
2296ath_stop(struct ifnet *ifp)
2297{
2298 struct ath_softc *sc = ifp->if_softc;
2299
2300 ATH_LOCK(sc);
2301 ath_stop_locked(ifp);
2302 ATH_UNLOCK(sc);
2303}
2304
2305/*
2306 * Reset the hardware w/o losing operational state. This is
2307 * basically a more efficient way of doing ath_stop, ath_init,
2308 * followed by state transitions to the current 802.11
2309 * operational state. Used to recover from various errors and
2310 * to reset or reload hardware state.
2311 */
2312int
2313ath_reset(struct ifnet *ifp, ATH_RESET_TYPE reset_type)
2314{
2315 struct ath_softc *sc = ifp->if_softc;
2316 struct ieee80211com *ic = ifp->if_l2com;
2317 struct ath_hal *ah = sc->sc_ah;
2318 HAL_STATUS status;
2319 int i;
2320
2321 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
2322
2323 /* Ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */
2324 ATH_PCU_UNLOCK_ASSERT(sc);
2325 ATH_UNLOCK_ASSERT(sc);
2326
2327 /* Try to (stop any further TX/RX from occuring */
2328 taskqueue_block(sc->sc_tq);
2329
2330 ATH_PCU_LOCK(sc);
2331 ath_hal_intrset(ah, 0); /* disable interrupts */
2332 ath_txrx_stop_locked(sc); /* Ensure TX/RX is stopped */
2333 if (ath_reset_grablock(sc, 1) == 0) {
2334 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
2335 __func__);
2336 }
2337 ATH_PCU_UNLOCK(sc);
2338
2339 /*
2340 * Should now wait for pending TX/RX to complete
2341 * and block future ones from occuring. This needs to be
2342 * done before the TX queue is drained.
2343 */
2344 ath_draintxq(sc, reset_type); /* stop xmit side */
2345
2346 /*
2347 * Regardless of whether we're doing a no-loss flush or
2348 * not, stop the PCU and handle what's in the RX queue.
2349 * That way frames aren't dropped which shouldn't be.
2350 */
2351 ath_stoprecv(sc, (reset_type != ATH_RESET_NOLOSS));
2352 ath_rx_flush(sc);
2353
2354 ath_settkipmic(sc); /* configure TKIP MIC handling */
2355 /* NB: indicate channel change so we do a full reset */
2356 ath_update_chainmasks(sc, ic->ic_curchan);
2357 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2358 sc->sc_cur_rxchainmask);
2359 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status))
2360 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
2361 __func__, status);
2362 sc->sc_diversity = ath_hal_getdiversity(ah);
2363
2364 /* Let DFS at it in case it's a DFS channel */
2365 ath_dfs_radar_enable(sc, ic->ic_curchan);
2366
2367 /* Let spectral at in case spectral is enabled */
2368 ath_spectral_enable(sc, ic->ic_curchan);
2369
2370 /*
2371 * If we're doing TDMA, enforce the TXOP limitation for chips that
2372 * support it.
2373 */
2374 if (sc->sc_hasenforcetxop && sc->sc_tdma)
2375 ath_hal_setenforcetxop(sc->sc_ah, 1);
2376 else
2377 ath_hal_setenforcetxop(sc->sc_ah, 0);
2378
2379 if (ath_startrecv(sc) != 0) /* restart recv */
2380 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
2381 /*
2382 * We may be doing a reset in response to an ioctl
2383 * that changes the channel so update any state that
2384 * might change as a result.
2385 */
2386 ath_chan_change(sc, ic->ic_curchan);
2387 if (sc->sc_beacons) { /* restart beacons */
2388#ifdef IEEE80211_SUPPORT_TDMA
2389 if (sc->sc_tdma)
2390 ath_tdma_config(sc, NULL);
2391 else
2392#endif
2393 ath_beacon_config(sc, NULL);
2394 }
2395
2396 /*
2397 * Release the reset lock and re-enable interrupts here.
2398 * If an interrupt was being processed in ath_intr(),
2399 * it would disable interrupts at this point. So we have
2400 * to atomically enable interrupts and decrement the
2401 * reset counter - this way ath_intr() doesn't end up
2402 * disabling interrupts without a corresponding enable
2403 * in the rest or channel change path.
2404 */
2405 ATH_PCU_LOCK(sc);
2406 sc->sc_inreset_cnt--;
2407 /* XXX only do this if sc_inreset_cnt == 0? */
2408 ath_hal_intrset(ah, sc->sc_imask);
2409 ATH_PCU_UNLOCK(sc);
2410
2411 /*
2412 * TX and RX can be started here. If it were started with
2413 * sc_inreset_cnt > 0, the TX and RX path would abort.
2414 * Thus if this is a nested call through the reset or
2415 * channel change code, TX completion will occur but
2416 * RX completion and ath_start / ath_tx_start will not
2417 * run.
2418 */
2419
2420 /* Restart TX/RX as needed */
2421 ath_txrx_start(sc);
2422
2423 /* Restart TX completion and pending TX */
2424 if (reset_type == ATH_RESET_NOLOSS) {
2425 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
2426 if (ATH_TXQ_SETUP(sc, i)) {
2427 ATH_TXQ_LOCK(&sc->sc_txq[i]);
2428 ath_txq_restart_dma(sc, &sc->sc_txq[i]);
2429 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
2430
2431 ATH_TX_LOCK(sc);
2432 ath_txq_sched(sc, &sc->sc_txq[i]);
2433 ATH_TX_UNLOCK(sc);
2434 }
2435 }
2436 }
2437
2438 /*
2439 * This may have been set during an ath_start() call which
2440 * set this once it detected a concurrent TX was going on.
2441 * So, clear it.
2442 */
2443 IF_LOCK(&ifp->if_snd);
2444 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2445 IF_UNLOCK(&ifp->if_snd);
2446
2447 /* Handle any frames in the TX queue */
2448 /*
2449 * XXX should this be done by the caller, rather than
2450 * ath_reset() ?
2451 */
2452 ath_tx_kick(sc); /* restart xmit */
2453 return 0;
2454}
2455
2456static int
2457ath_reset_vap(struct ieee80211vap *vap, u_long cmd)
2458{
2459 struct ieee80211com *ic = vap->iv_ic;
2460 struct ifnet *ifp = ic->ic_ifp;
2461 struct ath_softc *sc = ifp->if_softc;
2462 struct ath_hal *ah = sc->sc_ah;
2463
2464 switch (cmd) {
2465 case IEEE80211_IOC_TXPOWER:
2466 /*
2467 * If per-packet TPC is enabled, then we have nothing
2468 * to do; otherwise we need to force the global limit.
2469 * All this can happen directly; no need to reset.
2470 */
2471 if (!ath_hal_gettpc(ah))
2472 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
2473 return 0;
2474 }
2475 /* XXX? Full or NOLOSS? */
2476 return ath_reset(ifp, ATH_RESET_FULL);
2477}
2478
2479struct ath_buf *
2480_ath_getbuf_locked(struct ath_softc *sc, ath_buf_type_t btype)
2481{
2482 struct ath_buf *bf;
2483
2484 ATH_TXBUF_LOCK_ASSERT(sc);
2485
2486 if (btype == ATH_BUFTYPE_MGMT)
2487 bf = TAILQ_FIRST(&sc->sc_txbuf_mgmt);
2488 else
2489 bf = TAILQ_FIRST(&sc->sc_txbuf);
2490
2491 if (bf == NULL) {
2492 sc->sc_stats.ast_tx_getnobuf++;
2493 } else {
2494 if (bf->bf_flags & ATH_BUF_BUSY) {
2495 sc->sc_stats.ast_tx_getbusybuf++;
2496 bf = NULL;
2497 }
2498 }
2499
2500 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) {
2501 if (btype == ATH_BUFTYPE_MGMT)
2502 TAILQ_REMOVE(&sc->sc_txbuf_mgmt, bf, bf_list);
2503 else {
2504 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list);
2505 sc->sc_txbuf_cnt--;
2506
2507 /*
2508 * This shuldn't happen; however just to be
2509 * safe print a warning and fudge the txbuf
2510 * count.
2511 */
2512 if (sc->sc_txbuf_cnt < 0) {
2513 device_printf(sc->sc_dev,
2514 "%s: sc_txbuf_cnt < 0?\n",
2515 __func__);
2516 sc->sc_txbuf_cnt = 0;
2517 }
2518 }
2519 } else
2520 bf = NULL;
2521
2522 if (bf == NULL) {
2523 /* XXX should check which list, mgmt or otherwise */
2524 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__,
2525 TAILQ_FIRST(&sc->sc_txbuf) == NULL ?
2526 "out of xmit buffers" : "xmit buffer busy");
2527 return NULL;
2528 }
2529
2530 /* XXX TODO: should do this at buffer list initialisation */
2531 /* XXX (then, ensure the buffer has the right flag set) */
2532 bf->bf_flags = 0;
2533 if (btype == ATH_BUFTYPE_MGMT)
2534 bf->bf_flags |= ATH_BUF_MGMT;
2535 else
2536 bf->bf_flags &= (~ATH_BUF_MGMT);
2537
2538 /* Valid bf here; clear some basic fields */
2539 bf->bf_next = NULL; /* XXX just to be sure */
2540 bf->bf_last = NULL; /* XXX again, just to be sure */
2541 bf->bf_comp = NULL; /* XXX again, just to be sure */
2542 bzero(&bf->bf_state, sizeof(bf->bf_state));
2543
2544 /*
2545 * Track the descriptor ID only if doing EDMA
2546 */
2547 if (sc->sc_isedma) {
2548 bf->bf_descid = sc->sc_txbuf_descid;
2549 sc->sc_txbuf_descid++;
2550 }
2551
2552 return bf;
2553}
2554
2555/*
2556 * When retrying a software frame, buffers marked ATH_BUF_BUSY
2557 * can't be thrown back on the queue as they could still be
2558 * in use by the hardware.
2559 *
2560 * This duplicates the buffer, or returns NULL.
2561 *
2562 * The descriptor is also copied but the link pointers and
2563 * the DMA segments aren't copied; this frame should thus
2564 * be again passed through the descriptor setup/chain routines
2565 * so the link is correct.
2566 *
2567 * The caller must free the buffer using ath_freebuf().
2568 */
2569struct ath_buf *
2570ath_buf_clone(struct ath_softc *sc, struct ath_buf *bf)
2571{
2572 struct ath_buf *tbf;
2573
2574 tbf = ath_getbuf(sc,
2575 (bf->bf_flags & ATH_BUF_MGMT) ?
2576 ATH_BUFTYPE_MGMT : ATH_BUFTYPE_NORMAL);
2577 if (tbf == NULL)
2578 return NULL; /* XXX failure? Why? */
2579
2580 /* Copy basics */
2581 tbf->bf_next = NULL;
2582 tbf->bf_nseg = bf->bf_nseg;
2583 tbf->bf_flags = bf->bf_flags & ATH_BUF_FLAGS_CLONE;
2584 tbf->bf_status = bf->bf_status;
2585 tbf->bf_m = bf->bf_m;
2586 tbf->bf_node = bf->bf_node;
2587 /* will be setup by the chain/setup function */
2588 tbf->bf_lastds = NULL;
2589 /* for now, last == self */
2590 tbf->bf_last = tbf;
2591 tbf->bf_comp = bf->bf_comp;
2592
2593 /* NOTE: DMA segments will be setup by the setup/chain functions */
2594
2595 /* The caller has to re-init the descriptor + links */
2596
2597 /*
2598 * Free the DMA mapping here, before we NULL the mbuf.
2599 * We must only call bus_dmamap_unload() once per mbuf chain
2600 * or behaviour is undefined.
2601 */
2602 if (bf->bf_m != NULL) {
2603 /*
2604 * XXX is this POSTWRITE call required?
2605 */
2606 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
2607 BUS_DMASYNC_POSTWRITE);
2608 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2609 }
2610
2611 bf->bf_m = NULL;
2612 bf->bf_node = NULL;
2613
2614 /* Copy state */
2615 memcpy(&tbf->bf_state, &bf->bf_state, sizeof(bf->bf_state));
2616
2617 return tbf;
2618}
2619
2620struct ath_buf *
2621ath_getbuf(struct ath_softc *sc, ath_buf_type_t btype)
2622{
2623 struct ath_buf *bf;
2624
2625 ATH_TXBUF_LOCK(sc);
2626 bf = _ath_getbuf_locked(sc, btype);
2627 /*
2628 * If a mgmt buffer was requested but we're out of those,
2629 * try requesting a normal one.
2630 */
2631 if (bf == NULL && btype == ATH_BUFTYPE_MGMT)
2632 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL);
2633 ATH_TXBUF_UNLOCK(sc);
2634 if (bf == NULL) {
2635 struct ifnet *ifp = sc->sc_ifp;
2636
2637 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__);
2638 sc->sc_stats.ast_tx_qstop++;
2639 IF_LOCK(&ifp->if_snd);
2640 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2641 IF_UNLOCK(&ifp->if_snd);
2642 }
2643 return bf;
2644}
2645
2646static void
2647ath_start_queue(struct ifnet *ifp)
2648{
2649 struct ath_softc *sc = ifp->if_softc;
2650
2651 ATH_PCU_LOCK(sc);
2652 if (sc->sc_inreset_cnt > 0) {
2653 device_printf(sc->sc_dev,
2654 "%s: sc_inreset_cnt > 0; bailing\n", __func__);
2655 ATH_PCU_UNLOCK(sc);
2656 IF_LOCK(&ifp->if_snd);
2657 sc->sc_stats.ast_tx_qstop++;
2658 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2659 IF_UNLOCK(&ifp->if_snd);
2660 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: OACTIVE, finish");
2661 return;
2662 }
2663 sc->sc_txstart_cnt++;
2664 ATH_PCU_UNLOCK(sc);
2665
2666 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_queue: start");
2667 ath_tx_kick(sc);
2668 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_queue: finished");
2669
2670 ATH_PCU_LOCK(sc);
2671 sc->sc_txstart_cnt--;
2672 ATH_PCU_UNLOCK(sc);
2673}
2674
2675void
2676ath_start_task(void *arg, int npending)
2677{
2678 struct ath_softc *sc = (struct ath_softc *) arg;
2679 struct ifnet *ifp = sc->sc_ifp;
2680
2681 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: start");
2682
2683 /* XXX is it ok to hold the ATH_LOCK here? */
2684 ATH_PCU_LOCK(sc);
2685 if (sc->sc_inreset_cnt > 0) {
2686 device_printf(sc->sc_dev,
2687 "%s: sc_inreset_cnt > 0; bailing\n", __func__);
2688 ATH_PCU_UNLOCK(sc);
2689 IF_LOCK(&ifp->if_snd);
2690 sc->sc_stats.ast_tx_qstop++;
2691 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2692 IF_UNLOCK(&ifp->if_snd);
2693 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: OACTIVE, finish");
2694 return;
2695 }
2696 sc->sc_txstart_cnt++;
2697 ATH_PCU_UNLOCK(sc);
2698
2699 ATH_TX_LOCK(sc);
2700 ath_start(sc->sc_ifp);
2701 ATH_TX_UNLOCK(sc);
2702
2703 ATH_PCU_LOCK(sc);
2704 sc->sc_txstart_cnt--;
2705 ATH_PCU_UNLOCK(sc);
2706 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: finished");
2707}
2708
2709void
2710ath_start(struct ifnet *ifp)
2711{
2712 struct ath_softc *sc = ifp->if_softc;
2713 struct ieee80211_node *ni;
2714 struct ath_buf *bf;
2715 struct mbuf *m, *next;
2716 ath_bufhead frags;
2717 int npkts = 0;
2718
2719 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid)
2720 return;
2721
2722 ATH_TX_LOCK_ASSERT(sc);
2723
2724 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start: called");
2725
2726 for (;;) {
2727 /*
2728 * Grab the frame that we're going to try and transmit.
2729 */
2730 IFQ_DEQUEUE(&ifp->if_snd, m);
2731 if (m == NULL)
2732 break;
2733 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
2734
2735 /*
2736 * Enforce how deep a node queue can get.
2737 *
2738 * XXX it would be nicer if we kept an mbuf queue per
2739 * node and only whacked them into ath_bufs when we
2740 * are ready to schedule some traffic from them.
2741 * .. that may come later.
2742 *
2743 * XXX we should also track the per-node hardware queue
2744 * depth so it is easy to limit the _SUM_ of the swq and
2745 * hwq frames. Since we only schedule two HWQ frames
2746 * at a time, this should be OK for now.
2747 */
2748 if ((!(m->m_flags & M_EAPOL)) &&
2749 (ATH_NODE(ni)->an_swq_depth > sc->sc_txq_node_maxdepth)) {
2750 sc->sc_stats.ast_tx_nodeq_overflow++;
2751 if (ni != NULL)
2752 ieee80211_free_node(ni);
2753 m_freem(m);
2754 m = NULL;
2755 continue;
2756 }
2757
2758 /*
2759 * Check how many TX buffers are available.
2760 *
2761 * If this is for non-EAPOL traffic, just leave some
2762 * space free in order for buffer cloning and raw
2763 * frame transmission to occur.
2764 *
2765 * If it's for EAPOL traffic, ignore this for now.
2766 * Management traffic will be sent via the raw transmit
2767 * method which bypasses this check.
2768 *
2769 * This is needed to ensure that EAPOL frames during
2770 * (re) keying have a chance to go out.
2771 *
2772 * See kern/138379 for more information.
2773 */
2774 if ((!(m->m_flags & M_EAPOL)) &&
2775 (sc->sc_txbuf_cnt <= sc->sc_txq_data_minfree)) {
2776 sc->sc_stats.ast_tx_nobuf++;
2777 IF_LOCK(&ifp->if_snd);
2778 _IF_PREPEND(&ifp->if_snd, m);
2779 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2780 IF_UNLOCK(&ifp->if_snd);
2781 m = NULL;
2782 break;
2783 }
2784
2785 /*
2786 * Grab a TX buffer and associated resources.
2787 *
2788 * If it's an EAPOL frame, allocate a MGMT ath_buf.
2789 * That way even with temporary buffer exhaustion due to
2790 * the data path doesn't leave us without the ability
2791 * to transmit management frames.
2792 *
2793 * Otherwise allocate a normal buffer.
2794 */
2795 if (m->m_flags & M_EAPOL)
2796 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT);
2797 else
2798 bf = ath_getbuf(sc, ATH_BUFTYPE_NORMAL);
2799
2800 if (bf == NULL) {
2801 /*
2802 * If we failed to allocate a buffer, prepend it
2803 * and continue.
2804 *
2805 * We shouldn't fail normally, due to the check
2806 * above.
2807 */
2808 sc->sc_stats.ast_tx_nobuf++;
2809 IF_LOCK(&ifp->if_snd);
2810 _IF_PREPEND(&ifp->if_snd, m);
2811 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2812 IF_UNLOCK(&ifp->if_snd);
2813 m = NULL;
2814 break;
2815 }
2816
2817 npkts ++;
2818
2819 /*
2820 * Check for fragmentation. If this frame
2821 * has been broken up verify we have enough
2822 * buffers to send all the fragments so all
2823 * go out or none...
2824 */
2825 TAILQ_INIT(&frags);
2826 if ((m->m_flags & M_FRAG) &&
2827 !ath_txfrag_setup(sc, &frags, m, ni)) {
2828 DPRINTF(sc, ATH_DEBUG_XMIT,
2829 "%s: out of txfrag buffers\n", __func__);
2830 sc->sc_stats.ast_tx_nofrag++;
2831 ifp->if_oerrors++;
2832 ath_freetx(m);
2833 goto bad;
2834 }
2835 ifp->if_opackets++;
2836 nextfrag:
2837 /*
2838 * Pass the frame to the h/w for transmission.
2839 * Fragmented frames have each frag chained together
2840 * with m_nextpkt. We know there are sufficient ath_buf's
2841 * to send all the frags because of work done by
2842 * ath_txfrag_setup. We leave m_nextpkt set while
2843 * calling ath_tx_start so it can use it to extend the
2844 * the tx duration to cover the subsequent frag and
2845 * so it can reclaim all the mbufs in case of an error;
2846 * ath_tx_start clears m_nextpkt once it commits to
2847 * handing the frame to the hardware.
2848 */
2849 next = m->m_nextpkt;
2850 if (ath_tx_start(sc, ni, bf, m)) {
2851 bad:
2852 ifp->if_oerrors++;
2853 reclaim:
2854 bf->bf_m = NULL;
2855 bf->bf_node = NULL;
2856 ATH_TXBUF_LOCK(sc);
2857 ath_returnbuf_head(sc, bf);
2858 ath_txfrag_cleanup(sc, &frags, ni);
2859 ATH_TXBUF_UNLOCK(sc);
2860 /*
2861 * XXX todo, free the node outside of
2862 * the TX lock context!
2863 */
2864 if (ni != NULL)
2865 ieee80211_free_node(ni);
2866 continue;
2867 }
2868
2869 /*
2870 * Check here if the node is in power save state.
2871 */
2872 ath_tx_update_tim(sc, ni, 1);
2873
2874 if (next != NULL) {
2875 /*
2876 * Beware of state changing between frags.
2877 * XXX check sta power-save state?
2878 */
2879 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) {
2880 DPRINTF(sc, ATH_DEBUG_XMIT,
2881 "%s: flush fragmented packet, state %s\n",
2882 __func__,
2883 ieee80211_state_name[ni->ni_vap->iv_state]);
2884 /* XXX dmamap */
2885 ath_freetx(next);
2886 goto reclaim;
2887 }
2888 m = next;
2889 bf = TAILQ_FIRST(&frags);
2890 KASSERT(bf != NULL, ("no buf for txfrag"));
2891 TAILQ_REMOVE(&frags, bf, bf_list);
2892 goto nextfrag;
2893 }
2894
2895 sc->sc_wd_timer = 5;
2896 }
2897 ATH_KTR(sc, ATH_KTR_TX, 1, "ath_start: finished; npkts=%d", npkts);
2898}
2899static int
2900ath_media_change(struct ifnet *ifp)
2901{
2902 int error = ieee80211_media_change(ifp);
2903 /* NB: only the fixed rate can change and that doesn't need a reset */
2904 return (error == ENETRESET ? 0 : error);
2905}
2906
2907/*
2908 * Block/unblock tx+rx processing while a key change is done.
2909 * We assume the caller serializes key management operations
2910 * so we only need to worry about synchronization with other
2911 * uses that originate in the driver.
2912 */
2913static void
2914ath_key_update_begin(struct ieee80211vap *vap)
2915{
2916 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2917 struct ath_softc *sc = ifp->if_softc;
2918
2919 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
2920 taskqueue_block(sc->sc_tq);
2921 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */
2922}
2923
2924static void
2925ath_key_update_end(struct ieee80211vap *vap)
2926{
2927 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2928 struct ath_softc *sc = ifp->if_softc;
2929
2930 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
2931 IF_UNLOCK(&ifp->if_snd);
2932 taskqueue_unblock(sc->sc_tq);
2933}
2934
2935static void
2936ath_update_promisc(struct ifnet *ifp)
2937{
2938 struct ath_softc *sc = ifp->if_softc;
2939 u_int32_t rfilt;
2940
2941 /* configure rx filter */
2942 rfilt = ath_calcrxfilter(sc);
2943 ath_hal_setrxfilter(sc->sc_ah, rfilt);
2944
2945 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt);
2946}
2947
2948static void
2949ath_update_mcast(struct ifnet *ifp)
2950{
2951 struct ath_softc *sc = ifp->if_softc;
2952 u_int32_t mfilt[2];
2953
2954 /* calculate and install multicast filter */
2955 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
2956 struct ifmultiaddr *ifma;
2957 /*
2958 * Merge multicast addresses to form the hardware filter.
2959 */
2960 mfilt[0] = mfilt[1] = 0;
2961 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */
2962 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2963 caddr_t dl;
2964 u_int32_t val;
2965 u_int8_t pos;
2966
2967 /* calculate XOR of eight 6bit values */
2968 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
2969 val = LE_READ_4(dl + 0);
2970 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2971 val = LE_READ_4(dl + 3);
2972 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2973 pos &= 0x3f;
2974 mfilt[pos / 32] |= (1 << (pos % 32));
2975 }
2976 if_maddr_runlock(ifp);
2977 } else
2978 mfilt[0] = mfilt[1] = ~0;
2979 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]);
2980 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n",
2981 __func__, mfilt[0], mfilt[1]);
2982}
2983
2984void
2985ath_mode_init(struct ath_softc *sc)
2986{
2987 struct ifnet *ifp = sc->sc_ifp;
2988 struct ath_hal *ah = sc->sc_ah;
2989 u_int32_t rfilt;
2990
2991 /* configure rx filter */
2992 rfilt = ath_calcrxfilter(sc);
2993 ath_hal_setrxfilter(ah, rfilt);
2994
2995 /* configure operational mode */
2996 ath_hal_setopmode(ah);
2997
2998 DPRINTF(sc, ATH_DEBUG_STATE | ATH_DEBUG_MODE,
2999 "%s: ah=%p, ifp=%p, if_addr=%p\n",
3000 __func__,
3001 ah,
3002 ifp,
3003 (ifp == NULL) ? NULL : ifp->if_addr);
3004
3005 /* handle any link-level address change */
3006 ath_hal_setmac(ah, IF_LLADDR(ifp));
3007
3008 /* calculate and install multicast filter */
3009 ath_update_mcast(ifp);
3010}
3011
3012/*
3013 * Set the slot time based on the current setting.
3014 */
3015void
3016ath_setslottime(struct ath_softc *sc)
3017{
3018 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3019 struct ath_hal *ah = sc->sc_ah;
3020 u_int usec;
3021
3022 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan))
3023 usec = 13;
3024 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan))
3025 usec = 21;
3026 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
3027 /* honor short/long slot time only in 11g */
3028 /* XXX shouldn't honor on pure g or turbo g channel */
3029 if (ic->ic_flags & IEEE80211_F_SHSLOT)
3030 usec = HAL_SLOT_TIME_9;
3031 else
3032 usec = HAL_SLOT_TIME_20;
3033 } else
3034 usec = HAL_SLOT_TIME_9;
3035
3036 DPRINTF(sc, ATH_DEBUG_RESET,
3037 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n",
3038 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags,
3039 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec);
3040
3041 ath_hal_setslottime(ah, usec);
3042 sc->sc_updateslot = OK;
3043}
3044
3045/*
3046 * Callback from the 802.11 layer to update the
3047 * slot time based on the current setting.
3048 */
3049static void
3050ath_updateslot(struct ifnet *ifp)
3051{
3052 struct ath_softc *sc = ifp->if_softc;
3053 struct ieee80211com *ic = ifp->if_l2com;
3054
3055 /*
3056 * When not coordinating the BSS, change the hardware
3057 * immediately. For other operation we defer the change
3058 * until beacon updates have propagated to the stations.
3059 */
3060 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3061 ic->ic_opmode == IEEE80211_M_MBSS)
3062 sc->sc_updateslot = UPDATE;
3063 else
3064 ath_setslottime(sc);
3065}
3066
3067/*
3068 * Append the contents of src to dst; both queues
3069 * are assumed to be locked.
3070 */
3071void
3072ath_txqmove(struct ath_txq *dst, struct ath_txq *src)
3073{
3074
3075 ATH_TXQ_LOCK_ASSERT(src);
3076 ATH_TXQ_LOCK_ASSERT(dst);
3077
3078 TAILQ_CONCAT(&dst->axq_q, &src->axq_q, bf_list);
3079 dst->axq_link = src->axq_link;
3080 src->axq_link = NULL;
3081 dst->axq_depth += src->axq_depth;
3082 dst->axq_aggr_depth += src->axq_aggr_depth;
3083 src->axq_depth = 0;
3084 src->axq_aggr_depth = 0;
3085}
3086
3087/*
3088 * Reset the hardware, with no loss.
3089 *
3090 * This can't be used for a general case reset.
3091 */
3092static void
3093ath_reset_proc(void *arg, int pending)
3094{
3095 struct ath_softc *sc = arg;
3096 struct ifnet *ifp = sc->sc_ifp;
3097
3098#if 0
3099 if_printf(ifp, "%s: resetting\n", __func__);
3100#endif
3101 ath_reset(ifp, ATH_RESET_NOLOSS);
3102}
3103
3104/*
3105 * Reset the hardware after detecting beacons have stopped.
3106 */
3107static void
3108ath_bstuck_proc(void *arg, int pending)
3109{
3110 struct ath_softc *sc = arg;
3111 struct ifnet *ifp = sc->sc_ifp;
3112 uint32_t hangs = 0;
3113
3114 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0)
3115 if_printf(ifp, "bb hang detected (0x%x)\n", hangs);
3116
3117#ifdef ATH_DEBUG_ALQ
3118 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_STUCK_BEACON))
3119 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_STUCK_BEACON, 0, NULL);
3120#endif
3121
3122 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
3123 sc->sc_bmisscount);
3124 sc->sc_stats.ast_bstuck++;
3125 /*
3126 * This assumes that there's no simultaneous channel mode change
3127 * occuring.
3128 */
3129 ath_reset(ifp, ATH_RESET_NOLOSS);
3130}
3131
3132static void
3133ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3134{
3135 bus_addr_t *paddr = (bus_addr_t*) arg;
3136 KASSERT(error == 0, ("error %u on bus_dma callback", error));
3137 *paddr = segs->ds_addr;
3138}
3139
3140/*
3141 * Allocate the descriptors and appropriate DMA tag/setup.
3142 *
3143 * For some situations (eg EDMA TX completion), there isn't a requirement
3144 * for the ath_buf entries to be allocated.
3145 */
3146int
3147ath_descdma_alloc_desc(struct ath_softc *sc,
3148 struct ath_descdma *dd, ath_bufhead *head,
3149 const char *name, int ds_size, int ndesc)
3150{
3151#define DS2PHYS(_dd, _ds) \
3152 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
3153#define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \
3154 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0)
3155 struct ifnet *ifp = sc->sc_ifp;
3156 int error;
3157
3158 dd->dd_descsize = ds_size;
3159
3160 DPRINTF(sc, ATH_DEBUG_RESET,
3161 "%s: %s DMA: %u desc, %d bytes per descriptor\n",
3162 __func__, name, ndesc, dd->dd_descsize);
3163
3164 dd->dd_name = name;
3165 dd->dd_desc_len = dd->dd_descsize * ndesc;
3166
3167 /*
3168 * Merlin work-around:
3169 * Descriptors that cross the 4KB boundary can't be used.
3170 * Assume one skipped descriptor per 4KB page.
3171 */
3172 if (! ath_hal_split4ktrans(sc->sc_ah)) {
3173 int numpages = dd->dd_desc_len / 4096;
3174 dd->dd_desc_len += ds_size * numpages;
3175 }
3176
3177 /*
3178 * Setup DMA descriptor area.
3179 *
3180 * BUS_DMA_ALLOCNOW is not used; we never use bounce
3181 * buffers for the descriptors themselves.
3182 */
3183 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
3184 PAGE_SIZE, 0, /* alignment, bounds */
3185 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
3186 BUS_SPACE_MAXADDR, /* highaddr */
3187 NULL, NULL, /* filter, filterarg */
3188 dd->dd_desc_len, /* maxsize */
3189 1, /* nsegments */
3190 dd->dd_desc_len, /* maxsegsize */
3191 0, /* flags */
3192 NULL, /* lockfunc */
3193 NULL, /* lockarg */
3194 &dd->dd_dmat);
3195 if (error != 0) {
3196 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
3197 return error;
3198 }
3199
3200 /* allocate descriptors */
3201 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc,
3202 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
3203 &dd->dd_dmamap);
3204 if (error != 0) {
3205 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
3206 "error %u\n", ndesc, dd->dd_name, error);
3207 goto fail1;
3208 }
3209
3210 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
3211 dd->dd_desc, dd->dd_desc_len,
3212 ath_load_cb, &dd->dd_desc_paddr,
3213 BUS_DMA_NOWAIT);
3214 if (error != 0) {
3215 if_printf(ifp, "unable to map %s descriptors, error %u\n",
3216 dd->dd_name, error);
3217 goto fail2;
3218 }
3219
3220 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
3221 __func__, dd->dd_name, (uint8_t *) dd->dd_desc,
3222 (u_long) dd->dd_desc_len, (caddr_t) dd->dd_desc_paddr,
3223 /*XXX*/ (u_long) dd->dd_desc_len);
3224
3225 return (0);
3226
3227fail2:
3228 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3229fail1:
3230 bus_dma_tag_destroy(dd->dd_dmat);
3231 memset(dd, 0, sizeof(*dd));
3232 return error;
3233#undef DS2PHYS
3234#undef ATH_DESC_4KB_BOUND_CHECK
3235}
3236
3237int
3238ath_descdma_setup(struct ath_softc *sc,
3239 struct ath_descdma *dd, ath_bufhead *head,
3240 const char *name, int ds_size, int nbuf, int ndesc)
3241{
3242#define DS2PHYS(_dd, _ds) \
3243 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
3244#define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \
3245 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0)
3246 struct ifnet *ifp = sc->sc_ifp;
3247 uint8_t *ds;
3248 struct ath_buf *bf;
3249 int i, bsize, error;
3250
3251 /* Allocate descriptors */
3252 error = ath_descdma_alloc_desc(sc, dd, head, name, ds_size,
3253 nbuf * ndesc);
3254
3255 /* Assume any errors during allocation were dealt with */
3256 if (error != 0) {
3257 return (error);
3258 }
3259
3260 ds = (uint8_t *) dd->dd_desc;
3261
3262 /* allocate rx buffers */
3263 bsize = sizeof(struct ath_buf) * nbuf;
3264 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
3265 if (bf == NULL) {
3266 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
3267 dd->dd_name, bsize);
3268 goto fail3;
3269 }
3270 dd->dd_bufptr = bf;
3271
3272 TAILQ_INIT(head);
3273 for (i = 0; i < nbuf; i++, bf++, ds += (ndesc * dd->dd_descsize)) {
3274 bf->bf_desc = (struct ath_desc *) ds;
3275 bf->bf_daddr = DS2PHYS(dd, ds);
3276 if (! ath_hal_split4ktrans(sc->sc_ah)) {
3277 /*
3278 * Merlin WAR: Skip descriptor addresses which
3279 * cause 4KB boundary crossing along any point
3280 * in the descriptor.
3281 */
3282 if (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr,
3283 dd->dd_descsize)) {
3284 /* Start at the next page */
3285 ds += 0x1000 - (bf->bf_daddr & 0xFFF);
3286 bf->bf_desc = (struct ath_desc *) ds;
3287 bf->bf_daddr = DS2PHYS(dd, ds);
3288 }
3289 }
3290 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
3291 &bf->bf_dmamap);
3292 if (error != 0) {
3293 if_printf(ifp, "unable to create dmamap for %s "
3294 "buffer %u, error %u\n", dd->dd_name, i, error);
3295 ath_descdma_cleanup(sc, dd, head);
3296 return error;
3297 }
3298 bf->bf_lastds = bf->bf_desc; /* Just an initial value */
3299 TAILQ_INSERT_TAIL(head, bf, bf_list);
3300 }
3301
3302 /*
3303 * XXX TODO: ensure that ds doesn't overflow the descriptor
3304 * allocation otherwise weird stuff will occur and crash your
3305 * machine.
3306 */
3307 return 0;
3308 /* XXX this should likely just call ath_descdma_cleanup() */
3309fail3:
3310 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3311 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3312 bus_dma_tag_destroy(dd->dd_dmat);
3313 memset(dd, 0, sizeof(*dd));
3314 return error;
3315#undef DS2PHYS
3316#undef ATH_DESC_4KB_BOUND_CHECK
3317}
3318
3319/*
3320 * Allocate ath_buf entries but no descriptor contents.
3321 *
3322 * This is for RX EDMA where the descriptors are the header part of
3323 * the RX buffer.
3324 */
3325int
3326ath_descdma_setup_rx_edma(struct ath_softc *sc,
3327 struct ath_descdma *dd, ath_bufhead *head,
3328 const char *name, int nbuf, int rx_status_len)
3329{
3330 struct ifnet *ifp = sc->sc_ifp;
3331 struct ath_buf *bf;
3332 int i, bsize, error;
3333
3334 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers\n",
3335 __func__, name, nbuf);
3336
3337 dd->dd_name = name;
3338 /*
3339 * This is (mostly) purely for show. We're not allocating any actual
3340 * descriptors here as EDMA RX has the descriptor be part
3341 * of the RX buffer.
3342 *
3343 * However, dd_desc_len is used by ath_descdma_free() to determine
3344 * whether we have already freed this DMA mapping.
3345 */
3346 dd->dd_desc_len = rx_status_len * nbuf;
3347 dd->dd_descsize = rx_status_len;
3348
3349 /* allocate rx buffers */
3350 bsize = sizeof(struct ath_buf) * nbuf;
3351 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
3352 if (bf == NULL) {
3353 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
3354 dd->dd_name, bsize);
3355 error = ENOMEM;
3356 goto fail3;
3357 }
3358 dd->dd_bufptr = bf;
3359
3360 TAILQ_INIT(head);
3361 for (i = 0; i < nbuf; i++, bf++) {
3362 bf->bf_desc = NULL;
3363 bf->bf_daddr = 0;
3364 bf->bf_lastds = NULL; /* Just an initial value */
3365
3366 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
3367 &bf->bf_dmamap);
3368 if (error != 0) {
3369 if_printf(ifp, "unable to create dmamap for %s "
3370 "buffer %u, error %u\n", dd->dd_name, i, error);
3371 ath_descdma_cleanup(sc, dd, head);
3372 return error;
3373 }
3374 TAILQ_INSERT_TAIL(head, bf, bf_list);
3375 }
3376 return 0;
3377fail3:
3378 memset(dd, 0, sizeof(*dd));
3379 return error;
3380}
3381
3382void
3383ath_descdma_cleanup(struct ath_softc *sc,
3384 struct ath_descdma *dd, ath_bufhead *head)
3385{
3386 struct ath_buf *bf;
3387 struct ieee80211_node *ni;
3388 int do_warning = 0;
3389
3390 if (dd->dd_dmamap != 0) {
3391 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3392 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3393 bus_dma_tag_destroy(dd->dd_dmat);
3394 }
3395
3396 if (head != NULL) {
3397 TAILQ_FOREACH(bf, head, bf_list) {
3398 if (bf->bf_m) {
3399 /*
3400 * XXX warn if there's buffers here.
3401 * XXX it should have been freed by the
3402 * owner!
3403 */
3404
3405 if (do_warning == 0) {
3406 do_warning = 1;
3407 device_printf(sc->sc_dev,
3408 "%s: %s: mbuf should've been"
3409 " unmapped/freed!\n",
3410 __func__,
3411 dd->dd_name);
3412 }
3413 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3414 BUS_DMASYNC_POSTREAD);
3415 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3416 m_freem(bf->bf_m);
3417 bf->bf_m = NULL;
3418 }
3419 if (bf->bf_dmamap != NULL) {
3420 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
3421 bf->bf_dmamap = NULL;
3422 }
3423 ni = bf->bf_node;
3424 bf->bf_node = NULL;
3425 if (ni != NULL) {
3426 /*
3427 * Reclaim node reference.
3428 */
3429 ieee80211_free_node(ni);
3430 }
3431 }
3432 }
3433
3434 if (head != NULL)
3435 TAILQ_INIT(head);
3436
3437 if (dd->dd_bufptr != NULL)
3438 free(dd->dd_bufptr, M_ATHDEV);
3439 memset(dd, 0, sizeof(*dd));
3440}
3441
3442static int
3443ath_desc_alloc(struct ath_softc *sc)
3444{
3445 int error;
3446
3447 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
3448 "tx", sc->sc_tx_desclen, ath_txbuf, ATH_MAX_SCATTER);
3449 if (error != 0) {
3450 return error;
3451 }
3452 sc->sc_txbuf_cnt = ath_txbuf;
3453
3454 error = ath_descdma_setup(sc, &sc->sc_txdma_mgmt, &sc->sc_txbuf_mgmt,
3455 "tx_mgmt", sc->sc_tx_desclen, ath_txbuf_mgmt,
3456 ATH_TXDESC);
3457 if (error != 0) {
3458 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3459 return error;
3460 }
3461
3462 /*
3463 * XXX mark txbuf_mgmt frames with ATH_BUF_MGMT, so the
3464 * flag doesn't have to be set in ath_getbuf_locked().
3465 */
3466
3467 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
3468 "beacon", sc->sc_tx_desclen, ATH_BCBUF, 1);
3469 if (error != 0) {
3470 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3471 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
3472 &sc->sc_txbuf_mgmt);
3473 return error;
3474 }
3475 return 0;
3476}
3477
3478static void
3479ath_desc_free(struct ath_softc *sc)
3480{
3481
3482 if (sc->sc_bdma.dd_desc_len != 0)
3483 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
3484 if (sc->sc_txdma.dd_desc_len != 0)
3485 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3486 if (sc->sc_txdma_mgmt.dd_desc_len != 0)
3487 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
3488 &sc->sc_txbuf_mgmt);
3489}
3490
3491static struct ieee80211_node *
3492ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
3493{
3494 struct ieee80211com *ic = vap->iv_ic;
3495 struct ath_softc *sc = ic->ic_ifp->if_softc;
3496 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
3497 struct ath_node *an;
3498
3499 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
3500 if (an == NULL) {
3501 /* XXX stat+msg */
3502 return NULL;
3503 }
3504 ath_rate_node_init(sc, an);
3505
3506 /* Setup the mutex - there's no associd yet so set the name to NULL */
3507 snprintf(an->an_name, sizeof(an->an_name), "%s: node %p",
3508 device_get_nameunit(sc->sc_dev), an);
3509 mtx_init(&an->an_mtx, an->an_name, NULL, MTX_DEF);
3510
3511 /* XXX setup ath_tid */
3512 ath_tx_tid_init(sc, an);
3513
3514 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, mac, ":", an);
3515 return &an->an_node;
3516}
3517
3518static void
3519ath_node_cleanup(struct ieee80211_node *ni)
3520{
3521 struct ieee80211com *ic = ni->ni_ic;
3522 struct ath_softc *sc = ic->ic_ifp->if_softc;
3523
3524 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__,
3525 ni->ni_macaddr, ":", ATH_NODE(ni));
3526
3527 /* Cleanup ath_tid, free unused bufs, unlink bufs in TXQ */
3528 ath_tx_node_flush(sc, ATH_NODE(ni));
3529 ath_rate_node_cleanup(sc, ATH_NODE(ni));
3530 sc->sc_node_cleanup(ni);
3531}
3532
3533static void
3534ath_node_free(struct ieee80211_node *ni)
3535{
3536 struct ieee80211com *ic = ni->ni_ic;
3537 struct ath_softc *sc = ic->ic_ifp->if_softc;
3538
3539 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__,
3540 ni->ni_macaddr, ":", ATH_NODE(ni));
3541 mtx_destroy(&ATH_NODE(ni)->an_mtx);
3542 sc->sc_node_free(ni);
3543}
3544
3545static void
3546ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise)
3547{
3548 struct ieee80211com *ic = ni->ni_ic;
3549 struct ath_softc *sc = ic->ic_ifp->if_softc;
3550 struct ath_hal *ah = sc->sc_ah;
3551
3552 *rssi = ic->ic_node_getrssi(ni);
3553 if (ni->ni_chan != IEEE80211_CHAN_ANYC)
3554 *noise = ath_hal_getchannoise(ah, ni->ni_chan);
3555 else
3556 *noise = -95; /* nominally correct */
3557}
3558
3559/*
3560 * Set the default antenna.
3561 */
3562void
3563ath_setdefantenna(struct ath_softc *sc, u_int antenna)
3564{
3565 struct ath_hal *ah = sc->sc_ah;
3566
3567 /* XXX block beacon interrupts */
3568 ath_hal_setdefantenna(ah, antenna);
3569 if (sc->sc_defant != antenna)
3570 sc->sc_stats.ast_ant_defswitch++;
3571 sc->sc_defant = antenna;
3572 sc->sc_rxotherant = 0;
3573}
3574
3575static void
3576ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum)
3577{
3578 txq->axq_qnum = qnum;
3579 txq->axq_ac = 0;
3580 txq->axq_depth = 0;
3581 txq->axq_aggr_depth = 0;
3582 txq->axq_intrcnt = 0;
3583 txq->axq_link = NULL;
3584 txq->axq_softc = sc;
3585 TAILQ_INIT(&txq->axq_q);
3586 TAILQ_INIT(&txq->axq_tidq);
3587 TAILQ_INIT(&txq->fifo.axq_q);
3588 ATH_TXQ_LOCK_INIT(sc, txq);
3589}
3590
3591/*
3592 * Setup a h/w transmit queue.
3593 */
3594static struct ath_txq *
3595ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
3596{
3597#define N(a) (sizeof(a)/sizeof(a[0]))
3598 struct ath_hal *ah = sc->sc_ah;
3599 HAL_TXQ_INFO qi;
3600 int qnum;
3601
3602 memset(&qi, 0, sizeof(qi));
3603 qi.tqi_subtype = subtype;
3604 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
3605 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
3606 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
3607 /*
3608 * Enable interrupts only for EOL and DESC conditions.
3609 * We mark tx descriptors to receive a DESC interrupt
3610 * when a tx queue gets deep; otherwise waiting for the
3611 * EOL to reap descriptors. Note that this is done to
3612 * reduce interrupt load and this only defers reaping
3613 * descriptors, never transmitting frames. Aside from
3614 * reducing interrupts this also permits more concurrency.
3615 * The only potential downside is if the tx queue backs
3616 * up in which case the top half of the kernel may backup
3617 * due to a lack of tx descriptors.
3618 */
3619 if (sc->sc_isedma)
3620 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE |
3621 HAL_TXQ_TXOKINT_ENABLE;
3622 else
3623 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE |
3624 HAL_TXQ_TXDESCINT_ENABLE;
3625
3626 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
3627 if (qnum == -1) {
3628 /*
3629 * NB: don't print a message, this happens
3630 * normally on parts with too few tx queues
3631 */
3632 return NULL;
3633 }
3634 if (qnum >= N(sc->sc_txq)) {
3635 device_printf(sc->sc_dev,
3636 "hal qnum %u out of range, max %zu!\n",
3637 qnum, N(sc->sc_txq));
3638 ath_hal_releasetxqueue(ah, qnum);
3639 return NULL;
3640 }
3641 if (!ATH_TXQ_SETUP(sc, qnum)) {
3642 ath_txq_init(sc, &sc->sc_txq[qnum], qnum);
3643 sc->sc_txqsetup |= 1<<qnum;
3644 }
3645 return &sc->sc_txq[qnum];
3646#undef N
3647}
3648
3649/*
3650 * Setup a hardware data transmit queue for the specified
3651 * access control. The hal may not support all requested
3652 * queues in which case it will return a reference to a
3653 * previously setup queue. We record the mapping from ac's
3654 * to h/w queues for use by ath_tx_start and also track
3655 * the set of h/w queues being used to optimize work in the
3656 * transmit interrupt handler and related routines.
3657 */
3658static int
3659ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
3660{
3661#define N(a) (sizeof(a)/sizeof(a[0]))
3662 struct ath_txq *txq;
3663
3664 if (ac >= N(sc->sc_ac2q)) {
3665 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
3666 ac, N(sc->sc_ac2q));
3667 return 0;
3668 }
3669 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
3670 if (txq != NULL) {
3671 txq->axq_ac = ac;
3672 sc->sc_ac2q[ac] = txq;
3673 return 1;
3674 } else
3675 return 0;
3676#undef N
3677}
3678
3679/*
3680 * Update WME parameters for a transmit queue.
3681 */
3682static int
3683ath_txq_update(struct ath_softc *sc, int ac)
3684{
3685#define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
3686#define ATH_TXOP_TO_US(v) (v<<5)
3687 struct ifnet *ifp = sc->sc_ifp;
3688 struct ieee80211com *ic = ifp->if_l2com;
3689 struct ath_txq *txq = sc->sc_ac2q[ac];
3690 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
3691 struct ath_hal *ah = sc->sc_ah;
3692 HAL_TXQ_INFO qi;
3693
3694 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
3695#ifdef IEEE80211_SUPPORT_TDMA
3696 if (sc->sc_tdma) {
3697 /*
3698 * AIFS is zero so there's no pre-transmit wait. The
3699 * burst time defines the slot duration and is configured
3700 * through net80211. The QCU is setup to not do post-xmit
3701 * back off, lockout all lower-priority QCU's, and fire
3702 * off the DMA beacon alert timer which is setup based
3703 * on the slot configuration.
3704 */
3705 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
3706 | HAL_TXQ_TXERRINT_ENABLE
3707 | HAL_TXQ_TXURNINT_ENABLE
3708 | HAL_TXQ_TXEOLINT_ENABLE
3709 | HAL_TXQ_DBA_GATED
3710 | HAL_TXQ_BACKOFF_DISABLE
3711 | HAL_TXQ_ARB_LOCKOUT_GLOBAL
3712 ;
3713 qi.tqi_aifs = 0;
3714 /* XXX +dbaprep? */
3715 qi.tqi_readyTime = sc->sc_tdmaslotlen;
3716 qi.tqi_burstTime = qi.tqi_readyTime;
3717 } else {
3718#endif
3719 /*
3720 * XXX shouldn't this just use the default flags
3721 * used in the previous queue setup?
3722 */
3723 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
3724 | HAL_TXQ_TXERRINT_ENABLE
3725 | HAL_TXQ_TXDESCINT_ENABLE
3726 | HAL_TXQ_TXURNINT_ENABLE
3727 | HAL_TXQ_TXEOLINT_ENABLE
3728 ;
3729 qi.tqi_aifs = wmep->wmep_aifsn;
3730 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
3731 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
3732 qi.tqi_readyTime = 0;
3733 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
3734#ifdef IEEE80211_SUPPORT_TDMA
3735 }
3736#endif
3737
3738 DPRINTF(sc, ATH_DEBUG_RESET,
3739 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n",
3740 __func__, txq->axq_qnum, qi.tqi_qflags,
3741 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime);
3742
3743 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
3744 if_printf(ifp, "unable to update hardware queue "
3745 "parameters for %s traffic!\n",
3746 ieee80211_wme_acnames[ac]);
3747 return 0;
3748 } else {
3749 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
3750 return 1;
3751 }
3752#undef ATH_TXOP_TO_US
3753#undef ATH_EXPONENT_TO_VALUE
3754}
3755
3756/*
3757 * Callback from the 802.11 layer to update WME parameters.
3758 */
3759int
3760ath_wme_update(struct ieee80211com *ic)
3761{
3762 struct ath_softc *sc = ic->ic_ifp->if_softc;
3763
3764 return !ath_txq_update(sc, WME_AC_BE) ||
3765 !ath_txq_update(sc, WME_AC_BK) ||
3766 !ath_txq_update(sc, WME_AC_VI) ||
3767 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
3768}
3769
3770/*
3771 * Reclaim resources for a setup queue.
3772 */
3773static void
3774ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
3775{
3776
3777 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
3778 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
3779 ATH_TXQ_LOCK_DESTROY(txq);
3780}
3781
3782/*
3783 * Reclaim all tx queue resources.
3784 */
3785static void
3786ath_tx_cleanup(struct ath_softc *sc)
3787{
3788 int i;
3789
3790 ATH_TXBUF_LOCK_DESTROY(sc);
3791 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3792 if (ATH_TXQ_SETUP(sc, i))
3793 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
3794}
3795
3796/*
3797 * Return h/w rate index for an IEEE rate (w/o basic rate bit)
3798 * using the current rates in sc_rixmap.
3799 */
3800int
3801ath_tx_findrix(const struct ath_softc *sc, uint8_t rate)
3802{
3803 int rix = sc->sc_rixmap[rate];
3804 /* NB: return lowest rix for invalid rate */
3805 return (rix == 0xff ? 0 : rix);
3806}
3807
3808static void
3809ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts,
3810 struct ath_buf *bf)
3811{
3812 struct ieee80211_node *ni = bf->bf_node;
3813 struct ifnet *ifp = sc->sc_ifp;
3814 struct ieee80211com *ic = ifp->if_l2com;
3815 int sr, lr, pri;
3816
3817 if (ts->ts_status == 0) {
3818 u_int8_t txant = ts->ts_antenna;
3819 sc->sc_stats.ast_ant_tx[txant]++;
3820 sc->sc_ant_tx[txant]++;
3821 if (ts->ts_finaltsi != 0)
3822 sc->sc_stats.ast_tx_altrate++;
3823 pri = M_WME_GETAC(bf->bf_m);
3824 if (pri >= WME_AC_VO)
3825 ic->ic_wme.wme_hipri_traffic++;
3826 if ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)
3827 ni->ni_inact = ni->ni_inact_reload;
3828 } else {
3829 if (ts->ts_status & HAL_TXERR_XRETRY)
3830 sc->sc_stats.ast_tx_xretries++;
3831 if (ts->ts_status & HAL_TXERR_FIFO)
3832 sc->sc_stats.ast_tx_fifoerr++;
3833 if (ts->ts_status & HAL_TXERR_FILT)
3834 sc->sc_stats.ast_tx_filtered++;
3835 if (ts->ts_status & HAL_TXERR_XTXOP)
3836 sc->sc_stats.ast_tx_xtxop++;
3837 if (ts->ts_status & HAL_TXERR_TIMER_EXPIRED)
3838 sc->sc_stats.ast_tx_timerexpired++;
3839
3840 if (bf->bf_m->m_flags & M_FF)
3841 sc->sc_stats.ast_ff_txerr++;
3842 }
3843 /* XXX when is this valid? */
3844 if (ts->ts_flags & HAL_TX_DESC_CFG_ERR)
3845 sc->sc_stats.ast_tx_desccfgerr++;
3846 /*
3847 * This can be valid for successful frame transmission!
3848 * If there's a TX FIFO underrun during aggregate transmission,
3849 * the MAC will pad the rest of the aggregate with delimiters.
3850 * If a BA is returned, the frame is marked as "OK" and it's up
3851 * to the TX completion code to notice which frames weren't
3852 * successfully transmitted.
3853 */
3854 if (ts->ts_flags & HAL_TX_DATA_UNDERRUN)
3855 sc->sc_stats.ast_tx_data_underrun++;
3856 if (ts->ts_flags & HAL_TX_DELIM_UNDERRUN)
3857 sc->sc_stats.ast_tx_delim_underrun++;
3858
3859 sr = ts->ts_shortretry;
3860 lr = ts->ts_longretry;
3861 sc->sc_stats.ast_tx_shortretry += sr;
3862 sc->sc_stats.ast_tx_longretry += lr;
3863
3864}
3865
3866/*
3867 * The default completion. If fail is 1, this means
3868 * "please don't retry the frame, and just return -1 status
3869 * to the net80211 stack.
3870 */
3871void
3872ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
3873{
3874 struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
3875 int st;
3876
3877 if (fail == 1)
3878 st = -1;
3879 else
3880 st = ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) ?
3881 ts->ts_status : HAL_TXERR_XRETRY;
3882
3883#if 0
3884 if (bf->bf_state.bfs_dobaw)
3885 device_printf(sc->sc_dev,
3886 "%s: bf %p: seqno %d: dobaw should've been cleared!\n",
3887 __func__,
3888 bf,
3889 SEQNO(bf->bf_state.bfs_seqno));
3890#endif
3891 if (bf->bf_next != NULL)
3892 device_printf(sc->sc_dev,
3893 "%s: bf %p: seqno %d: bf_next not NULL!\n",
3894 __func__,
3895 bf,
3896 SEQNO(bf->bf_state.bfs_seqno));
3897
3898 /*
3899 * Check if the node software queue is empty; if so
3900 * then clear the TIM.
3901 *
3902 * This needs to be done before the buffer is freed as
3903 * otherwise the node reference will have been released
3904 * and the node may not actually exist any longer.
3905 *
3906 * XXX I don't like this belonging here, but it's cleaner
3907 * to do it here right now then all the other places
3908 * where ath_tx_default_comp() is called.
3909 *
3910 * XXX TODO: during drain, ensure that the callback is
3911 * being called so we get a chance to update the TIM.
3912 */
3913 if (bf->bf_node) {
3914 ATH_TX_LOCK(sc);
3915 ath_tx_update_tim(sc, bf->bf_node, 0);
3916 ATH_TX_UNLOCK(sc);
3917 }
3918
3919 /*
3920 * Do any tx complete callback. Note this must
3921 * be done before releasing the node reference.
3922 * This will free the mbuf, release the net80211
3923 * node and recycle the ath_buf.
3924 */
3925 ath_tx_freebuf(sc, bf, st);
3926}
3927
3928/*
3929 * Update rate control with the given completion status.
3930 */
3931void
3932ath_tx_update_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni,
3933 struct ath_rc_series *rc, struct ath_tx_status *ts, int frmlen,
3934 int nframes, int nbad)
3935{
3936 struct ath_node *an;
3937
3938 /* Only for unicast frames */
3939 if (ni == NULL)
3940 return;
3941
3942 an = ATH_NODE(ni);
3943 ATH_NODE_UNLOCK_ASSERT(an);
3944
3945 if ((ts->ts_status & HAL_TXERR_FILT) == 0) {
3946 ATH_NODE_LOCK(an);
3947 ath_rate_tx_complete(sc, an, rc, ts, frmlen, nframes, nbad);
3948 ATH_NODE_UNLOCK(an);
3949 }
3950}
3951
3952/*
3953 * Process the completion of the given buffer.
3954 *
3955 * This calls the rate control update and then the buffer completion.
3956 * This will either free the buffer or requeue it. In any case, the
3957 * bf pointer should be treated as invalid after this function is called.
3958 */
3959void
3960ath_tx_process_buf_completion(struct ath_softc *sc, struct ath_txq *txq,
3961 struct ath_tx_status *ts, struct ath_buf *bf)
3962{
3963 struct ieee80211_node *ni = bf->bf_node;
3964 struct ath_node *an = NULL;
3965
3966 ATH_TX_UNLOCK_ASSERT(sc);
3967 ATH_TXQ_UNLOCK_ASSERT(txq);
3968
3969 /* If unicast frame, update general statistics */
3970 if (ni != NULL) {
3971 an = ATH_NODE(ni);
3972 /* update statistics */
3973 ath_tx_update_stats(sc, ts, bf);
3974 }
3975
3976 /*
3977 * Call the completion handler.
3978 * The completion handler is responsible for
3979 * calling the rate control code.
3980 *
3981 * Frames with no completion handler get the
3982 * rate control code called here.
3983 */
3984 if (bf->bf_comp == NULL) {
3985 if ((ts->ts_status & HAL_TXERR_FILT) == 0 &&
3986 (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) {
3987 /*
3988 * XXX assume this isn't an aggregate
3989 * frame.
3990 */
3991 ath_tx_update_ratectrl(sc, ni,
3992 bf->bf_state.bfs_rc, ts,
3993 bf->bf_state.bfs_pktlen, 1,
3994 (ts->ts_status == 0 ? 0 : 1));
3995 }
3996 ath_tx_default_comp(sc, bf, 0);
3997 } else
3998 bf->bf_comp(sc, bf, 0);
3999}
4000
4001
4002
4003/*
4004 * Process completed xmit descriptors from the specified queue.
4005 * Kick the packet scheduler if needed. This can occur from this
4006 * particular task.
4007 */
4008static int
4009ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, int dosched)
4010{
4011 struct ath_hal *ah = sc->sc_ah;
4012 struct ath_buf *bf;
4013 struct ath_desc *ds;
4014 struct ath_tx_status *ts;
4015 struct ieee80211_node *ni;
4016#ifdef IEEE80211_SUPPORT_SUPERG
4017 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
4018#endif /* IEEE80211_SUPPORT_SUPERG */
4019 int nacked;
4020 HAL_STATUS status;
4021
4022 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
4023 __func__, txq->axq_qnum,
4024 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4025 txq->axq_link);
4026
4027 ATH_KTR(sc, ATH_KTR_TXCOMP, 4,
4028 "ath_tx_processq: txq=%u head %p link %p depth %p",
4029 txq->axq_qnum,
4030 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4031 txq->axq_link,
4032 txq->axq_depth);
4033
4034 nacked = 0;
4035 for (;;) {
4036 ATH_TXQ_LOCK(txq);
4037 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
4038 bf = TAILQ_FIRST(&txq->axq_q);
4039 if (bf == NULL) {
4040 ATH_TXQ_UNLOCK(txq);
4041 break;
4042 }
4043 ds = bf->bf_lastds; /* XXX must be setup correctly! */
4044 ts = &bf->bf_status.ds_txstat;
4045
4046 status = ath_hal_txprocdesc(ah, ds, ts);
4047#ifdef ATH_DEBUG
4048 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
4049 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4050 status == HAL_OK);
4051 else if ((sc->sc_debug & ATH_DEBUG_RESET) && (dosched == 0))
4052 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4053 status == HAL_OK);
4054#endif
4055#ifdef ATH_DEBUG_ALQ
4056 if (if_ath_alq_checkdebug(&sc->sc_alq,
4057 ATH_ALQ_EDMA_TXSTATUS)) {
4058 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS,
4059 sc->sc_tx_statuslen,
4060 (char *) ds);
4061 }
4062#endif
4063
4064 if (status == HAL_EINPROGRESS) {
4065 ATH_KTR(sc, ATH_KTR_TXCOMP, 3,
4066 "ath_tx_processq: txq=%u, bf=%p ds=%p, HAL_EINPROGRESS",
4067 txq->axq_qnum, bf, ds);
4068 ATH_TXQ_UNLOCK(txq);
4069 break;
4070 }
4071 ATH_TXQ_REMOVE(txq, bf, bf_list);
4072
4073 /*
4074 * Sanity check.
4075 */
4076 if (txq->axq_qnum != bf->bf_state.bfs_tx_queue) {
4077 device_printf(sc->sc_dev,
4078 "%s: TXQ=%d: bf=%p, bfs_tx_queue=%d\n",
4079 __func__,
4080 txq->axq_qnum,
4081 bf,
4082 bf->bf_state.bfs_tx_queue);
4083 }
4084 if (txq->axq_qnum != bf->bf_last->bf_state.bfs_tx_queue) {
4085 device_printf(sc->sc_dev,
4086 "%s: TXQ=%d: bf_last=%p, bfs_tx_queue=%d\n",
4087 __func__,
4088 txq->axq_qnum,
4089 bf->bf_last,
4090 bf->bf_last->bf_state.bfs_tx_queue);
4091 }
4092
4093#if 0
4094 if (txq->axq_depth > 0) {
4095 /*
4096 * More frames follow. Mark the buffer busy
4097 * so it's not re-used while the hardware may
4098 * still re-read the link field in the descriptor.
4099 *
4100 * Use the last buffer in an aggregate as that
4101 * is where the hardware may be - intermediate
4102 * descriptors won't be "busy".
4103 */
4104 bf->bf_last->bf_flags |= ATH_BUF_BUSY;
4105 } else
4106 txq->axq_link = NULL;
4107#else
4108 bf->bf_last->bf_flags |= ATH_BUF_BUSY;
4109#endif
4110 if (bf->bf_state.bfs_aggr)
4111 txq->axq_aggr_depth--;
4112
4113 ni = bf->bf_node;
4114
4115 ATH_KTR(sc, ATH_KTR_TXCOMP, 5,
4116 "ath_tx_processq: txq=%u, bf=%p, ds=%p, ni=%p, ts_status=0x%08x",
4117 txq->axq_qnum, bf, ds, ni, ts->ts_status);
4118 /*
4119 * If unicast frame was ack'd update RSSI,
4120 * including the last rx time used to
4121 * workaround phantom bmiss interrupts.
4122 */
4123 if (ni != NULL && ts->ts_status == 0 &&
4124 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) {
4125 nacked++;
4126 sc->sc_stats.ast_tx_rssi = ts->ts_rssi;
4127 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
4128 ts->ts_rssi);
4129 }
4130 ATH_TXQ_UNLOCK(txq);
4131
4132 /*
4133 * Update statistics and call completion
4134 */
4135 ath_tx_process_buf_completion(sc, txq, ts, bf);
4136
4137 /* XXX at this point, bf and ni may be totally invalid */
4138 }
4139#ifdef IEEE80211_SUPPORT_SUPERG
4140 /*
4141 * Flush fast-frame staging queue when traffic slows.
4142 */
4143 if (txq->axq_depth <= 1)
4144 ieee80211_ff_flush(ic, txq->axq_ac);
4145#endif
4146
4147 /* Kick the software TXQ scheduler */
4148 if (dosched) {
4149 ATH_TX_LOCK(sc);
4150 ath_txq_sched(sc, txq);
4151 ATH_TX_UNLOCK(sc);
4152 }
4153
4154 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4155 "ath_tx_processq: txq=%u: done",
4156 txq->axq_qnum);
4157
4158 return nacked;
4159}
4160
4161#define TXQACTIVE(t, q) ( (t) & (1 << (q)))
4162
4163/*
4164 * Deferred processing of transmit interrupt; special-cased
4165 * for a single hardware transmit queue (e.g. 5210 and 5211).
4166 */
4167static void
4168ath_tx_proc_q0(void *arg, int npending)
4169{
4170 struct ath_softc *sc = arg;
4171 struct ifnet *ifp = sc->sc_ifp;
4172 uint32_t txqs;
4173
4174 ATH_PCU_LOCK(sc);
4175 sc->sc_txproc_cnt++;
4176 txqs = sc->sc_txq_active;
4177 sc->sc_txq_active &= ~txqs;
4178 ATH_PCU_UNLOCK(sc);
4179
4180 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4181 "ath_tx_proc_q0: txqs=0x%08x", txqs);
4182
4183 if (TXQACTIVE(txqs, 0) && ath_tx_processq(sc, &sc->sc_txq[0], 1))
4184 /* XXX why is lastrx updated in tx code? */
4185 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4186 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
4187 ath_tx_processq(sc, sc->sc_cabq, 1);
4188 IF_LOCK(&ifp->if_snd);
4189 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4190 IF_UNLOCK(&ifp->if_snd);
4191 sc->sc_wd_timer = 0;
4192
4193 if (sc->sc_softled)
4194 ath_led_event(sc, sc->sc_txrix);
4195
4196 ATH_PCU_LOCK(sc);
4197 sc->sc_txproc_cnt--;
4198 ATH_PCU_UNLOCK(sc);
4199
4200 ath_tx_kick(sc);
4201}
4202
4203/*
4204 * Deferred processing of transmit interrupt; special-cased
4205 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
4206 */
4207static void
4208ath_tx_proc_q0123(void *arg, int npending)
4209{
4210 struct ath_softc *sc = arg;
4211 struct ifnet *ifp = sc->sc_ifp;
4212 int nacked;
4213 uint32_t txqs;
4214
4215 ATH_PCU_LOCK(sc);
4216 sc->sc_txproc_cnt++;
4217 txqs = sc->sc_txq_active;
4218 sc->sc_txq_active &= ~txqs;
4219 ATH_PCU_UNLOCK(sc);
4220
4221 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4222 "ath_tx_proc_q0123: txqs=0x%08x", txqs);
4223
4224 /*
4225 * Process each active queue.
4226 */
4227 nacked = 0;
4228 if (TXQACTIVE(txqs, 0))
4229 nacked += ath_tx_processq(sc, &sc->sc_txq[0], 1);
4230 if (TXQACTIVE(txqs, 1))
4231 nacked += ath_tx_processq(sc, &sc->sc_txq[1], 1);
4232 if (TXQACTIVE(txqs, 2))
4233 nacked += ath_tx_processq(sc, &sc->sc_txq[2], 1);
4234 if (TXQACTIVE(txqs, 3))
4235 nacked += ath_tx_processq(sc, &sc->sc_txq[3], 1);
4236 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
4237 ath_tx_processq(sc, sc->sc_cabq, 1);
4238 if (nacked)
4239 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4240
4241 IF_LOCK(&ifp->if_snd);
4242 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4243 IF_UNLOCK(&ifp->if_snd);
4244 sc->sc_wd_timer = 0;
4245
4246 if (sc->sc_softled)
4247 ath_led_event(sc, sc->sc_txrix);
4248
4249 ATH_PCU_LOCK(sc);
4250 sc->sc_txproc_cnt--;
4251 ATH_PCU_UNLOCK(sc);
4252
4253 ath_tx_kick(sc);
4254}
4255
4256/*
4257 * Deferred processing of transmit interrupt.
4258 */
4259static void
4260ath_tx_proc(void *arg, int npending)
4261{
4262 struct ath_softc *sc = arg;
4263 struct ifnet *ifp = sc->sc_ifp;
4264 int i, nacked;
4265 uint32_t txqs;
4266
4267 ATH_PCU_LOCK(sc);
4268 sc->sc_txproc_cnt++;
4269 txqs = sc->sc_txq_active;
4270 sc->sc_txq_active &= ~txqs;
4271 ATH_PCU_UNLOCK(sc);
4272
4273 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, "ath_tx_proc: txqs=0x%08x", txqs);
4274
4275 /*
4276 * Process each active queue.
4277 */
4278 nacked = 0;
4279 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4280 if (ATH_TXQ_SETUP(sc, i) && TXQACTIVE(txqs, i))
4281 nacked += ath_tx_processq(sc, &sc->sc_txq[i], 1);
4282 if (nacked)
4283 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4284
4285 /* XXX check this inside of IF_LOCK? */
4286 IF_LOCK(&ifp->if_snd);
4287 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4288 IF_UNLOCK(&ifp->if_snd);
4289 sc->sc_wd_timer = 0;
4290
4291 if (sc->sc_softled)
4292 ath_led_event(sc, sc->sc_txrix);
4293
4294 ATH_PCU_LOCK(sc);
4295 sc->sc_txproc_cnt--;
4296 ATH_PCU_UNLOCK(sc);
4297
4298 ath_tx_kick(sc);
4299}
4300#undef TXQACTIVE
4301
4302/*
4303 * Deferred processing of TXQ rescheduling.
4304 */
4305static void
4306ath_txq_sched_tasklet(void *arg, int npending)
4307{
4308 struct ath_softc *sc = arg;
4309 int i;
4310
4311 /* XXX is skipping ok? */
4312 ATH_PCU_LOCK(sc);
4313#if 0
4314 if (sc->sc_inreset_cnt > 0) {
4315 device_printf(sc->sc_dev,
4316 "%s: sc_inreset_cnt > 0; skipping\n", __func__);
4317 ATH_PCU_UNLOCK(sc);
4318 return;
4319 }
4320#endif
4321 sc->sc_txproc_cnt++;
4322 ATH_PCU_UNLOCK(sc);
4323
4324 ATH_TX_LOCK(sc);
4325 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
4326 if (ATH_TXQ_SETUP(sc, i)) {
4327 ath_txq_sched(sc, &sc->sc_txq[i]);
4328 }
4329 }
4330 ATH_TX_UNLOCK(sc);
4331
4332 ATH_PCU_LOCK(sc);
4333 sc->sc_txproc_cnt--;
4334 ATH_PCU_UNLOCK(sc);
4335}
4336
4337void
4338ath_returnbuf_tail(struct ath_softc *sc, struct ath_buf *bf)
4339{
4340
4341 ATH_TXBUF_LOCK_ASSERT(sc);
4342
4343 if (bf->bf_flags & ATH_BUF_MGMT)
4344 TAILQ_INSERT_TAIL(&sc->sc_txbuf_mgmt, bf, bf_list);
4345 else {
4346 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
4347 sc->sc_txbuf_cnt++;
4348 if (sc->sc_txbuf_cnt > ath_txbuf) {
4349 device_printf(sc->sc_dev,
4350 "%s: sc_txbuf_cnt > %d?\n",
4351 __func__,
4352 ath_txbuf);
4353 sc->sc_txbuf_cnt = ath_txbuf;
4354 }
4355 }
4356}
4357
4358void
4359ath_returnbuf_head(struct ath_softc *sc, struct ath_buf *bf)
4360{
4361
4362 ATH_TXBUF_LOCK_ASSERT(sc);
4363
4364 if (bf->bf_flags & ATH_BUF_MGMT)
4365 TAILQ_INSERT_HEAD(&sc->sc_txbuf_mgmt, bf, bf_list);
4366 else {
4367 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
4368 sc->sc_txbuf_cnt++;
4369 if (sc->sc_txbuf_cnt > ATH_TXBUF) {
4370 device_printf(sc->sc_dev,
4371 "%s: sc_txbuf_cnt > %d?\n",
4372 __func__,
4373 ATH_TXBUF);
4374 sc->sc_txbuf_cnt = ATH_TXBUF;
4375 }
4376 }
4377}
4378
4379/*
4380 * Free the holding buffer if it exists
4381 */
4382void
4383ath_txq_freeholdingbuf(struct ath_softc *sc, struct ath_txq *txq)
4384{
4385 ATH_TXBUF_UNLOCK_ASSERT(sc);
4386 ATH_TXQ_LOCK_ASSERT(txq);
4387
4388 if (txq->axq_holdingbf == NULL)
4389 return;
4390
4391 txq->axq_holdingbf->bf_flags &= ~ATH_BUF_BUSY;
4392
4393 ATH_TXBUF_LOCK(sc);
4394 ath_returnbuf_tail(sc, txq->axq_holdingbf);
4395 ATH_TXBUF_UNLOCK(sc);
4396
4397 txq->axq_holdingbf = NULL;
4398}
4399
4400/*
4401 * Add this buffer to the holding queue, freeing the previous
4402 * one if it exists.
4403 */
4404static void
4405ath_txq_addholdingbuf(struct ath_softc *sc, struct ath_buf *bf)
4406{
4407 struct ath_txq *txq;
4408
4409 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue];
4410
4411 ATH_TXBUF_UNLOCK_ASSERT(sc);
4412 ATH_TXQ_LOCK_ASSERT(txq);
4413
4414 /* XXX assert ATH_BUF_BUSY is set */
4415
4416 /* XXX assert the tx queue is under the max number */
4417 if (bf->bf_state.bfs_tx_queue > HAL_NUM_TX_QUEUES) {
4418 device_printf(sc->sc_dev, "%s: bf=%p: invalid tx queue (%d)\n",
4419 __func__,
4420 bf,
4421 bf->bf_state.bfs_tx_queue);
4422 bf->bf_flags &= ~ATH_BUF_BUSY;
4423 ath_returnbuf_tail(sc, bf);
4424 return;
4425 }
4426 ath_txq_freeholdingbuf(sc, txq);
4427 txq->axq_holdingbf = bf;
4428}
4429
4430/*
4431 * Return a buffer to the pool and update the 'busy' flag on the
4432 * previous 'tail' entry.
4433 *
4434 * This _must_ only be called when the buffer is involved in a completed
4435 * TX. The logic is that if it was part of an active TX, the previous
4436 * buffer on the list is now not involved in a halted TX DMA queue, waiting
4437 * for restart (eg for TDMA.)
4438 *
4439 * The caller must free the mbuf and recycle the node reference.
4440 *
4441 * XXX This method of handling busy / holding buffers is insanely stupid.
4442 * It requires bf_state.bfs_tx_queue to be correctly assigned. It would
4443 * be much nicer if buffers in the processq() methods would instead be
4444 * always completed there (pushed onto a txq or ath_bufhead) so we knew
4445 * exactly what hardware queue they came from in the first place.
4446 */
4447void
4448ath_freebuf(struct ath_softc *sc, struct ath_buf *bf)
4449{
4450 struct ath_txq *txq;
4451
4452 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue];
4453
4454 KASSERT((bf->bf_node == NULL), ("%s: bf->bf_node != NULL\n", __func__));
4455 KASSERT((bf->bf_m == NULL), ("%s: bf->bf_m != NULL\n", __func__));
4456
4457 /*
4458 * If this buffer is busy, push it onto the holding queue.
4459 */
4460 if (bf->bf_flags & ATH_BUF_BUSY) {
4461 ATH_TXQ_LOCK(txq);
4462 ath_txq_addholdingbuf(sc, bf);
4463 ATH_TXQ_UNLOCK(txq);
4464 return;
4465 }
4466
4467 /*
4468 * Not a busy buffer, so free normally
4469 */
4470 ATH_TXBUF_LOCK(sc);
4471 ath_returnbuf_tail(sc, bf);
4472 ATH_TXBUF_UNLOCK(sc);
4473}
4474
4475/*
4476 * This is currently used by ath_tx_draintxq() and
4477 * ath_tx_tid_free_pkts().
4478 *
4479 * It recycles a single ath_buf.
4480 */
4481void
4482ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf, int status)
4483{
4484 struct ieee80211_node *ni = bf->bf_node;
4485 struct mbuf *m0 = bf->bf_m;
4486
4487 /*
4488 * Make sure that we only sync/unload if there's an mbuf.
4489 * If not (eg we cloned a buffer), the unload will have already
4490 * occured.
4491 */
4492 if (bf->bf_m != NULL) {
4493 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
4494 BUS_DMASYNC_POSTWRITE);
4495 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4496 }
4497
4498 bf->bf_node = NULL;
4499 bf->bf_m = NULL;
4500
4501 /* Free the buffer, it's not needed any longer */
4502 ath_freebuf(sc, bf);
4503
4504 if (ni != NULL) {
4505 /*
4506 * Do any callback and reclaim the node reference.
4507 */
4508 if (m0->m_flags & M_TXCB)
4509 ieee80211_process_callback(ni, m0, status);
4510 ieee80211_free_node(ni);
4511 }
4512
4513 /* Finally, we don't need this mbuf any longer */
4514 m_freem(m0);
4515}
4516
4517static struct ath_buf *
4518ath_tx_draintxq_get_one(struct ath_softc *sc, struct ath_txq *txq)
4519{
4520 struct ath_buf *bf;
4521
4522 ATH_TXQ_LOCK_ASSERT(txq);
4523
4524 /*
4525 * Drain the FIFO queue first, then if it's
4526 * empty, move to the normal frame queue.
4527 */
4528 bf = TAILQ_FIRST(&txq->fifo.axq_q);
4529 if (bf != NULL) {
4530 /*
4531 * Is it the last buffer in this set?
4532 * Decrement the FIFO counter.
4533 */
4534 if (bf->bf_flags & ATH_BUF_FIFOEND) {
4535 if (txq->axq_fifo_depth == 0) {
4536 device_printf(sc->sc_dev,
4537 "%s: Q%d: fifo_depth=0, fifo.axq_depth=%d?\n",
4538 __func__,
4539 txq->axq_qnum,
4540 txq->fifo.axq_depth);
4541 } else
4542 txq->axq_fifo_depth--;
4543 }
4544 ATH_TXQ_REMOVE(&txq->fifo, bf, bf_list);
4545 return (bf);
4546 }
4547
4548 /*
4549 * Debugging!
4550 */
4551 if (txq->axq_fifo_depth != 0 || txq->fifo.axq_depth != 0) {
4552 device_printf(sc->sc_dev,
4553 "%s: Q%d: fifo_depth=%d, fifo.axq_depth=%d\n",
4554 __func__,
4555 txq->axq_qnum,
4556 txq->axq_fifo_depth,
4557 txq->fifo.axq_depth);
4558 }
4559
4560 /*
4561 * Now drain the pending queue.
4562 */
4563 bf = TAILQ_FIRST(&txq->axq_q);
4564 if (bf == NULL) {
4565 txq->axq_link = NULL;
4566 return (NULL);
4567 }
4568 ATH_TXQ_REMOVE(txq, bf, bf_list);
4569 return (bf);
4570}
4571
4572void
4573ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
4574{
4575#ifdef ATH_DEBUG
4576 struct ath_hal *ah = sc->sc_ah;
4577#endif
4578 struct ath_buf *bf;
4579 u_int ix;
4580
4581 /*
4582 * NB: this assumes output has been stopped and
4583 * we do not need to block ath_tx_proc
4584 */
4585 for (ix = 0;; ix++) {
4586 ATH_TXQ_LOCK(txq);
4587 bf = ath_tx_draintxq_get_one(sc, txq);
4588 if (bf == NULL) {
4589 ATH_TXQ_UNLOCK(txq);
4590 break;
4591 }
4592 if (bf->bf_state.bfs_aggr)
4593 txq->axq_aggr_depth--;
4594#ifdef ATH_DEBUG
4595 if (sc->sc_debug & ATH_DEBUG_RESET) {
4596 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
4597 int status = 0;
4598
4599 /*
4600 * EDMA operation has a TX completion FIFO
4601 * separate from the TX descriptor, so this
4602 * method of checking the "completion" status
4603 * is wrong.
4604 */
4605 if (! sc->sc_isedma) {
4606 status = (ath_hal_txprocdesc(ah,
4607 bf->bf_lastds,
4608 &bf->bf_status.ds_txstat) == HAL_OK);
4609 }
4610 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, status);
4611 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *),
4612 bf->bf_m->m_len, 0, -1);
4613 }
4614#endif /* ATH_DEBUG */
4615 /*
4616 * Since we're now doing magic in the completion
4617 * functions, we -must- call it for aggregation
4618 * destinations or BAW tracking will get upset.
4619 */
4620 /*
4621 * Clear ATH_BUF_BUSY; the completion handler
4622 * will free the buffer.
4623 */
4624 ATH_TXQ_UNLOCK(txq);
4625 bf->bf_flags &= ~ATH_BUF_BUSY;
4626 if (bf->bf_comp)
4627 bf->bf_comp(sc, bf, 1);
4628 else
4629 ath_tx_default_comp(sc, bf, 1);
4630 }
4631
4632 /*
4633 * Free the holding buffer if it exists
4634 */
4635 ATH_TXQ_LOCK(txq);
4636 ath_txq_freeholdingbuf(sc, txq);
4637 ATH_TXQ_UNLOCK(txq);
4638
4639 /*
4640 * Drain software queued frames which are on
4641 * active TIDs.
4642 */
4643 ath_tx_txq_drain(sc, txq);
4644}
4645
4646static void
4647ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
4648{
4649 struct ath_hal *ah = sc->sc_ah;
4650
4651 ATH_TXQ_LOCK_ASSERT(txq);
4652
4653 DPRINTF(sc, ATH_DEBUG_RESET,
4654 "%s: tx queue [%u] %p, active=%d, hwpending=%d, flags 0x%08x, "
4655 "link %p, holdingbf=%p\n",
4656 __func__,
4657 txq->axq_qnum,
4658 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
4659 (int) (!! ath_hal_txqenabled(ah, txq->axq_qnum)),
4660 (int) ath_hal_numtxpending(ah, txq->axq_qnum),
4661 txq->axq_flags,
4662 txq->axq_link,
4663 txq->axq_holdingbf);
4664
4665 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
4666 /* We've stopped TX DMA, so mark this as stopped. */
4667 txq->axq_flags &= ~ATH_TXQ_PUTRUNNING;
4668
4669#ifdef ATH_DEBUG
4670 if ((sc->sc_debug & ATH_DEBUG_RESET)
4671 && (txq->axq_holdingbf != NULL)) {
4672 ath_printtxbuf(sc, txq->axq_holdingbf, txq->axq_qnum, 0, 0);
4673 }
4674#endif
4675}
4676
4677int
4678ath_stoptxdma(struct ath_softc *sc)
4679{
4680 struct ath_hal *ah = sc->sc_ah;
4681 int i;
4682
4683 /* XXX return value */
4684 if (sc->sc_invalid)
4685 return 0;
4686
4687 if (!sc->sc_invalid) {
4688 /* don't touch the hardware if marked invalid */
4689 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
4690 __func__, sc->sc_bhalq,
4691 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq),
4692 NULL);
4693
4694 /* stop the beacon queue */
4695 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
4696
4697 /* Stop the data queues */
4698 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
4699 if (ATH_TXQ_SETUP(sc, i)) {
4700 ATH_TXQ_LOCK(&sc->sc_txq[i]);
4701 ath_tx_stopdma(sc, &sc->sc_txq[i]);
4702 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
4703 }
4704 }
4705 }
4706
4707 return 1;
4708}
4709
4710#ifdef ATH_DEBUG
4711void
4712ath_tx_dump(struct ath_softc *sc, struct ath_txq *txq)
4713{
4714 struct ath_hal *ah = sc->sc_ah;
4715 struct ath_buf *bf;
4716 int i = 0;
4717
4718 if (! (sc->sc_debug & ATH_DEBUG_RESET))
4719 return;
4720
4721 device_printf(sc->sc_dev, "%s: Q%d: begin\n",
4722 __func__, txq->axq_qnum);
4723 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) {
4724 ath_printtxbuf(sc, bf, txq->axq_qnum, i,
4725 ath_hal_txprocdesc(ah, bf->bf_lastds,
4726 &bf->bf_status.ds_txstat) == HAL_OK);
4727 i++;
4728 }
4729 device_printf(sc->sc_dev, "%s: Q%d: end\n",
4730 __func__, txq->axq_qnum);
4731}
4732#endif /* ATH_DEBUG */
4733
4734/*
4735 * Drain the transmit queues and reclaim resources.
4736 */
4737void
4738ath_legacy_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type)
4739{
4740 struct ath_hal *ah = sc->sc_ah;
4741 struct ifnet *ifp = sc->sc_ifp;
4742 int i;
4743 struct ath_buf *bf_last;
4744
4745 (void) ath_stoptxdma(sc);
4746
4747 /*
4748 * Dump the queue contents
4749 */
4750 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
4751 /*
4752 * XXX TODO: should we just handle the completed TX frames
4753 * here, whether or not the reset is a full one or not?
4754 */
4755 if (ATH_TXQ_SETUP(sc, i)) {
4756#ifdef ATH_DEBUG
4757 if (sc->sc_debug & ATH_DEBUG_RESET)
4758 ath_tx_dump(sc, &sc->sc_txq[i]);
4759#endif /* ATH_DEBUG */
4760 if (reset_type == ATH_RESET_NOLOSS) {
4761 ath_tx_processq(sc, &sc->sc_txq[i], 0);
4762 ATH_TXQ_LOCK(&sc->sc_txq[i]);
4763 /*
4764 * Free the holding buffer; DMA is now
4765 * stopped.
4766 */
4767 ath_txq_freeholdingbuf(sc, &sc->sc_txq[i]);
4768 /*
4769 * Setup the link pointer to be the
4770 * _last_ buffer/descriptor in the list.
4771 * If there's nothing in the list, set it
4772 * to NULL.
4773 */
4774 bf_last = ATH_TXQ_LAST(&sc->sc_txq[i],
4775 axq_q_s);
4776 if (bf_last != NULL) {
4777 ath_hal_gettxdesclinkptr(ah,
4778 bf_last->bf_lastds,
4779 &sc->sc_txq[i].axq_link);
4780 } else {
4781 sc->sc_txq[i].axq_link = NULL;
4782 }
4783 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
4784 } else
4785 ath_tx_draintxq(sc, &sc->sc_txq[i]);
4786 }
4787 }
4788#ifdef ATH_DEBUG
4789 if (sc->sc_debug & ATH_DEBUG_RESET) {
4790 struct ath_buf *bf = TAILQ_FIRST(&sc->sc_bbuf);
4791 if (bf != NULL && bf->bf_m != NULL) {
4792 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0,
4793 ath_hal_txprocdesc(ah, bf->bf_lastds,
4794 &bf->bf_status.ds_txstat) == HAL_OK);
4795 ieee80211_dump_pkt(ifp->if_l2com,
4796 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len,
4797 0, -1);
4798 }
4799 }
4800#endif /* ATH_DEBUG */
4801 IF_LOCK(&ifp->if_snd);
4802 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4803 IF_UNLOCK(&ifp->if_snd);
4804 sc->sc_wd_timer = 0;
4805}
4806
4807/*
4808 * Update internal state after a channel change.
4809 */
4810static void
4811ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
4812{
4813 enum ieee80211_phymode mode;
4814
4815 /*
4816 * Change channels and update the h/w rate map
4817 * if we're switching; e.g. 11a to 11b/g.
4818 */
4819 mode = ieee80211_chan2mode(chan);
4820 if (mode != sc->sc_curmode)
4821 ath_setcurmode(sc, mode);
4822 sc->sc_curchan = chan;
4823}
4824
4825/*
4826 * Set/change channels. If the channel is really being changed,
4827 * it's done by resetting the chip. To accomplish this we must
4828 * first cleanup any pending DMA, then restart stuff after a la
4829 * ath_init.
4830 */
4831static int
4832ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
4833{
4834 struct ifnet *ifp = sc->sc_ifp;
4835 struct ieee80211com *ic = ifp->if_l2com;
4836 struct ath_hal *ah = sc->sc_ah;
4837 int ret = 0;
4838
4839 /* Treat this as an interface reset */
4840 ATH_PCU_UNLOCK_ASSERT(sc);
4841 ATH_UNLOCK_ASSERT(sc);
4842
4843 /* (Try to) stop TX/RX from occuring */
4844 taskqueue_block(sc->sc_tq);
4845
4846 ATH_PCU_LOCK(sc);
4847 ath_hal_intrset(ah, 0); /* Stop new RX/TX completion */
4848 ath_txrx_stop_locked(sc); /* Stop pending RX/TX completion */
4849 if (ath_reset_grablock(sc, 1) == 0) {
4850 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
4851 __func__);
4852 }
4853 ATH_PCU_UNLOCK(sc);
4854
4855 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n",
4856 __func__, ieee80211_chan2ieee(ic, chan),
4857 chan->ic_freq, chan->ic_flags);
4858 if (chan != sc->sc_curchan) {
4859 HAL_STATUS status;
4860 /*
4861 * To switch channels clear any pending DMA operations;
4862 * wait long enough for the RX fifo to drain, reset the
4863 * hardware at the new frequency, and then re-enable
4864 * the relevant bits of the h/w.
4865 */
4866#if 0
4867 ath_hal_intrset(ah, 0); /* disable interrupts */
4868#endif
4869 ath_stoprecv(sc, 1); /* turn off frame recv */
4870 /*
4871 * First, handle completed TX/RX frames.
4872 */
4873 ath_rx_flush(sc);
4874 ath_draintxq(sc, ATH_RESET_NOLOSS);
4875 /*
4876 * Next, flush the non-scheduled frames.
4877 */
4878 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */
4879
4880 ath_update_chainmasks(sc, chan);
4881 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
4882 sc->sc_cur_rxchainmask);
4883 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) {
4884 if_printf(ifp, "%s: unable to reset "
4885 "channel %u (%u MHz, flags 0x%x), hal status %u\n",
4886 __func__, ieee80211_chan2ieee(ic, chan),
4887 chan->ic_freq, chan->ic_flags, status);
4888 ret = EIO;
4889 goto finish;
4890 }
4891 sc->sc_diversity = ath_hal_getdiversity(ah);
4892
4893 /* Let DFS at it in case it's a DFS channel */
4894 ath_dfs_radar_enable(sc, chan);
4895
4896 /* Let spectral at in case spectral is enabled */
4897 ath_spectral_enable(sc, chan);
4898
4899 /*
4900 * If we're doing TDMA, enforce the TXOP limitation for chips
4901 * that support it.
4902 */
4903 if (sc->sc_hasenforcetxop && sc->sc_tdma)
4904 ath_hal_setenforcetxop(sc->sc_ah, 1);
4905 else
4906 ath_hal_setenforcetxop(sc->sc_ah, 0);
4907
4908 /*
4909 * Re-enable rx framework.
4910 */
4911 if (ath_startrecv(sc) != 0) {
4912 if_printf(ifp, "%s: unable to restart recv logic\n",
4913 __func__);
4914 ret = EIO;
4915 goto finish;
4916 }
4917
4918 /*
4919 * Change channels and update the h/w rate map
4920 * if we're switching; e.g. 11a to 11b/g.
4921 */
4922 ath_chan_change(sc, chan);
4923
4924 /*
4925 * Reset clears the beacon timers; reset them
4926 * here if needed.
4927 */
4928 if (sc->sc_beacons) { /* restart beacons */
4929#ifdef IEEE80211_SUPPORT_TDMA
4930 if (sc->sc_tdma)
4931 ath_tdma_config(sc, NULL);
4932 else
4933#endif
4934 ath_beacon_config(sc, NULL);
4935 }
4936
4937 /*
4938 * Re-enable interrupts.
4939 */
4940#if 0
4941 ath_hal_intrset(ah, sc->sc_imask);
4942#endif
4943 }
4944
4945finish:
4946 ATH_PCU_LOCK(sc);
4947 sc->sc_inreset_cnt--;
4948 /* XXX only do this if sc_inreset_cnt == 0? */
4949 ath_hal_intrset(ah, sc->sc_imask);
4950 ATH_PCU_UNLOCK(sc);
4951
4952 IF_LOCK(&ifp->if_snd);
4953 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4954 IF_UNLOCK(&ifp->if_snd);
4955 ath_txrx_start(sc);
4956 /* XXX ath_start? */
4957
4958 return ret;
4959}
4960
4961/*
4962 * Periodically recalibrate the PHY to account
4963 * for temperature/environment changes.
4964 */
4965static void
4966ath_calibrate(void *arg)
4967{
4968 struct ath_softc *sc = arg;
4969 struct ath_hal *ah = sc->sc_ah;
4970 struct ifnet *ifp = sc->sc_ifp;
4971 struct ieee80211com *ic = ifp->if_l2com;
4972 HAL_BOOL longCal, isCalDone = AH_TRUE;
4973 HAL_BOOL aniCal, shortCal = AH_FALSE;
4974 int nextcal;
4975
4976 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */
4977 goto restart;
4978 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz);
4979 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000);
4980 if (sc->sc_doresetcal)
4981 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000);
4982
4983 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal);
4984 if (aniCal) {
4985 sc->sc_stats.ast_ani_cal++;
4986 sc->sc_lastani = ticks;
4987 ath_hal_ani_poll(ah, sc->sc_curchan);
4988 }
4989
4990 if (longCal) {
4991 sc->sc_stats.ast_per_cal++;
4992 sc->sc_lastlongcal = ticks;
4993 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
4994 /*
4995 * Rfgain is out of bounds, reset the chip
4996 * to load new gain values.
4997 */
4998 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
4999 "%s: rfgain change\n", __func__);
5000 sc->sc_stats.ast_per_rfgain++;
5001 sc->sc_resetcal = 0;
5002 sc->sc_doresetcal = AH_TRUE;
5003 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
5004 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
5005 return;
5006 }
5007 /*
5008 * If this long cal is after an idle period, then
5009 * reset the data collection state so we start fresh.
5010 */
5011 if (sc->sc_resetcal) {
5012 (void) ath_hal_calreset(ah, sc->sc_curchan);
5013 sc->sc_lastcalreset = ticks;
5014 sc->sc_lastshortcal = ticks;
5015 sc->sc_resetcal = 0;
5016 sc->sc_doresetcal = AH_TRUE;
5017 }
5018 }
5019
5020 /* Only call if we're doing a short/long cal, not for ANI calibration */
5021 if (shortCal || longCal) {
5022 isCalDone = AH_FALSE;
5023 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) {
5024 if (longCal) {
5025 /*
5026 * Calibrate noise floor data again in case of change.
5027 */
5028 ath_hal_process_noisefloor(ah);
5029 }
5030 } else {
5031 DPRINTF(sc, ATH_DEBUG_ANY,
5032 "%s: calibration of channel %u failed\n",
5033 __func__, sc->sc_curchan->ic_freq);
5034 sc->sc_stats.ast_per_calfail++;
5035 }
5036 if (shortCal)
5037 sc->sc_lastshortcal = ticks;
5038 }
5039 if (!isCalDone) {
5040restart:
5041 /*
5042 * Use a shorter interval to potentially collect multiple
5043 * data samples required to complete calibration. Once
5044 * we're told the work is done we drop back to a longer
5045 * interval between requests. We're more aggressive doing
5046 * work when operating as an AP to improve operation right
5047 * after startup.
5048 */
5049 sc->sc_lastshortcal = ticks;
5050 nextcal = ath_shortcalinterval*hz/1000;
5051 if (sc->sc_opmode != HAL_M_HOSTAP)
5052 nextcal *= 10;
5053 sc->sc_doresetcal = AH_TRUE;
5054 } else {
5055 /* nextcal should be the shortest time for next event */
5056 nextcal = ath_longcalinterval*hz;
5057 if (sc->sc_lastcalreset == 0)
5058 sc->sc_lastcalreset = sc->sc_lastlongcal;
5059 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz)
5060 sc->sc_resetcal = 1; /* setup reset next trip */
5061 sc->sc_doresetcal = AH_FALSE;
5062 }
5063 /* ANI calibration may occur more often than short/long/resetcal */
5064 if (ath_anicalinterval > 0)
5065 nextcal = MIN(nextcal, ath_anicalinterval*hz/1000);
5066
5067 if (nextcal != 0) {
5068 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n",
5069 __func__, nextcal, isCalDone ? "" : "!");
5070 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc);
5071 } else {
5072 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n",
5073 __func__);
5074 /* NB: don't rearm timer */
5075 }
5076}
5077
5078static void
5079ath_scan_start(struct ieee80211com *ic)
5080{
5081 struct ifnet *ifp = ic->ic_ifp;
5082 struct ath_softc *sc = ifp->if_softc;
5083 struct ath_hal *ah = sc->sc_ah;
5084 u_int32_t rfilt;
5085
5086 /* XXX calibration timer? */
5087
5088 ATH_LOCK(sc);
5089 sc->sc_scanning = 1;
5090 sc->sc_syncbeacon = 0;
5091 rfilt = ath_calcrxfilter(sc);
5092 ATH_UNLOCK(sc);
5093
5094 ATH_PCU_LOCK(sc);
5095 ath_hal_setrxfilter(ah, rfilt);
5096 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0);
5097 ATH_PCU_UNLOCK(sc);
5098
5099 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n",
5100 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr));
5101}
5102
5103static void
5104ath_scan_end(struct ieee80211com *ic)
5105{
5106 struct ifnet *ifp = ic->ic_ifp;
5107 struct ath_softc *sc = ifp->if_softc;
5108 struct ath_hal *ah = sc->sc_ah;
5109 u_int32_t rfilt;
5110
5111 ATH_LOCK(sc);
5112 sc->sc_scanning = 0;
5113 rfilt = ath_calcrxfilter(sc);
5114 ATH_UNLOCK(sc);
5115
5116 ATH_PCU_LOCK(sc);
5117 ath_hal_setrxfilter(ah, rfilt);
5118 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5119
5120 ath_hal_process_noisefloor(ah);
5121 ATH_PCU_UNLOCK(sc);
5122
5123 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5124 __func__, rfilt, ether_sprintf(sc->sc_curbssid),
5125 sc->sc_curaid);
5126}
5127
5128#ifdef ATH_ENABLE_11N
5129/*
5130 * For now, just do a channel change.
5131 *
5132 * Later, we'll go through the hard slog of suspending tx/rx, changing rate
5133 * control state and resetting the hardware without dropping frames out
5134 * of the queue.
5135 *
5136 * The unfortunate trouble here is making absolutely sure that the
5137 * channel width change has propagated enough so the hardware
5138 * absolutely isn't handed bogus frames for it's current operating
5139 * mode. (Eg, 40MHz frames in 20MHz mode.) Since TX and RX can and
5140 * does occur in parallel, we need to make certain we've blocked
5141 * any further ongoing TX (and RX, that can cause raw TX)
5142 * before we do this.
5143 */
5144static void
5145ath_update_chw(struct ieee80211com *ic)
5146{
5147 struct ifnet *ifp = ic->ic_ifp;
5148 struct ath_softc *sc = ifp->if_softc;
5149
5150 DPRINTF(sc, ATH_DEBUG_STATE, "%s: called\n", __func__);
5151 ath_set_channel(ic);
5152}
5153#endif /* ATH_ENABLE_11N */
5154
5155static void
5156ath_set_channel(struct ieee80211com *ic)
5157{
5158 struct ifnet *ifp = ic->ic_ifp;
5159 struct ath_softc *sc = ifp->if_softc;
5160
5161 (void) ath_chan_set(sc, ic->ic_curchan);
5162 /*
5163 * If we are returning to our bss channel then mark state
5164 * so the next recv'd beacon's tsf will be used to sync the
5165 * beacon timers. Note that since we only hear beacons in
5166 * sta/ibss mode this has no effect in other operating modes.
5167 */
5168 ATH_LOCK(sc);
5169 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan)
5170 sc->sc_syncbeacon = 1;
5171 ATH_UNLOCK(sc);
5172}
5173
5174/*
5175 * Walk the vap list and check if there any vap's in RUN state.
5176 */
5177static int
5178ath_isanyrunningvaps(struct ieee80211vap *this)
5179{
5180 struct ieee80211com *ic = this->iv_ic;
5181 struct ieee80211vap *vap;
5182
5183 IEEE80211_LOCK_ASSERT(ic);
5184
5185 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
5186 if (vap != this && vap->iv_state >= IEEE80211_S_RUN)
5187 return 1;
5188 }
5189 return 0;
5190}
5191
5192static int
5193ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
5194{
5195 struct ieee80211com *ic = vap->iv_ic;
5196 struct ath_softc *sc = ic->ic_ifp->if_softc;
5197 struct ath_vap *avp = ATH_VAP(vap);
5198 struct ath_hal *ah = sc->sc_ah;
5199 struct ieee80211_node *ni = NULL;
5200 int i, error, stamode;
5201 u_int32_t rfilt;
5202 int csa_run_transition = 0;
5203
5204 static const HAL_LED_STATE leds[] = {
5205 HAL_LED_INIT, /* IEEE80211_S_INIT */
5206 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
5207 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
5208 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
5209 HAL_LED_RUN, /* IEEE80211_S_CAC */
5210 HAL_LED_RUN, /* IEEE80211_S_RUN */
5211 HAL_LED_RUN, /* IEEE80211_S_CSA */
5212 HAL_LED_RUN, /* IEEE80211_S_SLEEP */
5213 };
5214
5215 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
5216 ieee80211_state_name[vap->iv_state],
5217 ieee80211_state_name[nstate]);
5218
5219 /*
5220 * net80211 _should_ have the comlock asserted at this point.
5221 * There are some comments around the calls to vap->iv_newstate
5222 * which indicate that it (newstate) may end up dropping the
5223 * lock. This and the subsequent lock assert check after newstate
5224 * are an attempt to catch these and figure out how/why.
5225 */
5226 IEEE80211_LOCK_ASSERT(ic);
5227
5228 if (vap->iv_state == IEEE80211_S_CSA && nstate == IEEE80211_S_RUN)
5229 csa_run_transition = 1;
5230
5231 callout_drain(&sc->sc_cal_ch);
5232 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
5233
5234 if (nstate == IEEE80211_S_SCAN) {
5235 /*
5236 * Scanning: turn off beacon miss and don't beacon.
5237 * Mark beacon state so when we reach RUN state we'll
5238 * [re]setup beacons. Unblock the task q thread so
5239 * deferred interrupt processing is done.
5240 */
5241 ath_hal_intrset(ah,
5242 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
5243 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5244 sc->sc_beacons = 0;
5245 taskqueue_unblock(sc->sc_tq);
5246 }
5247
5248 ni = ieee80211_ref_node(vap->iv_bss);
5249 rfilt = ath_calcrxfilter(sc);
5250 stamode = (vap->iv_opmode == IEEE80211_M_STA ||
5251 vap->iv_opmode == IEEE80211_M_AHDEMO ||
5252 vap->iv_opmode == IEEE80211_M_IBSS);
5253 if (stamode && nstate == IEEE80211_S_RUN) {
5254 sc->sc_curaid = ni->ni_associd;
5255 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid);
5256 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5257 }
5258 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5259 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid);
5260 ath_hal_setrxfilter(ah, rfilt);
5261
5262 /* XXX is this to restore keycache on resume? */
5263 if (vap->iv_opmode != IEEE80211_M_STA &&
5264 (vap->iv_flags & IEEE80211_F_PRIVACY)) {
5265 for (i = 0; i < IEEE80211_WEP_NKID; i++)
5266 if (ath_hal_keyisvalid(ah, i))
5267 ath_hal_keysetmac(ah, i, ni->ni_bssid);
5268 }
5269
5270 /*
5271 * Invoke the parent method to do net80211 work.
5272 */
5273 error = avp->av_newstate(vap, nstate, arg);
5274 if (error != 0)
5275 goto bad;
5276
5277 /*
5278 * See above: ensure av_newstate() doesn't drop the lock
5279 * on us.
5280 */
5281 IEEE80211_LOCK_ASSERT(ic);
5282
5283 if (nstate == IEEE80211_S_RUN) {
5284 /* NB: collect bss node again, it may have changed */
5285 ieee80211_free_node(ni);
5286 ni = ieee80211_ref_node(vap->iv_bss);
5287
5288 DPRINTF(sc, ATH_DEBUG_STATE,
5289 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s "
5290 "capinfo 0x%04x chan %d\n", __func__,
5291 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid),
5292 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan));
5293
5294 switch (vap->iv_opmode) {
5295#ifdef IEEE80211_SUPPORT_TDMA
5296 case IEEE80211_M_AHDEMO:
5297 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0)
5298 break;
5299 /* fall thru... */
5300#endif
5301 case IEEE80211_M_HOSTAP:
5302 case IEEE80211_M_IBSS:
5303 case IEEE80211_M_MBSS:
5304 /*
5305 * Allocate and setup the beacon frame.
5306 *
5307 * Stop any previous beacon DMA. This may be
5308 * necessary, for example, when an ibss merge
5309 * causes reconfiguration; there will be a state
5310 * transition from RUN->RUN that means we may
5311 * be called with beacon transmission active.
5312 */
5313 ath_hal_stoptxdma(ah, sc->sc_bhalq);
5314
5315 error = ath_beacon_alloc(sc, ni);
5316 if (error != 0)
5317 goto bad;
5318 /*
5319 * If joining an adhoc network defer beacon timer
5320 * configuration to the next beacon frame so we
5321 * have a current TSF to use. Otherwise we're
5322 * starting an ibss/bss so there's no need to delay;
5323 * if this is the first vap moving to RUN state, then
5324 * beacon state needs to be [re]configured.
5325 */
5326 if (vap->iv_opmode == IEEE80211_M_IBSS &&
5327 ni->ni_tstamp.tsf != 0) {
5328 sc->sc_syncbeacon = 1;
5329 } else if (!sc->sc_beacons) {
5330#ifdef IEEE80211_SUPPORT_TDMA
5331 if (vap->iv_caps & IEEE80211_C_TDMA)
5332 ath_tdma_config(sc, vap);
5333 else
5334#endif
5335 ath_beacon_config(sc, vap);
5336 sc->sc_beacons = 1;
5337 }
5338 break;
5339 case IEEE80211_M_STA:
5340 /*
5341 * Defer beacon timer configuration to the next
5342 * beacon frame so we have a current TSF to use
5343 * (any TSF collected when scanning is likely old).
5344 * However if it's due to a CSA -> RUN transition,
5345 * force a beacon update so we pick up a lack of
5346 * beacons from an AP in CAC and thus force a
5347 * scan.
5348 *
5349 * And, there's also corner cases here where
5350 * after a scan, the AP may have disappeared.
5351 * In that case, we may not receive an actual
5352 * beacon to update the beacon timer and thus we
5353 * won't get notified of the missing beacons.
5354 */
5355 sc->sc_syncbeacon = 1;
5356#if 0
5357 if (csa_run_transition)
5358#endif
5359 ath_beacon_config(sc, vap);
5360
5361 /*
5362 * PR: kern/175227
5363 *
5364 * Reconfigure beacons during reset; as otherwise
5365 * we won't get the beacon timers reprogrammed
5366 * after a reset and thus we won't pick up a
5367 * beacon miss interrupt.
5368 *
5369 * Hopefully we'll see a beacon before the BMISS
5370 * timer fires (too often), leading to a STA
5371 * disassociation.
5372 */
5373 sc->sc_beacons = 1;
5374 break;
5375 case IEEE80211_M_MONITOR:
5376 /*
5377 * Monitor mode vaps have only INIT->RUN and RUN->RUN
5378 * transitions so we must re-enable interrupts here to
5379 * handle the case of a single monitor mode vap.
5380 */
5381 ath_hal_intrset(ah, sc->sc_imask);
5382 break;
5383 case IEEE80211_M_WDS:
5384 break;
5385 default:
5386 break;
5387 }
5388 /*
5389 * Let the hal process statistics collected during a
5390 * scan so it can provide calibrated noise floor data.
5391 */
5392 ath_hal_process_noisefloor(ah);
5393 /*
5394 * Reset rssi stats; maybe not the best place...
5395 */
5396 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
5397 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
5398 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
5399 /*
5400 * Finally, start any timers and the task q thread
5401 * (in case we didn't go through SCAN state).
5402 */
5403 if (ath_longcalinterval != 0) {
5404 /* start periodic recalibration timer */
5405 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
5406 } else {
5407 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5408 "%s: calibration disabled\n", __func__);
5409 }
5410 taskqueue_unblock(sc->sc_tq);
5411 } else if (nstate == IEEE80211_S_INIT) {
5412 /*
5413 * If there are no vaps left in RUN state then
5414 * shutdown host/driver operation:
5415 * o disable interrupts
5416 * o disable the task queue thread
5417 * o mark beacon processing as stopped
5418 */
5419 if (!ath_isanyrunningvaps(vap)) {
5420 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5421 /* disable interrupts */
5422 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
5423 taskqueue_block(sc->sc_tq);
5424 sc->sc_beacons = 0;
5425 }
5426#ifdef IEEE80211_SUPPORT_TDMA
5427 ath_hal_setcca(ah, AH_TRUE);
5428#endif
5429 }
5430bad:
5431 ieee80211_free_node(ni);
5432 return error;
5433}
5434
5435/*
5436 * Allocate a key cache slot to the station so we can
5437 * setup a mapping from key index to node. The key cache
5438 * slot is needed for managing antenna state and for
5439 * compression when stations do not use crypto. We do
5440 * it uniliaterally here; if crypto is employed this slot
5441 * will be reassigned.
5442 */
5443static void
5444ath_setup_stationkey(struct ieee80211_node *ni)
5445{
5446 struct ieee80211vap *vap = ni->ni_vap;
5447 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
5448 ieee80211_keyix keyix, rxkeyix;
5449
5450 /* XXX should take a locked ref to vap->iv_bss */
5451 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
5452 /*
5453 * Key cache is full; we'll fall back to doing
5454 * the more expensive lookup in software. Note
5455 * this also means no h/w compression.
5456 */
5457 /* XXX msg+statistic */
5458 } else {
5459 /* XXX locking? */
5460 ni->ni_ucastkey.wk_keyix = keyix;
5461 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
5462 /* NB: must mark device key to get called back on delete */
5463 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY;
5464 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr);
5465 /* NB: this will create a pass-thru key entry */
5466 ath_keyset(sc, vap, &ni->ni_ucastkey, vap->iv_bss);
5467 }
5468}
5469
5470/*
5471 * Setup driver-specific state for a newly associated node.
5472 * Note that we're called also on a re-associate, the isnew
5473 * param tells us if this is the first time or not.
5474 */
5475static void
5476ath_newassoc(struct ieee80211_node *ni, int isnew)
5477{
5478 struct ath_node *an = ATH_NODE(ni);
5479 struct ieee80211vap *vap = ni->ni_vap;
5480 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
5481 const struct ieee80211_txparam *tp = ni->ni_txparms;
5482
5483 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate);
5484 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate);
5485
5486 ath_rate_newassoc(sc, an, isnew);
5487 if (isnew &&
5488 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey &&
5489 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
5490 ath_setup_stationkey(ni);
5491
5492 /*
5493 * If we're reassociating, make sure that any paused queues
5494 * get unpaused.
5495 *
5496 * Now, we may hvae frames in the hardware queue for this node.
5497 * So if we are reassociating and there are frames in the queue,
5498 * we need to go through the cleanup path to ensure that they're
5499 * marked as non-aggregate.
5500 */
5501 if (! isnew) {
5502 device_printf(sc->sc_dev,
5503 "%s: %6D: reassoc; is_powersave=%d\n",
5504 __func__,
5505 ni->ni_macaddr,
5506 ":",
5507 an->an_is_powersave);
5508
5509 /* XXX for now, we can't hold the lock across assoc */
5510 ath_tx_node_reassoc(sc, an);
5511
5512 /* XXX for now, we can't hold the lock across wakeup */
5513 if (an->an_is_powersave)
5514 ath_tx_node_wakeup(sc, an);
5515 }
5516}
5517
5518static int
5519ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg,
5520 int nchans, struct ieee80211_channel chans[])
5521{
5522 struct ath_softc *sc = ic->ic_ifp->if_softc;
5523 struct ath_hal *ah = sc->sc_ah;
5524 HAL_STATUS status;
5525
5526 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
5527 "%s: rd %u cc %u location %c%s\n",
5528 __func__, reg->regdomain, reg->country, reg->location,
5529 reg->ecm ? " ecm" : "");
5530
5531 status = ath_hal_set_channels(ah, chans, nchans,
5532 reg->country, reg->regdomain);
5533 if (status != HAL_OK) {
5534 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n",
5535 __func__, status);
5536 return EINVAL; /* XXX */
5537 }
5538
5539 return 0;
5540}
5541
5542static void
5543ath_getradiocaps(struct ieee80211com *ic,
5544 int maxchans, int *nchans, struct ieee80211_channel chans[])
5545{
5546 struct ath_softc *sc = ic->ic_ifp->if_softc;
5547 struct ath_hal *ah = sc->sc_ah;
5548
5549 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n",
5550 __func__, SKU_DEBUG, CTRY_DEFAULT);
5551
5552 /* XXX check return */
5553 (void) ath_hal_getchannels(ah, chans, maxchans, nchans,
5554 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE);
5555
5556}
5557
5558static int
5559ath_getchannels(struct ath_softc *sc)
5560{
5561 struct ifnet *ifp = sc->sc_ifp;
5562 struct ieee80211com *ic = ifp->if_l2com;
5563 struct ath_hal *ah = sc->sc_ah;
5564 HAL_STATUS status;
5565
5566 /*
5567 * Collect channel set based on EEPROM contents.
5568 */
5569 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX,
5570 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE);
5571 if (status != HAL_OK) {
5572 if_printf(ifp, "%s: unable to collect channel list from hal, "
5573 "status %d\n", __func__, status);
5574 return EINVAL;
5575 }
5576 (void) ath_hal_getregdomain(ah, &sc->sc_eerd);
5577 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */
5578 /* XXX map Atheros sku's to net80211 SKU's */
5579 /* XXX net80211 types too small */
5580 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd;
5581 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc;
5582 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */
5583 ic->ic_regdomain.isocc[1] = ' ';
5584
5585 ic->ic_regdomain.ecm = 1;
5586 ic->ic_regdomain.location = 'I';
5587
5588 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
5589 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n",
5590 __func__, sc->sc_eerd, sc->sc_eecc,
5591 ic->ic_regdomain.regdomain, ic->ic_regdomain.country,
5592 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : "");
5593 return 0;
5594}
5595
5596static int
5597ath_rate_setup(struct ath_softc *sc, u_int mode)
5598{
5599 struct ath_hal *ah = sc->sc_ah;
5600 const HAL_RATE_TABLE *rt;
5601
5602 switch (mode) {
5603 case IEEE80211_MODE_11A:
5604 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
5605 break;
5606 case IEEE80211_MODE_HALF:
5607 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE);
5608 break;
5609 case IEEE80211_MODE_QUARTER:
5610 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE);
5611 break;
5612 case IEEE80211_MODE_11B:
5613 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
5614 break;
5615 case IEEE80211_MODE_11G:
5616 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
5617 break;
5618 case IEEE80211_MODE_TURBO_A:
5619 rt = ath_hal_getratetable(ah, HAL_MODE_108A);
5620 break;
5621 case IEEE80211_MODE_TURBO_G:
5622 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
5623 break;
5624 case IEEE80211_MODE_STURBO_A:
5625 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
5626 break;
5627 case IEEE80211_MODE_11NA:
5628 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20);
5629 break;
5630 case IEEE80211_MODE_11NG:
5631 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20);
5632 break;
5633 default:
5634 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
5635 __func__, mode);
5636 return 0;
5637 }
5638 sc->sc_rates[mode] = rt;
5639 return (rt != NULL);
5640}
5641
5642static void
5643ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
5644{
5645#define N(a) (sizeof(a)/sizeof(a[0]))
5646 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
5647 static const struct {
5648 u_int rate; /* tx/rx 802.11 rate */
5649 u_int16_t timeOn; /* LED on time (ms) */
5650 u_int16_t timeOff; /* LED off time (ms) */
5651 } blinkrates[] = {
5652 { 108, 40, 10 },
5653 { 96, 44, 11 },
5654 { 72, 50, 13 },
5655 { 48, 57, 14 },
5656 { 36, 67, 16 },
5657 { 24, 80, 20 },
5658 { 22, 100, 25 },
5659 { 18, 133, 34 },
5660 { 12, 160, 40 },
5661 { 10, 200, 50 },
5662 { 6, 240, 58 },
5663 { 4, 267, 66 },
5664 { 2, 400, 100 },
5665 { 0, 500, 130 },
5666 /* XXX half/quarter rates */
5667 };
5668 const HAL_RATE_TABLE *rt;
5669 int i, j;
5670
5671 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
5672 rt = sc->sc_rates[mode];
5673 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
5674 for (i = 0; i < rt->rateCount; i++) {
5675 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
5676 if (rt->info[i].phy != IEEE80211_T_HT)
5677 sc->sc_rixmap[ieeerate] = i;
5678 else
5679 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i;
5680 }
5681 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
5682 for (i = 0; i < N(sc->sc_hwmap); i++) {
5683 if (i >= rt->rateCount) {
5684 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
5685 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
5686 continue;
5687 }
5688 sc->sc_hwmap[i].ieeerate =
5689 rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
5690 if (rt->info[i].phy == IEEE80211_T_HT)
5691 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS;
5692 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
5693 if (rt->info[i].shortPreamble ||
5694 rt->info[i].phy == IEEE80211_T_OFDM)
5695 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
5696 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags;
5697 for (j = 0; j < N(blinkrates)-1; j++)
5698 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
5699 break;
5700 /* NB: this uses the last entry if the rate isn't found */
5701 /* XXX beware of overlow */
5702 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
5703 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
5704 }
5705 sc->sc_currates = rt;
5706 sc->sc_curmode = mode;
5707 /*
5708 * All protection frames are transmited at 2Mb/s for
5709 * 11g, otherwise at 1Mb/s.
5710 */
5711 if (mode == IEEE80211_MODE_11G)
5712 sc->sc_protrix = ath_tx_findrix(sc, 2*2);
5713 else
5714 sc->sc_protrix = ath_tx_findrix(sc, 2*1);
5715 /* NB: caller is responsible for resetting rate control state */
5716#undef N
5717}
5718
5719static void
5720ath_watchdog(void *arg)
5721{
5722 struct ath_softc *sc = arg;
5723 int do_reset = 0;
5724
5725 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) {
5726 struct ifnet *ifp = sc->sc_ifp;
5727 uint32_t hangs;
5728
5729 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) &&
5730 hangs != 0) {
5731 if_printf(ifp, "%s hang detected (0x%x)\n",
5732 hangs & 0xff ? "bb" : "mac", hangs);
5733 } else
5734 if_printf(ifp, "device timeout\n");
5735 do_reset = 1;
5736 ifp->if_oerrors++;
5737 sc->sc_stats.ast_watchdog++;
5738 }
5739
5740 /*
5741 * We can't hold the lock across the ath_reset() call.
5742 *
5743 * And since this routine can't hold a lock and sleep,
5744 * do the reset deferred.
5745 */
5746 if (do_reset) {
5747 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
5748 }
5749
5750 callout_schedule(&sc->sc_wd_ch, hz);
5751}
5752
5753/*
5754 * Fetch the rate control statistics for the given node.
5755 */
5756static int
5757ath_ioctl_ratestats(struct ath_softc *sc, struct ath_rateioctl *rs)
5758{
5759 struct ath_node *an;
5760 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
5761 struct ieee80211_node *ni;
5762 int error = 0;
5763
5764 /* Perform a lookup on the given node */
5765 ni = ieee80211_find_node(&ic->ic_sta, rs->is_u.macaddr);
5766 if (ni == NULL) {
5767 error = EINVAL;
5768 goto bad;
5769 }
5770
5771 /* Lock the ath_node */
5772 an = ATH_NODE(ni);
5773 ATH_NODE_LOCK(an);
5774
5775 /* Fetch the rate control stats for this node */
5776 error = ath_rate_fetch_node_stats(sc, an, rs);
5777
5778 /* No matter what happens here, just drop through */
5779
5780 /* Unlock the ath_node */
5781 ATH_NODE_UNLOCK(an);
5782
5783 /* Unref the node */
5784 ieee80211_node_decref(ni);
5785
5786bad:
5787 return (error);
5788}
5789
5790#ifdef ATH_DIAGAPI
5791/*
5792 * Diagnostic interface to the HAL. This is used by various
5793 * tools to do things like retrieve register contents for
5794 * debugging. The mechanism is intentionally opaque so that
5795 * it can change frequently w/o concern for compatiblity.
5796 */
5797static int
5798ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
5799{
5800 struct ath_hal *ah = sc->sc_ah;
5801 u_int id = ad->ad_id & ATH_DIAG_ID;
5802 void *indata = NULL;
5803 void *outdata = NULL;
5804 u_int32_t insize = ad->ad_in_size;
5805 u_int32_t outsize = ad->ad_out_size;
5806 int error = 0;
5807
5808 if (ad->ad_id & ATH_DIAG_IN) {
5809 /*
5810 * Copy in data.
5811 */
5812 indata = malloc(insize, M_TEMP, M_NOWAIT);
5813 if (indata == NULL) {
5814 error = ENOMEM;
5815 goto bad;
5816 }
5817 error = copyin(ad->ad_in_data, indata, insize);
5818 if (error)
5819 goto bad;
5820 }
5821 if (ad->ad_id & ATH_DIAG_DYN) {
5822 /*
5823 * Allocate a buffer for the results (otherwise the HAL
5824 * returns a pointer to a buffer where we can read the
5825 * results). Note that we depend on the HAL leaving this
5826 * pointer for us to use below in reclaiming the buffer;
5827 * may want to be more defensive.
5828 */
5829 outdata = malloc(outsize, M_TEMP, M_NOWAIT);
5830 if (outdata == NULL) {
5831 error = ENOMEM;
5832 goto bad;
5833 }
5834 }
5835 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
5836 if (outsize < ad->ad_out_size)
5837 ad->ad_out_size = outsize;
5838 if (outdata != NULL)
5839 error = copyout(outdata, ad->ad_out_data,
5840 ad->ad_out_size);
5841 } else {
5842 error = EINVAL;
5843 }
5844bad:
5845 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
5846 free(indata, M_TEMP);
5847 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
5848 free(outdata, M_TEMP);
5849 return error;
5850}
5851#endif /* ATH_DIAGAPI */
5852
5853static int
5854ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
5855{
5856#define IS_RUNNING(ifp) \
5857 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
5858 struct ath_softc *sc = ifp->if_softc;
5859 struct ieee80211com *ic = ifp->if_l2com;
5860 struct ifreq *ifr = (struct ifreq *)data;
5861 const HAL_RATE_TABLE *rt;
5862 int error = 0;
5863
5864 switch (cmd) {
5865 case SIOCSIFFLAGS:
5866 ATH_LOCK(sc);
5867 if (IS_RUNNING(ifp)) {
5868 /*
5869 * To avoid rescanning another access point,
5870 * do not call ath_init() here. Instead,
5871 * only reflect promisc mode settings.
5872 */
5873 ath_mode_init(sc);
5874 } else if (ifp->if_flags & IFF_UP) {
5875 /*
5876 * Beware of being called during attach/detach
5877 * to reset promiscuous mode. In that case we
5878 * will still be marked UP but not RUNNING.
5879 * However trying to re-init the interface
5880 * is the wrong thing to do as we've already
5881 * torn down much of our state. There's
5882 * probably a better way to deal with this.
5883 */
5884 if (!sc->sc_invalid)
5885 ath_init(sc); /* XXX lose error */
5886 } else {
5887 ath_stop_locked(ifp);
5888#ifdef notyet
5889 /* XXX must wakeup in places like ath_vap_delete */
5890 if (!sc->sc_invalid)
5891 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP);
5892#endif
5893 }
5894 ATH_UNLOCK(sc);
5895 break;
5896 case SIOCGIFMEDIA:
5897 case SIOCSIFMEDIA:
5898 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
5899 break;
5900 case SIOCGATHSTATS:
5901 /* NB: embed these numbers to get a consistent view */
5902 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
5903 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
5904 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi);
5905 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi);
5906#ifdef IEEE80211_SUPPORT_TDMA
5907 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap);
5908 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam);
5909#endif
5910 rt = sc->sc_currates;
5911 sc->sc_stats.ast_tx_rate =
5912 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC;
5913 if (rt->info[sc->sc_txrix].phy & IEEE80211_T_HT)
5914 sc->sc_stats.ast_tx_rate |= IEEE80211_RATE_MCS;
5915 return copyout(&sc->sc_stats,
5916 ifr->ifr_data, sizeof (sc->sc_stats));
5917 case SIOCGATHAGSTATS:
5918 return copyout(&sc->sc_aggr_stats,
5919 ifr->ifr_data, sizeof (sc->sc_aggr_stats));
5920 case SIOCZATHSTATS:
5921 error = priv_check(curthread, PRIV_DRIVER);
5922 if (error == 0) {
5923 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats));
5924 memset(&sc->sc_aggr_stats, 0,
5925 sizeof(sc->sc_aggr_stats));
5926 memset(&sc->sc_intr_stats, 0,
5927 sizeof(sc->sc_intr_stats));
5928 }
5929 break;
5930#ifdef ATH_DIAGAPI
5931 case SIOCGATHDIAG:
5932 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr);
5933 break;
5934 case SIOCGATHPHYERR:
5935 error = ath_ioctl_phyerr(sc,(struct ath_diag*) ifr);
5936 break;
5937#endif
5938 case SIOCGATHSPECTRAL:
5939 error = ath_ioctl_spectral(sc,(struct ath_diag*) ifr);
5940 break;
5941 case SIOCGATHNODERATESTATS:
5942 error = ath_ioctl_ratestats(sc, (struct ath_rateioctl *) ifr);
5943 break;
5944 case SIOCGIFADDR:
5945 error = ether_ioctl(ifp, cmd, data);
5946 break;
5947 default:
5948 error = EINVAL;
5949 break;
5950 }
5951 return error;
5952#undef IS_RUNNING
5953}
5954
5955/*
5956 * Announce various information on device/driver attach.
5957 */
5958static void
5959ath_announce(struct ath_softc *sc)
5960{
5961 struct ifnet *ifp = sc->sc_ifp;
5962 struct ath_hal *ah = sc->sc_ah;
5963
5964 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n",
5965 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev,
5966 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
5967 if_printf(ifp, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n",
5968 ah->ah_analog2GhzRev, ah->ah_analog5GhzRev);
5969 if (bootverbose) {
5970 int i;
5971 for (i = 0; i <= WME_AC_VO; i++) {
5972 struct ath_txq *txq = sc->sc_ac2q[i];
5973 if_printf(ifp, "Use hw queue %u for %s traffic\n",
5974 txq->axq_qnum, ieee80211_wme_acnames[i]);
5975 }
5976 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
5977 sc->sc_cabq->axq_qnum);
5978 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
5979 }
5980 if (ath_rxbuf != ATH_RXBUF)
5981 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
5982 if (ath_txbuf != ATH_TXBUF)
5983 if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
5984 if (sc->sc_mcastkey && bootverbose)
5985 if_printf(ifp, "using multicast key search\n");
5986}
5987
5988static void
5989ath_dfs_tasklet(void *p, int npending)
5990{
5991 struct ath_softc *sc = (struct ath_softc *) p;
5992 struct ifnet *ifp = sc->sc_ifp;
5993 struct ieee80211com *ic = ifp->if_l2com;
5994
5995 /*
5996 * If previous processing has found a radar event,
5997 * signal this to the net80211 layer to begin DFS
5998 * processing.
5999 */
6000 if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) {
6001 /* DFS event found, initiate channel change */
6002 /*
6003 * XXX doesn't currently tell us whether the event
6004 * XXX was found in the primary or extension
6005 * XXX channel!
6006 */
6007 IEEE80211_LOCK(ic);
6008 ieee80211_dfs_notify_radar(ic, sc->sc_curchan);
6009 IEEE80211_UNLOCK(ic);
6010 }
6011}
6012
6013/*
6014 * Enable/disable power save. This must be called with
6015 * no TX driver locks currently held, so it should only
6016 * be called from the RX path (which doesn't hold any
6017 * TX driver locks.)
6018 */
6019static void
6020ath_node_powersave(struct ieee80211_node *ni, int enable)
6021{
6022#ifdef ATH_SW_PSQ
6023 struct ath_node *an = ATH_NODE(ni);
6024 struct ieee80211com *ic = ni->ni_ic;
6025 struct ath_softc *sc = ic->ic_ifp->if_softc;
6026 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6027
6028 /* XXX and no TXQ locks should be held here */
6029
6030 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, "%s: %6D: enable=%d\n",
6031 __func__,
6032 ni->ni_macaddr,
6033 ":",
6034 !! enable);
6035
6036 /* Suspend or resume software queue handling */
6037 if (enable)
6038 ath_tx_node_sleep(sc, an);
6039 else
6040 ath_tx_node_wakeup(sc, an);
6041
6042 /* Update net80211 state */
6043 avp->av_node_ps(ni, enable);
6044#else
6045 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6046
6047 /* Update net80211 state */
6048 avp->av_node_ps(ni, enable);
6049#endif/* ATH_SW_PSQ */
6050}
6051
6052/*
6053 * Notification from net80211 that the powersave queue state has
6054 * changed.
6055 *
6056 * Since the software queue also may have some frames:
6057 *
6058 * + if the node software queue has frames and the TID state
6059 * is 0, we set the TIM;
6060 * + if the node and the stack are both empty, we clear the TIM bit.
6061 * + If the stack tries to set the bit, always set it.
6062 * + If the stack tries to clear the bit, only clear it if the
6063 * software queue in question is also cleared.
6064 *
6065 * TODO: this is called during node teardown; so let's ensure this
6066 * is all correctly handled and that the TIM bit is cleared.
6067 * It may be that the node flush is called _AFTER_ the net80211
6068 * stack clears the TIM.
6069 *
6070 * Here is the racy part. Since it's possible >1 concurrent,
6071 * overlapping TXes will appear complete with a TX completion in
6072 * another thread, it's possible that the concurrent TIM calls will
6073 * clash. We can't hold the node lock here because setting the
6074 * TIM grabs the net80211 comlock and this may cause a LOR.
6075 * The solution is either to totally serialise _everything_ at
6076 * this point (ie, all TX, completion and any reset/flush go into
6077 * one taskqueue) or a new "ath TIM lock" needs to be created that
6078 * just wraps the driver state change and this call to avp->av_set_tim().
6079 *
6080 * The same race exists in the net80211 power save queue handling
6081 * as well. Since multiple transmitting threads may queue frames
6082 * into the driver, as well as ps-poll and the driver transmitting
6083 * frames (and thus clearing the psq), it's quite possible that
6084 * a packet entering the PSQ and a ps-poll being handled will
6085 * race, causing the TIM to be cleared and not re-set.
6086 */
6087static int
6088ath_node_set_tim(struct ieee80211_node *ni, int enable)
6089{
6090#ifdef ATH_SW_PSQ
6091 struct ieee80211com *ic = ni->ni_ic;
6092 struct ath_softc *sc = ic->ic_ifp->if_softc;
6093 struct ath_node *an = ATH_NODE(ni);
6094 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6095 int changed = 0;
6096
6097 ATH_TX_LOCK(sc);
6098 an->an_stack_psq = enable;
6099
6100 /*
6101 * This will get called for all operating modes,
6102 * even if avp->av_set_tim is unset.
6103 * It's currently set for hostap/ibss modes; but
6104 * the same infrastructure is used for both STA
6105 * and AP/IBSS node power save.
6106 */
6107 if (avp->av_set_tim == NULL) {
6108 ATH_TX_UNLOCK(sc);
6109 return (0);
6110 }
6111
6112 /*
6113 * If setting the bit, always set it here.
6114 * If clearing the bit, only clear it if the
6115 * software queue is also empty.
6116 *
6117 * If the node has left power save, just clear the TIM
6118 * bit regardless of the state of the power save queue.
6119 *
6120 * XXX TODO: although atomics are used, it's quite possible
6121 * that a race will occur between this and setting/clearing
6122 * in another thread. TX completion will occur always in
6123 * one thread, however setting/clearing the TIM bit can come
6124 * from a variety of different process contexts!
6125 */
6126 if (enable && an->an_tim_set == 1) {
6127 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6128 "%s: %6D: enable=%d, tim_set=1, ignoring\n",
6129 __func__,
6130 ni->ni_macaddr,
6131 ":",
6132 enable);
6133 ATH_TX_UNLOCK(sc);
6134 } else if (enable) {
6135 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6136 "%s: %6D: enable=%d, enabling TIM\n",
6137 __func__,
6138 ni->ni_macaddr,
6139 ":",
6140 enable);
6141 an->an_tim_set = 1;
6142 ATH_TX_UNLOCK(sc);
6143 changed = avp->av_set_tim(ni, enable);
6144 } else if (an->an_swq_depth == 0) {
6145 /* disable */
6146 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6147 "%s: %6D: enable=%d, an_swq_depth == 0, disabling\n",
6148 __func__,
6149 ni->ni_macaddr,
6150 ":",
6151 enable);
6152 an->an_tim_set = 0;
6153 ATH_TX_UNLOCK(sc);
6154 changed = avp->av_set_tim(ni, enable);
6155 } else if (! an->an_is_powersave) {
6156 /*
6157 * disable regardless; the node isn't in powersave now
6158 */
6159 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6160 "%s: %6D: enable=%d, an_pwrsave=0, disabling\n",
6161 __func__,
6162 ni->ni_macaddr,
6163 ":",
6164 enable);
6165 an->an_tim_set = 0;
6166 ATH_TX_UNLOCK(sc);
6167 changed = avp->av_set_tim(ni, enable);
6168 } else {
6169 /*
6170 * psq disable, node is currently in powersave, node
6171 * software queue isn't empty, so don't clear the TIM bit
6172 * for now.
6173 */
6174 ATH_TX_UNLOCK(sc);
6175 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6176 "%s: %6D: enable=%d, an_swq_depth > 0, ignoring\n",
6177 __func__,
6178 ni->ni_macaddr,
6179 ":",
6180 enable);
6181 changed = 0;
6182 }
6183
6184 return (changed);
6185#else
6186 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6187
6188 /*
6189 * Some operating modes don't set av_set_tim(), so don't
6190 * update it here.
6191 */
6192 if (avp->av_set_tim == NULL)
6193 return (0);
6194
6195 return (avp->av_set_tim(ni, enable));
6196#endif /* ATH_SW_PSQ */
6197}
6198
6199/*
6200 * Set or update the TIM from the software queue.
6201 *
6202 * Check the software queue depth before attempting to do lock
6203 * anything; that avoids trying to obtain the lock. Then,
6204 * re-check afterwards to ensure nothing has changed in the
6205 * meantime.
6206 *
6207 * set: This is designed to be called from the TX path, after
6208 * a frame has been queued; to see if the swq > 0.
6209 *
6210 * clear: This is designed to be called from the buffer completion point
6211 * (right now it's ath_tx_default_comp()) where the state of
6212 * a software queue has changed.
6213 *
6214 * It makes sense to place it at buffer free / completion rather
6215 * than after each software queue operation, as there's no real
6216 * point in churning the TIM bit as the last frames in the software
6217 * queue are transmitted. If they fail and we retry them, we'd
6218 * just be setting the TIM bit again anyway.
6219 */
6220void
6221ath_tx_update_tim(struct ath_softc *sc, struct ieee80211_node *ni,
6222 int enable)
6223{
6224#ifdef ATH_SW_PSQ
6225 struct ath_node *an;
6226 struct ath_vap *avp;
6227
6228 /* Don't do this for broadcast/etc frames */
6229 if (ni == NULL)
6230 return;
6231
6232 an = ATH_NODE(ni);
6233 avp = ATH_VAP(ni->ni_vap);
6234
6235 /*
6236 * And for operating modes without the TIM handler set, let's
6237 * just skip those.
6238 */
6239 if (avp->av_set_tim == NULL)
6240 return;
6241
6242 ATH_TX_LOCK_ASSERT(sc);
6243
6244 if (enable) {
6245 if (an->an_is_powersave &&
6246 an->an_tim_set == 0 &&
6247 an->an_swq_depth != 0) {
6248 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6249 "%s: %6D: swq_depth>0, tim_set=0, set!\n",
6250 __func__,
6251 ni->ni_macaddr,
6252 ":");
6253 an->an_tim_set = 1;
6254 (void) avp->av_set_tim(ni, 1);
6255 }
6256 } else {
6257 /*
6258 * Don't bother grabbing the lock unless the queue is empty.
6259 */
6260 if (&an->an_swq_depth != 0)
6261 return;
6262
6263 if (an->an_is_powersave &&
6264 an->an_stack_psq == 0 &&
6265 an->an_tim_set == 1 &&
6266 an->an_swq_depth == 0) {
6267 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6268 "%s: %6D: swq_depth=0, tim_set=1, psq_set=0,"
6269 " clear!\n",
6270 __func__,
6271 ni->ni_macaddr,
6272 ":");
6273 an->an_tim_set = 0;
6274 (void) avp->av_set_tim(ni, 0);
6275 }
6276 }
6277#else
6278 return;
6279#endif /* ATH_SW_PSQ */
6280}
6281
6282/*
6283 * Received a ps-poll frame from net80211.
6284 *
6285 * Here we get a chance to serve out a software-queued frame ourselves
6286 * before we punt it to net80211 to transmit us one itself - either
6287 * because there's traffic in the net80211 psq, or a NULL frame to
6288 * indicate there's nothing else.
6289 */
6290static void
6291ath_node_recv_pspoll(struct ieee80211_node *ni, struct mbuf *m)
6292{
6293#ifdef ATH_SW_PSQ
6294 struct ath_node *an;
6295 struct ath_vap *avp;
6296 struct ieee80211com *ic = ni->ni_ic;
6297 struct ath_softc *sc = ic->ic_ifp->if_softc;
6298 int tid;
6299
6300 /* Just paranoia */
6301 if (ni == NULL)
6302 return;
6303
6304 /*
6305 * Unassociated (temporary node) station.
6306 */
6307 if (ni->ni_associd == 0)
6308 return;
6309
6310 /*
6311 * We do have an active node, so let's begin looking into it.
6312 */
6313 an = ATH_NODE(ni);
6314 avp = ATH_VAP(ni->ni_vap);
6315
6316 /*
6317 * For now, we just call the original ps-poll method.
6318 * Once we're ready to flip this on:
6319 *
6320 * + Set leak to 1, as no matter what we're going to have
6321 * to send a frame;
6322 * + Check the software queue and if there's something in it,
6323 * schedule the highest TID thas has traffic from this node.
6324 * Then make sure we schedule the software scheduler to
6325 * run so it picks up said frame.
6326 *
6327 * That way whatever happens, we'll at least send _a_ frame
6328 * to the given node.
6329 *
6330 * Again, yes, it's crappy QoS if the node has multiple
6331 * TIDs worth of traffic - but let's get it working first
6332 * before we optimise it.
6333 *
6334 * Also yes, there's definitely latency here - we're not
6335 * direct dispatching to the hardware in this path (and
6336 * we're likely being called from the packet receive path,
6337 * so going back into TX may be a little hairy!) but again
6338 * I'd like to get this working first before optimising
6339 * turn-around time.
6340 */
6341
6342 ATH_TX_LOCK(sc);
6343
6344 /*
6345 * Legacy - we're called and the node isn't asleep.
6346 * Immediately punt.
6347 */
6348 if (! an->an_is_powersave) {
6349 device_printf(sc->sc_dev,
6350 "%s: %6D: not in powersave?\n",
6351 __func__,
6352 ni->ni_macaddr,
6353 ":");
6354 ATH_TX_UNLOCK(sc);
6355 avp->av_recv_pspoll(ni, m);
6356 return;
6357 }
6358
6359 /*
6360 * We're in powersave.
6361 *
6362 * Leak a frame.
6363 */
6364 an->an_leak_count = 1;
6365
6366 /*
6367 * Now, if there's no frames in the node, just punt to
6368 * recv_pspoll.
6369 *
6370 * Don't bother checking if the TIM bit is set, we really
6371 * only care if there are any frames here!
6372 */
6373 if (an->an_swq_depth == 0) {
6374 ATH_TX_UNLOCK(sc);
6375 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6376 "%s: %6D: SWQ empty; punting to net80211\n",
6377 __func__,
6378 ni->ni_macaddr,
6379 ":");
6380 avp->av_recv_pspoll(ni, m);
6381 return;
6382 }
6383
6384 /*
6385 * Ok, let's schedule the highest TID that has traffic
6386 * and then schedule something.
6387 */
6388 for (tid = IEEE80211_TID_SIZE - 1; tid >= 0; tid--) {
6389 struct ath_tid *atid = &an->an_tid[tid];
6390 /*
6391 * No frames? Skip.
6392 */
6393 if (atid->axq_depth == 0)
6394 continue;
6395 ath_tx_tid_sched(sc, atid);
6396 /*
6397 * XXX we could do a direct call to the TXQ
6398 * scheduler code here to optimise latency
6399 * at the expense of a REALLY deep callstack.
6400 */
6401 ATH_TX_UNLOCK(sc);
6402 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask);
6403 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6404 "%s: %6D: leaking frame to TID %d\n",
6405 __func__,
6406 ni->ni_macaddr,
6407 ":",
6408 tid);
6409 return;
6410 }
6411
6412 ATH_TX_UNLOCK(sc);
6413
6414 /*
6415 * XXX nothing in the TIDs at this point? Eek.
6416 */
6417 device_printf(sc->sc_dev, "%s: %6D: TIDs empty, but ath_node showed traffic?!\n",
6418 __func__,
6419 ni->ni_macaddr,
6420 ":");
6421 avp->av_recv_pspoll(ni, m);
6422#else
6423 avp->av_recv_pspoll(ni, m);
6424#endif /* ATH_SW_PSQ */
6425}
6426
6427MODULE_VERSION(if_ath, 1);
6428MODULE_DEPEND(if_ath, wlan, 1, 1, 1); /* 802.11 media layer */
6429#if defined(IEEE80211_ALQ) || defined(AH_DEBUG_ALQ)
6430MODULE_DEPEND(if_ath, alq, 1, 1, 1);
6431#endif
| 844 sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW;
845 sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH;
846 sc->sc_aggr_limit = ATH_AGGR_MAXSIZE;
847 sc->sc_delim_min_pad = 0;
848
849 /*
850 * Check if the hardware requires PCI register serialisation.
851 * Some of the Owl based MACs require this.
852 */
853 if (mp_ncpus > 1 &&
854 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR,
855 0, NULL) == HAL_OK) {
856 sc->sc_ah->ah_config.ah_serialise_reg_war = 1;
857 device_printf(sc->sc_dev,
858 "Enabling register serialisation\n");
859 }
860
861 /*
862 * Initialise the deferred completed RX buffer list.
863 */
864 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP]);
865 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP]);
866
867 /*
868 * Indicate we need the 802.11 header padded to a
869 * 32-bit boundary for 4-address and QoS frames.
870 */
871 ic->ic_flags |= IEEE80211_F_DATAPAD;
872
873 /*
874 * Query the hal about antenna support.
875 */
876 sc->sc_defant = ath_hal_getdefantenna(ah);
877
878 /*
879 * Not all chips have the VEOL support we want to
880 * use with IBSS beacons; check here for it.
881 */
882 sc->sc_hasveol = ath_hal_hasveol(ah);
883
884 /* get mac address from hardware */
885 ath_hal_getmac(ah, macaddr);
886 if (sc->sc_hasbmask)
887 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask);
888
889 /* NB: used to size node table key mapping array */
890 ic->ic_max_keyix = sc->sc_keymax;
891 /* call MI attach routine. */
892 ieee80211_ifattach(ic, macaddr);
893 ic->ic_setregdomain = ath_setregdomain;
894 ic->ic_getradiocaps = ath_getradiocaps;
895 sc->sc_opmode = HAL_M_STA;
896
897 /* override default methods */
898 ic->ic_newassoc = ath_newassoc;
899 ic->ic_updateslot = ath_updateslot;
900 ic->ic_wme.wme_update = ath_wme_update;
901 ic->ic_vap_create = ath_vap_create;
902 ic->ic_vap_delete = ath_vap_delete;
903 ic->ic_raw_xmit = ath_raw_xmit;
904 ic->ic_update_mcast = ath_update_mcast;
905 ic->ic_update_promisc = ath_update_promisc;
906 ic->ic_node_alloc = ath_node_alloc;
907 sc->sc_node_free = ic->ic_node_free;
908 ic->ic_node_free = ath_node_free;
909 sc->sc_node_cleanup = ic->ic_node_cleanup;
910 ic->ic_node_cleanup = ath_node_cleanup;
911 ic->ic_node_getsignal = ath_node_getsignal;
912 ic->ic_scan_start = ath_scan_start;
913 ic->ic_scan_end = ath_scan_end;
914 ic->ic_set_channel = ath_set_channel;
915#ifdef ATH_ENABLE_11N
916 /* 802.11n specific - but just override anyway */
917 sc->sc_addba_request = ic->ic_addba_request;
918 sc->sc_addba_response = ic->ic_addba_response;
919 sc->sc_addba_stop = ic->ic_addba_stop;
920 sc->sc_bar_response = ic->ic_bar_response;
921 sc->sc_addba_response_timeout = ic->ic_addba_response_timeout;
922
923 ic->ic_addba_request = ath_addba_request;
924 ic->ic_addba_response = ath_addba_response;
925 ic->ic_addba_response_timeout = ath_addba_response_timeout;
926 ic->ic_addba_stop = ath_addba_stop;
927 ic->ic_bar_response = ath_bar_response;
928
929 ic->ic_update_chw = ath_update_chw;
930#endif /* ATH_ENABLE_11N */
931
932#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
933 /*
934 * There's one vendor bitmap entry in the RX radiotap
935 * header; make sure that's taken into account.
936 */
937 ieee80211_radiotap_attachv(ic,
938 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 0,
939 ATH_TX_RADIOTAP_PRESENT,
940 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 1,
941 ATH_RX_RADIOTAP_PRESENT);
942#else
943 /*
944 * No vendor bitmap/extensions are present.
945 */
946 ieee80211_radiotap_attach(ic,
947 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
948 ATH_TX_RADIOTAP_PRESENT,
949 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
950 ATH_RX_RADIOTAP_PRESENT);
951#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
952
953 /*
954 * Setup the ALQ logging if required
955 */
956#ifdef ATH_DEBUG_ALQ
957 if_ath_alq_init(&sc->sc_alq, device_get_nameunit(sc->sc_dev));
958 if_ath_alq_setcfg(&sc->sc_alq,
959 sc->sc_ah->ah_macVersion,
960 sc->sc_ah->ah_macRev,
961 sc->sc_ah->ah_phyRev,
962 sc->sc_ah->ah_magic);
963#endif
964
965 /*
966 * Setup dynamic sysctl's now that country code and
967 * regdomain are available from the hal.
968 */
969 ath_sysctlattach(sc);
970 ath_sysctl_stats_attach(sc);
971 ath_sysctl_hal_attach(sc);
972
973 if (bootverbose)
974 ieee80211_announce(ic);
975 ath_announce(sc);
976 return 0;
977bad2:
978 ath_tx_cleanup(sc);
979 ath_desc_free(sc);
980 ath_txdma_teardown(sc);
981 ath_rxdma_teardown(sc);
982bad:
983 if (ah)
984 ath_hal_detach(ah);
985
986 /*
987 * To work around scoping issues with CURVNET_SET/CURVNET_RESTORE..
988 */
989 if (ifp != NULL && ifp->if_vnet) {
990 CURVNET_SET(ifp->if_vnet);
991 if_free(ifp);
992 CURVNET_RESTORE();
993 } else if (ifp != NULL)
994 if_free(ifp);
995 sc->sc_invalid = 1;
996 return error;
997}
998
999int
1000ath_detach(struct ath_softc *sc)
1001{
1002 struct ifnet *ifp = sc->sc_ifp;
1003
1004 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1005 __func__, ifp->if_flags);
1006
1007 /*
1008 * NB: the order of these is important:
1009 * o stop the chip so no more interrupts will fire
1010 * o call the 802.11 layer before detaching the hal to
1011 * insure callbacks into the driver to delete global
1012 * key cache entries can be handled
1013 * o free the taskqueue which drains any pending tasks
1014 * o reclaim the tx queue data structures after calling
1015 * the 802.11 layer as we'll get called back to reclaim
1016 * node state and potentially want to use them
1017 * o to cleanup the tx queues the hal is called, so detach
1018 * it last
1019 * Other than that, it's straightforward...
1020 */
1021 ath_stop(ifp);
1022 ieee80211_ifdetach(ifp->if_l2com);
1023 taskqueue_free(sc->sc_tq);
1024#ifdef ATH_TX99_DIAG
1025 if (sc->sc_tx99 != NULL)
1026 sc->sc_tx99->detach(sc->sc_tx99);
1027#endif
1028 ath_rate_detach(sc->sc_rc);
1029#ifdef ATH_DEBUG_ALQ
1030 if_ath_alq_tidyup(&sc->sc_alq);
1031#endif
1032 ath_spectral_detach(sc);
1033 ath_dfs_detach(sc);
1034 ath_desc_free(sc);
1035 ath_txdma_teardown(sc);
1036 ath_rxdma_teardown(sc);
1037 ath_tx_cleanup(sc);
1038 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */
1039
1040 CURVNET_SET(ifp->if_vnet);
1041 if_free(ifp);
1042 CURVNET_RESTORE();
1043
1044 return 0;
1045}
1046
1047/*
1048 * MAC address handling for multiple BSS on the same radio.
1049 * The first vap uses the MAC address from the EEPROM. For
1050 * subsequent vap's we set the U/L bit (bit 1) in the MAC
1051 * address and use the next six bits as an index.
1052 */
1053static void
1054assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone)
1055{
1056 int i;
1057
1058 if (clone && sc->sc_hasbmask) {
1059 /* NB: we only do this if h/w supports multiple bssid */
1060 for (i = 0; i < 8; i++)
1061 if ((sc->sc_bssidmask & (1<<i)) == 0)
1062 break;
1063 if (i != 0)
1064 mac[0] |= (i << 2)|0x2;
1065 } else
1066 i = 0;
1067 sc->sc_bssidmask |= 1<<i;
1068 sc->sc_hwbssidmask[0] &= ~mac[0];
1069 if (i == 0)
1070 sc->sc_nbssid0++;
1071}
1072
1073static void
1074reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN])
1075{
1076 int i = mac[0] >> 2;
1077 uint8_t mask;
1078
1079 if (i != 0 || --sc->sc_nbssid0 == 0) {
1080 sc->sc_bssidmask &= ~(1<<i);
1081 /* recalculate bssid mask from remaining addresses */
1082 mask = 0xff;
1083 for (i = 1; i < 8; i++)
1084 if (sc->sc_bssidmask & (1<<i))
1085 mask &= ~((i<<2)|0x2);
1086 sc->sc_hwbssidmask[0] |= mask;
1087 }
1088}
1089
1090/*
1091 * Assign a beacon xmit slot. We try to space out
1092 * assignments so when beacons are staggered the
1093 * traffic coming out of the cab q has maximal time
1094 * to go out before the next beacon is scheduled.
1095 */
1096static int
1097assign_bslot(struct ath_softc *sc)
1098{
1099 u_int slot, free;
1100
1101 free = 0;
1102 for (slot = 0; slot < ATH_BCBUF; slot++)
1103 if (sc->sc_bslot[slot] == NULL) {
1104 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL &&
1105 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL)
1106 return slot;
1107 free = slot;
1108 /* NB: keep looking for a double slot */
1109 }
1110 return free;
1111}
1112
1113static struct ieee80211vap *
1114ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
1115 enum ieee80211_opmode opmode, int flags,
1116 const uint8_t bssid[IEEE80211_ADDR_LEN],
1117 const uint8_t mac0[IEEE80211_ADDR_LEN])
1118{
1119 struct ath_softc *sc = ic->ic_ifp->if_softc;
1120 struct ath_vap *avp;
1121 struct ieee80211vap *vap;
1122 uint8_t mac[IEEE80211_ADDR_LEN];
1123 int needbeacon, error;
1124 enum ieee80211_opmode ic_opmode;
1125
1126 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap),
1127 M_80211_VAP, M_WAITOK | M_ZERO);
1128 needbeacon = 0;
1129 IEEE80211_ADDR_COPY(mac, mac0);
1130
1131 ATH_LOCK(sc);
1132 ic_opmode = opmode; /* default to opmode of new vap */
1133 switch (opmode) {
1134 case IEEE80211_M_STA:
1135 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */
1136 device_printf(sc->sc_dev, "only 1 sta vap supported\n");
1137 goto bad;
1138 }
1139 if (sc->sc_nvaps) {
1140 /*
1141 * With multiple vaps we must fall back
1142 * to s/w beacon miss handling.
1143 */
1144 flags |= IEEE80211_CLONE_NOBEACONS;
1145 }
1146 if (flags & IEEE80211_CLONE_NOBEACONS) {
1147 /*
1148 * Station mode w/o beacons are implemented w/ AP mode.
1149 */
1150 ic_opmode = IEEE80211_M_HOSTAP;
1151 }
1152 break;
1153 case IEEE80211_M_IBSS:
1154 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */
1155 device_printf(sc->sc_dev,
1156 "only 1 ibss vap supported\n");
1157 goto bad;
1158 }
1159 needbeacon = 1;
1160 break;
1161 case IEEE80211_M_AHDEMO:
1162#ifdef IEEE80211_SUPPORT_TDMA
1163 if (flags & IEEE80211_CLONE_TDMA) {
1164 if (sc->sc_nvaps != 0) {
1165 device_printf(sc->sc_dev,
1166 "only 1 tdma vap supported\n");
1167 goto bad;
1168 }
1169 needbeacon = 1;
1170 flags |= IEEE80211_CLONE_NOBEACONS;
1171 }
1172 /* fall thru... */
1173#endif
1174 case IEEE80211_M_MONITOR:
1175 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) {
1176 /*
1177 * Adopt existing mode. Adding a monitor or ahdemo
1178 * vap to an existing configuration is of dubious
1179 * value but should be ok.
1180 */
1181 /* XXX not right for monitor mode */
1182 ic_opmode = ic->ic_opmode;
1183 }
1184 break;
1185 case IEEE80211_M_HOSTAP:
1186 case IEEE80211_M_MBSS:
1187 needbeacon = 1;
1188 break;
1189 case IEEE80211_M_WDS:
1190 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) {
1191 device_printf(sc->sc_dev,
1192 "wds not supported in sta mode\n");
1193 goto bad;
1194 }
1195 /*
1196 * Silently remove any request for a unique
1197 * bssid; WDS vap's always share the local
1198 * mac address.
1199 */
1200 flags &= ~IEEE80211_CLONE_BSSID;
1201 if (sc->sc_nvaps == 0)
1202 ic_opmode = IEEE80211_M_HOSTAP;
1203 else
1204 ic_opmode = ic->ic_opmode;
1205 break;
1206 default:
1207 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
1208 goto bad;
1209 }
1210 /*
1211 * Check that a beacon buffer is available; the code below assumes it.
1212 */
1213 if (needbeacon & TAILQ_EMPTY(&sc->sc_bbuf)) {
1214 device_printf(sc->sc_dev, "no beacon buffer available\n");
1215 goto bad;
1216 }
1217
1218 /* STA, AHDEMO? */
1219 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) {
1220 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID);
1221 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1222 }
1223
1224 vap = &avp->av_vap;
1225 /* XXX can't hold mutex across if_alloc */
1226 ATH_UNLOCK(sc);
1227 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags,
1228 bssid, mac);
1229 ATH_LOCK(sc);
1230 if (error != 0) {
1231 device_printf(sc->sc_dev, "%s: error %d creating vap\n",
1232 __func__, error);
1233 goto bad2;
1234 }
1235
1236 /* h/w crypto support */
1237 vap->iv_key_alloc = ath_key_alloc;
1238 vap->iv_key_delete = ath_key_delete;
1239 vap->iv_key_set = ath_key_set;
1240 vap->iv_key_update_begin = ath_key_update_begin;
1241 vap->iv_key_update_end = ath_key_update_end;
1242
1243 /* override various methods */
1244 avp->av_recv_mgmt = vap->iv_recv_mgmt;
1245 vap->iv_recv_mgmt = ath_recv_mgmt;
1246 vap->iv_reset = ath_reset_vap;
1247 vap->iv_update_beacon = ath_beacon_update;
1248 avp->av_newstate = vap->iv_newstate;
1249 vap->iv_newstate = ath_newstate;
1250 avp->av_bmiss = vap->iv_bmiss;
1251 vap->iv_bmiss = ath_bmiss_vap;
1252
1253 avp->av_node_ps = vap->iv_node_ps;
1254 vap->iv_node_ps = ath_node_powersave;
1255
1256 avp->av_set_tim = vap->iv_set_tim;
1257 vap->iv_set_tim = ath_node_set_tim;
1258
1259 avp->av_recv_pspoll = vap->iv_recv_pspoll;
1260 vap->iv_recv_pspoll = ath_node_recv_pspoll;
1261
1262 /* Set default parameters */
1263
1264 /*
1265 * Anything earlier than some AR9300 series MACs don't
1266 * support a smaller MPDU density.
1267 */
1268 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8;
1269 /*
1270 * All NICs can handle the maximum size, however
1271 * AR5416 based MACs can only TX aggregates w/ RTS
1272 * protection when the total aggregate size is <= 8k.
1273 * However, for now that's enforced by the TX path.
1274 */
1275 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K;
1276
1277 avp->av_bslot = -1;
1278 if (needbeacon) {
1279 /*
1280 * Allocate beacon state and setup the q for buffered
1281 * multicast frames. We know a beacon buffer is
1282 * available because we checked above.
1283 */
1284 avp->av_bcbuf = TAILQ_FIRST(&sc->sc_bbuf);
1285 TAILQ_REMOVE(&sc->sc_bbuf, avp->av_bcbuf, bf_list);
1286 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) {
1287 /*
1288 * Assign the vap to a beacon xmit slot. As above
1289 * this cannot fail to find a free one.
1290 */
1291 avp->av_bslot = assign_bslot(sc);
1292 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL,
1293 ("beacon slot %u not empty", avp->av_bslot));
1294 sc->sc_bslot[avp->av_bslot] = vap;
1295 sc->sc_nbcnvaps++;
1296 }
1297 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) {
1298 /*
1299 * Multple vaps are to transmit beacons and we
1300 * have h/w support for TSF adjusting; enable
1301 * use of staggered beacons.
1302 */
1303 sc->sc_stagbeacons = 1;
1304 }
1305 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ);
1306 }
1307
1308 ic->ic_opmode = ic_opmode;
1309 if (opmode != IEEE80211_M_WDS) {
1310 sc->sc_nvaps++;
1311 if (opmode == IEEE80211_M_STA)
1312 sc->sc_nstavaps++;
1313 if (opmode == IEEE80211_M_MBSS)
1314 sc->sc_nmeshvaps++;
1315 }
1316 switch (ic_opmode) {
1317 case IEEE80211_M_IBSS:
1318 sc->sc_opmode = HAL_M_IBSS;
1319 break;
1320 case IEEE80211_M_STA:
1321 sc->sc_opmode = HAL_M_STA;
1322 break;
1323 case IEEE80211_M_AHDEMO:
1324#ifdef IEEE80211_SUPPORT_TDMA
1325 if (vap->iv_caps & IEEE80211_C_TDMA) {
1326 sc->sc_tdma = 1;
1327 /* NB: disable tsf adjust */
1328 sc->sc_stagbeacons = 0;
1329 }
1330 /*
1331 * NB: adhoc demo mode is a pseudo mode; to the hal it's
1332 * just ap mode.
1333 */
1334 /* fall thru... */
1335#endif
1336 case IEEE80211_M_HOSTAP:
1337 case IEEE80211_M_MBSS:
1338 sc->sc_opmode = HAL_M_HOSTAP;
1339 break;
1340 case IEEE80211_M_MONITOR:
1341 sc->sc_opmode = HAL_M_MONITOR;
1342 break;
1343 default:
1344 /* XXX should not happen */
1345 break;
1346 }
1347 if (sc->sc_hastsfadd) {
1348 /*
1349 * Configure whether or not TSF adjust should be done.
1350 */
1351 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons);
1352 }
1353 if (flags & IEEE80211_CLONE_NOBEACONS) {
1354 /*
1355 * Enable s/w beacon miss handling.
1356 */
1357 sc->sc_swbmiss = 1;
1358 }
1359 ATH_UNLOCK(sc);
1360
1361 /* complete setup */
1362 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status);
1363 return vap;
1364bad2:
1365 reclaim_address(sc, mac);
1366 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1367bad:
1368 free(avp, M_80211_VAP);
1369 ATH_UNLOCK(sc);
1370 return NULL;
1371}
1372
1373static void
1374ath_vap_delete(struct ieee80211vap *vap)
1375{
1376 struct ieee80211com *ic = vap->iv_ic;
1377 struct ifnet *ifp = ic->ic_ifp;
1378 struct ath_softc *sc = ifp->if_softc;
1379 struct ath_hal *ah = sc->sc_ah;
1380 struct ath_vap *avp = ATH_VAP(vap);
1381
1382 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
1383 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1384 /*
1385 * Quiesce the hardware while we remove the vap. In
1386 * particular we need to reclaim all references to
1387 * the vap state by any frames pending on the tx queues.
1388 */
1389 ath_hal_intrset(ah, 0); /* disable interrupts */
1390 ath_draintxq(sc, ATH_RESET_DEFAULT); /* stop hw xmit side */
1391 /* XXX Do all frames from all vaps/nodes need draining here? */
1392 ath_stoprecv(sc, 1); /* stop recv side */
1393 }
1394
1395 ieee80211_vap_detach(vap);
1396
1397 /*
1398 * XXX Danger Will Robinson! Danger!
1399 *
1400 * Because ieee80211_vap_detach() can queue a frame (the station
1401 * diassociate message?) after we've drained the TXQ and
1402 * flushed the software TXQ, we will end up with a frame queued
1403 * to a node whose vap is about to be freed.
1404 *
1405 * To work around this, flush the hardware/software again.
1406 * This may be racy - the ath task may be running and the packet
1407 * may be being scheduled between sw->hw txq. Tsk.
1408 *
1409 * TODO: figure out why a new node gets allocated somewhere around
1410 * here (after the ath_tx_swq() call; and after an ath_stop_locked()
1411 * call!)
1412 */
1413
1414 ath_draintxq(sc, ATH_RESET_DEFAULT);
1415
1416 ATH_LOCK(sc);
1417 /*
1418 * Reclaim beacon state. Note this must be done before
1419 * the vap instance is reclaimed as we may have a reference
1420 * to it in the buffer for the beacon frame.
1421 */
1422 if (avp->av_bcbuf != NULL) {
1423 if (avp->av_bslot != -1) {
1424 sc->sc_bslot[avp->av_bslot] = NULL;
1425 sc->sc_nbcnvaps--;
1426 }
1427 ath_beacon_return(sc, avp->av_bcbuf);
1428 avp->av_bcbuf = NULL;
1429 if (sc->sc_nbcnvaps == 0) {
1430 sc->sc_stagbeacons = 0;
1431 if (sc->sc_hastsfadd)
1432 ath_hal_settsfadjust(sc->sc_ah, 0);
1433 }
1434 /*
1435 * Reclaim any pending mcast frames for the vap.
1436 */
1437 ath_tx_draintxq(sc, &avp->av_mcastq);
1438 }
1439 /*
1440 * Update bookkeeping.
1441 */
1442 if (vap->iv_opmode == IEEE80211_M_STA) {
1443 sc->sc_nstavaps--;
1444 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss)
1445 sc->sc_swbmiss = 0;
1446 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
1447 vap->iv_opmode == IEEE80211_M_MBSS) {
1448 reclaim_address(sc, vap->iv_myaddr);
1449 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask);
1450 if (vap->iv_opmode == IEEE80211_M_MBSS)
1451 sc->sc_nmeshvaps--;
1452 }
1453 if (vap->iv_opmode != IEEE80211_M_WDS)
1454 sc->sc_nvaps--;
1455#ifdef IEEE80211_SUPPORT_TDMA
1456 /* TDMA operation ceases when the last vap is destroyed */
1457 if (sc->sc_tdma && sc->sc_nvaps == 0) {
1458 sc->sc_tdma = 0;
1459 sc->sc_swbmiss = 0;
1460 }
1461#endif
1462 free(avp, M_80211_VAP);
1463
1464 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1465 /*
1466 * Restart rx+tx machines if still running (RUNNING will
1467 * be reset if we just destroyed the last vap).
1468 */
1469 if (ath_startrecv(sc) != 0)
1470 if_printf(ifp, "%s: unable to restart recv logic\n",
1471 __func__);
1472 if (sc->sc_beacons) { /* restart beacons */
1473#ifdef IEEE80211_SUPPORT_TDMA
1474 if (sc->sc_tdma)
1475 ath_tdma_config(sc, NULL);
1476 else
1477#endif
1478 ath_beacon_config(sc, NULL);
1479 }
1480 ath_hal_intrset(ah, sc->sc_imask);
1481 }
1482 ATH_UNLOCK(sc);
1483}
1484
1485void
1486ath_suspend(struct ath_softc *sc)
1487{
1488 struct ifnet *ifp = sc->sc_ifp;
1489 struct ieee80211com *ic = ifp->if_l2com;
1490
1491 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1492 __func__, ifp->if_flags);
1493
1494 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0;
1495
1496 ieee80211_suspend_all(ic);
1497 /*
1498 * NB: don't worry about putting the chip in low power
1499 * mode; pci will power off our socket on suspend and
1500 * CardBus detaches the device.
1501 */
1502
1503 /*
1504 * XXX ensure none of the taskqueues are running
1505 * XXX ensure sc_invalid is 1
1506 * XXX ensure the calibration callout is disabled
1507 */
1508
1509 /* Disable the PCIe PHY, complete with workarounds */
1510 ath_hal_enablepcie(sc->sc_ah, 1, 1);
1511}
1512
1513/*
1514 * Reset the key cache since some parts do not reset the
1515 * contents on resume. First we clear all entries, then
1516 * re-load keys that the 802.11 layer assumes are setup
1517 * in h/w.
1518 */
1519static void
1520ath_reset_keycache(struct ath_softc *sc)
1521{
1522 struct ifnet *ifp = sc->sc_ifp;
1523 struct ieee80211com *ic = ifp->if_l2com;
1524 struct ath_hal *ah = sc->sc_ah;
1525 int i;
1526
1527 for (i = 0; i < sc->sc_keymax; i++)
1528 ath_hal_keyreset(ah, i);
1529 ieee80211_crypto_reload_keys(ic);
1530}
1531
1532/*
1533 * Fetch the current chainmask configuration based on the current
1534 * operating channel and options.
1535 */
1536static void
1537ath_update_chainmasks(struct ath_softc *sc, struct ieee80211_channel *chan)
1538{
1539
1540 /*
1541 * Set TX chainmask to the currently configured chainmask;
1542 * the TX chainmask depends upon the current operating mode.
1543 */
1544 sc->sc_cur_rxchainmask = sc->sc_rxchainmask;
1545 if (IEEE80211_IS_CHAN_HT(chan)) {
1546 sc->sc_cur_txchainmask = sc->sc_txchainmask;
1547 } else {
1548 sc->sc_cur_txchainmask = 1;
1549 }
1550
1551 DPRINTF(sc, ATH_DEBUG_RESET,
1552 "%s: TX chainmask is now 0x%x, RX is now 0x%x\n",
1553 __func__,
1554 sc->sc_cur_txchainmask,
1555 sc->sc_cur_rxchainmask);
1556}
1557
1558void
1559ath_resume(struct ath_softc *sc)
1560{
1561 struct ifnet *ifp = sc->sc_ifp;
1562 struct ieee80211com *ic = ifp->if_l2com;
1563 struct ath_hal *ah = sc->sc_ah;
1564 HAL_STATUS status;
1565
1566 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1567 __func__, ifp->if_flags);
1568
1569 /* Re-enable PCIe, re-enable the PCIe bus */
1570 ath_hal_enablepcie(ah, 0, 0);
1571
1572 /*
1573 * Must reset the chip before we reload the
1574 * keycache as we were powered down on suspend.
1575 */
1576 ath_update_chainmasks(sc,
1577 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan);
1578 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
1579 sc->sc_cur_rxchainmask);
1580 ath_hal_reset(ah, sc->sc_opmode,
1581 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan,
1582 AH_FALSE, &status);
1583 ath_reset_keycache(sc);
1584
1585 /* Let DFS at it in case it's a DFS channel */
1586 ath_dfs_radar_enable(sc, ic->ic_curchan);
1587
1588 /* Let spectral at in case spectral is enabled */
1589 ath_spectral_enable(sc, ic->ic_curchan);
1590
1591 /*
1592 * If we're doing TDMA, enforce the TXOP limitation for chips that
1593 * support it.
1594 */
1595 if (sc->sc_hasenforcetxop && sc->sc_tdma)
1596 ath_hal_setenforcetxop(sc->sc_ah, 1);
1597 else
1598 ath_hal_setenforcetxop(sc->sc_ah, 0);
1599
1600 /* Restore the LED configuration */
1601 ath_led_config(sc);
1602 ath_hal_setledstate(ah, HAL_LED_INIT);
1603
1604 if (sc->sc_resume_up)
1605 ieee80211_resume_all(ic);
1606
1607 /* XXX beacons ? */
1608}
1609
1610void
1611ath_shutdown(struct ath_softc *sc)
1612{
1613 struct ifnet *ifp = sc->sc_ifp;
1614
1615 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1616 __func__, ifp->if_flags);
1617
1618 ath_stop(ifp);
1619 /* NB: no point powering down chip as we're about to reboot */
1620}
1621
1622/*
1623 * Interrupt handler. Most of the actual processing is deferred.
1624 */
1625void
1626ath_intr(void *arg)
1627{
1628 struct ath_softc *sc = arg;
1629 struct ifnet *ifp = sc->sc_ifp;
1630 struct ath_hal *ah = sc->sc_ah;
1631 HAL_INT status = 0;
1632 uint32_t txqs;
1633
1634 /*
1635 * If we're inside a reset path, just print a warning and
1636 * clear the ISR. The reset routine will finish it for us.
1637 */
1638 ATH_PCU_LOCK(sc);
1639 if (sc->sc_inreset_cnt) {
1640 HAL_INT status;
1641 ath_hal_getisr(ah, &status); /* clear ISR */
1642 ath_hal_intrset(ah, 0); /* disable further intr's */
1643 DPRINTF(sc, ATH_DEBUG_ANY,
1644 "%s: in reset, ignoring: status=0x%x\n",
1645 __func__, status);
1646 ATH_PCU_UNLOCK(sc);
1647 return;
1648 }
1649
1650 if (sc->sc_invalid) {
1651 /*
1652 * The hardware is not ready/present, don't touch anything.
1653 * Note this can happen early on if the IRQ is shared.
1654 */
1655 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
1656 ATH_PCU_UNLOCK(sc);
1657 return;
1658 }
1659 if (!ath_hal_intrpend(ah)) { /* shared irq, not for us */
1660 ATH_PCU_UNLOCK(sc);
1661 return;
1662 }
1663
1664 if ((ifp->if_flags & IFF_UP) == 0 ||
1665 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1666 HAL_INT status;
1667
1668 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
1669 __func__, ifp->if_flags);
1670 ath_hal_getisr(ah, &status); /* clear ISR */
1671 ath_hal_intrset(ah, 0); /* disable further intr's */
1672 ATH_PCU_UNLOCK(sc);
1673 return;
1674 }
1675
1676 /*
1677 * Figure out the reason(s) for the interrupt. Note
1678 * that the hal returns a pseudo-ISR that may include
1679 * bits we haven't explicitly enabled so we mask the
1680 * value to insure we only process bits we requested.
1681 */
1682 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
1683 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
1684 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1, "ath_intr: mask=0x%.8x", status);
1685#ifdef ATH_DEBUG_ALQ
1686 if_ath_alq_post_intr(&sc->sc_alq, status, ah->ah_intrstate,
1687 ah->ah_syncstate);
1688#endif /* ATH_DEBUG_ALQ */
1689#ifdef ATH_KTR_INTR_DEBUG
1690 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 5,
1691 "ath_intr: ISR=0x%.8x, ISR_S0=0x%.8x, ISR_S1=0x%.8x, ISR_S2=0x%.8x, ISR_S5=0x%.8x",
1692 ah->ah_intrstate[0],
1693 ah->ah_intrstate[1],
1694 ah->ah_intrstate[2],
1695 ah->ah_intrstate[3],
1696 ah->ah_intrstate[6]);
1697#endif
1698
1699 /* Squirrel away SYNC interrupt debugging */
1700 if (ah->ah_syncstate != 0) {
1701 int i;
1702 for (i = 0; i < 32; i++)
1703 if (ah->ah_syncstate & (i << i))
1704 sc->sc_intr_stats.sync_intr[i]++;
1705 }
1706
1707 status &= sc->sc_imask; /* discard unasked for bits */
1708
1709 /* Short-circuit un-handled interrupts */
1710 if (status == 0x0) {
1711 ATH_PCU_UNLOCK(sc);
1712 return;
1713 }
1714
1715 /*
1716 * Take a note that we're inside the interrupt handler, so
1717 * the reset routines know to wait.
1718 */
1719 sc->sc_intr_cnt++;
1720 ATH_PCU_UNLOCK(sc);
1721
1722 /*
1723 * Handle the interrupt. We won't run concurrent with the reset
1724 * or channel change routines as they'll wait for sc_intr_cnt
1725 * to be 0 before continuing.
1726 */
1727 if (status & HAL_INT_FATAL) {
1728 sc->sc_stats.ast_hardware++;
1729 ath_hal_intrset(ah, 0); /* disable intr's until reset */
1730 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask);
1731 } else {
1732 if (status & HAL_INT_SWBA) {
1733 /*
1734 * Software beacon alert--time to send a beacon.
1735 * Handle beacon transmission directly; deferring
1736 * this is too slow to meet timing constraints
1737 * under load.
1738 */
1739#ifdef IEEE80211_SUPPORT_TDMA
1740 if (sc->sc_tdma) {
1741 if (sc->sc_tdmaswba == 0) {
1742 struct ieee80211com *ic = ifp->if_l2com;
1743 struct ieee80211vap *vap =
1744 TAILQ_FIRST(&ic->ic_vaps);
1745 ath_tdma_beacon_send(sc, vap);
1746 sc->sc_tdmaswba =
1747 vap->iv_tdma->tdma_bintval;
1748 } else
1749 sc->sc_tdmaswba--;
1750 } else
1751#endif
1752 {
1753 ath_beacon_proc(sc, 0);
1754#ifdef IEEE80211_SUPPORT_SUPERG
1755 /*
1756 * Schedule the rx taskq in case there's no
1757 * traffic so any frames held on the staging
1758 * queue are aged and potentially flushed.
1759 */
1760 sc->sc_rx.recv_sched(sc, 1);
1761#endif
1762 }
1763 }
1764 if (status & HAL_INT_RXEOL) {
1765 int imask;
1766 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXEOL");
1767 ATH_PCU_LOCK(sc);
1768 /*
1769 * NB: the hardware should re-read the link when
1770 * RXE bit is written, but it doesn't work at
1771 * least on older hardware revs.
1772 */
1773 sc->sc_stats.ast_rxeol++;
1774 /*
1775 * Disable RXEOL/RXORN - prevent an interrupt
1776 * storm until the PCU logic can be reset.
1777 * In case the interface is reset some other
1778 * way before "sc_kickpcu" is called, don't
1779 * modify sc_imask - that way if it is reset
1780 * by a call to ath_reset() somehow, the
1781 * interrupt mask will be correctly reprogrammed.
1782 */
1783 imask = sc->sc_imask;
1784 imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN);
1785 ath_hal_intrset(ah, imask);
1786 /*
1787 * Only blank sc_rxlink if we've not yet kicked
1788 * the PCU.
1789 *
1790 * This isn't entirely correct - the correct solution
1791 * would be to have a PCU lock and engage that for
1792 * the duration of the PCU fiddling; which would include
1793 * running the RX process. Otherwise we could end up
1794 * messing up the RX descriptor chain and making the
1795 * RX desc list much shorter.
1796 */
1797 if (! sc->sc_kickpcu)
1798 sc->sc_rxlink = NULL;
1799 sc->sc_kickpcu = 1;
1800 ATH_PCU_UNLOCK(sc);
1801 /*
1802 * Enqueue an RX proc, to handled whatever
1803 * is in the RX queue.
1804 * This will then kick the PCU.
1805 */
1806 sc->sc_rx.recv_sched(sc, 1);
1807 }
1808 if (status & HAL_INT_TXURN) {
1809 sc->sc_stats.ast_txurn++;
1810 /* bump tx trigger level */
1811 ath_hal_updatetxtriglevel(ah, AH_TRUE);
1812 }
1813 /*
1814 * Handle both the legacy and RX EDMA interrupt bits.
1815 * Note that HAL_INT_RXLP is also HAL_INT_RXDESC.
1816 */
1817 if (status & (HAL_INT_RX | HAL_INT_RXHP | HAL_INT_RXLP)) {
1818 sc->sc_stats.ast_rx_intr++;
1819 sc->sc_rx.recv_sched(sc, 1);
1820 }
1821 if (status & HAL_INT_TX) {
1822 sc->sc_stats.ast_tx_intr++;
1823 /*
1824 * Grab all the currently set bits in the HAL txq bitmap
1825 * and blank them. This is the only place we should be
1826 * doing this.
1827 */
1828 if (! sc->sc_isedma) {
1829 ATH_PCU_LOCK(sc);
1830 txqs = 0xffffffff;
1831 ath_hal_gettxintrtxqs(sc->sc_ah, &txqs);
1832 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 3,
1833 "ath_intr: TX; txqs=0x%08x, txq_active was 0x%08x, now 0x%08x",
1834 txqs,
1835 sc->sc_txq_active,
1836 sc->sc_txq_active | txqs);
1837 sc->sc_txq_active |= txqs;
1838 ATH_PCU_UNLOCK(sc);
1839 }
1840 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask);
1841 }
1842 if (status & HAL_INT_BMISS) {
1843 sc->sc_stats.ast_bmiss++;
1844 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask);
1845 }
1846 if (status & HAL_INT_GTT)
1847 sc->sc_stats.ast_tx_timeout++;
1848 if (status & HAL_INT_CST)
1849 sc->sc_stats.ast_tx_cst++;
1850 if (status & HAL_INT_MIB) {
1851 sc->sc_stats.ast_mib++;
1852 ATH_PCU_LOCK(sc);
1853 /*
1854 * Disable interrupts until we service the MIB
1855 * interrupt; otherwise it will continue to fire.
1856 */
1857 ath_hal_intrset(ah, 0);
1858 /*
1859 * Let the hal handle the event. We assume it will
1860 * clear whatever condition caused the interrupt.
1861 */
1862 ath_hal_mibevent(ah, &sc->sc_halstats);
1863 /*
1864 * Don't reset the interrupt if we've just
1865 * kicked the PCU, or we may get a nested
1866 * RXEOL before the rxproc has had a chance
1867 * to run.
1868 */
1869 if (sc->sc_kickpcu == 0)
1870 ath_hal_intrset(ah, sc->sc_imask);
1871 ATH_PCU_UNLOCK(sc);
1872 }
1873 if (status & HAL_INT_RXORN) {
1874 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */
1875 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXORN");
1876 sc->sc_stats.ast_rxorn++;
1877 }
1878 }
1879 ATH_PCU_LOCK(sc);
1880 sc->sc_intr_cnt--;
1881 ATH_PCU_UNLOCK(sc);
1882}
1883
1884static void
1885ath_fatal_proc(void *arg, int pending)
1886{
1887 struct ath_softc *sc = arg;
1888 struct ifnet *ifp = sc->sc_ifp;
1889 u_int32_t *state;
1890 u_int32_t len;
1891 void *sp;
1892
1893 if_printf(ifp, "hardware error; resetting\n");
1894 /*
1895 * Fatal errors are unrecoverable. Typically these
1896 * are caused by DMA errors. Collect h/w state from
1897 * the hal so we can diagnose what's going on.
1898 */
1899 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) {
1900 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len));
1901 state = sp;
1902 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n",
1903 state[0], state[1] , state[2], state[3],
1904 state[4], state[5]);
1905 }
1906 ath_reset(ifp, ATH_RESET_NOLOSS);
1907}
1908
1909static void
1910ath_bmiss_vap(struct ieee80211vap *vap)
1911{
1912 /*
1913 * Workaround phantom bmiss interrupts by sanity-checking
1914 * the time of our last rx'd frame. If it is within the
1915 * beacon miss interval then ignore the interrupt. If it's
1916 * truly a bmiss we'll get another interrupt soon and that'll
1917 * be dispatched up for processing. Note this applies only
1918 * for h/w beacon miss events.
1919 */
1920 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) {
1921 struct ifnet *ifp = vap->iv_ic->ic_ifp;
1922 struct ath_softc *sc = ifp->if_softc;
1923 u_int64_t lastrx = sc->sc_lastrx;
1924 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah);
1925 /* XXX should take a locked ref to iv_bss */
1926 u_int bmisstimeout =
1927 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024;
1928
1929 DPRINTF(sc, ATH_DEBUG_BEACON,
1930 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
1931 __func__, (unsigned long long) tsf,
1932 (unsigned long long)(tsf - lastrx),
1933 (unsigned long long) lastrx, bmisstimeout);
1934
1935 if (tsf - lastrx <= bmisstimeout) {
1936 sc->sc_stats.ast_bmiss_phantom++;
1937 return;
1938 }
1939 }
1940 ATH_VAP(vap)->av_bmiss(vap);
1941}
1942
1943int
1944ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs)
1945{
1946 uint32_t rsize;
1947 void *sp;
1948
1949 if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize))
1950 return 0;
1951 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize));
1952 *hangs = *(uint32_t *)sp;
1953 return 1;
1954}
1955
1956static void
1957ath_bmiss_proc(void *arg, int pending)
1958{
1959 struct ath_softc *sc = arg;
1960 struct ifnet *ifp = sc->sc_ifp;
1961 uint32_t hangs;
1962
1963 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
1964
1965 /*
1966 * Do a reset upon any becaon miss event.
1967 *
1968 * It may be a non-recognised RX clear hang which needs a reset
1969 * to clear.
1970 */
1971 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) {
1972 ath_reset(ifp, ATH_RESET_NOLOSS);
1973 if_printf(ifp, "bb hang detected (0x%x), resetting\n", hangs);
1974 } else {
1975 ath_reset(ifp, ATH_RESET_NOLOSS);
1976 ieee80211_beacon_miss(ifp->if_l2com);
1977 }
1978}
1979
1980/*
1981 * Handle TKIP MIC setup to deal hardware that doesn't do MIC
1982 * calcs together with WME. If necessary disable the crypto
1983 * hardware and mark the 802.11 state so keys will be setup
1984 * with the MIC work done in software.
1985 */
1986static void
1987ath_settkipmic(struct ath_softc *sc)
1988{
1989 struct ifnet *ifp = sc->sc_ifp;
1990 struct ieee80211com *ic = ifp->if_l2com;
1991
1992 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) {
1993 if (ic->ic_flags & IEEE80211_F_WME) {
1994 ath_hal_settkipmic(sc->sc_ah, AH_FALSE);
1995 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC;
1996 } else {
1997 ath_hal_settkipmic(sc->sc_ah, AH_TRUE);
1998 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
1999 }
2000 }
2001}
2002
2003static void
2004ath_init(void *arg)
2005{
2006 struct ath_softc *sc = (struct ath_softc *) arg;
2007 struct ifnet *ifp = sc->sc_ifp;
2008 struct ieee80211com *ic = ifp->if_l2com;
2009 struct ath_hal *ah = sc->sc_ah;
2010 HAL_STATUS status;
2011
2012 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
2013 __func__, ifp->if_flags);
2014
2015 ATH_LOCK(sc);
2016 /*
2017 * Stop anything previously setup. This is safe
2018 * whether this is the first time through or not.
2019 */
2020 ath_stop_locked(ifp);
2021
2022 /*
2023 * The basic interface to setting the hardware in a good
2024 * state is ``reset''. On return the hardware is known to
2025 * be powered up and with interrupts disabled. This must
2026 * be followed by initialization of the appropriate bits
2027 * and then setup of the interrupt mask.
2028 */
2029 ath_settkipmic(sc);
2030 ath_update_chainmasks(sc, ic->ic_curchan);
2031 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2032 sc->sc_cur_rxchainmask);
2033 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) {
2034 if_printf(ifp, "unable to reset hardware; hal status %u\n",
2035 status);
2036 ATH_UNLOCK(sc);
2037 return;
2038 }
2039 ath_chan_change(sc, ic->ic_curchan);
2040
2041 /* Let DFS at it in case it's a DFS channel */
2042 ath_dfs_radar_enable(sc, ic->ic_curchan);
2043
2044 /* Let spectral at in case spectral is enabled */
2045 ath_spectral_enable(sc, ic->ic_curchan);
2046
2047 /*
2048 * If we're doing TDMA, enforce the TXOP limitation for chips that
2049 * support it.
2050 */
2051 if (sc->sc_hasenforcetxop && sc->sc_tdma)
2052 ath_hal_setenforcetxop(sc->sc_ah, 1);
2053 else
2054 ath_hal_setenforcetxop(sc->sc_ah, 0);
2055
2056 /*
2057 * Likewise this is set during reset so update
2058 * state cached in the driver.
2059 */
2060 sc->sc_diversity = ath_hal_getdiversity(ah);
2061 sc->sc_lastlongcal = 0;
2062 sc->sc_resetcal = 1;
2063 sc->sc_lastcalreset = 0;
2064 sc->sc_lastani = 0;
2065 sc->sc_lastshortcal = 0;
2066 sc->sc_doresetcal = AH_FALSE;
2067 /*
2068 * Beacon timers were cleared here; give ath_newstate()
2069 * a hint that the beacon timers should be poked when
2070 * things transition to the RUN state.
2071 */
2072 sc->sc_beacons = 0;
2073
2074 /*
2075 * Setup the hardware after reset: the key cache
2076 * is filled as needed and the receive engine is
2077 * set going. Frame transmit is handled entirely
2078 * in the frame output path; there's nothing to do
2079 * here except setup the interrupt mask.
2080 */
2081 if (ath_startrecv(sc) != 0) {
2082 if_printf(ifp, "unable to start recv logic\n");
2083 ATH_UNLOCK(sc);
2084 return;
2085 }
2086
2087 /*
2088 * Enable interrupts.
2089 */
2090 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
2091 | HAL_INT_RXEOL | HAL_INT_RXORN
2092 | HAL_INT_TXURN
2093 | HAL_INT_FATAL | HAL_INT_GLOBAL;
2094
2095 /*
2096 * Enable RX EDMA bits. Note these overlap with
2097 * HAL_INT_RX and HAL_INT_RXDESC respectively.
2098 */
2099 if (sc->sc_isedma)
2100 sc->sc_imask |= (HAL_INT_RXHP | HAL_INT_RXLP);
2101
2102 /*
2103 * Enable MIB interrupts when there are hardware phy counters.
2104 * Note we only do this (at the moment) for station mode.
2105 */
2106 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
2107 sc->sc_imask |= HAL_INT_MIB;
2108
2109 /* Enable global TX timeout and carrier sense timeout if available */
2110 if (ath_hal_gtxto_supported(ah))
2111 sc->sc_imask |= HAL_INT_GTT;
2112
2113 DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n",
2114 __func__, sc->sc_imask);
2115
2116 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2117 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc);
2118 ath_hal_intrset(ah, sc->sc_imask);
2119
2120 ATH_UNLOCK(sc);
2121
2122#ifdef ATH_TX99_DIAG
2123 if (sc->sc_tx99 != NULL)
2124 sc->sc_tx99->start(sc->sc_tx99);
2125 else
2126#endif
2127 ieee80211_start_all(ic); /* start all vap's */
2128}
2129
2130static void
2131ath_stop_locked(struct ifnet *ifp)
2132{
2133 struct ath_softc *sc = ifp->if_softc;
2134 struct ath_hal *ah = sc->sc_ah;
2135
2136 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
2137 __func__, sc->sc_invalid, ifp->if_flags);
2138
2139 ATH_LOCK_ASSERT(sc);
2140 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2141 /*
2142 * Shutdown the hardware and driver:
2143 * reset 802.11 state machine
2144 * turn off timers
2145 * disable interrupts
2146 * turn off the radio
2147 * clear transmit machinery
2148 * clear receive machinery
2149 * drain and release tx queues
2150 * reclaim beacon resources
2151 * power down hardware
2152 *
2153 * Note that some of this work is not possible if the
2154 * hardware is gone (invalid).
2155 */
2156#ifdef ATH_TX99_DIAG
2157 if (sc->sc_tx99 != NULL)
2158 sc->sc_tx99->stop(sc->sc_tx99);
2159#endif
2160 callout_stop(&sc->sc_wd_ch);
2161 sc->sc_wd_timer = 0;
2162 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2163 if (!sc->sc_invalid) {
2164 if (sc->sc_softled) {
2165 callout_stop(&sc->sc_ledtimer);
2166 ath_hal_gpioset(ah, sc->sc_ledpin,
2167 !sc->sc_ledon);
2168 sc->sc_blinking = 0;
2169 }
2170 ath_hal_intrset(ah, 0);
2171 }
2172 ath_draintxq(sc, ATH_RESET_DEFAULT);
2173 if (!sc->sc_invalid) {
2174 ath_stoprecv(sc, 1);
2175 ath_hal_phydisable(ah);
2176 } else
2177 sc->sc_rxlink = NULL;
2178 ath_beacon_free(sc); /* XXX not needed */
2179 }
2180}
2181
2182#define MAX_TXRX_ITERATIONS 1000
2183static void
2184ath_txrx_stop_locked(struct ath_softc *sc)
2185{
2186 int i = MAX_TXRX_ITERATIONS;
2187
2188 ATH_UNLOCK_ASSERT(sc);
2189 ATH_PCU_LOCK_ASSERT(sc);
2190
2191 /*
2192 * Sleep until all the pending operations have completed.
2193 *
2194 * The caller must ensure that reset has been incremented
2195 * or the pending operations may continue being queued.
2196 */
2197 while (sc->sc_rxproc_cnt || sc->sc_txproc_cnt ||
2198 sc->sc_txstart_cnt || sc->sc_intr_cnt) {
2199 if (i <= 0)
2200 break;
2201 msleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop", 1);
2202 i--;
2203 }
2204
2205 if (i <= 0)
2206 device_printf(sc->sc_dev,
2207 "%s: didn't finish after %d iterations\n",
2208 __func__, MAX_TXRX_ITERATIONS);
2209}
2210#undef MAX_TXRX_ITERATIONS
2211
2212#if 0
2213static void
2214ath_txrx_stop(struct ath_softc *sc)
2215{
2216 ATH_UNLOCK_ASSERT(sc);
2217 ATH_PCU_UNLOCK_ASSERT(sc);
2218
2219 ATH_PCU_LOCK(sc);
2220 ath_txrx_stop_locked(sc);
2221 ATH_PCU_UNLOCK(sc);
2222}
2223#endif
2224
2225static void
2226ath_txrx_start(struct ath_softc *sc)
2227{
2228
2229 taskqueue_unblock(sc->sc_tq);
2230}
2231
2232/*
2233 * Grab the reset lock, and wait around until noone else
2234 * is trying to do anything with it.
2235 *
2236 * This is totally horrible but we can't hold this lock for
2237 * long enough to do TX/RX or we end up with net80211/ip stack
2238 * LORs and eventual deadlock.
2239 *
2240 * "dowait" signals whether to spin, waiting for the reset
2241 * lock count to reach 0. This should (for now) only be used
2242 * during the reset path, as the rest of the code may not
2243 * be locking-reentrant enough to behave correctly.
2244 *
2245 * Another, cleaner way should be found to serialise all of
2246 * these operations.
2247 */
2248#define MAX_RESET_ITERATIONS 10
2249static int
2250ath_reset_grablock(struct ath_softc *sc, int dowait)
2251{
2252 int w = 0;
2253 int i = MAX_RESET_ITERATIONS;
2254
2255 ATH_PCU_LOCK_ASSERT(sc);
2256 do {
2257 if (sc->sc_inreset_cnt == 0) {
2258 w = 1;
2259 break;
2260 }
2261 if (dowait == 0) {
2262 w = 0;
2263 break;
2264 }
2265 ATH_PCU_UNLOCK(sc);
2266 pause("ath_reset_grablock", 1);
2267 i--;
2268 ATH_PCU_LOCK(sc);
2269 } while (i > 0);
2270
2271 /*
2272 * We always increment the refcounter, regardless
2273 * of whether we succeeded to get it in an exclusive
2274 * way.
2275 */
2276 sc->sc_inreset_cnt++;
2277
2278 if (i <= 0)
2279 device_printf(sc->sc_dev,
2280 "%s: didn't finish after %d iterations\n",
2281 __func__, MAX_RESET_ITERATIONS);
2282
2283 if (w == 0)
2284 device_printf(sc->sc_dev,
2285 "%s: warning, recursive reset path!\n",
2286 __func__);
2287
2288 return w;
2289}
2290#undef MAX_RESET_ITERATIONS
2291
2292/*
2293 * XXX TODO: write ath_reset_releaselock
2294 */
2295
2296static void
2297ath_stop(struct ifnet *ifp)
2298{
2299 struct ath_softc *sc = ifp->if_softc;
2300
2301 ATH_LOCK(sc);
2302 ath_stop_locked(ifp);
2303 ATH_UNLOCK(sc);
2304}
2305
2306/*
2307 * Reset the hardware w/o losing operational state. This is
2308 * basically a more efficient way of doing ath_stop, ath_init,
2309 * followed by state transitions to the current 802.11
2310 * operational state. Used to recover from various errors and
2311 * to reset or reload hardware state.
2312 */
2313int
2314ath_reset(struct ifnet *ifp, ATH_RESET_TYPE reset_type)
2315{
2316 struct ath_softc *sc = ifp->if_softc;
2317 struct ieee80211com *ic = ifp->if_l2com;
2318 struct ath_hal *ah = sc->sc_ah;
2319 HAL_STATUS status;
2320 int i;
2321
2322 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
2323
2324 /* Ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */
2325 ATH_PCU_UNLOCK_ASSERT(sc);
2326 ATH_UNLOCK_ASSERT(sc);
2327
2328 /* Try to (stop any further TX/RX from occuring */
2329 taskqueue_block(sc->sc_tq);
2330
2331 ATH_PCU_LOCK(sc);
2332 ath_hal_intrset(ah, 0); /* disable interrupts */
2333 ath_txrx_stop_locked(sc); /* Ensure TX/RX is stopped */
2334 if (ath_reset_grablock(sc, 1) == 0) {
2335 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
2336 __func__);
2337 }
2338 ATH_PCU_UNLOCK(sc);
2339
2340 /*
2341 * Should now wait for pending TX/RX to complete
2342 * and block future ones from occuring. This needs to be
2343 * done before the TX queue is drained.
2344 */
2345 ath_draintxq(sc, reset_type); /* stop xmit side */
2346
2347 /*
2348 * Regardless of whether we're doing a no-loss flush or
2349 * not, stop the PCU and handle what's in the RX queue.
2350 * That way frames aren't dropped which shouldn't be.
2351 */
2352 ath_stoprecv(sc, (reset_type != ATH_RESET_NOLOSS));
2353 ath_rx_flush(sc);
2354
2355 ath_settkipmic(sc); /* configure TKIP MIC handling */
2356 /* NB: indicate channel change so we do a full reset */
2357 ath_update_chainmasks(sc, ic->ic_curchan);
2358 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2359 sc->sc_cur_rxchainmask);
2360 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status))
2361 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
2362 __func__, status);
2363 sc->sc_diversity = ath_hal_getdiversity(ah);
2364
2365 /* Let DFS at it in case it's a DFS channel */
2366 ath_dfs_radar_enable(sc, ic->ic_curchan);
2367
2368 /* Let spectral at in case spectral is enabled */
2369 ath_spectral_enable(sc, ic->ic_curchan);
2370
2371 /*
2372 * If we're doing TDMA, enforce the TXOP limitation for chips that
2373 * support it.
2374 */
2375 if (sc->sc_hasenforcetxop && sc->sc_tdma)
2376 ath_hal_setenforcetxop(sc->sc_ah, 1);
2377 else
2378 ath_hal_setenforcetxop(sc->sc_ah, 0);
2379
2380 if (ath_startrecv(sc) != 0) /* restart recv */
2381 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
2382 /*
2383 * We may be doing a reset in response to an ioctl
2384 * that changes the channel so update any state that
2385 * might change as a result.
2386 */
2387 ath_chan_change(sc, ic->ic_curchan);
2388 if (sc->sc_beacons) { /* restart beacons */
2389#ifdef IEEE80211_SUPPORT_TDMA
2390 if (sc->sc_tdma)
2391 ath_tdma_config(sc, NULL);
2392 else
2393#endif
2394 ath_beacon_config(sc, NULL);
2395 }
2396
2397 /*
2398 * Release the reset lock and re-enable interrupts here.
2399 * If an interrupt was being processed in ath_intr(),
2400 * it would disable interrupts at this point. So we have
2401 * to atomically enable interrupts and decrement the
2402 * reset counter - this way ath_intr() doesn't end up
2403 * disabling interrupts without a corresponding enable
2404 * in the rest or channel change path.
2405 */
2406 ATH_PCU_LOCK(sc);
2407 sc->sc_inreset_cnt--;
2408 /* XXX only do this if sc_inreset_cnt == 0? */
2409 ath_hal_intrset(ah, sc->sc_imask);
2410 ATH_PCU_UNLOCK(sc);
2411
2412 /*
2413 * TX and RX can be started here. If it were started with
2414 * sc_inreset_cnt > 0, the TX and RX path would abort.
2415 * Thus if this is a nested call through the reset or
2416 * channel change code, TX completion will occur but
2417 * RX completion and ath_start / ath_tx_start will not
2418 * run.
2419 */
2420
2421 /* Restart TX/RX as needed */
2422 ath_txrx_start(sc);
2423
2424 /* Restart TX completion and pending TX */
2425 if (reset_type == ATH_RESET_NOLOSS) {
2426 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
2427 if (ATH_TXQ_SETUP(sc, i)) {
2428 ATH_TXQ_LOCK(&sc->sc_txq[i]);
2429 ath_txq_restart_dma(sc, &sc->sc_txq[i]);
2430 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
2431
2432 ATH_TX_LOCK(sc);
2433 ath_txq_sched(sc, &sc->sc_txq[i]);
2434 ATH_TX_UNLOCK(sc);
2435 }
2436 }
2437 }
2438
2439 /*
2440 * This may have been set during an ath_start() call which
2441 * set this once it detected a concurrent TX was going on.
2442 * So, clear it.
2443 */
2444 IF_LOCK(&ifp->if_snd);
2445 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2446 IF_UNLOCK(&ifp->if_snd);
2447
2448 /* Handle any frames in the TX queue */
2449 /*
2450 * XXX should this be done by the caller, rather than
2451 * ath_reset() ?
2452 */
2453 ath_tx_kick(sc); /* restart xmit */
2454 return 0;
2455}
2456
2457static int
2458ath_reset_vap(struct ieee80211vap *vap, u_long cmd)
2459{
2460 struct ieee80211com *ic = vap->iv_ic;
2461 struct ifnet *ifp = ic->ic_ifp;
2462 struct ath_softc *sc = ifp->if_softc;
2463 struct ath_hal *ah = sc->sc_ah;
2464
2465 switch (cmd) {
2466 case IEEE80211_IOC_TXPOWER:
2467 /*
2468 * If per-packet TPC is enabled, then we have nothing
2469 * to do; otherwise we need to force the global limit.
2470 * All this can happen directly; no need to reset.
2471 */
2472 if (!ath_hal_gettpc(ah))
2473 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
2474 return 0;
2475 }
2476 /* XXX? Full or NOLOSS? */
2477 return ath_reset(ifp, ATH_RESET_FULL);
2478}
2479
2480struct ath_buf *
2481_ath_getbuf_locked(struct ath_softc *sc, ath_buf_type_t btype)
2482{
2483 struct ath_buf *bf;
2484
2485 ATH_TXBUF_LOCK_ASSERT(sc);
2486
2487 if (btype == ATH_BUFTYPE_MGMT)
2488 bf = TAILQ_FIRST(&sc->sc_txbuf_mgmt);
2489 else
2490 bf = TAILQ_FIRST(&sc->sc_txbuf);
2491
2492 if (bf == NULL) {
2493 sc->sc_stats.ast_tx_getnobuf++;
2494 } else {
2495 if (bf->bf_flags & ATH_BUF_BUSY) {
2496 sc->sc_stats.ast_tx_getbusybuf++;
2497 bf = NULL;
2498 }
2499 }
2500
2501 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) {
2502 if (btype == ATH_BUFTYPE_MGMT)
2503 TAILQ_REMOVE(&sc->sc_txbuf_mgmt, bf, bf_list);
2504 else {
2505 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list);
2506 sc->sc_txbuf_cnt--;
2507
2508 /*
2509 * This shuldn't happen; however just to be
2510 * safe print a warning and fudge the txbuf
2511 * count.
2512 */
2513 if (sc->sc_txbuf_cnt < 0) {
2514 device_printf(sc->sc_dev,
2515 "%s: sc_txbuf_cnt < 0?\n",
2516 __func__);
2517 sc->sc_txbuf_cnt = 0;
2518 }
2519 }
2520 } else
2521 bf = NULL;
2522
2523 if (bf == NULL) {
2524 /* XXX should check which list, mgmt or otherwise */
2525 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__,
2526 TAILQ_FIRST(&sc->sc_txbuf) == NULL ?
2527 "out of xmit buffers" : "xmit buffer busy");
2528 return NULL;
2529 }
2530
2531 /* XXX TODO: should do this at buffer list initialisation */
2532 /* XXX (then, ensure the buffer has the right flag set) */
2533 bf->bf_flags = 0;
2534 if (btype == ATH_BUFTYPE_MGMT)
2535 bf->bf_flags |= ATH_BUF_MGMT;
2536 else
2537 bf->bf_flags &= (~ATH_BUF_MGMT);
2538
2539 /* Valid bf here; clear some basic fields */
2540 bf->bf_next = NULL; /* XXX just to be sure */
2541 bf->bf_last = NULL; /* XXX again, just to be sure */
2542 bf->bf_comp = NULL; /* XXX again, just to be sure */
2543 bzero(&bf->bf_state, sizeof(bf->bf_state));
2544
2545 /*
2546 * Track the descriptor ID only if doing EDMA
2547 */
2548 if (sc->sc_isedma) {
2549 bf->bf_descid = sc->sc_txbuf_descid;
2550 sc->sc_txbuf_descid++;
2551 }
2552
2553 return bf;
2554}
2555
2556/*
2557 * When retrying a software frame, buffers marked ATH_BUF_BUSY
2558 * can't be thrown back on the queue as they could still be
2559 * in use by the hardware.
2560 *
2561 * This duplicates the buffer, or returns NULL.
2562 *
2563 * The descriptor is also copied but the link pointers and
2564 * the DMA segments aren't copied; this frame should thus
2565 * be again passed through the descriptor setup/chain routines
2566 * so the link is correct.
2567 *
2568 * The caller must free the buffer using ath_freebuf().
2569 */
2570struct ath_buf *
2571ath_buf_clone(struct ath_softc *sc, struct ath_buf *bf)
2572{
2573 struct ath_buf *tbf;
2574
2575 tbf = ath_getbuf(sc,
2576 (bf->bf_flags & ATH_BUF_MGMT) ?
2577 ATH_BUFTYPE_MGMT : ATH_BUFTYPE_NORMAL);
2578 if (tbf == NULL)
2579 return NULL; /* XXX failure? Why? */
2580
2581 /* Copy basics */
2582 tbf->bf_next = NULL;
2583 tbf->bf_nseg = bf->bf_nseg;
2584 tbf->bf_flags = bf->bf_flags & ATH_BUF_FLAGS_CLONE;
2585 tbf->bf_status = bf->bf_status;
2586 tbf->bf_m = bf->bf_m;
2587 tbf->bf_node = bf->bf_node;
2588 /* will be setup by the chain/setup function */
2589 tbf->bf_lastds = NULL;
2590 /* for now, last == self */
2591 tbf->bf_last = tbf;
2592 tbf->bf_comp = bf->bf_comp;
2593
2594 /* NOTE: DMA segments will be setup by the setup/chain functions */
2595
2596 /* The caller has to re-init the descriptor + links */
2597
2598 /*
2599 * Free the DMA mapping here, before we NULL the mbuf.
2600 * We must only call bus_dmamap_unload() once per mbuf chain
2601 * or behaviour is undefined.
2602 */
2603 if (bf->bf_m != NULL) {
2604 /*
2605 * XXX is this POSTWRITE call required?
2606 */
2607 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
2608 BUS_DMASYNC_POSTWRITE);
2609 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2610 }
2611
2612 bf->bf_m = NULL;
2613 bf->bf_node = NULL;
2614
2615 /* Copy state */
2616 memcpy(&tbf->bf_state, &bf->bf_state, sizeof(bf->bf_state));
2617
2618 return tbf;
2619}
2620
2621struct ath_buf *
2622ath_getbuf(struct ath_softc *sc, ath_buf_type_t btype)
2623{
2624 struct ath_buf *bf;
2625
2626 ATH_TXBUF_LOCK(sc);
2627 bf = _ath_getbuf_locked(sc, btype);
2628 /*
2629 * If a mgmt buffer was requested but we're out of those,
2630 * try requesting a normal one.
2631 */
2632 if (bf == NULL && btype == ATH_BUFTYPE_MGMT)
2633 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL);
2634 ATH_TXBUF_UNLOCK(sc);
2635 if (bf == NULL) {
2636 struct ifnet *ifp = sc->sc_ifp;
2637
2638 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__);
2639 sc->sc_stats.ast_tx_qstop++;
2640 IF_LOCK(&ifp->if_snd);
2641 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2642 IF_UNLOCK(&ifp->if_snd);
2643 }
2644 return bf;
2645}
2646
2647static void
2648ath_start_queue(struct ifnet *ifp)
2649{
2650 struct ath_softc *sc = ifp->if_softc;
2651
2652 ATH_PCU_LOCK(sc);
2653 if (sc->sc_inreset_cnt > 0) {
2654 device_printf(sc->sc_dev,
2655 "%s: sc_inreset_cnt > 0; bailing\n", __func__);
2656 ATH_PCU_UNLOCK(sc);
2657 IF_LOCK(&ifp->if_snd);
2658 sc->sc_stats.ast_tx_qstop++;
2659 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2660 IF_UNLOCK(&ifp->if_snd);
2661 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: OACTIVE, finish");
2662 return;
2663 }
2664 sc->sc_txstart_cnt++;
2665 ATH_PCU_UNLOCK(sc);
2666
2667 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_queue: start");
2668 ath_tx_kick(sc);
2669 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_queue: finished");
2670
2671 ATH_PCU_LOCK(sc);
2672 sc->sc_txstart_cnt--;
2673 ATH_PCU_UNLOCK(sc);
2674}
2675
2676void
2677ath_start_task(void *arg, int npending)
2678{
2679 struct ath_softc *sc = (struct ath_softc *) arg;
2680 struct ifnet *ifp = sc->sc_ifp;
2681
2682 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: start");
2683
2684 /* XXX is it ok to hold the ATH_LOCK here? */
2685 ATH_PCU_LOCK(sc);
2686 if (sc->sc_inreset_cnt > 0) {
2687 device_printf(sc->sc_dev,
2688 "%s: sc_inreset_cnt > 0; bailing\n", __func__);
2689 ATH_PCU_UNLOCK(sc);
2690 IF_LOCK(&ifp->if_snd);
2691 sc->sc_stats.ast_tx_qstop++;
2692 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2693 IF_UNLOCK(&ifp->if_snd);
2694 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: OACTIVE, finish");
2695 return;
2696 }
2697 sc->sc_txstart_cnt++;
2698 ATH_PCU_UNLOCK(sc);
2699
2700 ATH_TX_LOCK(sc);
2701 ath_start(sc->sc_ifp);
2702 ATH_TX_UNLOCK(sc);
2703
2704 ATH_PCU_LOCK(sc);
2705 sc->sc_txstart_cnt--;
2706 ATH_PCU_UNLOCK(sc);
2707 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: finished");
2708}
2709
2710void
2711ath_start(struct ifnet *ifp)
2712{
2713 struct ath_softc *sc = ifp->if_softc;
2714 struct ieee80211_node *ni;
2715 struct ath_buf *bf;
2716 struct mbuf *m, *next;
2717 ath_bufhead frags;
2718 int npkts = 0;
2719
2720 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid)
2721 return;
2722
2723 ATH_TX_LOCK_ASSERT(sc);
2724
2725 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start: called");
2726
2727 for (;;) {
2728 /*
2729 * Grab the frame that we're going to try and transmit.
2730 */
2731 IFQ_DEQUEUE(&ifp->if_snd, m);
2732 if (m == NULL)
2733 break;
2734 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
2735
2736 /*
2737 * Enforce how deep a node queue can get.
2738 *
2739 * XXX it would be nicer if we kept an mbuf queue per
2740 * node and only whacked them into ath_bufs when we
2741 * are ready to schedule some traffic from them.
2742 * .. that may come later.
2743 *
2744 * XXX we should also track the per-node hardware queue
2745 * depth so it is easy to limit the _SUM_ of the swq and
2746 * hwq frames. Since we only schedule two HWQ frames
2747 * at a time, this should be OK for now.
2748 */
2749 if ((!(m->m_flags & M_EAPOL)) &&
2750 (ATH_NODE(ni)->an_swq_depth > sc->sc_txq_node_maxdepth)) {
2751 sc->sc_stats.ast_tx_nodeq_overflow++;
2752 if (ni != NULL)
2753 ieee80211_free_node(ni);
2754 m_freem(m);
2755 m = NULL;
2756 continue;
2757 }
2758
2759 /*
2760 * Check how many TX buffers are available.
2761 *
2762 * If this is for non-EAPOL traffic, just leave some
2763 * space free in order for buffer cloning and raw
2764 * frame transmission to occur.
2765 *
2766 * If it's for EAPOL traffic, ignore this for now.
2767 * Management traffic will be sent via the raw transmit
2768 * method which bypasses this check.
2769 *
2770 * This is needed to ensure that EAPOL frames during
2771 * (re) keying have a chance to go out.
2772 *
2773 * See kern/138379 for more information.
2774 */
2775 if ((!(m->m_flags & M_EAPOL)) &&
2776 (sc->sc_txbuf_cnt <= sc->sc_txq_data_minfree)) {
2777 sc->sc_stats.ast_tx_nobuf++;
2778 IF_LOCK(&ifp->if_snd);
2779 _IF_PREPEND(&ifp->if_snd, m);
2780 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2781 IF_UNLOCK(&ifp->if_snd);
2782 m = NULL;
2783 break;
2784 }
2785
2786 /*
2787 * Grab a TX buffer and associated resources.
2788 *
2789 * If it's an EAPOL frame, allocate a MGMT ath_buf.
2790 * That way even with temporary buffer exhaustion due to
2791 * the data path doesn't leave us without the ability
2792 * to transmit management frames.
2793 *
2794 * Otherwise allocate a normal buffer.
2795 */
2796 if (m->m_flags & M_EAPOL)
2797 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT);
2798 else
2799 bf = ath_getbuf(sc, ATH_BUFTYPE_NORMAL);
2800
2801 if (bf == NULL) {
2802 /*
2803 * If we failed to allocate a buffer, prepend it
2804 * and continue.
2805 *
2806 * We shouldn't fail normally, due to the check
2807 * above.
2808 */
2809 sc->sc_stats.ast_tx_nobuf++;
2810 IF_LOCK(&ifp->if_snd);
2811 _IF_PREPEND(&ifp->if_snd, m);
2812 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2813 IF_UNLOCK(&ifp->if_snd);
2814 m = NULL;
2815 break;
2816 }
2817
2818 npkts ++;
2819
2820 /*
2821 * Check for fragmentation. If this frame
2822 * has been broken up verify we have enough
2823 * buffers to send all the fragments so all
2824 * go out or none...
2825 */
2826 TAILQ_INIT(&frags);
2827 if ((m->m_flags & M_FRAG) &&
2828 !ath_txfrag_setup(sc, &frags, m, ni)) {
2829 DPRINTF(sc, ATH_DEBUG_XMIT,
2830 "%s: out of txfrag buffers\n", __func__);
2831 sc->sc_stats.ast_tx_nofrag++;
2832 ifp->if_oerrors++;
2833 ath_freetx(m);
2834 goto bad;
2835 }
2836 ifp->if_opackets++;
2837 nextfrag:
2838 /*
2839 * Pass the frame to the h/w for transmission.
2840 * Fragmented frames have each frag chained together
2841 * with m_nextpkt. We know there are sufficient ath_buf's
2842 * to send all the frags because of work done by
2843 * ath_txfrag_setup. We leave m_nextpkt set while
2844 * calling ath_tx_start so it can use it to extend the
2845 * the tx duration to cover the subsequent frag and
2846 * so it can reclaim all the mbufs in case of an error;
2847 * ath_tx_start clears m_nextpkt once it commits to
2848 * handing the frame to the hardware.
2849 */
2850 next = m->m_nextpkt;
2851 if (ath_tx_start(sc, ni, bf, m)) {
2852 bad:
2853 ifp->if_oerrors++;
2854 reclaim:
2855 bf->bf_m = NULL;
2856 bf->bf_node = NULL;
2857 ATH_TXBUF_LOCK(sc);
2858 ath_returnbuf_head(sc, bf);
2859 ath_txfrag_cleanup(sc, &frags, ni);
2860 ATH_TXBUF_UNLOCK(sc);
2861 /*
2862 * XXX todo, free the node outside of
2863 * the TX lock context!
2864 */
2865 if (ni != NULL)
2866 ieee80211_free_node(ni);
2867 continue;
2868 }
2869
2870 /*
2871 * Check here if the node is in power save state.
2872 */
2873 ath_tx_update_tim(sc, ni, 1);
2874
2875 if (next != NULL) {
2876 /*
2877 * Beware of state changing between frags.
2878 * XXX check sta power-save state?
2879 */
2880 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) {
2881 DPRINTF(sc, ATH_DEBUG_XMIT,
2882 "%s: flush fragmented packet, state %s\n",
2883 __func__,
2884 ieee80211_state_name[ni->ni_vap->iv_state]);
2885 /* XXX dmamap */
2886 ath_freetx(next);
2887 goto reclaim;
2888 }
2889 m = next;
2890 bf = TAILQ_FIRST(&frags);
2891 KASSERT(bf != NULL, ("no buf for txfrag"));
2892 TAILQ_REMOVE(&frags, bf, bf_list);
2893 goto nextfrag;
2894 }
2895
2896 sc->sc_wd_timer = 5;
2897 }
2898 ATH_KTR(sc, ATH_KTR_TX, 1, "ath_start: finished; npkts=%d", npkts);
2899}
2900static int
2901ath_media_change(struct ifnet *ifp)
2902{
2903 int error = ieee80211_media_change(ifp);
2904 /* NB: only the fixed rate can change and that doesn't need a reset */
2905 return (error == ENETRESET ? 0 : error);
2906}
2907
2908/*
2909 * Block/unblock tx+rx processing while a key change is done.
2910 * We assume the caller serializes key management operations
2911 * so we only need to worry about synchronization with other
2912 * uses that originate in the driver.
2913 */
2914static void
2915ath_key_update_begin(struct ieee80211vap *vap)
2916{
2917 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2918 struct ath_softc *sc = ifp->if_softc;
2919
2920 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
2921 taskqueue_block(sc->sc_tq);
2922 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */
2923}
2924
2925static void
2926ath_key_update_end(struct ieee80211vap *vap)
2927{
2928 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2929 struct ath_softc *sc = ifp->if_softc;
2930
2931 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
2932 IF_UNLOCK(&ifp->if_snd);
2933 taskqueue_unblock(sc->sc_tq);
2934}
2935
2936static void
2937ath_update_promisc(struct ifnet *ifp)
2938{
2939 struct ath_softc *sc = ifp->if_softc;
2940 u_int32_t rfilt;
2941
2942 /* configure rx filter */
2943 rfilt = ath_calcrxfilter(sc);
2944 ath_hal_setrxfilter(sc->sc_ah, rfilt);
2945
2946 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt);
2947}
2948
2949static void
2950ath_update_mcast(struct ifnet *ifp)
2951{
2952 struct ath_softc *sc = ifp->if_softc;
2953 u_int32_t mfilt[2];
2954
2955 /* calculate and install multicast filter */
2956 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
2957 struct ifmultiaddr *ifma;
2958 /*
2959 * Merge multicast addresses to form the hardware filter.
2960 */
2961 mfilt[0] = mfilt[1] = 0;
2962 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */
2963 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2964 caddr_t dl;
2965 u_int32_t val;
2966 u_int8_t pos;
2967
2968 /* calculate XOR of eight 6bit values */
2969 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
2970 val = LE_READ_4(dl + 0);
2971 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2972 val = LE_READ_4(dl + 3);
2973 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2974 pos &= 0x3f;
2975 mfilt[pos / 32] |= (1 << (pos % 32));
2976 }
2977 if_maddr_runlock(ifp);
2978 } else
2979 mfilt[0] = mfilt[1] = ~0;
2980 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]);
2981 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n",
2982 __func__, mfilt[0], mfilt[1]);
2983}
2984
2985void
2986ath_mode_init(struct ath_softc *sc)
2987{
2988 struct ifnet *ifp = sc->sc_ifp;
2989 struct ath_hal *ah = sc->sc_ah;
2990 u_int32_t rfilt;
2991
2992 /* configure rx filter */
2993 rfilt = ath_calcrxfilter(sc);
2994 ath_hal_setrxfilter(ah, rfilt);
2995
2996 /* configure operational mode */
2997 ath_hal_setopmode(ah);
2998
2999 DPRINTF(sc, ATH_DEBUG_STATE | ATH_DEBUG_MODE,
3000 "%s: ah=%p, ifp=%p, if_addr=%p\n",
3001 __func__,
3002 ah,
3003 ifp,
3004 (ifp == NULL) ? NULL : ifp->if_addr);
3005
3006 /* handle any link-level address change */
3007 ath_hal_setmac(ah, IF_LLADDR(ifp));
3008
3009 /* calculate and install multicast filter */
3010 ath_update_mcast(ifp);
3011}
3012
3013/*
3014 * Set the slot time based on the current setting.
3015 */
3016void
3017ath_setslottime(struct ath_softc *sc)
3018{
3019 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3020 struct ath_hal *ah = sc->sc_ah;
3021 u_int usec;
3022
3023 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan))
3024 usec = 13;
3025 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan))
3026 usec = 21;
3027 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
3028 /* honor short/long slot time only in 11g */
3029 /* XXX shouldn't honor on pure g or turbo g channel */
3030 if (ic->ic_flags & IEEE80211_F_SHSLOT)
3031 usec = HAL_SLOT_TIME_9;
3032 else
3033 usec = HAL_SLOT_TIME_20;
3034 } else
3035 usec = HAL_SLOT_TIME_9;
3036
3037 DPRINTF(sc, ATH_DEBUG_RESET,
3038 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n",
3039 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags,
3040 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec);
3041
3042 ath_hal_setslottime(ah, usec);
3043 sc->sc_updateslot = OK;
3044}
3045
3046/*
3047 * Callback from the 802.11 layer to update the
3048 * slot time based on the current setting.
3049 */
3050static void
3051ath_updateslot(struct ifnet *ifp)
3052{
3053 struct ath_softc *sc = ifp->if_softc;
3054 struct ieee80211com *ic = ifp->if_l2com;
3055
3056 /*
3057 * When not coordinating the BSS, change the hardware
3058 * immediately. For other operation we defer the change
3059 * until beacon updates have propagated to the stations.
3060 */
3061 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3062 ic->ic_opmode == IEEE80211_M_MBSS)
3063 sc->sc_updateslot = UPDATE;
3064 else
3065 ath_setslottime(sc);
3066}
3067
3068/*
3069 * Append the contents of src to dst; both queues
3070 * are assumed to be locked.
3071 */
3072void
3073ath_txqmove(struct ath_txq *dst, struct ath_txq *src)
3074{
3075
3076 ATH_TXQ_LOCK_ASSERT(src);
3077 ATH_TXQ_LOCK_ASSERT(dst);
3078
3079 TAILQ_CONCAT(&dst->axq_q, &src->axq_q, bf_list);
3080 dst->axq_link = src->axq_link;
3081 src->axq_link = NULL;
3082 dst->axq_depth += src->axq_depth;
3083 dst->axq_aggr_depth += src->axq_aggr_depth;
3084 src->axq_depth = 0;
3085 src->axq_aggr_depth = 0;
3086}
3087
3088/*
3089 * Reset the hardware, with no loss.
3090 *
3091 * This can't be used for a general case reset.
3092 */
3093static void
3094ath_reset_proc(void *arg, int pending)
3095{
3096 struct ath_softc *sc = arg;
3097 struct ifnet *ifp = sc->sc_ifp;
3098
3099#if 0
3100 if_printf(ifp, "%s: resetting\n", __func__);
3101#endif
3102 ath_reset(ifp, ATH_RESET_NOLOSS);
3103}
3104
3105/*
3106 * Reset the hardware after detecting beacons have stopped.
3107 */
3108static void
3109ath_bstuck_proc(void *arg, int pending)
3110{
3111 struct ath_softc *sc = arg;
3112 struct ifnet *ifp = sc->sc_ifp;
3113 uint32_t hangs = 0;
3114
3115 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0)
3116 if_printf(ifp, "bb hang detected (0x%x)\n", hangs);
3117
3118#ifdef ATH_DEBUG_ALQ
3119 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_STUCK_BEACON))
3120 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_STUCK_BEACON, 0, NULL);
3121#endif
3122
3123 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
3124 sc->sc_bmisscount);
3125 sc->sc_stats.ast_bstuck++;
3126 /*
3127 * This assumes that there's no simultaneous channel mode change
3128 * occuring.
3129 */
3130 ath_reset(ifp, ATH_RESET_NOLOSS);
3131}
3132
3133static void
3134ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3135{
3136 bus_addr_t *paddr = (bus_addr_t*) arg;
3137 KASSERT(error == 0, ("error %u on bus_dma callback", error));
3138 *paddr = segs->ds_addr;
3139}
3140
3141/*
3142 * Allocate the descriptors and appropriate DMA tag/setup.
3143 *
3144 * For some situations (eg EDMA TX completion), there isn't a requirement
3145 * for the ath_buf entries to be allocated.
3146 */
3147int
3148ath_descdma_alloc_desc(struct ath_softc *sc,
3149 struct ath_descdma *dd, ath_bufhead *head,
3150 const char *name, int ds_size, int ndesc)
3151{
3152#define DS2PHYS(_dd, _ds) \
3153 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
3154#define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \
3155 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0)
3156 struct ifnet *ifp = sc->sc_ifp;
3157 int error;
3158
3159 dd->dd_descsize = ds_size;
3160
3161 DPRINTF(sc, ATH_DEBUG_RESET,
3162 "%s: %s DMA: %u desc, %d bytes per descriptor\n",
3163 __func__, name, ndesc, dd->dd_descsize);
3164
3165 dd->dd_name = name;
3166 dd->dd_desc_len = dd->dd_descsize * ndesc;
3167
3168 /*
3169 * Merlin work-around:
3170 * Descriptors that cross the 4KB boundary can't be used.
3171 * Assume one skipped descriptor per 4KB page.
3172 */
3173 if (! ath_hal_split4ktrans(sc->sc_ah)) {
3174 int numpages = dd->dd_desc_len / 4096;
3175 dd->dd_desc_len += ds_size * numpages;
3176 }
3177
3178 /*
3179 * Setup DMA descriptor area.
3180 *
3181 * BUS_DMA_ALLOCNOW is not used; we never use bounce
3182 * buffers for the descriptors themselves.
3183 */
3184 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
3185 PAGE_SIZE, 0, /* alignment, bounds */
3186 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
3187 BUS_SPACE_MAXADDR, /* highaddr */
3188 NULL, NULL, /* filter, filterarg */
3189 dd->dd_desc_len, /* maxsize */
3190 1, /* nsegments */
3191 dd->dd_desc_len, /* maxsegsize */
3192 0, /* flags */
3193 NULL, /* lockfunc */
3194 NULL, /* lockarg */
3195 &dd->dd_dmat);
3196 if (error != 0) {
3197 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
3198 return error;
3199 }
3200
3201 /* allocate descriptors */
3202 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc,
3203 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
3204 &dd->dd_dmamap);
3205 if (error != 0) {
3206 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
3207 "error %u\n", ndesc, dd->dd_name, error);
3208 goto fail1;
3209 }
3210
3211 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
3212 dd->dd_desc, dd->dd_desc_len,
3213 ath_load_cb, &dd->dd_desc_paddr,
3214 BUS_DMA_NOWAIT);
3215 if (error != 0) {
3216 if_printf(ifp, "unable to map %s descriptors, error %u\n",
3217 dd->dd_name, error);
3218 goto fail2;
3219 }
3220
3221 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
3222 __func__, dd->dd_name, (uint8_t *) dd->dd_desc,
3223 (u_long) dd->dd_desc_len, (caddr_t) dd->dd_desc_paddr,
3224 /*XXX*/ (u_long) dd->dd_desc_len);
3225
3226 return (0);
3227
3228fail2:
3229 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3230fail1:
3231 bus_dma_tag_destroy(dd->dd_dmat);
3232 memset(dd, 0, sizeof(*dd));
3233 return error;
3234#undef DS2PHYS
3235#undef ATH_DESC_4KB_BOUND_CHECK
3236}
3237
3238int
3239ath_descdma_setup(struct ath_softc *sc,
3240 struct ath_descdma *dd, ath_bufhead *head,
3241 const char *name, int ds_size, int nbuf, int ndesc)
3242{
3243#define DS2PHYS(_dd, _ds) \
3244 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
3245#define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \
3246 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0)
3247 struct ifnet *ifp = sc->sc_ifp;
3248 uint8_t *ds;
3249 struct ath_buf *bf;
3250 int i, bsize, error;
3251
3252 /* Allocate descriptors */
3253 error = ath_descdma_alloc_desc(sc, dd, head, name, ds_size,
3254 nbuf * ndesc);
3255
3256 /* Assume any errors during allocation were dealt with */
3257 if (error != 0) {
3258 return (error);
3259 }
3260
3261 ds = (uint8_t *) dd->dd_desc;
3262
3263 /* allocate rx buffers */
3264 bsize = sizeof(struct ath_buf) * nbuf;
3265 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
3266 if (bf == NULL) {
3267 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
3268 dd->dd_name, bsize);
3269 goto fail3;
3270 }
3271 dd->dd_bufptr = bf;
3272
3273 TAILQ_INIT(head);
3274 for (i = 0; i < nbuf; i++, bf++, ds += (ndesc * dd->dd_descsize)) {
3275 bf->bf_desc = (struct ath_desc *) ds;
3276 bf->bf_daddr = DS2PHYS(dd, ds);
3277 if (! ath_hal_split4ktrans(sc->sc_ah)) {
3278 /*
3279 * Merlin WAR: Skip descriptor addresses which
3280 * cause 4KB boundary crossing along any point
3281 * in the descriptor.
3282 */
3283 if (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr,
3284 dd->dd_descsize)) {
3285 /* Start at the next page */
3286 ds += 0x1000 - (bf->bf_daddr & 0xFFF);
3287 bf->bf_desc = (struct ath_desc *) ds;
3288 bf->bf_daddr = DS2PHYS(dd, ds);
3289 }
3290 }
3291 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
3292 &bf->bf_dmamap);
3293 if (error != 0) {
3294 if_printf(ifp, "unable to create dmamap for %s "
3295 "buffer %u, error %u\n", dd->dd_name, i, error);
3296 ath_descdma_cleanup(sc, dd, head);
3297 return error;
3298 }
3299 bf->bf_lastds = bf->bf_desc; /* Just an initial value */
3300 TAILQ_INSERT_TAIL(head, bf, bf_list);
3301 }
3302
3303 /*
3304 * XXX TODO: ensure that ds doesn't overflow the descriptor
3305 * allocation otherwise weird stuff will occur and crash your
3306 * machine.
3307 */
3308 return 0;
3309 /* XXX this should likely just call ath_descdma_cleanup() */
3310fail3:
3311 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3312 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3313 bus_dma_tag_destroy(dd->dd_dmat);
3314 memset(dd, 0, sizeof(*dd));
3315 return error;
3316#undef DS2PHYS
3317#undef ATH_DESC_4KB_BOUND_CHECK
3318}
3319
3320/*
3321 * Allocate ath_buf entries but no descriptor contents.
3322 *
3323 * This is for RX EDMA where the descriptors are the header part of
3324 * the RX buffer.
3325 */
3326int
3327ath_descdma_setup_rx_edma(struct ath_softc *sc,
3328 struct ath_descdma *dd, ath_bufhead *head,
3329 const char *name, int nbuf, int rx_status_len)
3330{
3331 struct ifnet *ifp = sc->sc_ifp;
3332 struct ath_buf *bf;
3333 int i, bsize, error;
3334
3335 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers\n",
3336 __func__, name, nbuf);
3337
3338 dd->dd_name = name;
3339 /*
3340 * This is (mostly) purely for show. We're not allocating any actual
3341 * descriptors here as EDMA RX has the descriptor be part
3342 * of the RX buffer.
3343 *
3344 * However, dd_desc_len is used by ath_descdma_free() to determine
3345 * whether we have already freed this DMA mapping.
3346 */
3347 dd->dd_desc_len = rx_status_len * nbuf;
3348 dd->dd_descsize = rx_status_len;
3349
3350 /* allocate rx buffers */
3351 bsize = sizeof(struct ath_buf) * nbuf;
3352 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
3353 if (bf == NULL) {
3354 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
3355 dd->dd_name, bsize);
3356 error = ENOMEM;
3357 goto fail3;
3358 }
3359 dd->dd_bufptr = bf;
3360
3361 TAILQ_INIT(head);
3362 for (i = 0; i < nbuf; i++, bf++) {
3363 bf->bf_desc = NULL;
3364 bf->bf_daddr = 0;
3365 bf->bf_lastds = NULL; /* Just an initial value */
3366
3367 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
3368 &bf->bf_dmamap);
3369 if (error != 0) {
3370 if_printf(ifp, "unable to create dmamap for %s "
3371 "buffer %u, error %u\n", dd->dd_name, i, error);
3372 ath_descdma_cleanup(sc, dd, head);
3373 return error;
3374 }
3375 TAILQ_INSERT_TAIL(head, bf, bf_list);
3376 }
3377 return 0;
3378fail3:
3379 memset(dd, 0, sizeof(*dd));
3380 return error;
3381}
3382
3383void
3384ath_descdma_cleanup(struct ath_softc *sc,
3385 struct ath_descdma *dd, ath_bufhead *head)
3386{
3387 struct ath_buf *bf;
3388 struct ieee80211_node *ni;
3389 int do_warning = 0;
3390
3391 if (dd->dd_dmamap != 0) {
3392 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3393 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3394 bus_dma_tag_destroy(dd->dd_dmat);
3395 }
3396
3397 if (head != NULL) {
3398 TAILQ_FOREACH(bf, head, bf_list) {
3399 if (bf->bf_m) {
3400 /*
3401 * XXX warn if there's buffers here.
3402 * XXX it should have been freed by the
3403 * owner!
3404 */
3405
3406 if (do_warning == 0) {
3407 do_warning = 1;
3408 device_printf(sc->sc_dev,
3409 "%s: %s: mbuf should've been"
3410 " unmapped/freed!\n",
3411 __func__,
3412 dd->dd_name);
3413 }
3414 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3415 BUS_DMASYNC_POSTREAD);
3416 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3417 m_freem(bf->bf_m);
3418 bf->bf_m = NULL;
3419 }
3420 if (bf->bf_dmamap != NULL) {
3421 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
3422 bf->bf_dmamap = NULL;
3423 }
3424 ni = bf->bf_node;
3425 bf->bf_node = NULL;
3426 if (ni != NULL) {
3427 /*
3428 * Reclaim node reference.
3429 */
3430 ieee80211_free_node(ni);
3431 }
3432 }
3433 }
3434
3435 if (head != NULL)
3436 TAILQ_INIT(head);
3437
3438 if (dd->dd_bufptr != NULL)
3439 free(dd->dd_bufptr, M_ATHDEV);
3440 memset(dd, 0, sizeof(*dd));
3441}
3442
3443static int
3444ath_desc_alloc(struct ath_softc *sc)
3445{
3446 int error;
3447
3448 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
3449 "tx", sc->sc_tx_desclen, ath_txbuf, ATH_MAX_SCATTER);
3450 if (error != 0) {
3451 return error;
3452 }
3453 sc->sc_txbuf_cnt = ath_txbuf;
3454
3455 error = ath_descdma_setup(sc, &sc->sc_txdma_mgmt, &sc->sc_txbuf_mgmt,
3456 "tx_mgmt", sc->sc_tx_desclen, ath_txbuf_mgmt,
3457 ATH_TXDESC);
3458 if (error != 0) {
3459 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3460 return error;
3461 }
3462
3463 /*
3464 * XXX mark txbuf_mgmt frames with ATH_BUF_MGMT, so the
3465 * flag doesn't have to be set in ath_getbuf_locked().
3466 */
3467
3468 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
3469 "beacon", sc->sc_tx_desclen, ATH_BCBUF, 1);
3470 if (error != 0) {
3471 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3472 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
3473 &sc->sc_txbuf_mgmt);
3474 return error;
3475 }
3476 return 0;
3477}
3478
3479static void
3480ath_desc_free(struct ath_softc *sc)
3481{
3482
3483 if (sc->sc_bdma.dd_desc_len != 0)
3484 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
3485 if (sc->sc_txdma.dd_desc_len != 0)
3486 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3487 if (sc->sc_txdma_mgmt.dd_desc_len != 0)
3488 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
3489 &sc->sc_txbuf_mgmt);
3490}
3491
3492static struct ieee80211_node *
3493ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
3494{
3495 struct ieee80211com *ic = vap->iv_ic;
3496 struct ath_softc *sc = ic->ic_ifp->if_softc;
3497 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
3498 struct ath_node *an;
3499
3500 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
3501 if (an == NULL) {
3502 /* XXX stat+msg */
3503 return NULL;
3504 }
3505 ath_rate_node_init(sc, an);
3506
3507 /* Setup the mutex - there's no associd yet so set the name to NULL */
3508 snprintf(an->an_name, sizeof(an->an_name), "%s: node %p",
3509 device_get_nameunit(sc->sc_dev), an);
3510 mtx_init(&an->an_mtx, an->an_name, NULL, MTX_DEF);
3511
3512 /* XXX setup ath_tid */
3513 ath_tx_tid_init(sc, an);
3514
3515 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, mac, ":", an);
3516 return &an->an_node;
3517}
3518
3519static void
3520ath_node_cleanup(struct ieee80211_node *ni)
3521{
3522 struct ieee80211com *ic = ni->ni_ic;
3523 struct ath_softc *sc = ic->ic_ifp->if_softc;
3524
3525 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__,
3526 ni->ni_macaddr, ":", ATH_NODE(ni));
3527
3528 /* Cleanup ath_tid, free unused bufs, unlink bufs in TXQ */
3529 ath_tx_node_flush(sc, ATH_NODE(ni));
3530 ath_rate_node_cleanup(sc, ATH_NODE(ni));
3531 sc->sc_node_cleanup(ni);
3532}
3533
3534static void
3535ath_node_free(struct ieee80211_node *ni)
3536{
3537 struct ieee80211com *ic = ni->ni_ic;
3538 struct ath_softc *sc = ic->ic_ifp->if_softc;
3539
3540 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__,
3541 ni->ni_macaddr, ":", ATH_NODE(ni));
3542 mtx_destroy(&ATH_NODE(ni)->an_mtx);
3543 sc->sc_node_free(ni);
3544}
3545
3546static void
3547ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise)
3548{
3549 struct ieee80211com *ic = ni->ni_ic;
3550 struct ath_softc *sc = ic->ic_ifp->if_softc;
3551 struct ath_hal *ah = sc->sc_ah;
3552
3553 *rssi = ic->ic_node_getrssi(ni);
3554 if (ni->ni_chan != IEEE80211_CHAN_ANYC)
3555 *noise = ath_hal_getchannoise(ah, ni->ni_chan);
3556 else
3557 *noise = -95; /* nominally correct */
3558}
3559
3560/*
3561 * Set the default antenna.
3562 */
3563void
3564ath_setdefantenna(struct ath_softc *sc, u_int antenna)
3565{
3566 struct ath_hal *ah = sc->sc_ah;
3567
3568 /* XXX block beacon interrupts */
3569 ath_hal_setdefantenna(ah, antenna);
3570 if (sc->sc_defant != antenna)
3571 sc->sc_stats.ast_ant_defswitch++;
3572 sc->sc_defant = antenna;
3573 sc->sc_rxotherant = 0;
3574}
3575
3576static void
3577ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum)
3578{
3579 txq->axq_qnum = qnum;
3580 txq->axq_ac = 0;
3581 txq->axq_depth = 0;
3582 txq->axq_aggr_depth = 0;
3583 txq->axq_intrcnt = 0;
3584 txq->axq_link = NULL;
3585 txq->axq_softc = sc;
3586 TAILQ_INIT(&txq->axq_q);
3587 TAILQ_INIT(&txq->axq_tidq);
3588 TAILQ_INIT(&txq->fifo.axq_q);
3589 ATH_TXQ_LOCK_INIT(sc, txq);
3590}
3591
3592/*
3593 * Setup a h/w transmit queue.
3594 */
3595static struct ath_txq *
3596ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
3597{
3598#define N(a) (sizeof(a)/sizeof(a[0]))
3599 struct ath_hal *ah = sc->sc_ah;
3600 HAL_TXQ_INFO qi;
3601 int qnum;
3602
3603 memset(&qi, 0, sizeof(qi));
3604 qi.tqi_subtype = subtype;
3605 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
3606 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
3607 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
3608 /*
3609 * Enable interrupts only for EOL and DESC conditions.
3610 * We mark tx descriptors to receive a DESC interrupt
3611 * when a tx queue gets deep; otherwise waiting for the
3612 * EOL to reap descriptors. Note that this is done to
3613 * reduce interrupt load and this only defers reaping
3614 * descriptors, never transmitting frames. Aside from
3615 * reducing interrupts this also permits more concurrency.
3616 * The only potential downside is if the tx queue backs
3617 * up in which case the top half of the kernel may backup
3618 * due to a lack of tx descriptors.
3619 */
3620 if (sc->sc_isedma)
3621 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE |
3622 HAL_TXQ_TXOKINT_ENABLE;
3623 else
3624 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE |
3625 HAL_TXQ_TXDESCINT_ENABLE;
3626
3627 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
3628 if (qnum == -1) {
3629 /*
3630 * NB: don't print a message, this happens
3631 * normally on parts with too few tx queues
3632 */
3633 return NULL;
3634 }
3635 if (qnum >= N(sc->sc_txq)) {
3636 device_printf(sc->sc_dev,
3637 "hal qnum %u out of range, max %zu!\n",
3638 qnum, N(sc->sc_txq));
3639 ath_hal_releasetxqueue(ah, qnum);
3640 return NULL;
3641 }
3642 if (!ATH_TXQ_SETUP(sc, qnum)) {
3643 ath_txq_init(sc, &sc->sc_txq[qnum], qnum);
3644 sc->sc_txqsetup |= 1<<qnum;
3645 }
3646 return &sc->sc_txq[qnum];
3647#undef N
3648}
3649
3650/*
3651 * Setup a hardware data transmit queue for the specified
3652 * access control. The hal may not support all requested
3653 * queues in which case it will return a reference to a
3654 * previously setup queue. We record the mapping from ac's
3655 * to h/w queues for use by ath_tx_start and also track
3656 * the set of h/w queues being used to optimize work in the
3657 * transmit interrupt handler and related routines.
3658 */
3659static int
3660ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
3661{
3662#define N(a) (sizeof(a)/sizeof(a[0]))
3663 struct ath_txq *txq;
3664
3665 if (ac >= N(sc->sc_ac2q)) {
3666 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
3667 ac, N(sc->sc_ac2q));
3668 return 0;
3669 }
3670 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
3671 if (txq != NULL) {
3672 txq->axq_ac = ac;
3673 sc->sc_ac2q[ac] = txq;
3674 return 1;
3675 } else
3676 return 0;
3677#undef N
3678}
3679
3680/*
3681 * Update WME parameters for a transmit queue.
3682 */
3683static int
3684ath_txq_update(struct ath_softc *sc, int ac)
3685{
3686#define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
3687#define ATH_TXOP_TO_US(v) (v<<5)
3688 struct ifnet *ifp = sc->sc_ifp;
3689 struct ieee80211com *ic = ifp->if_l2com;
3690 struct ath_txq *txq = sc->sc_ac2q[ac];
3691 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
3692 struct ath_hal *ah = sc->sc_ah;
3693 HAL_TXQ_INFO qi;
3694
3695 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
3696#ifdef IEEE80211_SUPPORT_TDMA
3697 if (sc->sc_tdma) {
3698 /*
3699 * AIFS is zero so there's no pre-transmit wait. The
3700 * burst time defines the slot duration and is configured
3701 * through net80211. The QCU is setup to not do post-xmit
3702 * back off, lockout all lower-priority QCU's, and fire
3703 * off the DMA beacon alert timer which is setup based
3704 * on the slot configuration.
3705 */
3706 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
3707 | HAL_TXQ_TXERRINT_ENABLE
3708 | HAL_TXQ_TXURNINT_ENABLE
3709 | HAL_TXQ_TXEOLINT_ENABLE
3710 | HAL_TXQ_DBA_GATED
3711 | HAL_TXQ_BACKOFF_DISABLE
3712 | HAL_TXQ_ARB_LOCKOUT_GLOBAL
3713 ;
3714 qi.tqi_aifs = 0;
3715 /* XXX +dbaprep? */
3716 qi.tqi_readyTime = sc->sc_tdmaslotlen;
3717 qi.tqi_burstTime = qi.tqi_readyTime;
3718 } else {
3719#endif
3720 /*
3721 * XXX shouldn't this just use the default flags
3722 * used in the previous queue setup?
3723 */
3724 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
3725 | HAL_TXQ_TXERRINT_ENABLE
3726 | HAL_TXQ_TXDESCINT_ENABLE
3727 | HAL_TXQ_TXURNINT_ENABLE
3728 | HAL_TXQ_TXEOLINT_ENABLE
3729 ;
3730 qi.tqi_aifs = wmep->wmep_aifsn;
3731 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
3732 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
3733 qi.tqi_readyTime = 0;
3734 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
3735#ifdef IEEE80211_SUPPORT_TDMA
3736 }
3737#endif
3738
3739 DPRINTF(sc, ATH_DEBUG_RESET,
3740 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n",
3741 __func__, txq->axq_qnum, qi.tqi_qflags,
3742 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime);
3743
3744 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
3745 if_printf(ifp, "unable to update hardware queue "
3746 "parameters for %s traffic!\n",
3747 ieee80211_wme_acnames[ac]);
3748 return 0;
3749 } else {
3750 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
3751 return 1;
3752 }
3753#undef ATH_TXOP_TO_US
3754#undef ATH_EXPONENT_TO_VALUE
3755}
3756
3757/*
3758 * Callback from the 802.11 layer to update WME parameters.
3759 */
3760int
3761ath_wme_update(struct ieee80211com *ic)
3762{
3763 struct ath_softc *sc = ic->ic_ifp->if_softc;
3764
3765 return !ath_txq_update(sc, WME_AC_BE) ||
3766 !ath_txq_update(sc, WME_AC_BK) ||
3767 !ath_txq_update(sc, WME_AC_VI) ||
3768 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
3769}
3770
3771/*
3772 * Reclaim resources for a setup queue.
3773 */
3774static void
3775ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
3776{
3777
3778 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
3779 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
3780 ATH_TXQ_LOCK_DESTROY(txq);
3781}
3782
3783/*
3784 * Reclaim all tx queue resources.
3785 */
3786static void
3787ath_tx_cleanup(struct ath_softc *sc)
3788{
3789 int i;
3790
3791 ATH_TXBUF_LOCK_DESTROY(sc);
3792 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3793 if (ATH_TXQ_SETUP(sc, i))
3794 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
3795}
3796
3797/*
3798 * Return h/w rate index for an IEEE rate (w/o basic rate bit)
3799 * using the current rates in sc_rixmap.
3800 */
3801int
3802ath_tx_findrix(const struct ath_softc *sc, uint8_t rate)
3803{
3804 int rix = sc->sc_rixmap[rate];
3805 /* NB: return lowest rix for invalid rate */
3806 return (rix == 0xff ? 0 : rix);
3807}
3808
3809static void
3810ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts,
3811 struct ath_buf *bf)
3812{
3813 struct ieee80211_node *ni = bf->bf_node;
3814 struct ifnet *ifp = sc->sc_ifp;
3815 struct ieee80211com *ic = ifp->if_l2com;
3816 int sr, lr, pri;
3817
3818 if (ts->ts_status == 0) {
3819 u_int8_t txant = ts->ts_antenna;
3820 sc->sc_stats.ast_ant_tx[txant]++;
3821 sc->sc_ant_tx[txant]++;
3822 if (ts->ts_finaltsi != 0)
3823 sc->sc_stats.ast_tx_altrate++;
3824 pri = M_WME_GETAC(bf->bf_m);
3825 if (pri >= WME_AC_VO)
3826 ic->ic_wme.wme_hipri_traffic++;
3827 if ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)
3828 ni->ni_inact = ni->ni_inact_reload;
3829 } else {
3830 if (ts->ts_status & HAL_TXERR_XRETRY)
3831 sc->sc_stats.ast_tx_xretries++;
3832 if (ts->ts_status & HAL_TXERR_FIFO)
3833 sc->sc_stats.ast_tx_fifoerr++;
3834 if (ts->ts_status & HAL_TXERR_FILT)
3835 sc->sc_stats.ast_tx_filtered++;
3836 if (ts->ts_status & HAL_TXERR_XTXOP)
3837 sc->sc_stats.ast_tx_xtxop++;
3838 if (ts->ts_status & HAL_TXERR_TIMER_EXPIRED)
3839 sc->sc_stats.ast_tx_timerexpired++;
3840
3841 if (bf->bf_m->m_flags & M_FF)
3842 sc->sc_stats.ast_ff_txerr++;
3843 }
3844 /* XXX when is this valid? */
3845 if (ts->ts_flags & HAL_TX_DESC_CFG_ERR)
3846 sc->sc_stats.ast_tx_desccfgerr++;
3847 /*
3848 * This can be valid for successful frame transmission!
3849 * If there's a TX FIFO underrun during aggregate transmission,
3850 * the MAC will pad the rest of the aggregate with delimiters.
3851 * If a BA is returned, the frame is marked as "OK" and it's up
3852 * to the TX completion code to notice which frames weren't
3853 * successfully transmitted.
3854 */
3855 if (ts->ts_flags & HAL_TX_DATA_UNDERRUN)
3856 sc->sc_stats.ast_tx_data_underrun++;
3857 if (ts->ts_flags & HAL_TX_DELIM_UNDERRUN)
3858 sc->sc_stats.ast_tx_delim_underrun++;
3859
3860 sr = ts->ts_shortretry;
3861 lr = ts->ts_longretry;
3862 sc->sc_stats.ast_tx_shortretry += sr;
3863 sc->sc_stats.ast_tx_longretry += lr;
3864
3865}
3866
3867/*
3868 * The default completion. If fail is 1, this means
3869 * "please don't retry the frame, and just return -1 status
3870 * to the net80211 stack.
3871 */
3872void
3873ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
3874{
3875 struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
3876 int st;
3877
3878 if (fail == 1)
3879 st = -1;
3880 else
3881 st = ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) ?
3882 ts->ts_status : HAL_TXERR_XRETRY;
3883
3884#if 0
3885 if (bf->bf_state.bfs_dobaw)
3886 device_printf(sc->sc_dev,
3887 "%s: bf %p: seqno %d: dobaw should've been cleared!\n",
3888 __func__,
3889 bf,
3890 SEQNO(bf->bf_state.bfs_seqno));
3891#endif
3892 if (bf->bf_next != NULL)
3893 device_printf(sc->sc_dev,
3894 "%s: bf %p: seqno %d: bf_next not NULL!\n",
3895 __func__,
3896 bf,
3897 SEQNO(bf->bf_state.bfs_seqno));
3898
3899 /*
3900 * Check if the node software queue is empty; if so
3901 * then clear the TIM.
3902 *
3903 * This needs to be done before the buffer is freed as
3904 * otherwise the node reference will have been released
3905 * and the node may not actually exist any longer.
3906 *
3907 * XXX I don't like this belonging here, but it's cleaner
3908 * to do it here right now then all the other places
3909 * where ath_tx_default_comp() is called.
3910 *
3911 * XXX TODO: during drain, ensure that the callback is
3912 * being called so we get a chance to update the TIM.
3913 */
3914 if (bf->bf_node) {
3915 ATH_TX_LOCK(sc);
3916 ath_tx_update_tim(sc, bf->bf_node, 0);
3917 ATH_TX_UNLOCK(sc);
3918 }
3919
3920 /*
3921 * Do any tx complete callback. Note this must
3922 * be done before releasing the node reference.
3923 * This will free the mbuf, release the net80211
3924 * node and recycle the ath_buf.
3925 */
3926 ath_tx_freebuf(sc, bf, st);
3927}
3928
3929/*
3930 * Update rate control with the given completion status.
3931 */
3932void
3933ath_tx_update_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni,
3934 struct ath_rc_series *rc, struct ath_tx_status *ts, int frmlen,
3935 int nframes, int nbad)
3936{
3937 struct ath_node *an;
3938
3939 /* Only for unicast frames */
3940 if (ni == NULL)
3941 return;
3942
3943 an = ATH_NODE(ni);
3944 ATH_NODE_UNLOCK_ASSERT(an);
3945
3946 if ((ts->ts_status & HAL_TXERR_FILT) == 0) {
3947 ATH_NODE_LOCK(an);
3948 ath_rate_tx_complete(sc, an, rc, ts, frmlen, nframes, nbad);
3949 ATH_NODE_UNLOCK(an);
3950 }
3951}
3952
3953/*
3954 * Process the completion of the given buffer.
3955 *
3956 * This calls the rate control update and then the buffer completion.
3957 * This will either free the buffer or requeue it. In any case, the
3958 * bf pointer should be treated as invalid after this function is called.
3959 */
3960void
3961ath_tx_process_buf_completion(struct ath_softc *sc, struct ath_txq *txq,
3962 struct ath_tx_status *ts, struct ath_buf *bf)
3963{
3964 struct ieee80211_node *ni = bf->bf_node;
3965 struct ath_node *an = NULL;
3966
3967 ATH_TX_UNLOCK_ASSERT(sc);
3968 ATH_TXQ_UNLOCK_ASSERT(txq);
3969
3970 /* If unicast frame, update general statistics */
3971 if (ni != NULL) {
3972 an = ATH_NODE(ni);
3973 /* update statistics */
3974 ath_tx_update_stats(sc, ts, bf);
3975 }
3976
3977 /*
3978 * Call the completion handler.
3979 * The completion handler is responsible for
3980 * calling the rate control code.
3981 *
3982 * Frames with no completion handler get the
3983 * rate control code called here.
3984 */
3985 if (bf->bf_comp == NULL) {
3986 if ((ts->ts_status & HAL_TXERR_FILT) == 0 &&
3987 (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) {
3988 /*
3989 * XXX assume this isn't an aggregate
3990 * frame.
3991 */
3992 ath_tx_update_ratectrl(sc, ni,
3993 bf->bf_state.bfs_rc, ts,
3994 bf->bf_state.bfs_pktlen, 1,
3995 (ts->ts_status == 0 ? 0 : 1));
3996 }
3997 ath_tx_default_comp(sc, bf, 0);
3998 } else
3999 bf->bf_comp(sc, bf, 0);
4000}
4001
4002
4003
4004/*
4005 * Process completed xmit descriptors from the specified queue.
4006 * Kick the packet scheduler if needed. This can occur from this
4007 * particular task.
4008 */
4009static int
4010ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, int dosched)
4011{
4012 struct ath_hal *ah = sc->sc_ah;
4013 struct ath_buf *bf;
4014 struct ath_desc *ds;
4015 struct ath_tx_status *ts;
4016 struct ieee80211_node *ni;
4017#ifdef IEEE80211_SUPPORT_SUPERG
4018 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
4019#endif /* IEEE80211_SUPPORT_SUPERG */
4020 int nacked;
4021 HAL_STATUS status;
4022
4023 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
4024 __func__, txq->axq_qnum,
4025 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4026 txq->axq_link);
4027
4028 ATH_KTR(sc, ATH_KTR_TXCOMP, 4,
4029 "ath_tx_processq: txq=%u head %p link %p depth %p",
4030 txq->axq_qnum,
4031 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4032 txq->axq_link,
4033 txq->axq_depth);
4034
4035 nacked = 0;
4036 for (;;) {
4037 ATH_TXQ_LOCK(txq);
4038 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
4039 bf = TAILQ_FIRST(&txq->axq_q);
4040 if (bf == NULL) {
4041 ATH_TXQ_UNLOCK(txq);
4042 break;
4043 }
4044 ds = bf->bf_lastds; /* XXX must be setup correctly! */
4045 ts = &bf->bf_status.ds_txstat;
4046
4047 status = ath_hal_txprocdesc(ah, ds, ts);
4048#ifdef ATH_DEBUG
4049 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
4050 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4051 status == HAL_OK);
4052 else if ((sc->sc_debug & ATH_DEBUG_RESET) && (dosched == 0))
4053 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4054 status == HAL_OK);
4055#endif
4056#ifdef ATH_DEBUG_ALQ
4057 if (if_ath_alq_checkdebug(&sc->sc_alq,
4058 ATH_ALQ_EDMA_TXSTATUS)) {
4059 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS,
4060 sc->sc_tx_statuslen,
4061 (char *) ds);
4062 }
4063#endif
4064
4065 if (status == HAL_EINPROGRESS) {
4066 ATH_KTR(sc, ATH_KTR_TXCOMP, 3,
4067 "ath_tx_processq: txq=%u, bf=%p ds=%p, HAL_EINPROGRESS",
4068 txq->axq_qnum, bf, ds);
4069 ATH_TXQ_UNLOCK(txq);
4070 break;
4071 }
4072 ATH_TXQ_REMOVE(txq, bf, bf_list);
4073
4074 /*
4075 * Sanity check.
4076 */
4077 if (txq->axq_qnum != bf->bf_state.bfs_tx_queue) {
4078 device_printf(sc->sc_dev,
4079 "%s: TXQ=%d: bf=%p, bfs_tx_queue=%d\n",
4080 __func__,
4081 txq->axq_qnum,
4082 bf,
4083 bf->bf_state.bfs_tx_queue);
4084 }
4085 if (txq->axq_qnum != bf->bf_last->bf_state.bfs_tx_queue) {
4086 device_printf(sc->sc_dev,
4087 "%s: TXQ=%d: bf_last=%p, bfs_tx_queue=%d\n",
4088 __func__,
4089 txq->axq_qnum,
4090 bf->bf_last,
4091 bf->bf_last->bf_state.bfs_tx_queue);
4092 }
4093
4094#if 0
4095 if (txq->axq_depth > 0) {
4096 /*
4097 * More frames follow. Mark the buffer busy
4098 * so it's not re-used while the hardware may
4099 * still re-read the link field in the descriptor.
4100 *
4101 * Use the last buffer in an aggregate as that
4102 * is where the hardware may be - intermediate
4103 * descriptors won't be "busy".
4104 */
4105 bf->bf_last->bf_flags |= ATH_BUF_BUSY;
4106 } else
4107 txq->axq_link = NULL;
4108#else
4109 bf->bf_last->bf_flags |= ATH_BUF_BUSY;
4110#endif
4111 if (bf->bf_state.bfs_aggr)
4112 txq->axq_aggr_depth--;
4113
4114 ni = bf->bf_node;
4115
4116 ATH_KTR(sc, ATH_KTR_TXCOMP, 5,
4117 "ath_tx_processq: txq=%u, bf=%p, ds=%p, ni=%p, ts_status=0x%08x",
4118 txq->axq_qnum, bf, ds, ni, ts->ts_status);
4119 /*
4120 * If unicast frame was ack'd update RSSI,
4121 * including the last rx time used to
4122 * workaround phantom bmiss interrupts.
4123 */
4124 if (ni != NULL && ts->ts_status == 0 &&
4125 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) {
4126 nacked++;
4127 sc->sc_stats.ast_tx_rssi = ts->ts_rssi;
4128 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
4129 ts->ts_rssi);
4130 }
4131 ATH_TXQ_UNLOCK(txq);
4132
4133 /*
4134 * Update statistics and call completion
4135 */
4136 ath_tx_process_buf_completion(sc, txq, ts, bf);
4137
4138 /* XXX at this point, bf and ni may be totally invalid */
4139 }
4140#ifdef IEEE80211_SUPPORT_SUPERG
4141 /*
4142 * Flush fast-frame staging queue when traffic slows.
4143 */
4144 if (txq->axq_depth <= 1)
4145 ieee80211_ff_flush(ic, txq->axq_ac);
4146#endif
4147
4148 /* Kick the software TXQ scheduler */
4149 if (dosched) {
4150 ATH_TX_LOCK(sc);
4151 ath_txq_sched(sc, txq);
4152 ATH_TX_UNLOCK(sc);
4153 }
4154
4155 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4156 "ath_tx_processq: txq=%u: done",
4157 txq->axq_qnum);
4158
4159 return nacked;
4160}
4161
4162#define TXQACTIVE(t, q) ( (t) & (1 << (q)))
4163
4164/*
4165 * Deferred processing of transmit interrupt; special-cased
4166 * for a single hardware transmit queue (e.g. 5210 and 5211).
4167 */
4168static void
4169ath_tx_proc_q0(void *arg, int npending)
4170{
4171 struct ath_softc *sc = arg;
4172 struct ifnet *ifp = sc->sc_ifp;
4173 uint32_t txqs;
4174
4175 ATH_PCU_LOCK(sc);
4176 sc->sc_txproc_cnt++;
4177 txqs = sc->sc_txq_active;
4178 sc->sc_txq_active &= ~txqs;
4179 ATH_PCU_UNLOCK(sc);
4180
4181 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4182 "ath_tx_proc_q0: txqs=0x%08x", txqs);
4183
4184 if (TXQACTIVE(txqs, 0) && ath_tx_processq(sc, &sc->sc_txq[0], 1))
4185 /* XXX why is lastrx updated in tx code? */
4186 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4187 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
4188 ath_tx_processq(sc, sc->sc_cabq, 1);
4189 IF_LOCK(&ifp->if_snd);
4190 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4191 IF_UNLOCK(&ifp->if_snd);
4192 sc->sc_wd_timer = 0;
4193
4194 if (sc->sc_softled)
4195 ath_led_event(sc, sc->sc_txrix);
4196
4197 ATH_PCU_LOCK(sc);
4198 sc->sc_txproc_cnt--;
4199 ATH_PCU_UNLOCK(sc);
4200
4201 ath_tx_kick(sc);
4202}
4203
4204/*
4205 * Deferred processing of transmit interrupt; special-cased
4206 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
4207 */
4208static void
4209ath_tx_proc_q0123(void *arg, int npending)
4210{
4211 struct ath_softc *sc = arg;
4212 struct ifnet *ifp = sc->sc_ifp;
4213 int nacked;
4214 uint32_t txqs;
4215
4216 ATH_PCU_LOCK(sc);
4217 sc->sc_txproc_cnt++;
4218 txqs = sc->sc_txq_active;
4219 sc->sc_txq_active &= ~txqs;
4220 ATH_PCU_UNLOCK(sc);
4221
4222 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4223 "ath_tx_proc_q0123: txqs=0x%08x", txqs);
4224
4225 /*
4226 * Process each active queue.
4227 */
4228 nacked = 0;
4229 if (TXQACTIVE(txqs, 0))
4230 nacked += ath_tx_processq(sc, &sc->sc_txq[0], 1);
4231 if (TXQACTIVE(txqs, 1))
4232 nacked += ath_tx_processq(sc, &sc->sc_txq[1], 1);
4233 if (TXQACTIVE(txqs, 2))
4234 nacked += ath_tx_processq(sc, &sc->sc_txq[2], 1);
4235 if (TXQACTIVE(txqs, 3))
4236 nacked += ath_tx_processq(sc, &sc->sc_txq[3], 1);
4237 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
4238 ath_tx_processq(sc, sc->sc_cabq, 1);
4239 if (nacked)
4240 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4241
4242 IF_LOCK(&ifp->if_snd);
4243 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4244 IF_UNLOCK(&ifp->if_snd);
4245 sc->sc_wd_timer = 0;
4246
4247 if (sc->sc_softled)
4248 ath_led_event(sc, sc->sc_txrix);
4249
4250 ATH_PCU_LOCK(sc);
4251 sc->sc_txproc_cnt--;
4252 ATH_PCU_UNLOCK(sc);
4253
4254 ath_tx_kick(sc);
4255}
4256
4257/*
4258 * Deferred processing of transmit interrupt.
4259 */
4260static void
4261ath_tx_proc(void *arg, int npending)
4262{
4263 struct ath_softc *sc = arg;
4264 struct ifnet *ifp = sc->sc_ifp;
4265 int i, nacked;
4266 uint32_t txqs;
4267
4268 ATH_PCU_LOCK(sc);
4269 sc->sc_txproc_cnt++;
4270 txqs = sc->sc_txq_active;
4271 sc->sc_txq_active &= ~txqs;
4272 ATH_PCU_UNLOCK(sc);
4273
4274 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, "ath_tx_proc: txqs=0x%08x", txqs);
4275
4276 /*
4277 * Process each active queue.
4278 */
4279 nacked = 0;
4280 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4281 if (ATH_TXQ_SETUP(sc, i) && TXQACTIVE(txqs, i))
4282 nacked += ath_tx_processq(sc, &sc->sc_txq[i], 1);
4283 if (nacked)
4284 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4285
4286 /* XXX check this inside of IF_LOCK? */
4287 IF_LOCK(&ifp->if_snd);
4288 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4289 IF_UNLOCK(&ifp->if_snd);
4290 sc->sc_wd_timer = 0;
4291
4292 if (sc->sc_softled)
4293 ath_led_event(sc, sc->sc_txrix);
4294
4295 ATH_PCU_LOCK(sc);
4296 sc->sc_txproc_cnt--;
4297 ATH_PCU_UNLOCK(sc);
4298
4299 ath_tx_kick(sc);
4300}
4301#undef TXQACTIVE
4302
4303/*
4304 * Deferred processing of TXQ rescheduling.
4305 */
4306static void
4307ath_txq_sched_tasklet(void *arg, int npending)
4308{
4309 struct ath_softc *sc = arg;
4310 int i;
4311
4312 /* XXX is skipping ok? */
4313 ATH_PCU_LOCK(sc);
4314#if 0
4315 if (sc->sc_inreset_cnt > 0) {
4316 device_printf(sc->sc_dev,
4317 "%s: sc_inreset_cnt > 0; skipping\n", __func__);
4318 ATH_PCU_UNLOCK(sc);
4319 return;
4320 }
4321#endif
4322 sc->sc_txproc_cnt++;
4323 ATH_PCU_UNLOCK(sc);
4324
4325 ATH_TX_LOCK(sc);
4326 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
4327 if (ATH_TXQ_SETUP(sc, i)) {
4328 ath_txq_sched(sc, &sc->sc_txq[i]);
4329 }
4330 }
4331 ATH_TX_UNLOCK(sc);
4332
4333 ATH_PCU_LOCK(sc);
4334 sc->sc_txproc_cnt--;
4335 ATH_PCU_UNLOCK(sc);
4336}
4337
4338void
4339ath_returnbuf_tail(struct ath_softc *sc, struct ath_buf *bf)
4340{
4341
4342 ATH_TXBUF_LOCK_ASSERT(sc);
4343
4344 if (bf->bf_flags & ATH_BUF_MGMT)
4345 TAILQ_INSERT_TAIL(&sc->sc_txbuf_mgmt, bf, bf_list);
4346 else {
4347 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
4348 sc->sc_txbuf_cnt++;
4349 if (sc->sc_txbuf_cnt > ath_txbuf) {
4350 device_printf(sc->sc_dev,
4351 "%s: sc_txbuf_cnt > %d?\n",
4352 __func__,
4353 ath_txbuf);
4354 sc->sc_txbuf_cnt = ath_txbuf;
4355 }
4356 }
4357}
4358
4359void
4360ath_returnbuf_head(struct ath_softc *sc, struct ath_buf *bf)
4361{
4362
4363 ATH_TXBUF_LOCK_ASSERT(sc);
4364
4365 if (bf->bf_flags & ATH_BUF_MGMT)
4366 TAILQ_INSERT_HEAD(&sc->sc_txbuf_mgmt, bf, bf_list);
4367 else {
4368 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
4369 sc->sc_txbuf_cnt++;
4370 if (sc->sc_txbuf_cnt > ATH_TXBUF) {
4371 device_printf(sc->sc_dev,
4372 "%s: sc_txbuf_cnt > %d?\n",
4373 __func__,
4374 ATH_TXBUF);
4375 sc->sc_txbuf_cnt = ATH_TXBUF;
4376 }
4377 }
4378}
4379
4380/*
4381 * Free the holding buffer if it exists
4382 */
4383void
4384ath_txq_freeholdingbuf(struct ath_softc *sc, struct ath_txq *txq)
4385{
4386 ATH_TXBUF_UNLOCK_ASSERT(sc);
4387 ATH_TXQ_LOCK_ASSERT(txq);
4388
4389 if (txq->axq_holdingbf == NULL)
4390 return;
4391
4392 txq->axq_holdingbf->bf_flags &= ~ATH_BUF_BUSY;
4393
4394 ATH_TXBUF_LOCK(sc);
4395 ath_returnbuf_tail(sc, txq->axq_holdingbf);
4396 ATH_TXBUF_UNLOCK(sc);
4397
4398 txq->axq_holdingbf = NULL;
4399}
4400
4401/*
4402 * Add this buffer to the holding queue, freeing the previous
4403 * one if it exists.
4404 */
4405static void
4406ath_txq_addholdingbuf(struct ath_softc *sc, struct ath_buf *bf)
4407{
4408 struct ath_txq *txq;
4409
4410 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue];
4411
4412 ATH_TXBUF_UNLOCK_ASSERT(sc);
4413 ATH_TXQ_LOCK_ASSERT(txq);
4414
4415 /* XXX assert ATH_BUF_BUSY is set */
4416
4417 /* XXX assert the tx queue is under the max number */
4418 if (bf->bf_state.bfs_tx_queue > HAL_NUM_TX_QUEUES) {
4419 device_printf(sc->sc_dev, "%s: bf=%p: invalid tx queue (%d)\n",
4420 __func__,
4421 bf,
4422 bf->bf_state.bfs_tx_queue);
4423 bf->bf_flags &= ~ATH_BUF_BUSY;
4424 ath_returnbuf_tail(sc, bf);
4425 return;
4426 }
4427 ath_txq_freeholdingbuf(sc, txq);
4428 txq->axq_holdingbf = bf;
4429}
4430
4431/*
4432 * Return a buffer to the pool and update the 'busy' flag on the
4433 * previous 'tail' entry.
4434 *
4435 * This _must_ only be called when the buffer is involved in a completed
4436 * TX. The logic is that if it was part of an active TX, the previous
4437 * buffer on the list is now not involved in a halted TX DMA queue, waiting
4438 * for restart (eg for TDMA.)
4439 *
4440 * The caller must free the mbuf and recycle the node reference.
4441 *
4442 * XXX This method of handling busy / holding buffers is insanely stupid.
4443 * It requires bf_state.bfs_tx_queue to be correctly assigned. It would
4444 * be much nicer if buffers in the processq() methods would instead be
4445 * always completed there (pushed onto a txq or ath_bufhead) so we knew
4446 * exactly what hardware queue they came from in the first place.
4447 */
4448void
4449ath_freebuf(struct ath_softc *sc, struct ath_buf *bf)
4450{
4451 struct ath_txq *txq;
4452
4453 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue];
4454
4455 KASSERT((bf->bf_node == NULL), ("%s: bf->bf_node != NULL\n", __func__));
4456 KASSERT((bf->bf_m == NULL), ("%s: bf->bf_m != NULL\n", __func__));
4457
4458 /*
4459 * If this buffer is busy, push it onto the holding queue.
4460 */
4461 if (bf->bf_flags & ATH_BUF_BUSY) {
4462 ATH_TXQ_LOCK(txq);
4463 ath_txq_addholdingbuf(sc, bf);
4464 ATH_TXQ_UNLOCK(txq);
4465 return;
4466 }
4467
4468 /*
4469 * Not a busy buffer, so free normally
4470 */
4471 ATH_TXBUF_LOCK(sc);
4472 ath_returnbuf_tail(sc, bf);
4473 ATH_TXBUF_UNLOCK(sc);
4474}
4475
4476/*
4477 * This is currently used by ath_tx_draintxq() and
4478 * ath_tx_tid_free_pkts().
4479 *
4480 * It recycles a single ath_buf.
4481 */
4482void
4483ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf, int status)
4484{
4485 struct ieee80211_node *ni = bf->bf_node;
4486 struct mbuf *m0 = bf->bf_m;
4487
4488 /*
4489 * Make sure that we only sync/unload if there's an mbuf.
4490 * If not (eg we cloned a buffer), the unload will have already
4491 * occured.
4492 */
4493 if (bf->bf_m != NULL) {
4494 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
4495 BUS_DMASYNC_POSTWRITE);
4496 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4497 }
4498
4499 bf->bf_node = NULL;
4500 bf->bf_m = NULL;
4501
4502 /* Free the buffer, it's not needed any longer */
4503 ath_freebuf(sc, bf);
4504
4505 if (ni != NULL) {
4506 /*
4507 * Do any callback and reclaim the node reference.
4508 */
4509 if (m0->m_flags & M_TXCB)
4510 ieee80211_process_callback(ni, m0, status);
4511 ieee80211_free_node(ni);
4512 }
4513
4514 /* Finally, we don't need this mbuf any longer */
4515 m_freem(m0);
4516}
4517
4518static struct ath_buf *
4519ath_tx_draintxq_get_one(struct ath_softc *sc, struct ath_txq *txq)
4520{
4521 struct ath_buf *bf;
4522
4523 ATH_TXQ_LOCK_ASSERT(txq);
4524
4525 /*
4526 * Drain the FIFO queue first, then if it's
4527 * empty, move to the normal frame queue.
4528 */
4529 bf = TAILQ_FIRST(&txq->fifo.axq_q);
4530 if (bf != NULL) {
4531 /*
4532 * Is it the last buffer in this set?
4533 * Decrement the FIFO counter.
4534 */
4535 if (bf->bf_flags & ATH_BUF_FIFOEND) {
4536 if (txq->axq_fifo_depth == 0) {
4537 device_printf(sc->sc_dev,
4538 "%s: Q%d: fifo_depth=0, fifo.axq_depth=%d?\n",
4539 __func__,
4540 txq->axq_qnum,
4541 txq->fifo.axq_depth);
4542 } else
4543 txq->axq_fifo_depth--;
4544 }
4545 ATH_TXQ_REMOVE(&txq->fifo, bf, bf_list);
4546 return (bf);
4547 }
4548
4549 /*
4550 * Debugging!
4551 */
4552 if (txq->axq_fifo_depth != 0 || txq->fifo.axq_depth != 0) {
4553 device_printf(sc->sc_dev,
4554 "%s: Q%d: fifo_depth=%d, fifo.axq_depth=%d\n",
4555 __func__,
4556 txq->axq_qnum,
4557 txq->axq_fifo_depth,
4558 txq->fifo.axq_depth);
4559 }
4560
4561 /*
4562 * Now drain the pending queue.
4563 */
4564 bf = TAILQ_FIRST(&txq->axq_q);
4565 if (bf == NULL) {
4566 txq->axq_link = NULL;
4567 return (NULL);
4568 }
4569 ATH_TXQ_REMOVE(txq, bf, bf_list);
4570 return (bf);
4571}
4572
4573void
4574ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
4575{
4576#ifdef ATH_DEBUG
4577 struct ath_hal *ah = sc->sc_ah;
4578#endif
4579 struct ath_buf *bf;
4580 u_int ix;
4581
4582 /*
4583 * NB: this assumes output has been stopped and
4584 * we do not need to block ath_tx_proc
4585 */
4586 for (ix = 0;; ix++) {
4587 ATH_TXQ_LOCK(txq);
4588 bf = ath_tx_draintxq_get_one(sc, txq);
4589 if (bf == NULL) {
4590 ATH_TXQ_UNLOCK(txq);
4591 break;
4592 }
4593 if (bf->bf_state.bfs_aggr)
4594 txq->axq_aggr_depth--;
4595#ifdef ATH_DEBUG
4596 if (sc->sc_debug & ATH_DEBUG_RESET) {
4597 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
4598 int status = 0;
4599
4600 /*
4601 * EDMA operation has a TX completion FIFO
4602 * separate from the TX descriptor, so this
4603 * method of checking the "completion" status
4604 * is wrong.
4605 */
4606 if (! sc->sc_isedma) {
4607 status = (ath_hal_txprocdesc(ah,
4608 bf->bf_lastds,
4609 &bf->bf_status.ds_txstat) == HAL_OK);
4610 }
4611 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, status);
4612 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *),
4613 bf->bf_m->m_len, 0, -1);
4614 }
4615#endif /* ATH_DEBUG */
4616 /*
4617 * Since we're now doing magic in the completion
4618 * functions, we -must- call it for aggregation
4619 * destinations or BAW tracking will get upset.
4620 */
4621 /*
4622 * Clear ATH_BUF_BUSY; the completion handler
4623 * will free the buffer.
4624 */
4625 ATH_TXQ_UNLOCK(txq);
4626 bf->bf_flags &= ~ATH_BUF_BUSY;
4627 if (bf->bf_comp)
4628 bf->bf_comp(sc, bf, 1);
4629 else
4630 ath_tx_default_comp(sc, bf, 1);
4631 }
4632
4633 /*
4634 * Free the holding buffer if it exists
4635 */
4636 ATH_TXQ_LOCK(txq);
4637 ath_txq_freeholdingbuf(sc, txq);
4638 ATH_TXQ_UNLOCK(txq);
4639
4640 /*
4641 * Drain software queued frames which are on
4642 * active TIDs.
4643 */
4644 ath_tx_txq_drain(sc, txq);
4645}
4646
4647static void
4648ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
4649{
4650 struct ath_hal *ah = sc->sc_ah;
4651
4652 ATH_TXQ_LOCK_ASSERT(txq);
4653
4654 DPRINTF(sc, ATH_DEBUG_RESET,
4655 "%s: tx queue [%u] %p, active=%d, hwpending=%d, flags 0x%08x, "
4656 "link %p, holdingbf=%p\n",
4657 __func__,
4658 txq->axq_qnum,
4659 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
4660 (int) (!! ath_hal_txqenabled(ah, txq->axq_qnum)),
4661 (int) ath_hal_numtxpending(ah, txq->axq_qnum),
4662 txq->axq_flags,
4663 txq->axq_link,
4664 txq->axq_holdingbf);
4665
4666 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
4667 /* We've stopped TX DMA, so mark this as stopped. */
4668 txq->axq_flags &= ~ATH_TXQ_PUTRUNNING;
4669
4670#ifdef ATH_DEBUG
4671 if ((sc->sc_debug & ATH_DEBUG_RESET)
4672 && (txq->axq_holdingbf != NULL)) {
4673 ath_printtxbuf(sc, txq->axq_holdingbf, txq->axq_qnum, 0, 0);
4674 }
4675#endif
4676}
4677
4678int
4679ath_stoptxdma(struct ath_softc *sc)
4680{
4681 struct ath_hal *ah = sc->sc_ah;
4682 int i;
4683
4684 /* XXX return value */
4685 if (sc->sc_invalid)
4686 return 0;
4687
4688 if (!sc->sc_invalid) {
4689 /* don't touch the hardware if marked invalid */
4690 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
4691 __func__, sc->sc_bhalq,
4692 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq),
4693 NULL);
4694
4695 /* stop the beacon queue */
4696 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
4697
4698 /* Stop the data queues */
4699 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
4700 if (ATH_TXQ_SETUP(sc, i)) {
4701 ATH_TXQ_LOCK(&sc->sc_txq[i]);
4702 ath_tx_stopdma(sc, &sc->sc_txq[i]);
4703 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
4704 }
4705 }
4706 }
4707
4708 return 1;
4709}
4710
4711#ifdef ATH_DEBUG
4712void
4713ath_tx_dump(struct ath_softc *sc, struct ath_txq *txq)
4714{
4715 struct ath_hal *ah = sc->sc_ah;
4716 struct ath_buf *bf;
4717 int i = 0;
4718
4719 if (! (sc->sc_debug & ATH_DEBUG_RESET))
4720 return;
4721
4722 device_printf(sc->sc_dev, "%s: Q%d: begin\n",
4723 __func__, txq->axq_qnum);
4724 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) {
4725 ath_printtxbuf(sc, bf, txq->axq_qnum, i,
4726 ath_hal_txprocdesc(ah, bf->bf_lastds,
4727 &bf->bf_status.ds_txstat) == HAL_OK);
4728 i++;
4729 }
4730 device_printf(sc->sc_dev, "%s: Q%d: end\n",
4731 __func__, txq->axq_qnum);
4732}
4733#endif /* ATH_DEBUG */
4734
4735/*
4736 * Drain the transmit queues and reclaim resources.
4737 */
4738void
4739ath_legacy_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type)
4740{
4741 struct ath_hal *ah = sc->sc_ah;
4742 struct ifnet *ifp = sc->sc_ifp;
4743 int i;
4744 struct ath_buf *bf_last;
4745
4746 (void) ath_stoptxdma(sc);
4747
4748 /*
4749 * Dump the queue contents
4750 */
4751 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
4752 /*
4753 * XXX TODO: should we just handle the completed TX frames
4754 * here, whether or not the reset is a full one or not?
4755 */
4756 if (ATH_TXQ_SETUP(sc, i)) {
4757#ifdef ATH_DEBUG
4758 if (sc->sc_debug & ATH_DEBUG_RESET)
4759 ath_tx_dump(sc, &sc->sc_txq[i]);
4760#endif /* ATH_DEBUG */
4761 if (reset_type == ATH_RESET_NOLOSS) {
4762 ath_tx_processq(sc, &sc->sc_txq[i], 0);
4763 ATH_TXQ_LOCK(&sc->sc_txq[i]);
4764 /*
4765 * Free the holding buffer; DMA is now
4766 * stopped.
4767 */
4768 ath_txq_freeholdingbuf(sc, &sc->sc_txq[i]);
4769 /*
4770 * Setup the link pointer to be the
4771 * _last_ buffer/descriptor in the list.
4772 * If there's nothing in the list, set it
4773 * to NULL.
4774 */
4775 bf_last = ATH_TXQ_LAST(&sc->sc_txq[i],
4776 axq_q_s);
4777 if (bf_last != NULL) {
4778 ath_hal_gettxdesclinkptr(ah,
4779 bf_last->bf_lastds,
4780 &sc->sc_txq[i].axq_link);
4781 } else {
4782 sc->sc_txq[i].axq_link = NULL;
4783 }
4784 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
4785 } else
4786 ath_tx_draintxq(sc, &sc->sc_txq[i]);
4787 }
4788 }
4789#ifdef ATH_DEBUG
4790 if (sc->sc_debug & ATH_DEBUG_RESET) {
4791 struct ath_buf *bf = TAILQ_FIRST(&sc->sc_bbuf);
4792 if (bf != NULL && bf->bf_m != NULL) {
4793 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0,
4794 ath_hal_txprocdesc(ah, bf->bf_lastds,
4795 &bf->bf_status.ds_txstat) == HAL_OK);
4796 ieee80211_dump_pkt(ifp->if_l2com,
4797 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len,
4798 0, -1);
4799 }
4800 }
4801#endif /* ATH_DEBUG */
4802 IF_LOCK(&ifp->if_snd);
4803 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4804 IF_UNLOCK(&ifp->if_snd);
4805 sc->sc_wd_timer = 0;
4806}
4807
4808/*
4809 * Update internal state after a channel change.
4810 */
4811static void
4812ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
4813{
4814 enum ieee80211_phymode mode;
4815
4816 /*
4817 * Change channels and update the h/w rate map
4818 * if we're switching; e.g. 11a to 11b/g.
4819 */
4820 mode = ieee80211_chan2mode(chan);
4821 if (mode != sc->sc_curmode)
4822 ath_setcurmode(sc, mode);
4823 sc->sc_curchan = chan;
4824}
4825
4826/*
4827 * Set/change channels. If the channel is really being changed,
4828 * it's done by resetting the chip. To accomplish this we must
4829 * first cleanup any pending DMA, then restart stuff after a la
4830 * ath_init.
4831 */
4832static int
4833ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
4834{
4835 struct ifnet *ifp = sc->sc_ifp;
4836 struct ieee80211com *ic = ifp->if_l2com;
4837 struct ath_hal *ah = sc->sc_ah;
4838 int ret = 0;
4839
4840 /* Treat this as an interface reset */
4841 ATH_PCU_UNLOCK_ASSERT(sc);
4842 ATH_UNLOCK_ASSERT(sc);
4843
4844 /* (Try to) stop TX/RX from occuring */
4845 taskqueue_block(sc->sc_tq);
4846
4847 ATH_PCU_LOCK(sc);
4848 ath_hal_intrset(ah, 0); /* Stop new RX/TX completion */
4849 ath_txrx_stop_locked(sc); /* Stop pending RX/TX completion */
4850 if (ath_reset_grablock(sc, 1) == 0) {
4851 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
4852 __func__);
4853 }
4854 ATH_PCU_UNLOCK(sc);
4855
4856 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n",
4857 __func__, ieee80211_chan2ieee(ic, chan),
4858 chan->ic_freq, chan->ic_flags);
4859 if (chan != sc->sc_curchan) {
4860 HAL_STATUS status;
4861 /*
4862 * To switch channels clear any pending DMA operations;
4863 * wait long enough for the RX fifo to drain, reset the
4864 * hardware at the new frequency, and then re-enable
4865 * the relevant bits of the h/w.
4866 */
4867#if 0
4868 ath_hal_intrset(ah, 0); /* disable interrupts */
4869#endif
4870 ath_stoprecv(sc, 1); /* turn off frame recv */
4871 /*
4872 * First, handle completed TX/RX frames.
4873 */
4874 ath_rx_flush(sc);
4875 ath_draintxq(sc, ATH_RESET_NOLOSS);
4876 /*
4877 * Next, flush the non-scheduled frames.
4878 */
4879 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */
4880
4881 ath_update_chainmasks(sc, chan);
4882 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
4883 sc->sc_cur_rxchainmask);
4884 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) {
4885 if_printf(ifp, "%s: unable to reset "
4886 "channel %u (%u MHz, flags 0x%x), hal status %u\n",
4887 __func__, ieee80211_chan2ieee(ic, chan),
4888 chan->ic_freq, chan->ic_flags, status);
4889 ret = EIO;
4890 goto finish;
4891 }
4892 sc->sc_diversity = ath_hal_getdiversity(ah);
4893
4894 /* Let DFS at it in case it's a DFS channel */
4895 ath_dfs_radar_enable(sc, chan);
4896
4897 /* Let spectral at in case spectral is enabled */
4898 ath_spectral_enable(sc, chan);
4899
4900 /*
4901 * If we're doing TDMA, enforce the TXOP limitation for chips
4902 * that support it.
4903 */
4904 if (sc->sc_hasenforcetxop && sc->sc_tdma)
4905 ath_hal_setenforcetxop(sc->sc_ah, 1);
4906 else
4907 ath_hal_setenforcetxop(sc->sc_ah, 0);
4908
4909 /*
4910 * Re-enable rx framework.
4911 */
4912 if (ath_startrecv(sc) != 0) {
4913 if_printf(ifp, "%s: unable to restart recv logic\n",
4914 __func__);
4915 ret = EIO;
4916 goto finish;
4917 }
4918
4919 /*
4920 * Change channels and update the h/w rate map
4921 * if we're switching; e.g. 11a to 11b/g.
4922 */
4923 ath_chan_change(sc, chan);
4924
4925 /*
4926 * Reset clears the beacon timers; reset them
4927 * here if needed.
4928 */
4929 if (sc->sc_beacons) { /* restart beacons */
4930#ifdef IEEE80211_SUPPORT_TDMA
4931 if (sc->sc_tdma)
4932 ath_tdma_config(sc, NULL);
4933 else
4934#endif
4935 ath_beacon_config(sc, NULL);
4936 }
4937
4938 /*
4939 * Re-enable interrupts.
4940 */
4941#if 0
4942 ath_hal_intrset(ah, sc->sc_imask);
4943#endif
4944 }
4945
4946finish:
4947 ATH_PCU_LOCK(sc);
4948 sc->sc_inreset_cnt--;
4949 /* XXX only do this if sc_inreset_cnt == 0? */
4950 ath_hal_intrset(ah, sc->sc_imask);
4951 ATH_PCU_UNLOCK(sc);
4952
4953 IF_LOCK(&ifp->if_snd);
4954 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4955 IF_UNLOCK(&ifp->if_snd);
4956 ath_txrx_start(sc);
4957 /* XXX ath_start? */
4958
4959 return ret;
4960}
4961
4962/*
4963 * Periodically recalibrate the PHY to account
4964 * for temperature/environment changes.
4965 */
4966static void
4967ath_calibrate(void *arg)
4968{
4969 struct ath_softc *sc = arg;
4970 struct ath_hal *ah = sc->sc_ah;
4971 struct ifnet *ifp = sc->sc_ifp;
4972 struct ieee80211com *ic = ifp->if_l2com;
4973 HAL_BOOL longCal, isCalDone = AH_TRUE;
4974 HAL_BOOL aniCal, shortCal = AH_FALSE;
4975 int nextcal;
4976
4977 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */
4978 goto restart;
4979 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz);
4980 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000);
4981 if (sc->sc_doresetcal)
4982 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000);
4983
4984 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal);
4985 if (aniCal) {
4986 sc->sc_stats.ast_ani_cal++;
4987 sc->sc_lastani = ticks;
4988 ath_hal_ani_poll(ah, sc->sc_curchan);
4989 }
4990
4991 if (longCal) {
4992 sc->sc_stats.ast_per_cal++;
4993 sc->sc_lastlongcal = ticks;
4994 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
4995 /*
4996 * Rfgain is out of bounds, reset the chip
4997 * to load new gain values.
4998 */
4999 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5000 "%s: rfgain change\n", __func__);
5001 sc->sc_stats.ast_per_rfgain++;
5002 sc->sc_resetcal = 0;
5003 sc->sc_doresetcal = AH_TRUE;
5004 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
5005 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
5006 return;
5007 }
5008 /*
5009 * If this long cal is after an idle period, then
5010 * reset the data collection state so we start fresh.
5011 */
5012 if (sc->sc_resetcal) {
5013 (void) ath_hal_calreset(ah, sc->sc_curchan);
5014 sc->sc_lastcalreset = ticks;
5015 sc->sc_lastshortcal = ticks;
5016 sc->sc_resetcal = 0;
5017 sc->sc_doresetcal = AH_TRUE;
5018 }
5019 }
5020
5021 /* Only call if we're doing a short/long cal, not for ANI calibration */
5022 if (shortCal || longCal) {
5023 isCalDone = AH_FALSE;
5024 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) {
5025 if (longCal) {
5026 /*
5027 * Calibrate noise floor data again in case of change.
5028 */
5029 ath_hal_process_noisefloor(ah);
5030 }
5031 } else {
5032 DPRINTF(sc, ATH_DEBUG_ANY,
5033 "%s: calibration of channel %u failed\n",
5034 __func__, sc->sc_curchan->ic_freq);
5035 sc->sc_stats.ast_per_calfail++;
5036 }
5037 if (shortCal)
5038 sc->sc_lastshortcal = ticks;
5039 }
5040 if (!isCalDone) {
5041restart:
5042 /*
5043 * Use a shorter interval to potentially collect multiple
5044 * data samples required to complete calibration. Once
5045 * we're told the work is done we drop back to a longer
5046 * interval between requests. We're more aggressive doing
5047 * work when operating as an AP to improve operation right
5048 * after startup.
5049 */
5050 sc->sc_lastshortcal = ticks;
5051 nextcal = ath_shortcalinterval*hz/1000;
5052 if (sc->sc_opmode != HAL_M_HOSTAP)
5053 nextcal *= 10;
5054 sc->sc_doresetcal = AH_TRUE;
5055 } else {
5056 /* nextcal should be the shortest time for next event */
5057 nextcal = ath_longcalinterval*hz;
5058 if (sc->sc_lastcalreset == 0)
5059 sc->sc_lastcalreset = sc->sc_lastlongcal;
5060 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz)
5061 sc->sc_resetcal = 1; /* setup reset next trip */
5062 sc->sc_doresetcal = AH_FALSE;
5063 }
5064 /* ANI calibration may occur more often than short/long/resetcal */
5065 if (ath_anicalinterval > 0)
5066 nextcal = MIN(nextcal, ath_anicalinterval*hz/1000);
5067
5068 if (nextcal != 0) {
5069 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n",
5070 __func__, nextcal, isCalDone ? "" : "!");
5071 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc);
5072 } else {
5073 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n",
5074 __func__);
5075 /* NB: don't rearm timer */
5076 }
5077}
5078
5079static void
5080ath_scan_start(struct ieee80211com *ic)
5081{
5082 struct ifnet *ifp = ic->ic_ifp;
5083 struct ath_softc *sc = ifp->if_softc;
5084 struct ath_hal *ah = sc->sc_ah;
5085 u_int32_t rfilt;
5086
5087 /* XXX calibration timer? */
5088
5089 ATH_LOCK(sc);
5090 sc->sc_scanning = 1;
5091 sc->sc_syncbeacon = 0;
5092 rfilt = ath_calcrxfilter(sc);
5093 ATH_UNLOCK(sc);
5094
5095 ATH_PCU_LOCK(sc);
5096 ath_hal_setrxfilter(ah, rfilt);
5097 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0);
5098 ATH_PCU_UNLOCK(sc);
5099
5100 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n",
5101 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr));
5102}
5103
5104static void
5105ath_scan_end(struct ieee80211com *ic)
5106{
5107 struct ifnet *ifp = ic->ic_ifp;
5108 struct ath_softc *sc = ifp->if_softc;
5109 struct ath_hal *ah = sc->sc_ah;
5110 u_int32_t rfilt;
5111
5112 ATH_LOCK(sc);
5113 sc->sc_scanning = 0;
5114 rfilt = ath_calcrxfilter(sc);
5115 ATH_UNLOCK(sc);
5116
5117 ATH_PCU_LOCK(sc);
5118 ath_hal_setrxfilter(ah, rfilt);
5119 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5120
5121 ath_hal_process_noisefloor(ah);
5122 ATH_PCU_UNLOCK(sc);
5123
5124 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5125 __func__, rfilt, ether_sprintf(sc->sc_curbssid),
5126 sc->sc_curaid);
5127}
5128
5129#ifdef ATH_ENABLE_11N
5130/*
5131 * For now, just do a channel change.
5132 *
5133 * Later, we'll go through the hard slog of suspending tx/rx, changing rate
5134 * control state and resetting the hardware without dropping frames out
5135 * of the queue.
5136 *
5137 * The unfortunate trouble here is making absolutely sure that the
5138 * channel width change has propagated enough so the hardware
5139 * absolutely isn't handed bogus frames for it's current operating
5140 * mode. (Eg, 40MHz frames in 20MHz mode.) Since TX and RX can and
5141 * does occur in parallel, we need to make certain we've blocked
5142 * any further ongoing TX (and RX, that can cause raw TX)
5143 * before we do this.
5144 */
5145static void
5146ath_update_chw(struct ieee80211com *ic)
5147{
5148 struct ifnet *ifp = ic->ic_ifp;
5149 struct ath_softc *sc = ifp->if_softc;
5150
5151 DPRINTF(sc, ATH_DEBUG_STATE, "%s: called\n", __func__);
5152 ath_set_channel(ic);
5153}
5154#endif /* ATH_ENABLE_11N */
5155
5156static void
5157ath_set_channel(struct ieee80211com *ic)
5158{
5159 struct ifnet *ifp = ic->ic_ifp;
5160 struct ath_softc *sc = ifp->if_softc;
5161
5162 (void) ath_chan_set(sc, ic->ic_curchan);
5163 /*
5164 * If we are returning to our bss channel then mark state
5165 * so the next recv'd beacon's tsf will be used to sync the
5166 * beacon timers. Note that since we only hear beacons in
5167 * sta/ibss mode this has no effect in other operating modes.
5168 */
5169 ATH_LOCK(sc);
5170 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan)
5171 sc->sc_syncbeacon = 1;
5172 ATH_UNLOCK(sc);
5173}
5174
5175/*
5176 * Walk the vap list and check if there any vap's in RUN state.
5177 */
5178static int
5179ath_isanyrunningvaps(struct ieee80211vap *this)
5180{
5181 struct ieee80211com *ic = this->iv_ic;
5182 struct ieee80211vap *vap;
5183
5184 IEEE80211_LOCK_ASSERT(ic);
5185
5186 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
5187 if (vap != this && vap->iv_state >= IEEE80211_S_RUN)
5188 return 1;
5189 }
5190 return 0;
5191}
5192
5193static int
5194ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
5195{
5196 struct ieee80211com *ic = vap->iv_ic;
5197 struct ath_softc *sc = ic->ic_ifp->if_softc;
5198 struct ath_vap *avp = ATH_VAP(vap);
5199 struct ath_hal *ah = sc->sc_ah;
5200 struct ieee80211_node *ni = NULL;
5201 int i, error, stamode;
5202 u_int32_t rfilt;
5203 int csa_run_transition = 0;
5204
5205 static const HAL_LED_STATE leds[] = {
5206 HAL_LED_INIT, /* IEEE80211_S_INIT */
5207 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
5208 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
5209 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
5210 HAL_LED_RUN, /* IEEE80211_S_CAC */
5211 HAL_LED_RUN, /* IEEE80211_S_RUN */
5212 HAL_LED_RUN, /* IEEE80211_S_CSA */
5213 HAL_LED_RUN, /* IEEE80211_S_SLEEP */
5214 };
5215
5216 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
5217 ieee80211_state_name[vap->iv_state],
5218 ieee80211_state_name[nstate]);
5219
5220 /*
5221 * net80211 _should_ have the comlock asserted at this point.
5222 * There are some comments around the calls to vap->iv_newstate
5223 * which indicate that it (newstate) may end up dropping the
5224 * lock. This and the subsequent lock assert check after newstate
5225 * are an attempt to catch these and figure out how/why.
5226 */
5227 IEEE80211_LOCK_ASSERT(ic);
5228
5229 if (vap->iv_state == IEEE80211_S_CSA && nstate == IEEE80211_S_RUN)
5230 csa_run_transition = 1;
5231
5232 callout_drain(&sc->sc_cal_ch);
5233 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
5234
5235 if (nstate == IEEE80211_S_SCAN) {
5236 /*
5237 * Scanning: turn off beacon miss and don't beacon.
5238 * Mark beacon state so when we reach RUN state we'll
5239 * [re]setup beacons. Unblock the task q thread so
5240 * deferred interrupt processing is done.
5241 */
5242 ath_hal_intrset(ah,
5243 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
5244 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5245 sc->sc_beacons = 0;
5246 taskqueue_unblock(sc->sc_tq);
5247 }
5248
5249 ni = ieee80211_ref_node(vap->iv_bss);
5250 rfilt = ath_calcrxfilter(sc);
5251 stamode = (vap->iv_opmode == IEEE80211_M_STA ||
5252 vap->iv_opmode == IEEE80211_M_AHDEMO ||
5253 vap->iv_opmode == IEEE80211_M_IBSS);
5254 if (stamode && nstate == IEEE80211_S_RUN) {
5255 sc->sc_curaid = ni->ni_associd;
5256 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid);
5257 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5258 }
5259 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5260 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid);
5261 ath_hal_setrxfilter(ah, rfilt);
5262
5263 /* XXX is this to restore keycache on resume? */
5264 if (vap->iv_opmode != IEEE80211_M_STA &&
5265 (vap->iv_flags & IEEE80211_F_PRIVACY)) {
5266 for (i = 0; i < IEEE80211_WEP_NKID; i++)
5267 if (ath_hal_keyisvalid(ah, i))
5268 ath_hal_keysetmac(ah, i, ni->ni_bssid);
5269 }
5270
5271 /*
5272 * Invoke the parent method to do net80211 work.
5273 */
5274 error = avp->av_newstate(vap, nstate, arg);
5275 if (error != 0)
5276 goto bad;
5277
5278 /*
5279 * See above: ensure av_newstate() doesn't drop the lock
5280 * on us.
5281 */
5282 IEEE80211_LOCK_ASSERT(ic);
5283
5284 if (nstate == IEEE80211_S_RUN) {
5285 /* NB: collect bss node again, it may have changed */
5286 ieee80211_free_node(ni);
5287 ni = ieee80211_ref_node(vap->iv_bss);
5288
5289 DPRINTF(sc, ATH_DEBUG_STATE,
5290 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s "
5291 "capinfo 0x%04x chan %d\n", __func__,
5292 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid),
5293 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan));
5294
5295 switch (vap->iv_opmode) {
5296#ifdef IEEE80211_SUPPORT_TDMA
5297 case IEEE80211_M_AHDEMO:
5298 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0)
5299 break;
5300 /* fall thru... */
5301#endif
5302 case IEEE80211_M_HOSTAP:
5303 case IEEE80211_M_IBSS:
5304 case IEEE80211_M_MBSS:
5305 /*
5306 * Allocate and setup the beacon frame.
5307 *
5308 * Stop any previous beacon DMA. This may be
5309 * necessary, for example, when an ibss merge
5310 * causes reconfiguration; there will be a state
5311 * transition from RUN->RUN that means we may
5312 * be called with beacon transmission active.
5313 */
5314 ath_hal_stoptxdma(ah, sc->sc_bhalq);
5315
5316 error = ath_beacon_alloc(sc, ni);
5317 if (error != 0)
5318 goto bad;
5319 /*
5320 * If joining an adhoc network defer beacon timer
5321 * configuration to the next beacon frame so we
5322 * have a current TSF to use. Otherwise we're
5323 * starting an ibss/bss so there's no need to delay;
5324 * if this is the first vap moving to RUN state, then
5325 * beacon state needs to be [re]configured.
5326 */
5327 if (vap->iv_opmode == IEEE80211_M_IBSS &&
5328 ni->ni_tstamp.tsf != 0) {
5329 sc->sc_syncbeacon = 1;
5330 } else if (!sc->sc_beacons) {
5331#ifdef IEEE80211_SUPPORT_TDMA
5332 if (vap->iv_caps & IEEE80211_C_TDMA)
5333 ath_tdma_config(sc, vap);
5334 else
5335#endif
5336 ath_beacon_config(sc, vap);
5337 sc->sc_beacons = 1;
5338 }
5339 break;
5340 case IEEE80211_M_STA:
5341 /*
5342 * Defer beacon timer configuration to the next
5343 * beacon frame so we have a current TSF to use
5344 * (any TSF collected when scanning is likely old).
5345 * However if it's due to a CSA -> RUN transition,
5346 * force a beacon update so we pick up a lack of
5347 * beacons from an AP in CAC and thus force a
5348 * scan.
5349 *
5350 * And, there's also corner cases here where
5351 * after a scan, the AP may have disappeared.
5352 * In that case, we may not receive an actual
5353 * beacon to update the beacon timer and thus we
5354 * won't get notified of the missing beacons.
5355 */
5356 sc->sc_syncbeacon = 1;
5357#if 0
5358 if (csa_run_transition)
5359#endif
5360 ath_beacon_config(sc, vap);
5361
5362 /*
5363 * PR: kern/175227
5364 *
5365 * Reconfigure beacons during reset; as otherwise
5366 * we won't get the beacon timers reprogrammed
5367 * after a reset and thus we won't pick up a
5368 * beacon miss interrupt.
5369 *
5370 * Hopefully we'll see a beacon before the BMISS
5371 * timer fires (too often), leading to a STA
5372 * disassociation.
5373 */
5374 sc->sc_beacons = 1;
5375 break;
5376 case IEEE80211_M_MONITOR:
5377 /*
5378 * Monitor mode vaps have only INIT->RUN and RUN->RUN
5379 * transitions so we must re-enable interrupts here to
5380 * handle the case of a single monitor mode vap.
5381 */
5382 ath_hal_intrset(ah, sc->sc_imask);
5383 break;
5384 case IEEE80211_M_WDS:
5385 break;
5386 default:
5387 break;
5388 }
5389 /*
5390 * Let the hal process statistics collected during a
5391 * scan so it can provide calibrated noise floor data.
5392 */
5393 ath_hal_process_noisefloor(ah);
5394 /*
5395 * Reset rssi stats; maybe not the best place...
5396 */
5397 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
5398 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
5399 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
5400 /*
5401 * Finally, start any timers and the task q thread
5402 * (in case we didn't go through SCAN state).
5403 */
5404 if (ath_longcalinterval != 0) {
5405 /* start periodic recalibration timer */
5406 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
5407 } else {
5408 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5409 "%s: calibration disabled\n", __func__);
5410 }
5411 taskqueue_unblock(sc->sc_tq);
5412 } else if (nstate == IEEE80211_S_INIT) {
5413 /*
5414 * If there are no vaps left in RUN state then
5415 * shutdown host/driver operation:
5416 * o disable interrupts
5417 * o disable the task queue thread
5418 * o mark beacon processing as stopped
5419 */
5420 if (!ath_isanyrunningvaps(vap)) {
5421 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5422 /* disable interrupts */
5423 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
5424 taskqueue_block(sc->sc_tq);
5425 sc->sc_beacons = 0;
5426 }
5427#ifdef IEEE80211_SUPPORT_TDMA
5428 ath_hal_setcca(ah, AH_TRUE);
5429#endif
5430 }
5431bad:
5432 ieee80211_free_node(ni);
5433 return error;
5434}
5435
5436/*
5437 * Allocate a key cache slot to the station so we can
5438 * setup a mapping from key index to node. The key cache
5439 * slot is needed for managing antenna state and for
5440 * compression when stations do not use crypto. We do
5441 * it uniliaterally here; if crypto is employed this slot
5442 * will be reassigned.
5443 */
5444static void
5445ath_setup_stationkey(struct ieee80211_node *ni)
5446{
5447 struct ieee80211vap *vap = ni->ni_vap;
5448 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
5449 ieee80211_keyix keyix, rxkeyix;
5450
5451 /* XXX should take a locked ref to vap->iv_bss */
5452 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
5453 /*
5454 * Key cache is full; we'll fall back to doing
5455 * the more expensive lookup in software. Note
5456 * this also means no h/w compression.
5457 */
5458 /* XXX msg+statistic */
5459 } else {
5460 /* XXX locking? */
5461 ni->ni_ucastkey.wk_keyix = keyix;
5462 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
5463 /* NB: must mark device key to get called back on delete */
5464 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY;
5465 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr);
5466 /* NB: this will create a pass-thru key entry */
5467 ath_keyset(sc, vap, &ni->ni_ucastkey, vap->iv_bss);
5468 }
5469}
5470
5471/*
5472 * Setup driver-specific state for a newly associated node.
5473 * Note that we're called also on a re-associate, the isnew
5474 * param tells us if this is the first time or not.
5475 */
5476static void
5477ath_newassoc(struct ieee80211_node *ni, int isnew)
5478{
5479 struct ath_node *an = ATH_NODE(ni);
5480 struct ieee80211vap *vap = ni->ni_vap;
5481 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
5482 const struct ieee80211_txparam *tp = ni->ni_txparms;
5483
5484 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate);
5485 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate);
5486
5487 ath_rate_newassoc(sc, an, isnew);
5488 if (isnew &&
5489 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey &&
5490 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
5491 ath_setup_stationkey(ni);
5492
5493 /*
5494 * If we're reassociating, make sure that any paused queues
5495 * get unpaused.
5496 *
5497 * Now, we may hvae frames in the hardware queue for this node.
5498 * So if we are reassociating and there are frames in the queue,
5499 * we need to go through the cleanup path to ensure that they're
5500 * marked as non-aggregate.
5501 */
5502 if (! isnew) {
5503 device_printf(sc->sc_dev,
5504 "%s: %6D: reassoc; is_powersave=%d\n",
5505 __func__,
5506 ni->ni_macaddr,
5507 ":",
5508 an->an_is_powersave);
5509
5510 /* XXX for now, we can't hold the lock across assoc */
5511 ath_tx_node_reassoc(sc, an);
5512
5513 /* XXX for now, we can't hold the lock across wakeup */
5514 if (an->an_is_powersave)
5515 ath_tx_node_wakeup(sc, an);
5516 }
5517}
5518
5519static int
5520ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg,
5521 int nchans, struct ieee80211_channel chans[])
5522{
5523 struct ath_softc *sc = ic->ic_ifp->if_softc;
5524 struct ath_hal *ah = sc->sc_ah;
5525 HAL_STATUS status;
5526
5527 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
5528 "%s: rd %u cc %u location %c%s\n",
5529 __func__, reg->regdomain, reg->country, reg->location,
5530 reg->ecm ? " ecm" : "");
5531
5532 status = ath_hal_set_channels(ah, chans, nchans,
5533 reg->country, reg->regdomain);
5534 if (status != HAL_OK) {
5535 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n",
5536 __func__, status);
5537 return EINVAL; /* XXX */
5538 }
5539
5540 return 0;
5541}
5542
5543static void
5544ath_getradiocaps(struct ieee80211com *ic,
5545 int maxchans, int *nchans, struct ieee80211_channel chans[])
5546{
5547 struct ath_softc *sc = ic->ic_ifp->if_softc;
5548 struct ath_hal *ah = sc->sc_ah;
5549
5550 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n",
5551 __func__, SKU_DEBUG, CTRY_DEFAULT);
5552
5553 /* XXX check return */
5554 (void) ath_hal_getchannels(ah, chans, maxchans, nchans,
5555 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE);
5556
5557}
5558
5559static int
5560ath_getchannels(struct ath_softc *sc)
5561{
5562 struct ifnet *ifp = sc->sc_ifp;
5563 struct ieee80211com *ic = ifp->if_l2com;
5564 struct ath_hal *ah = sc->sc_ah;
5565 HAL_STATUS status;
5566
5567 /*
5568 * Collect channel set based on EEPROM contents.
5569 */
5570 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX,
5571 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE);
5572 if (status != HAL_OK) {
5573 if_printf(ifp, "%s: unable to collect channel list from hal, "
5574 "status %d\n", __func__, status);
5575 return EINVAL;
5576 }
5577 (void) ath_hal_getregdomain(ah, &sc->sc_eerd);
5578 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */
5579 /* XXX map Atheros sku's to net80211 SKU's */
5580 /* XXX net80211 types too small */
5581 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd;
5582 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc;
5583 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */
5584 ic->ic_regdomain.isocc[1] = ' ';
5585
5586 ic->ic_regdomain.ecm = 1;
5587 ic->ic_regdomain.location = 'I';
5588
5589 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
5590 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n",
5591 __func__, sc->sc_eerd, sc->sc_eecc,
5592 ic->ic_regdomain.regdomain, ic->ic_regdomain.country,
5593 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : "");
5594 return 0;
5595}
5596
5597static int
5598ath_rate_setup(struct ath_softc *sc, u_int mode)
5599{
5600 struct ath_hal *ah = sc->sc_ah;
5601 const HAL_RATE_TABLE *rt;
5602
5603 switch (mode) {
5604 case IEEE80211_MODE_11A:
5605 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
5606 break;
5607 case IEEE80211_MODE_HALF:
5608 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE);
5609 break;
5610 case IEEE80211_MODE_QUARTER:
5611 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE);
5612 break;
5613 case IEEE80211_MODE_11B:
5614 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
5615 break;
5616 case IEEE80211_MODE_11G:
5617 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
5618 break;
5619 case IEEE80211_MODE_TURBO_A:
5620 rt = ath_hal_getratetable(ah, HAL_MODE_108A);
5621 break;
5622 case IEEE80211_MODE_TURBO_G:
5623 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
5624 break;
5625 case IEEE80211_MODE_STURBO_A:
5626 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
5627 break;
5628 case IEEE80211_MODE_11NA:
5629 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20);
5630 break;
5631 case IEEE80211_MODE_11NG:
5632 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20);
5633 break;
5634 default:
5635 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
5636 __func__, mode);
5637 return 0;
5638 }
5639 sc->sc_rates[mode] = rt;
5640 return (rt != NULL);
5641}
5642
5643static void
5644ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
5645{
5646#define N(a) (sizeof(a)/sizeof(a[0]))
5647 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
5648 static const struct {
5649 u_int rate; /* tx/rx 802.11 rate */
5650 u_int16_t timeOn; /* LED on time (ms) */
5651 u_int16_t timeOff; /* LED off time (ms) */
5652 } blinkrates[] = {
5653 { 108, 40, 10 },
5654 { 96, 44, 11 },
5655 { 72, 50, 13 },
5656 { 48, 57, 14 },
5657 { 36, 67, 16 },
5658 { 24, 80, 20 },
5659 { 22, 100, 25 },
5660 { 18, 133, 34 },
5661 { 12, 160, 40 },
5662 { 10, 200, 50 },
5663 { 6, 240, 58 },
5664 { 4, 267, 66 },
5665 { 2, 400, 100 },
5666 { 0, 500, 130 },
5667 /* XXX half/quarter rates */
5668 };
5669 const HAL_RATE_TABLE *rt;
5670 int i, j;
5671
5672 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
5673 rt = sc->sc_rates[mode];
5674 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
5675 for (i = 0; i < rt->rateCount; i++) {
5676 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
5677 if (rt->info[i].phy != IEEE80211_T_HT)
5678 sc->sc_rixmap[ieeerate] = i;
5679 else
5680 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i;
5681 }
5682 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
5683 for (i = 0; i < N(sc->sc_hwmap); i++) {
5684 if (i >= rt->rateCount) {
5685 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
5686 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
5687 continue;
5688 }
5689 sc->sc_hwmap[i].ieeerate =
5690 rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
5691 if (rt->info[i].phy == IEEE80211_T_HT)
5692 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS;
5693 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
5694 if (rt->info[i].shortPreamble ||
5695 rt->info[i].phy == IEEE80211_T_OFDM)
5696 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
5697 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags;
5698 for (j = 0; j < N(blinkrates)-1; j++)
5699 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
5700 break;
5701 /* NB: this uses the last entry if the rate isn't found */
5702 /* XXX beware of overlow */
5703 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
5704 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
5705 }
5706 sc->sc_currates = rt;
5707 sc->sc_curmode = mode;
5708 /*
5709 * All protection frames are transmited at 2Mb/s for
5710 * 11g, otherwise at 1Mb/s.
5711 */
5712 if (mode == IEEE80211_MODE_11G)
5713 sc->sc_protrix = ath_tx_findrix(sc, 2*2);
5714 else
5715 sc->sc_protrix = ath_tx_findrix(sc, 2*1);
5716 /* NB: caller is responsible for resetting rate control state */
5717#undef N
5718}
5719
5720static void
5721ath_watchdog(void *arg)
5722{
5723 struct ath_softc *sc = arg;
5724 int do_reset = 0;
5725
5726 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) {
5727 struct ifnet *ifp = sc->sc_ifp;
5728 uint32_t hangs;
5729
5730 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) &&
5731 hangs != 0) {
5732 if_printf(ifp, "%s hang detected (0x%x)\n",
5733 hangs & 0xff ? "bb" : "mac", hangs);
5734 } else
5735 if_printf(ifp, "device timeout\n");
5736 do_reset = 1;
5737 ifp->if_oerrors++;
5738 sc->sc_stats.ast_watchdog++;
5739 }
5740
5741 /*
5742 * We can't hold the lock across the ath_reset() call.
5743 *
5744 * And since this routine can't hold a lock and sleep,
5745 * do the reset deferred.
5746 */
5747 if (do_reset) {
5748 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
5749 }
5750
5751 callout_schedule(&sc->sc_wd_ch, hz);
5752}
5753
5754/*
5755 * Fetch the rate control statistics for the given node.
5756 */
5757static int
5758ath_ioctl_ratestats(struct ath_softc *sc, struct ath_rateioctl *rs)
5759{
5760 struct ath_node *an;
5761 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
5762 struct ieee80211_node *ni;
5763 int error = 0;
5764
5765 /* Perform a lookup on the given node */
5766 ni = ieee80211_find_node(&ic->ic_sta, rs->is_u.macaddr);
5767 if (ni == NULL) {
5768 error = EINVAL;
5769 goto bad;
5770 }
5771
5772 /* Lock the ath_node */
5773 an = ATH_NODE(ni);
5774 ATH_NODE_LOCK(an);
5775
5776 /* Fetch the rate control stats for this node */
5777 error = ath_rate_fetch_node_stats(sc, an, rs);
5778
5779 /* No matter what happens here, just drop through */
5780
5781 /* Unlock the ath_node */
5782 ATH_NODE_UNLOCK(an);
5783
5784 /* Unref the node */
5785 ieee80211_node_decref(ni);
5786
5787bad:
5788 return (error);
5789}
5790
5791#ifdef ATH_DIAGAPI
5792/*
5793 * Diagnostic interface to the HAL. This is used by various
5794 * tools to do things like retrieve register contents for
5795 * debugging. The mechanism is intentionally opaque so that
5796 * it can change frequently w/o concern for compatiblity.
5797 */
5798static int
5799ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
5800{
5801 struct ath_hal *ah = sc->sc_ah;
5802 u_int id = ad->ad_id & ATH_DIAG_ID;
5803 void *indata = NULL;
5804 void *outdata = NULL;
5805 u_int32_t insize = ad->ad_in_size;
5806 u_int32_t outsize = ad->ad_out_size;
5807 int error = 0;
5808
5809 if (ad->ad_id & ATH_DIAG_IN) {
5810 /*
5811 * Copy in data.
5812 */
5813 indata = malloc(insize, M_TEMP, M_NOWAIT);
5814 if (indata == NULL) {
5815 error = ENOMEM;
5816 goto bad;
5817 }
5818 error = copyin(ad->ad_in_data, indata, insize);
5819 if (error)
5820 goto bad;
5821 }
5822 if (ad->ad_id & ATH_DIAG_DYN) {
5823 /*
5824 * Allocate a buffer for the results (otherwise the HAL
5825 * returns a pointer to a buffer where we can read the
5826 * results). Note that we depend on the HAL leaving this
5827 * pointer for us to use below in reclaiming the buffer;
5828 * may want to be more defensive.
5829 */
5830 outdata = malloc(outsize, M_TEMP, M_NOWAIT);
5831 if (outdata == NULL) {
5832 error = ENOMEM;
5833 goto bad;
5834 }
5835 }
5836 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
5837 if (outsize < ad->ad_out_size)
5838 ad->ad_out_size = outsize;
5839 if (outdata != NULL)
5840 error = copyout(outdata, ad->ad_out_data,
5841 ad->ad_out_size);
5842 } else {
5843 error = EINVAL;
5844 }
5845bad:
5846 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
5847 free(indata, M_TEMP);
5848 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
5849 free(outdata, M_TEMP);
5850 return error;
5851}
5852#endif /* ATH_DIAGAPI */
5853
5854static int
5855ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
5856{
5857#define IS_RUNNING(ifp) \
5858 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
5859 struct ath_softc *sc = ifp->if_softc;
5860 struct ieee80211com *ic = ifp->if_l2com;
5861 struct ifreq *ifr = (struct ifreq *)data;
5862 const HAL_RATE_TABLE *rt;
5863 int error = 0;
5864
5865 switch (cmd) {
5866 case SIOCSIFFLAGS:
5867 ATH_LOCK(sc);
5868 if (IS_RUNNING(ifp)) {
5869 /*
5870 * To avoid rescanning another access point,
5871 * do not call ath_init() here. Instead,
5872 * only reflect promisc mode settings.
5873 */
5874 ath_mode_init(sc);
5875 } else if (ifp->if_flags & IFF_UP) {
5876 /*
5877 * Beware of being called during attach/detach
5878 * to reset promiscuous mode. In that case we
5879 * will still be marked UP but not RUNNING.
5880 * However trying to re-init the interface
5881 * is the wrong thing to do as we've already
5882 * torn down much of our state. There's
5883 * probably a better way to deal with this.
5884 */
5885 if (!sc->sc_invalid)
5886 ath_init(sc); /* XXX lose error */
5887 } else {
5888 ath_stop_locked(ifp);
5889#ifdef notyet
5890 /* XXX must wakeup in places like ath_vap_delete */
5891 if (!sc->sc_invalid)
5892 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP);
5893#endif
5894 }
5895 ATH_UNLOCK(sc);
5896 break;
5897 case SIOCGIFMEDIA:
5898 case SIOCSIFMEDIA:
5899 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
5900 break;
5901 case SIOCGATHSTATS:
5902 /* NB: embed these numbers to get a consistent view */
5903 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
5904 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
5905 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi);
5906 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi);
5907#ifdef IEEE80211_SUPPORT_TDMA
5908 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap);
5909 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam);
5910#endif
5911 rt = sc->sc_currates;
5912 sc->sc_stats.ast_tx_rate =
5913 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC;
5914 if (rt->info[sc->sc_txrix].phy & IEEE80211_T_HT)
5915 sc->sc_stats.ast_tx_rate |= IEEE80211_RATE_MCS;
5916 return copyout(&sc->sc_stats,
5917 ifr->ifr_data, sizeof (sc->sc_stats));
5918 case SIOCGATHAGSTATS:
5919 return copyout(&sc->sc_aggr_stats,
5920 ifr->ifr_data, sizeof (sc->sc_aggr_stats));
5921 case SIOCZATHSTATS:
5922 error = priv_check(curthread, PRIV_DRIVER);
5923 if (error == 0) {
5924 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats));
5925 memset(&sc->sc_aggr_stats, 0,
5926 sizeof(sc->sc_aggr_stats));
5927 memset(&sc->sc_intr_stats, 0,
5928 sizeof(sc->sc_intr_stats));
5929 }
5930 break;
5931#ifdef ATH_DIAGAPI
5932 case SIOCGATHDIAG:
5933 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr);
5934 break;
5935 case SIOCGATHPHYERR:
5936 error = ath_ioctl_phyerr(sc,(struct ath_diag*) ifr);
5937 break;
5938#endif
5939 case SIOCGATHSPECTRAL:
5940 error = ath_ioctl_spectral(sc,(struct ath_diag*) ifr);
5941 break;
5942 case SIOCGATHNODERATESTATS:
5943 error = ath_ioctl_ratestats(sc, (struct ath_rateioctl *) ifr);
5944 break;
5945 case SIOCGIFADDR:
5946 error = ether_ioctl(ifp, cmd, data);
5947 break;
5948 default:
5949 error = EINVAL;
5950 break;
5951 }
5952 return error;
5953#undef IS_RUNNING
5954}
5955
5956/*
5957 * Announce various information on device/driver attach.
5958 */
5959static void
5960ath_announce(struct ath_softc *sc)
5961{
5962 struct ifnet *ifp = sc->sc_ifp;
5963 struct ath_hal *ah = sc->sc_ah;
5964
5965 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n",
5966 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev,
5967 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
5968 if_printf(ifp, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n",
5969 ah->ah_analog2GhzRev, ah->ah_analog5GhzRev);
5970 if (bootverbose) {
5971 int i;
5972 for (i = 0; i <= WME_AC_VO; i++) {
5973 struct ath_txq *txq = sc->sc_ac2q[i];
5974 if_printf(ifp, "Use hw queue %u for %s traffic\n",
5975 txq->axq_qnum, ieee80211_wme_acnames[i]);
5976 }
5977 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
5978 sc->sc_cabq->axq_qnum);
5979 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
5980 }
5981 if (ath_rxbuf != ATH_RXBUF)
5982 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
5983 if (ath_txbuf != ATH_TXBUF)
5984 if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
5985 if (sc->sc_mcastkey && bootverbose)
5986 if_printf(ifp, "using multicast key search\n");
5987}
5988
5989static void
5990ath_dfs_tasklet(void *p, int npending)
5991{
5992 struct ath_softc *sc = (struct ath_softc *) p;
5993 struct ifnet *ifp = sc->sc_ifp;
5994 struct ieee80211com *ic = ifp->if_l2com;
5995
5996 /*
5997 * If previous processing has found a radar event,
5998 * signal this to the net80211 layer to begin DFS
5999 * processing.
6000 */
6001 if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) {
6002 /* DFS event found, initiate channel change */
6003 /*
6004 * XXX doesn't currently tell us whether the event
6005 * XXX was found in the primary or extension
6006 * XXX channel!
6007 */
6008 IEEE80211_LOCK(ic);
6009 ieee80211_dfs_notify_radar(ic, sc->sc_curchan);
6010 IEEE80211_UNLOCK(ic);
6011 }
6012}
6013
6014/*
6015 * Enable/disable power save. This must be called with
6016 * no TX driver locks currently held, so it should only
6017 * be called from the RX path (which doesn't hold any
6018 * TX driver locks.)
6019 */
6020static void
6021ath_node_powersave(struct ieee80211_node *ni, int enable)
6022{
6023#ifdef ATH_SW_PSQ
6024 struct ath_node *an = ATH_NODE(ni);
6025 struct ieee80211com *ic = ni->ni_ic;
6026 struct ath_softc *sc = ic->ic_ifp->if_softc;
6027 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6028
6029 /* XXX and no TXQ locks should be held here */
6030
6031 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, "%s: %6D: enable=%d\n",
6032 __func__,
6033 ni->ni_macaddr,
6034 ":",
6035 !! enable);
6036
6037 /* Suspend or resume software queue handling */
6038 if (enable)
6039 ath_tx_node_sleep(sc, an);
6040 else
6041 ath_tx_node_wakeup(sc, an);
6042
6043 /* Update net80211 state */
6044 avp->av_node_ps(ni, enable);
6045#else
6046 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6047
6048 /* Update net80211 state */
6049 avp->av_node_ps(ni, enable);
6050#endif/* ATH_SW_PSQ */
6051}
6052
6053/*
6054 * Notification from net80211 that the powersave queue state has
6055 * changed.
6056 *
6057 * Since the software queue also may have some frames:
6058 *
6059 * + if the node software queue has frames and the TID state
6060 * is 0, we set the TIM;
6061 * + if the node and the stack are both empty, we clear the TIM bit.
6062 * + If the stack tries to set the bit, always set it.
6063 * + If the stack tries to clear the bit, only clear it if the
6064 * software queue in question is also cleared.
6065 *
6066 * TODO: this is called during node teardown; so let's ensure this
6067 * is all correctly handled and that the TIM bit is cleared.
6068 * It may be that the node flush is called _AFTER_ the net80211
6069 * stack clears the TIM.
6070 *
6071 * Here is the racy part. Since it's possible >1 concurrent,
6072 * overlapping TXes will appear complete with a TX completion in
6073 * another thread, it's possible that the concurrent TIM calls will
6074 * clash. We can't hold the node lock here because setting the
6075 * TIM grabs the net80211 comlock and this may cause a LOR.
6076 * The solution is either to totally serialise _everything_ at
6077 * this point (ie, all TX, completion and any reset/flush go into
6078 * one taskqueue) or a new "ath TIM lock" needs to be created that
6079 * just wraps the driver state change and this call to avp->av_set_tim().
6080 *
6081 * The same race exists in the net80211 power save queue handling
6082 * as well. Since multiple transmitting threads may queue frames
6083 * into the driver, as well as ps-poll and the driver transmitting
6084 * frames (and thus clearing the psq), it's quite possible that
6085 * a packet entering the PSQ and a ps-poll being handled will
6086 * race, causing the TIM to be cleared and not re-set.
6087 */
6088static int
6089ath_node_set_tim(struct ieee80211_node *ni, int enable)
6090{
6091#ifdef ATH_SW_PSQ
6092 struct ieee80211com *ic = ni->ni_ic;
6093 struct ath_softc *sc = ic->ic_ifp->if_softc;
6094 struct ath_node *an = ATH_NODE(ni);
6095 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6096 int changed = 0;
6097
6098 ATH_TX_LOCK(sc);
6099 an->an_stack_psq = enable;
6100
6101 /*
6102 * This will get called for all operating modes,
6103 * even if avp->av_set_tim is unset.
6104 * It's currently set for hostap/ibss modes; but
6105 * the same infrastructure is used for both STA
6106 * and AP/IBSS node power save.
6107 */
6108 if (avp->av_set_tim == NULL) {
6109 ATH_TX_UNLOCK(sc);
6110 return (0);
6111 }
6112
6113 /*
6114 * If setting the bit, always set it here.
6115 * If clearing the bit, only clear it if the
6116 * software queue is also empty.
6117 *
6118 * If the node has left power save, just clear the TIM
6119 * bit regardless of the state of the power save queue.
6120 *
6121 * XXX TODO: although atomics are used, it's quite possible
6122 * that a race will occur between this and setting/clearing
6123 * in another thread. TX completion will occur always in
6124 * one thread, however setting/clearing the TIM bit can come
6125 * from a variety of different process contexts!
6126 */
6127 if (enable && an->an_tim_set == 1) {
6128 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6129 "%s: %6D: enable=%d, tim_set=1, ignoring\n",
6130 __func__,
6131 ni->ni_macaddr,
6132 ":",
6133 enable);
6134 ATH_TX_UNLOCK(sc);
6135 } else if (enable) {
6136 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6137 "%s: %6D: enable=%d, enabling TIM\n",
6138 __func__,
6139 ni->ni_macaddr,
6140 ":",
6141 enable);
6142 an->an_tim_set = 1;
6143 ATH_TX_UNLOCK(sc);
6144 changed = avp->av_set_tim(ni, enable);
6145 } else if (an->an_swq_depth == 0) {
6146 /* disable */
6147 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6148 "%s: %6D: enable=%d, an_swq_depth == 0, disabling\n",
6149 __func__,
6150 ni->ni_macaddr,
6151 ":",
6152 enable);
6153 an->an_tim_set = 0;
6154 ATH_TX_UNLOCK(sc);
6155 changed = avp->av_set_tim(ni, enable);
6156 } else if (! an->an_is_powersave) {
6157 /*
6158 * disable regardless; the node isn't in powersave now
6159 */
6160 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6161 "%s: %6D: enable=%d, an_pwrsave=0, disabling\n",
6162 __func__,
6163 ni->ni_macaddr,
6164 ":",
6165 enable);
6166 an->an_tim_set = 0;
6167 ATH_TX_UNLOCK(sc);
6168 changed = avp->av_set_tim(ni, enable);
6169 } else {
6170 /*
6171 * psq disable, node is currently in powersave, node
6172 * software queue isn't empty, so don't clear the TIM bit
6173 * for now.
6174 */
6175 ATH_TX_UNLOCK(sc);
6176 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6177 "%s: %6D: enable=%d, an_swq_depth > 0, ignoring\n",
6178 __func__,
6179 ni->ni_macaddr,
6180 ":",
6181 enable);
6182 changed = 0;
6183 }
6184
6185 return (changed);
6186#else
6187 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6188
6189 /*
6190 * Some operating modes don't set av_set_tim(), so don't
6191 * update it here.
6192 */
6193 if (avp->av_set_tim == NULL)
6194 return (0);
6195
6196 return (avp->av_set_tim(ni, enable));
6197#endif /* ATH_SW_PSQ */
6198}
6199
6200/*
6201 * Set or update the TIM from the software queue.
6202 *
6203 * Check the software queue depth before attempting to do lock
6204 * anything; that avoids trying to obtain the lock. Then,
6205 * re-check afterwards to ensure nothing has changed in the
6206 * meantime.
6207 *
6208 * set: This is designed to be called from the TX path, after
6209 * a frame has been queued; to see if the swq > 0.
6210 *
6211 * clear: This is designed to be called from the buffer completion point
6212 * (right now it's ath_tx_default_comp()) where the state of
6213 * a software queue has changed.
6214 *
6215 * It makes sense to place it at buffer free / completion rather
6216 * than after each software queue operation, as there's no real
6217 * point in churning the TIM bit as the last frames in the software
6218 * queue are transmitted. If they fail and we retry them, we'd
6219 * just be setting the TIM bit again anyway.
6220 */
6221void
6222ath_tx_update_tim(struct ath_softc *sc, struct ieee80211_node *ni,
6223 int enable)
6224{
6225#ifdef ATH_SW_PSQ
6226 struct ath_node *an;
6227 struct ath_vap *avp;
6228
6229 /* Don't do this for broadcast/etc frames */
6230 if (ni == NULL)
6231 return;
6232
6233 an = ATH_NODE(ni);
6234 avp = ATH_VAP(ni->ni_vap);
6235
6236 /*
6237 * And for operating modes without the TIM handler set, let's
6238 * just skip those.
6239 */
6240 if (avp->av_set_tim == NULL)
6241 return;
6242
6243 ATH_TX_LOCK_ASSERT(sc);
6244
6245 if (enable) {
6246 if (an->an_is_powersave &&
6247 an->an_tim_set == 0 &&
6248 an->an_swq_depth != 0) {
6249 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6250 "%s: %6D: swq_depth>0, tim_set=0, set!\n",
6251 __func__,
6252 ni->ni_macaddr,
6253 ":");
6254 an->an_tim_set = 1;
6255 (void) avp->av_set_tim(ni, 1);
6256 }
6257 } else {
6258 /*
6259 * Don't bother grabbing the lock unless the queue is empty.
6260 */
6261 if (&an->an_swq_depth != 0)
6262 return;
6263
6264 if (an->an_is_powersave &&
6265 an->an_stack_psq == 0 &&
6266 an->an_tim_set == 1 &&
6267 an->an_swq_depth == 0) {
6268 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6269 "%s: %6D: swq_depth=0, tim_set=1, psq_set=0,"
6270 " clear!\n",
6271 __func__,
6272 ni->ni_macaddr,
6273 ":");
6274 an->an_tim_set = 0;
6275 (void) avp->av_set_tim(ni, 0);
6276 }
6277 }
6278#else
6279 return;
6280#endif /* ATH_SW_PSQ */
6281}
6282
6283/*
6284 * Received a ps-poll frame from net80211.
6285 *
6286 * Here we get a chance to serve out a software-queued frame ourselves
6287 * before we punt it to net80211 to transmit us one itself - either
6288 * because there's traffic in the net80211 psq, or a NULL frame to
6289 * indicate there's nothing else.
6290 */
6291static void
6292ath_node_recv_pspoll(struct ieee80211_node *ni, struct mbuf *m)
6293{
6294#ifdef ATH_SW_PSQ
6295 struct ath_node *an;
6296 struct ath_vap *avp;
6297 struct ieee80211com *ic = ni->ni_ic;
6298 struct ath_softc *sc = ic->ic_ifp->if_softc;
6299 int tid;
6300
6301 /* Just paranoia */
6302 if (ni == NULL)
6303 return;
6304
6305 /*
6306 * Unassociated (temporary node) station.
6307 */
6308 if (ni->ni_associd == 0)
6309 return;
6310
6311 /*
6312 * We do have an active node, so let's begin looking into it.
6313 */
6314 an = ATH_NODE(ni);
6315 avp = ATH_VAP(ni->ni_vap);
6316
6317 /*
6318 * For now, we just call the original ps-poll method.
6319 * Once we're ready to flip this on:
6320 *
6321 * + Set leak to 1, as no matter what we're going to have
6322 * to send a frame;
6323 * + Check the software queue and if there's something in it,
6324 * schedule the highest TID thas has traffic from this node.
6325 * Then make sure we schedule the software scheduler to
6326 * run so it picks up said frame.
6327 *
6328 * That way whatever happens, we'll at least send _a_ frame
6329 * to the given node.
6330 *
6331 * Again, yes, it's crappy QoS if the node has multiple
6332 * TIDs worth of traffic - but let's get it working first
6333 * before we optimise it.
6334 *
6335 * Also yes, there's definitely latency here - we're not
6336 * direct dispatching to the hardware in this path (and
6337 * we're likely being called from the packet receive path,
6338 * so going back into TX may be a little hairy!) but again
6339 * I'd like to get this working first before optimising
6340 * turn-around time.
6341 */
6342
6343 ATH_TX_LOCK(sc);
6344
6345 /*
6346 * Legacy - we're called and the node isn't asleep.
6347 * Immediately punt.
6348 */
6349 if (! an->an_is_powersave) {
6350 device_printf(sc->sc_dev,
6351 "%s: %6D: not in powersave?\n",
6352 __func__,
6353 ni->ni_macaddr,
6354 ":");
6355 ATH_TX_UNLOCK(sc);
6356 avp->av_recv_pspoll(ni, m);
6357 return;
6358 }
6359
6360 /*
6361 * We're in powersave.
6362 *
6363 * Leak a frame.
6364 */
6365 an->an_leak_count = 1;
6366
6367 /*
6368 * Now, if there's no frames in the node, just punt to
6369 * recv_pspoll.
6370 *
6371 * Don't bother checking if the TIM bit is set, we really
6372 * only care if there are any frames here!
6373 */
6374 if (an->an_swq_depth == 0) {
6375 ATH_TX_UNLOCK(sc);
6376 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6377 "%s: %6D: SWQ empty; punting to net80211\n",
6378 __func__,
6379 ni->ni_macaddr,
6380 ":");
6381 avp->av_recv_pspoll(ni, m);
6382 return;
6383 }
6384
6385 /*
6386 * Ok, let's schedule the highest TID that has traffic
6387 * and then schedule something.
6388 */
6389 for (tid = IEEE80211_TID_SIZE - 1; tid >= 0; tid--) {
6390 struct ath_tid *atid = &an->an_tid[tid];
6391 /*
6392 * No frames? Skip.
6393 */
6394 if (atid->axq_depth == 0)
6395 continue;
6396 ath_tx_tid_sched(sc, atid);
6397 /*
6398 * XXX we could do a direct call to the TXQ
6399 * scheduler code here to optimise latency
6400 * at the expense of a REALLY deep callstack.
6401 */
6402 ATH_TX_UNLOCK(sc);
6403 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask);
6404 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6405 "%s: %6D: leaking frame to TID %d\n",
6406 __func__,
6407 ni->ni_macaddr,
6408 ":",
6409 tid);
6410 return;
6411 }
6412
6413 ATH_TX_UNLOCK(sc);
6414
6415 /*
6416 * XXX nothing in the TIDs at this point? Eek.
6417 */
6418 device_printf(sc->sc_dev, "%s: %6D: TIDs empty, but ath_node showed traffic?!\n",
6419 __func__,
6420 ni->ni_macaddr,
6421 ":");
6422 avp->av_recv_pspoll(ni, m);
6423#else
6424 avp->av_recv_pspoll(ni, m);
6425#endif /* ATH_SW_PSQ */
6426}
6427
6428MODULE_VERSION(if_ath, 1);
6429MODULE_DEPEND(if_ath, wlan, 1, 1, 1); /* 802.11 media layer */
6430#if defined(IEEE80211_ALQ) || defined(AH_DEBUG_ALQ)
6431MODULE_DEPEND(if_ath, alq, 1, 1, 1);
6432#endif
|