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acpi_cpu.c (166184) acpi_cpu.c (167814)
1/*-
2 * Copyright (c) 2003-2005 Nate Lawson (SDG)
3 * Copyright (c) 2001 Michael Smith
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2003-2005 Nate Lawson (SDG)
3 * Copyright (c) 2001 Michael Smith
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_cpu.c 166184 2007-01-23 07:20:44Z njl $");
29__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_cpu.c 167814 2007-03-22 18:16:43Z jkim $");
30
31#include "opt_acpi.h"
32#include <sys/param.h>
33#include <sys/bus.h>
34#include <sys/cpu.h>
35#include <sys/kernel.h>
36#include <sys/malloc.h>
37#include <sys/module.h>

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270 sc = device_get_softc(dev);
271 sc->cpu_dev = dev;
272 sc->cpu_handle = acpi_get_handle(dev);
273 cpu_id = acpi_get_magic(dev);
274 cpu_softc[cpu_id] = sc;
275 pcpu_data = pcpu_find(cpu_id);
276 pcpu_data->pc_device = dev;
277 sc->cpu_pcpu = pcpu_data;
30
31#include "opt_acpi.h"
32#include <sys/param.h>
33#include <sys/bus.h>
34#include <sys/cpu.h>
35#include <sys/kernel.h>
36#include <sys/malloc.h>
37#include <sys/module.h>

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270 sc = device_get_softc(dev);
271 sc->cpu_dev = dev;
272 sc->cpu_handle = acpi_get_handle(dev);
273 cpu_id = acpi_get_magic(dev);
274 cpu_softc[cpu_id] = sc;
275 pcpu_data = pcpu_find(cpu_id);
276 pcpu_data->pc_device = dev;
277 sc->cpu_pcpu = pcpu_data;
278 cpu_smi_cmd = AcpiGbl_FADT->SmiCmd;
279 cpu_cst_cnt = AcpiGbl_FADT->CstCnt;
278 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand;
279 cpu_cst_cnt = AcpiGbl_FADT.CstControl;
280
281 buf.Pointer = NULL;
282 buf.Length = ACPI_ALLOCATE_BUFFER;
283 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf);
284 if (ACPI_FAILURE(status)) {
285 device_printf(dev, "attach failed to get Processor obj - %s\n",
286 AcpiFormatException(status));
287 return (ENXIO);

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305 /* Install hw.acpi.cpu sysctl tree */
306 acpi_sc = acpi_device_get_parent_softc(dev);
307 sysctl_ctx_init(&cpu_sysctl_ctx);
308 cpu_sysctl_tree = SYSCTL_ADD_NODE(&cpu_sysctl_ctx,
309 SYSCTL_CHILDREN(acpi_sc->acpi_sysctl_tree), OID_AUTO, "cpu",
310 CTLFLAG_RD, 0, "node for CPU children");
311
312 /* Queue post cpu-probing task handler */
280
281 buf.Pointer = NULL;
282 buf.Length = ACPI_ALLOCATE_BUFFER;
283 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf);
284 if (ACPI_FAILURE(status)) {
285 device_printf(dev, "attach failed to get Processor obj - %s\n",
286 AcpiFormatException(status));
287 return (ENXIO);

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305 /* Install hw.acpi.cpu sysctl tree */
306 acpi_sc = acpi_device_get_parent_softc(dev);
307 sysctl_ctx_init(&cpu_sysctl_ctx);
308 cpu_sysctl_tree = SYSCTL_ADD_NODE(&cpu_sysctl_ctx,
309 SYSCTL_CHILDREN(acpi_sc->acpi_sysctl_tree), OID_AUTO, "cpu",
310 CTLFLAG_RD, 0, "node for CPU children");
311
312 /* Queue post cpu-probing task handler */
313 AcpiOsQueueForExecution(OSD_PRIORITY_LO, acpi_cpu_startup, NULL);
313 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL);
314 }
315
316 /*
317 * Before calling any CPU methods, collect child driver feature hints
318 * and notify ACPI of them. We support unified SMP power control
319 * so advertise this ourselves. Note this is not the same as independent
320 * SMP control where each CPU can have different settings.
321 */

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513 * take 5 as C2. Some may also have a value of 7 to indicate
514 * another C3 but most use _CST for this (as required) and having
515 * "only" C1-C3 is not a hardship.
516 */
517 if (sc->cpu_p_blk_len < 5)
518 return;
519
520 /* Validate and allocate resources for C2 (P_LVL2). */
314 }
315
316 /*
317 * Before calling any CPU methods, collect child driver feature hints
318 * and notify ACPI of them. We support unified SMP power control
319 * so advertise this ourselves. Note this is not the same as independent
320 * SMP control where each CPU can have different settings.
321 */

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513 * take 5 as C2. Some may also have a value of 7 to indicate
514 * another C3 but most use _CST for this (as required) and having
515 * "only" C1-C3 is not a hardship.
516 */
517 if (sc->cpu_p_blk_len < 5)
518 return;
519
520 /* Validate and allocate resources for C2 (P_LVL2). */
521 gas.AddressSpaceId = ACPI_ADR_SPACE_SYSTEM_IO;
522 gas.RegisterBitWidth = 8;
523 if (AcpiGbl_FADT->Plvl2Lat <= 100) {
521 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO;
522 gas.BitWidth = 8;
523 if (AcpiGbl_FADT.C2Latency <= 100) {
524 gas.Address = sc->cpu_p_blk + 4;
525 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &sc->cpu_rid,
526 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE);
527 if (cx_ptr->p_lvlx != NULL) {
528 sc->cpu_rid++;
529 cx_ptr->type = ACPI_STATE_C2;
524 gas.Address = sc->cpu_p_blk + 4;
525 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &sc->cpu_rid,
526 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE);
527 if (cx_ptr->p_lvlx != NULL) {
528 sc->cpu_rid++;
529 cx_ptr->type = ACPI_STATE_C2;
530 cx_ptr->trans_lat = AcpiGbl_FADT->Plvl2Lat;
530 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency;
531 cx_ptr++;
532 sc->cpu_cx_count++;
533 }
534 }
535 if (sc->cpu_p_blk_len < 6)
536 return;
537
538 /* Validate and allocate resources for C3 (P_LVL3). */
531 cx_ptr++;
532 sc->cpu_cx_count++;
533 }
534 }
535 if (sc->cpu_p_blk_len < 6)
536 return;
537
538 /* Validate and allocate resources for C3 (P_LVL3). */
539 if (AcpiGbl_FADT->Plvl3Lat <= 1000) {
539 if (AcpiGbl_FADT.C3Latency <= 1000) {
540 gas.Address = sc->cpu_p_blk + 5;
541 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &sc->cpu_rid, &gas,
542 &cx_ptr->p_lvlx, RF_SHAREABLE);
543 if (cx_ptr->p_lvlx != NULL) {
544 sc->cpu_rid++;
545 cx_ptr->type = ACPI_STATE_C3;
540 gas.Address = sc->cpu_p_blk + 5;
541 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &sc->cpu_rid, &gas,
542 &cx_ptr->p_lvlx, RF_SHAREABLE);
543 if (cx_ptr->p_lvlx != NULL) {
544 sc->cpu_rid++;
545 cx_ptr->type = ACPI_STATE_C3;
546 cx_ptr->trans_lat = AcpiGbl_FADT->Plvl3Lat;
546 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency;
547 cx_ptr++;
548 sc->cpu_cx_count++;
549 }
550 }
551
552 /* Update the largest cx_count seen so far */
553 if (sc->cpu_cx_count > cpu_cx_count)
554 cpu_cx_count = sc->cpu_cx_count;

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858
859 /*
860 * Check for bus master activity. If there was activity, clear
861 * the bit and use the lowest non-C3 state. Note that the USB
862 * driver polling for new devices keeps this bit set all the
863 * time if USB is loaded.
864 */
865 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
547 cx_ptr++;
548 sc->cpu_cx_count++;
549 }
550 }
551
552 /* Update the largest cx_count seen so far */
553 if (sc->cpu_cx_count > cpu_cx_count)
554 cpu_cx_count = sc->cpu_cx_count;

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858
859 /*
860 * Check for bus master activity. If there was activity, clear
861 * the bit and use the lowest non-C3 state. Note that the USB
862 * driver polling for new devices keeps this bit set all the
863 * time if USB is loaded.
864 */
865 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
866 AcpiGetRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active,
867 ACPI_MTX_DO_NOT_LOCK);
866 AcpiGetRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active);
868 if (bm_active != 0) {
867 if (bm_active != 0) {
869 AcpiSetRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1,
870 ACPI_MTX_DO_NOT_LOCK);
868 AcpiSetRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1);
871 cx_next_idx = min(cx_next_idx, sc->cpu_non_c3);
872 }
873 }
874
875 /* Select the next state and update statistics. */
876 cx_next = &sc->cpu_cx_states[cx_next_idx];
877 sc->cpu_cx_stats[cx_next_idx]++;
878 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep"));

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889 }
890
891 /*
892 * For C3, disable bus master arbitration and enable bus master wake
893 * if BM control is available, otherwise flush the CPU cache.
894 */
895 if (cx_next->type == ACPI_STATE_C3) {
896 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
869 cx_next_idx = min(cx_next_idx, sc->cpu_non_c3);
870 }
871 }
872
873 /* Select the next state and update statistics. */
874 cx_next = &sc->cpu_cx_states[cx_next_idx];
875 sc->cpu_cx_stats[cx_next_idx]++;
876 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep"));

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887 }
888
889 /*
890 * For C3, disable bus master arbitration and enable bus master wake
891 * if BM control is available, otherwise flush the CPU cache.
892 */
893 if (cx_next->type == ACPI_STATE_C3) {
894 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
897 AcpiSetRegister(ACPI_BITREG_ARB_DISABLE, 1, ACPI_MTX_DO_NOT_LOCK);
898 AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 1,
899 ACPI_MTX_DO_NOT_LOCK);
895 AcpiSetRegister(ACPI_BITREG_ARB_DISABLE, 1);
896 AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 1);
900 } else
901 ACPI_FLUSH_CPU_CACHE();
902 }
903
904 /*
905 * Read from P_LVLx to enter C2(+), checking time spent asleep.
906 * Use the ACPI timer for measuring sleep time. Since we need to
907 * get the time very close to the CPU start/stop clock logic, this
908 * is the only reliable time source.
909 */
897 } else
898 ACPI_FLUSH_CPU_CACHE();
899 }
900
901 /*
902 * Read from P_LVLx to enter C2(+), checking time spent asleep.
903 * Use the ACPI timer for measuring sleep time. Since we need to
904 * get the time very close to the CPU start/stop clock logic, this
905 * is the only reliable time source.
906 */
910 AcpiHwLowLevelRead(32, &start_time, &AcpiGbl_FADT->XPmTmrBlk);
907 AcpiHwLowLevelRead(32, &start_time, &AcpiGbl_FADT.XPmTimerBlock);
911 CPU_GET_REG(cx_next->p_lvlx, 1);
912
913 /*
914 * Read the end time twice. Since it may take an arbitrary time
915 * to enter the idle state, the first read may be executed before
916 * the processor has stopped. Doing it again provides enough
917 * margin that we are certain to have a correct value.
918 */
908 CPU_GET_REG(cx_next->p_lvlx, 1);
909
910 /*
911 * Read the end time twice. Since it may take an arbitrary time
912 * to enter the idle state, the first read may be executed before
913 * the processor has stopped. Doing it again provides enough
914 * margin that we are certain to have a correct value.
915 */
919 AcpiHwLowLevelRead(32, &end_time, &AcpiGbl_FADT->XPmTmrBlk);
920 AcpiHwLowLevelRead(32, &end_time, &AcpiGbl_FADT->XPmTmrBlk);
916 AcpiHwLowLevelRead(32, &end_time, &AcpiGbl_FADT.XPmTimerBlock);
917 AcpiHwLowLevelRead(32, &end_time, &AcpiGbl_FADT.XPmTimerBlock);
921
922 /* Enable bus master arbitration and disable bus master wakeup. */
923 if (cx_next->type == ACPI_STATE_C3 &&
924 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
918
919 /* Enable bus master arbitration and disable bus master wakeup. */
920 if (cx_next->type == ACPI_STATE_C3 &&
921 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
925 AcpiSetRegister(ACPI_BITREG_ARB_DISABLE, 0, ACPI_MTX_DO_NOT_LOCK);
926 AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 0, ACPI_MTX_DO_NOT_LOCK);
922 AcpiSetRegister(ACPI_BITREG_ARB_DISABLE, 0);
923 AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
927 }
928 ACPI_ENABLE_IRQS();
929
930 /* Find the actual time asleep in microseconds, minus overhead. */
931 end_time = acpi_TimerDelta(end_time, start_time);
932 sc->cpu_prev_sleep = PM_USEC(end_time) - cx_next->trans_lat;
933}
934

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957 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
958
959 /*
960 * Bus mastering arbitration control is needed to keep caches coherent
961 * while sleeping in C3. If it's not present but a working flush cache
962 * instruction is present, flush the caches before entering C3 instead.
963 * Otherwise, just disable C3 completely.
964 */
924 }
925 ACPI_ENABLE_IRQS();
926
927 /* Find the actual time asleep in microseconds, minus overhead. */
928 end_time = acpi_TimerDelta(end_time, start_time);
929 sc->cpu_prev_sleep = PM_USEC(end_time) - cx_next->trans_lat;
930}
931

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954 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
955
956 /*
957 * Bus mastering arbitration control is needed to keep caches coherent
958 * while sleeping in C3. If it's not present but a working flush cache
959 * instruction is present, flush the caches before entering C3 instead.
960 * Otherwise, just disable C3 completely.
961 */
965 if (AcpiGbl_FADT->V1_Pm2CntBlk == 0 || AcpiGbl_FADT->Pm2CntLen == 0) {
966 if (AcpiGbl_FADT->WbInvd && AcpiGbl_FADT->WbInvdFlush == 0) {
962 if (AcpiGbl_FADT.Pm2ControlBlock == 0 ||
963 AcpiGbl_FADT.Pm2ControlLength == 0) {
964 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) &&
965 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) {
967 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
968 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
969 "acpi_cpu: no BM control, using flush cache method\n"));
970 } else {
971 cpu_quirks |= CPU_QUIRK_NO_C3;
972 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
973 "acpi_cpu: no BM control, C3 not available\n"));
974 }

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966 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
967 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
968 "acpi_cpu: no BM control, using flush cache method\n"));
969 } else {
970 cpu_quirks |= CPU_QUIRK_NO_C3;
971 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
972 "acpi_cpu: no BM control, C3 not available\n"));
973 }

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