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mpcore_timer.c (269605) mpcore_timer.c (271906)
1/*-
2 * Copyright (c) 2011 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * Developed by Ben Gray <ben.r.gray@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 29 unchanged lines hidden (view full) ---

38 * The timecount timer uses the global 64-bit counter, whereas the
39 * per-CPU eventtimer uses the private 32-bit counters.
40 *
41 *
42 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2)
43 */
44
45#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2011 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * Developed by Ben Gray <ben.r.gray@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 29 unchanged lines hidden (view full) ---

38 * The timecount timer uses the global 64-bit counter, whereas the
39 * per-CPU eventtimer uses the private 32-bit counters.
40 *
41 *
42 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2)
43 */
44
45#include <sys/cdefs.h>
46__FBSDID("$FreeBSD: head/sys/arm/arm/mpcore_timer.c 269605 2014-08-05 18:51:51Z ian $");
46__FBSDID("$FreeBSD: head/sys/arm/arm/mpcore_timer.c 271906 2014-09-20 14:49:21Z ian $");
47
48#include <sys/param.h>
49#include <sys/systm.h>
50#include <sys/bus.h>
51#include <sys/kernel.h>
52#include <sys/module.h>
53#include <sys/malloc.h>
54#include <sys/rman.h>

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92#define GBL_TIMER_CTRL_AUTO_INC (1UL << 3)
93#define GBL_TIMER_CTRL_IRQ_ENABLE (1UL << 2)
94#define GBL_TIMER_CTRL_COMP_ENABLE (1UL << 1)
95#define GBL_TIMER_CTRL_TIMER_ENABLE (1UL << 0)
96
97#define GBL_TIMER_INTR_EVENT (1UL << 0)
98
99struct arm_tmr_softc {
47
48#include <sys/param.h>
49#include <sys/systm.h>
50#include <sys/bus.h>
51#include <sys/kernel.h>
52#include <sys/module.h>
53#include <sys/malloc.h>
54#include <sys/rman.h>

--- 37 unchanged lines hidden (view full) ---

92#define GBL_TIMER_CTRL_AUTO_INC (1UL << 3)
93#define GBL_TIMER_CTRL_IRQ_ENABLE (1UL << 2)
94#define GBL_TIMER_CTRL_COMP_ENABLE (1UL << 1)
95#define GBL_TIMER_CTRL_TIMER_ENABLE (1UL << 0)
96
97#define GBL_TIMER_INTR_EVENT (1UL << 0)
98
99struct arm_tmr_softc {
100 struct resource * tmr_res[4];
101 bus_space_tag_t prv_bst;
102 bus_space_tag_t gbl_bst;
103 bus_space_handle_t prv_bsh;
104 bus_space_handle_t gbl_bsh;
100 device_t dev;
101 int irqrid;
102 int memrid;
103 struct resource * gbl_mem;
104 struct resource * prv_mem;
105 struct resource * prv_irq;
105 uint64_t clkfreq;
106 struct eventtimer et;
107};
108
106 uint64_t clkfreq;
107 struct eventtimer et;
108};
109
109static struct resource_spec arm_tmr_spec[] = {
110 { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Global registers */
111 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Global timer interrupt (unused) */
112 { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* Private (per-CPU) registers */
113 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Private timer interrupt */
114 { -1, 0 }
115};
110static struct eventtimer *arm_tmr_et;
111static struct timecounter *arm_tmr_tc;
112static uint64_t arm_tmr_freq;
113static boolean_t arm_tmr_freq_varies;
116
114
117static struct arm_tmr_softc *arm_tmr_sc = NULL;
115#define tmr_prv_read_4(sc, reg) bus_read_4((sc)->prv_mem, reg)
116#define tmr_prv_write_4(sc, reg, val) bus_write_4((sc)->prv_mem, reg, val)
117#define tmr_gbl_read_4(sc, reg) bus_read_4((sc)->gbl_mem, reg)
118#define tmr_gbl_write_4(sc, reg, val) bus_write_4((sc)->gbl_mem, reg, val)
118
119
119static uint64_t platform_arm_tmr_freq = 0;
120
121#define tmr_prv_read_4(reg) \
122 bus_space_read_4(arm_tmr_sc->prv_bst, arm_tmr_sc->prv_bsh, reg)
123#define tmr_prv_write_4(reg, val) \
124 bus_space_write_4(arm_tmr_sc->prv_bst, arm_tmr_sc->prv_bsh, reg, val)
125#define tmr_gbl_read_4(reg) \
126 bus_space_read_4(arm_tmr_sc->gbl_bst, arm_tmr_sc->gbl_bsh, reg)
127#define tmr_gbl_write_4(reg, val) \
128 bus_space_write_4(arm_tmr_sc->gbl_bst, arm_tmr_sc->gbl_bsh, reg, val)
129
130
131static timecounter_get_t arm_tmr_get_timecount;
132
133static struct timecounter arm_tmr_timecount = {
134 .tc_name = "MPCore",
135 .tc_get_timecount = arm_tmr_get_timecount,
136 .tc_poll_pps = NULL,
137 .tc_counter_mask = ~0u,
138 .tc_frequency = 0,
139 .tc_quality = 800,
140};
141
120static timecounter_get_t arm_tmr_get_timecount;
121
122static struct timecounter arm_tmr_timecount = {
123 .tc_name = "MPCore",
124 .tc_get_timecount = arm_tmr_get_timecount,
125 .tc_poll_pps = NULL,
126 .tc_counter_mask = ~0u,
127 .tc_frequency = 0,
128 .tc_quality = 800,
129};
130
131#define TMR_GBL 0x01
132#define TMR_PRV 0x02
133#define TMR_BOTH (TMR_GBL | TMR_PRV)
134#define TMR_NONE 0
135
136static struct ofw_compat_data compat_data[] = {
137 {"arm,mpcore-timers", TMR_BOTH}, /* Non-standard, FreeBSD. */
138 {"arm,cortex-a9-global-timer", TMR_GBL},
139 {"arm,cortex-a5-global-timer", TMR_GBL},
140 {"arm,cortex-a9-twd-timer", TMR_PRV},
141 {"arm,cortex-a5-twd-timer", TMR_PRV},
142 {"arm,arm11mp-twd-timer", TMR_PRV},
143 {NULL, TMR_NONE}
144};
145
142/**
143 * arm_tmr_get_timecount - reads the timecount (global) timer
144 * @tc: pointer to arm_tmr_timecount struct
145 *
146 * We only read the lower 32-bits, the timecount stuff only uses 32-bits
147 * so (for now?) ignore the upper 32-bits.
148 *
149 * RETURNS
150 * The lower 32-bits of the counter.
151 */
152static unsigned
153arm_tmr_get_timecount(struct timecounter *tc)
154{
146/**
147 * arm_tmr_get_timecount - reads the timecount (global) timer
148 * @tc: pointer to arm_tmr_timecount struct
149 *
150 * We only read the lower 32-bits, the timecount stuff only uses 32-bits
151 * so (for now?) ignore the upper 32-bits.
152 *
153 * RETURNS
154 * The lower 32-bits of the counter.
155 */
156static unsigned
157arm_tmr_get_timecount(struct timecounter *tc)
158{
155 return (tmr_gbl_read_4(GBL_TIMER_COUNT_LOW));
159 struct arm_tmr_softc *sc;
160
161 sc = tc->tc_priv;
162 return (tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW));
156}
157
158/**
159 * arm_tmr_start - starts the eventtimer (private) timer
160 * @et: pointer to eventtimer struct
161 * @first: the number of seconds and fractional sections to trigger in
162 * @period: the period (in seconds and fractional sections) to set
163 *
164 * If the eventtimer is required to be in oneshot mode, period will be
165 * NULL and first will point to the time to trigger. If in periodic mode
166 * period will contain the time period and first may optionally contain
167 * the time for the first period.
168 *
169 * RETURNS
170 * Always returns 0
171 */
172static int
173arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
174{
163}
164
165/**
166 * arm_tmr_start - starts the eventtimer (private) timer
167 * @et: pointer to eventtimer struct
168 * @first: the number of seconds and fractional sections to trigger in
169 * @period: the period (in seconds and fractional sections) to set
170 *
171 * If the eventtimer is required to be in oneshot mode, period will be
172 * NULL and first will point to the time to trigger. If in periodic mode
173 * period will contain the time period and first may optionally contain
174 * the time for the first period.
175 *
176 * RETURNS
177 * Always returns 0
178 */
179static int
180arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
181{
182 struct arm_tmr_softc *sc;
175 uint32_t load, count;
176 uint32_t ctrl;
177
183 uint32_t load, count;
184 uint32_t ctrl;
185
178 tmr_prv_write_4(PRV_TIMER_CTRL, 0);
179 tmr_prv_write_4(PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
186 sc = et->et_priv;
187 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0);
188 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
180
181 ctrl = PRV_TIMER_CTRL_IRQ_ENABLE | PRV_TIMER_CTRL_TIMER_ENABLE;
182
183 if (period != 0) {
184 load = ((uint32_t)et->et_frequency * period) >> 32;
185 ctrl |= PRV_TIMER_CTRL_AUTO_RELOAD;
186 } else
187 load = 0;
188
189 if (first != 0)
190 count = (uint32_t)((et->et_frequency * first) >> 32);
191 else
192 count = load;
193
189
190 ctrl = PRV_TIMER_CTRL_IRQ_ENABLE | PRV_TIMER_CTRL_TIMER_ENABLE;
191
192 if (period != 0) {
193 load = ((uint32_t)et->et_frequency * period) >> 32;
194 ctrl |= PRV_TIMER_CTRL_AUTO_RELOAD;
195 } else
196 load = 0;
197
198 if (first != 0)
199 count = (uint32_t)((et->et_frequency * first) >> 32);
200 else
201 count = load;
202
194 tmr_prv_write_4(PRV_TIMER_LOAD, load);
195 tmr_prv_write_4(PRV_TIMER_COUNT, count);
196 tmr_prv_write_4(PRV_TIMER_CTRL, ctrl);
203 tmr_prv_write_4(sc, PRV_TIMER_LOAD, load);
204 tmr_prv_write_4(sc, PRV_TIMER_COUNT, count);
205 tmr_prv_write_4(sc, PRV_TIMER_CTRL, ctrl);
197
198 return (0);
199}
200
201/**
202 * arm_tmr_stop - stops the eventtimer (private) timer
203 * @et: pointer to eventtimer struct
204 *
205 * Simply stops the private timer by clearing all bits in the ctrl register.
206 *
207 * RETURNS
208 * Always returns 0
209 */
210static int
211arm_tmr_stop(struct eventtimer *et)
212{
206
207 return (0);
208}
209
210/**
211 * arm_tmr_stop - stops the eventtimer (private) timer
212 * @et: pointer to eventtimer struct
213 *
214 * Simply stops the private timer by clearing all bits in the ctrl register.
215 *
216 * RETURNS
217 * Always returns 0
218 */
219static int
220arm_tmr_stop(struct eventtimer *et)
221{
213 tmr_prv_write_4(PRV_TIMER_CTRL, 0);
214 tmr_prv_write_4(PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
222 struct arm_tmr_softc *sc;
223
224 sc = et->et_priv;
225 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0);
226 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
215 return (0);
216}
217
218/**
219 * arm_tmr_intr - ISR for the eventtimer (private) timer
220 * @arg: pointer to arm_tmr_softc struct
221 *
222 * Clears the event register and then calls the eventtimer callback.
223 *
224 * RETURNS
225 * Always returns FILTER_HANDLED
226 */
227static int
228arm_tmr_intr(void *arg)
229{
227 return (0);
228}
229
230/**
231 * arm_tmr_intr - ISR for the eventtimer (private) timer
232 * @arg: pointer to arm_tmr_softc struct
233 *
234 * Clears the event register and then calls the eventtimer callback.
235 *
236 * RETURNS
237 * Always returns FILTER_HANDLED
238 */
239static int
240arm_tmr_intr(void *arg)
241{
230 struct arm_tmr_softc *sc = (struct arm_tmr_softc *)arg;
242 struct arm_tmr_softc *sc;
231
243
232 tmr_prv_write_4(PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
233
244 sc = arg;
245 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
234 if (sc->et.et_active)
235 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
246 if (sc->et.et_active)
247 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
236
237 return (FILTER_HANDLED);
238}
239
240
241
242
243/**
244 * arm_tmr_probe - timer probe routine

--- 7 unchanged lines hidden (view full) ---

252 */
253static int
254arm_tmr_probe(device_t dev)
255{
256
257 if (!ofw_bus_status_okay(dev))
258 return (ENXIO);
259
248 return (FILTER_HANDLED);
249}
250
251
252
253
254/**
255 * arm_tmr_probe - timer probe routine

--- 7 unchanged lines hidden (view full) ---

263 */
264static int
265arm_tmr_probe(device_t dev)
266{
267
268 if (!ofw_bus_status_okay(dev))
269 return (ENXIO);
270
260 if (!ofw_bus_is_compatible(dev, "arm,mpcore-timers"))
271 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == TMR_NONE)
261 return (ENXIO);
262
263 device_set_desc(dev, "ARM MPCore Timers");
264 return (BUS_PROBE_DEFAULT);
265}
266
272 return (ENXIO);
273
274 device_set_desc(dev, "ARM MPCore Timers");
275 return (BUS_PROBE_DEFAULT);
276}
277
278static int
279attach_tc(struct arm_tmr_softc *sc)
280{
281 int rid;
282
283 if (arm_tmr_tc != NULL)
284 return (EBUSY);
285
286 rid = sc->memrid;
287 sc->gbl_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid,
288 RF_ACTIVE);
289 if (sc->gbl_mem == NULL) {
290 device_printf(sc->dev, "could not allocate gbl mem resources\n");
291 return (ENXIO);
292 }
293 tmr_gbl_write_4(sc, GBL_TIMER_CTRL, 0x00000000);
294
295 arm_tmr_timecount.tc_frequency = sc->clkfreq;
296 arm_tmr_timecount.tc_priv = sc;
297 tc_init(&arm_tmr_timecount);
298 arm_tmr_tc = &arm_tmr_timecount;
299
300 tmr_gbl_write_4(sc, GBL_TIMER_CTRL, GBL_TIMER_CTRL_TIMER_ENABLE);
301
302 return (0);
303}
304
305static int
306attach_et(struct arm_tmr_softc *sc)
307{
308 void *ihl;
309 int irid, mrid;
310
311 if (arm_tmr_et != NULL)
312 return (EBUSY);
313
314 mrid = sc->memrid;
315 sc->prv_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &mrid,
316 RF_ACTIVE);
317 if (sc->prv_mem == NULL) {
318 device_printf(sc->dev, "could not allocate prv mem resources\n");
319 return (ENXIO);
320 }
321 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0x00000000);
322
323 irid = sc->irqrid;
324 sc->prv_irq = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irid, RF_ACTIVE);
325 if (sc->prv_irq == NULL) {
326 bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem);
327 device_printf(sc->dev, "could not allocate prv irq resources\n");
328 return (ENXIO);
329 }
330
331 if (bus_setup_intr(sc->dev, sc->prv_irq, INTR_TYPE_CLK, arm_tmr_intr,
332 NULL, sc, &ihl) != 0) {
333 bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem);
334 bus_release_resource(sc->dev, SYS_RES_IRQ, irid, sc->prv_irq);
335 device_printf(sc->dev, "unable to setup the et irq handler.\n");
336 return (ENXIO);
337 }
338
339 /*
340 * Setup and register the eventtimer. Most event timers set their min
341 * and max period values to some value calculated from the clock
342 * frequency. We might not know yet what our runtime clock frequency
343 * will be, so we just use some safe values. A max of 2 seconds ensures
344 * that even if our base clock frequency is 2GHz (meaning a 4GHz CPU),
345 * we won't overflow our 32-bit timer count register. A min of 20
346 * nanoseconds is pretty much completely arbitrary.
347 */
348 sc->et.et_name = "MPCore";
349 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
350 sc->et.et_quality = 1000;
351 sc->et.et_frequency = sc->clkfreq;
352 sc->et.et_min_period = 20 * SBT_1NS;
353 sc->et.et_max_period = 2 * SBT_1S;
354 sc->et.et_start = arm_tmr_start;
355 sc->et.et_stop = arm_tmr_stop;
356 sc->et.et_priv = sc;
357 et_register(&sc->et);
358 arm_tmr_et = &sc->et;
359
360 return (0);
361}
362
267/**
268 * arm_tmr_attach - attaches the timer to the simplebus
269 * @dev: new device
270 *
271 * Reserves memory and interrupt resources, stores the softc structure
272 * globally and registers both the timecount and eventtimer objects.
273 *
274 * RETURNS
275 * Zero on sucess or ENXIO if an error occuried.
276 */
277static int
278arm_tmr_attach(device_t dev)
279{
363/**
364 * arm_tmr_attach - attaches the timer to the simplebus
365 * @dev: new device
366 *
367 * Reserves memory and interrupt resources, stores the softc structure
368 * globally and registers both the timecount and eventtimer objects.
369 *
370 * RETURNS
371 * Zero on sucess or ENXIO if an error occuried.
372 */
373static int
374arm_tmr_attach(device_t dev)
375{
280 struct arm_tmr_softc *sc = device_get_softc(dev);
376 struct arm_tmr_softc *sc;
281 phandle_t node;
282 pcell_t clock;
377 phandle_t node;
378 pcell_t clock;
283 void *ihl;
284 boolean_t fixed_freq;
379 int et_err, tc_err, tmrtype;
285
380
286 if (arm_tmr_sc)
287 return (ENXIO);
381 sc = device_get_softc(dev);
382 sc->dev = dev;
288
383
289 if (platform_arm_tmr_freq == ARM_TMR_FREQUENCY_VARIES) {
290 fixed_freq = false;
384 if (arm_tmr_freq_varies) {
385 sc->clkfreq = arm_tmr_freq;
291 } else {
386 } else {
292 fixed_freq = true;
293 if (platform_arm_tmr_freq != 0) {
294 sc->clkfreq = platform_arm_tmr_freq;
387 if (arm_tmr_freq != 0) {
388 sc->clkfreq = arm_tmr_freq;
295 } else {
296 /* Get the base clock frequency */
297 node = ofw_bus_get_node(dev);
298 if ((OF_getencprop(node, "clock-frequency", &clock,
299 sizeof(clock))) <= 0) {
300 device_printf(dev, "missing clock-frequency "
301 "attribute in FDT\n");
302 return (ENXIO);
303 }
304 sc->clkfreq = clock;
305 }
306 }
307
389 } else {
390 /* Get the base clock frequency */
391 node = ofw_bus_get_node(dev);
392 if ((OF_getencprop(node, "clock-frequency", &clock,
393 sizeof(clock))) <= 0) {
394 device_printf(dev, "missing clock-frequency "
395 "attribute in FDT\n");
396 return (ENXIO);
397 }
398 sc->clkfreq = clock;
399 }
400 }
401
308 if (bus_alloc_resources(dev, arm_tmr_spec, sc->tmr_res)) {
309 device_printf(dev, "could not allocate resources\n");
310 return (ENXIO);
311 }
402 tmrtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
403 tc_err = ENXIO;
404 et_err = ENXIO;
312
405
313 /* Global timer interface */
314 sc->gbl_bst = rman_get_bustag(sc->tmr_res[0]);
315 sc->gbl_bsh = rman_get_bushandle(sc->tmr_res[0]);
316
317 /* Private per-CPU timer interface */
318 sc->prv_bst = rman_get_bustag(sc->tmr_res[2]);
319 sc->prv_bsh = rman_get_bushandle(sc->tmr_res[2]);
320
321 arm_tmr_sc = sc;
322
323 /* Disable both timers to start off */
324 tmr_prv_write_4(PRV_TIMER_CTRL, 0x00000000);
325 tmr_gbl_write_4(GBL_TIMER_CTRL, 0x00000000);
326
327 if (bus_setup_intr(dev, sc->tmr_res[3], INTR_TYPE_CLK, arm_tmr_intr,
328 NULL, sc, &ihl) != 0) {
329 bus_release_resources(dev, arm_tmr_spec, sc->tmr_res);
330 device_printf(dev, "Unable to setup the clock irq handler.\n");
331 return (ENXIO);
332 }
333
334 /*
406 /*
335 * If the clock is fixed-frequency, setup and enable the global timer to
336 * use as the timecounter. If it's variable frequency it won't work as
337 * a timecounter. We also can't use it for DELAY(), so hopefully the
338 * platform provides its own implementation. If it doesn't, ours will
407 * If we're handling the global timer and it is fixed-frequency, set it
408 * up to use as a timecounter. If it's variable frequency it won't work
409 * as a timecounter. We also can't use it for DELAY(), so hopefully the
410 * platform provides its own implementation. If it doesn't, ours will
339 * get used, but since the frequency isn't set, it will only use the
340 * bogus loop counter.
341 */
411 * get used, but since the frequency isn't set, it will only use the
412 * bogus loop counter.
413 */
342 if (fixed_freq) {
343 tmr_gbl_write_4(GBL_TIMER_CTRL, GBL_TIMER_CTRL_TIMER_ENABLE);
344 arm_tmr_timecount.tc_frequency = sc->clkfreq;
345 tc_init(&arm_tmr_timecount);
414 if (tmrtype & TMR_GBL) {
415 if (!arm_tmr_freq_varies)
416 tc_err = attach_tc(sc);
417 else if (bootverbose)
418 device_printf(sc->dev,
419 "not using variable-frequency device as timecounter");
420 sc->memrid++;
421 sc->irqrid++;
346 }
347
422 }
423
424 /* If we are handling the private timer, set it up as an eventtimer. */
425 if (tmrtype & TMR_PRV) {
426 et_err = attach_et(sc);
427 }
428
348 /*
429 /*
349 * Setup and register the eventtimer. Most event timers set their min
350 * and max period values to some value calculated from the clock
351 * frequency. We might not know yet what our runtime clock frequency
352 * will be, so we just use some safe values. A max of 2 seconds ensures
353 * that even if our base clock frequency is 2GHz (meaning a 4GHz CPU),
354 * we won't overflow our 32-bit timer count register. A min of 20
355 * nanoseconds is pretty much completely arbitrary.
430 * If we didn't successfully set up a timecounter or eventtimer then we
431 * didn't actually attach at all, return error.
356 */
432 */
357 sc->et.et_name = "MPCore";
358 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
359 sc->et.et_quality = 1000;
360 sc->et.et_frequency = sc->clkfreq;
361 sc->et.et_min_period = 20 * SBT_1NS;
362 sc->et.et_max_period = 2 * SBT_1S;
363 sc->et.et_start = arm_tmr_start;
364 sc->et.et_stop = arm_tmr_stop;
365 sc->et.et_priv = sc;
366 et_register(&sc->et);
367
433 if (tc_err != 0 && et_err != 0) {
434 return (ENXIO);
435 }
368 return (0);
369}
370
371static device_method_t arm_tmr_methods[] = {
372 DEVMETHOD(device_probe, arm_tmr_probe),
373 DEVMETHOD(device_attach, arm_tmr_attach),
374 { 0, 0 }
375};
376
377static driver_t arm_tmr_driver = {
378 "mp_tmr",
379 arm_tmr_methods,
380 sizeof(struct arm_tmr_softc),
381};
382
383static devclass_t arm_tmr_devclass;
384
385EARLY_DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0,
386 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
436 return (0);
437}
438
439static device_method_t arm_tmr_methods[] = {
440 DEVMETHOD(device_probe, arm_tmr_probe),
441 DEVMETHOD(device_attach, arm_tmr_attach),
442 { 0, 0 }
443};
444
445static driver_t arm_tmr_driver = {
446 "mp_tmr",
447 arm_tmr_methods,
448 sizeof(struct arm_tmr_softc),
449};
450
451static devclass_t arm_tmr_devclass;
452
453EARLY_DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0,
454 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
455EARLY_DRIVER_MODULE(mp_tmr, ofwbus, arm_tmr_driver, arm_tmr_devclass, 0, 0,
456 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
387
388/*
389 * Handle a change in clock frequency. The mpcore timer runs at half the CPU
390 * frequency. When the CPU frequency changes due to power-saving or thermal
391 * managment, the platform-specific code that causes the frequency change calls
392 * this routine to inform the clock driver, and we in turn inform the event
393 * timer system, which actually updates the value in et->frequency for us and
394 * reschedules the current event(s) in a way that's atomic with respect to

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399 * value passed is ARM_TMR_FREQUENCY_VARIES, that will cause the attach() code
400 * to register as an eventtimer, but not a timecounter. If the value passed in
401 * is any other non-zero value it is used as the fixed frequency for the timer.
402 */
403void
404arm_tmr_change_frequency(uint64_t newfreq)
405{
406
457
458/*
459 * Handle a change in clock frequency. The mpcore timer runs at half the CPU
460 * frequency. When the CPU frequency changes due to power-saving or thermal
461 * managment, the platform-specific code that causes the frequency change calls
462 * this routine to inform the clock driver, and we in turn inform the event
463 * timer system, which actually updates the value in et->frequency for us and
464 * reschedules the current event(s) in a way that's atomic with respect to

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469 * value passed is ARM_TMR_FREQUENCY_VARIES, that will cause the attach() code
470 * to register as an eventtimer, but not a timecounter. If the value passed in
471 * is any other non-zero value it is used as the fixed frequency for the timer.
472 */
473void
474arm_tmr_change_frequency(uint64_t newfreq)
475{
476
407 if (arm_tmr_sc == NULL)
408 platform_arm_tmr_freq = newfreq;
409 else
410 et_change_frequency(&arm_tmr_sc->et, newfreq);
477 if (newfreq == ARM_TMR_FREQUENCY_VARIES) {
478 arm_tmr_freq_varies = true;
479 return;
480 }
481
482 arm_tmr_freq = newfreq;
483 if (arm_tmr_et != NULL)
484 et_change_frequency(arm_tmr_et, newfreq);
411}
412
413/**
414 * DELAY - Delay for at least usec microseconds.
415 * @usec: number of microseconds to delay by
416 *
417 * This function is called all over the kernel and is suppose to provide a
418 * consistent delay. This function may also be called before the console
419 * is setup so no printf's can be called here.
420 *
421 * RETURNS:
422 * nothing
423 */
424static void __used /* Must emit function code for the weak ref below. */
425arm_tmr_DELAY(int usec)
426{
485}
486
487/**
488 * DELAY - Delay for at least usec microseconds.
489 * @usec: number of microseconds to delay by
490 *
491 * This function is called all over the kernel and is suppose to provide a
492 * consistent delay. This function may also be called before the console
493 * is setup so no printf's can be called here.
494 *
495 * RETURNS:
496 * nothing
497 */
498static void __used /* Must emit function code for the weak ref below. */
499arm_tmr_DELAY(int usec)
500{
501 struct arm_tmr_softc *sc;
427 int32_t counts_per_usec;
428 int32_t counts;
429 uint32_t first, last;
430
431 /* Check the timers are setup, if not just use a for loop for the meantime */
502 int32_t counts_per_usec;
503 int32_t counts;
504 uint32_t first, last;
505
506 /* Check the timers are setup, if not just use a for loop for the meantime */
432 if (arm_tmr_sc == NULL || arm_tmr_timecount.tc_frequency == 0) {
507 if (arm_tmr_tc == NULL || arm_tmr_timecount.tc_frequency == 0) {
433 for (; usec > 0; usec--)
434 for (counts = 200; counts > 0; counts--)
435 cpufunc_nullop(); /* Prevent gcc from optimizing
436 * out the loop
437 */
438 return;
439 }
440
508 for (; usec > 0; usec--)
509 for (counts = 200; counts > 0; counts--)
510 cpufunc_nullop(); /* Prevent gcc from optimizing
511 * out the loop
512 */
513 return;
514 }
515
516 sc = arm_tmr_tc->tc_priv;
517
441 /* Get the number of times to count */
442 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1);
443
444 /*
445 * Clamp the timeout at a maximum value (about 32 seconds with
446 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
447 * near that length of time and if they are, they should be hung
448 * out to dry.
449 */
450 if (usec >= (0x80000000U / counts_per_usec))
451 counts = (0x80000000U / counts_per_usec) - 1;
452 else
453 counts = usec * counts_per_usec;
454
518 /* Get the number of times to count */
519 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1);
520
521 /*
522 * Clamp the timeout at a maximum value (about 32 seconds with
523 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
524 * near that length of time and if they are, they should be hung
525 * out to dry.
526 */
527 if (usec >= (0x80000000U / counts_per_usec))
528 counts = (0x80000000U / counts_per_usec) - 1;
529 else
530 counts = usec * counts_per_usec;
531
455 first = tmr_gbl_read_4(GBL_TIMER_COUNT_LOW);
532 first = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW);
456
457 while (counts > 0) {
533
534 while (counts > 0) {
458 last = tmr_gbl_read_4(GBL_TIMER_COUNT_LOW);
535 last = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW);
459 counts -= (int32_t)(last - first);
460 first = last;
461 }
462}
463
464/*
465 * Supply a DELAY() implementation via weak linkage. A platform may want to use
466 * the mpcore per-cpu eventtimers but provide its own DELAY() routine,
467 * especially when the core frequency can change on the fly.
468 */
469__weak_reference(arm_tmr_DELAY, DELAY);
470
536 counts -= (int32_t)(last - first);
537 first = last;
538 }
539}
540
541/*
542 * Supply a DELAY() implementation via weak linkage. A platform may want to use
543 * the mpcore per-cpu eventtimers but provide its own DELAY() routine,
544 * especially when the core frequency can change on the fly.
545 */
546__weak_reference(arm_tmr_DELAY, DELAY);
547