| timer.c (245900) | timer.c (247463) |
|---|---|
| 1/*- 2 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@gmail.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@gmail.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> |
| 28__FBSDID("$FreeBSD: head/sys/arm/allwinner/timer.c 245900 2013-01-25 07:21:22Z ganbold $"); | 28__FBSDID("$FreeBSD: head/sys/arm/allwinner/timer.c 247463 2013-02-28 13:46:03Z mav $"); |
| 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/module.h> 35#include <sys/malloc.h> 36#include <sys/rman.h> --- 53 unchanged lines hidden (view full) --- 90 91#define timer_read_4(sc, reg) \ 92 bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg) 93#define timer_write_4(sc, reg, val) \ 94 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val) 95 96static u_int a10_timer_get_timecount(struct timecounter *); 97static int a10_timer_timer_start(struct eventtimer *, | 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/module.h> 35#include <sys/malloc.h> 36#include <sys/rman.h> --- 53 unchanged lines hidden (view full) --- 90 91#define timer_read_4(sc, reg) \ 92 bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg) 93#define timer_write_4(sc, reg, val) \ 94 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val) 95 96static u_int a10_timer_get_timecount(struct timecounter *); 97static int a10_timer_timer_start(struct eventtimer *, |
| 98 struct bintime *, struct bintime *); | 98 sbintime_t first, sbintime_t period); |
| 99static int a10_timer_timer_stop(struct eventtimer *); 100 101static uint64_t timer_read_counter64(void); 102 103static int a10_timer_initialized = 0; 104static int a10_timer_hardclock(void *); 105static int a10_timer_probe(device_t); 106static int a10_timer_attach(device_t); --- 81 unchanged lines hidden (view full) --- 188 189 sc->timer0_freq = SYS_TIMER_CLKSRC; 190 191 /* Set desired frequency in event timer and timecounter */ 192 sc->et.et_frequency = sc->timer0_freq; 193 sc->et.et_name = "a10_timer Eventtimer"; 194 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC; 195 sc->et.et_quality = 1000; | 99static int a10_timer_timer_stop(struct eventtimer *); 100 101static uint64_t timer_read_counter64(void); 102 103static int a10_timer_initialized = 0; 104static int a10_timer_hardclock(void *); 105static int a10_timer_probe(device_t); 106static int a10_timer_attach(device_t); --- 81 unchanged lines hidden (view full) --- 188 189 sc->timer0_freq = SYS_TIMER_CLKSRC; 190 191 /* Set desired frequency in event timer and timecounter */ 192 sc->et.et_frequency = sc->timer0_freq; 193 sc->et.et_name = "a10_timer Eventtimer"; 194 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC; 195 sc->et.et_quality = 1000; |
| 196 sc->et.et_min_period.sec = 0; 197 sc->et.et_min_period.frac = 198 ((0x00000005LLU << 32) / sc->et.et_frequency) << 32; 199 sc->et.et_max_period.sec = 0xfffffff0U / sc->et.et_frequency; 200 sc->et.et_max_period.frac = 201 ((0xfffffffeLLU << 32) / sc->et.et_frequency) << 32; | 196 sc->et.et_min_period = (0x00000005LLU << 32) / sc->et.et_frequency; 197 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; |
| 202 sc->et.et_start = a10_timer_timer_start; 203 sc->et.et_stop = a10_timer_timer_stop; 204 sc->et.et_priv = sc; 205 et_register(&sc->et); 206 207 if (device_get_unit(dev) == 0) 208 a10_timer_sc = sc; 209 --- 10 unchanged lines hidden (view full) --- 220 } 221 222 a10_timer_initialized = 1; 223 224 return (0); 225} 226 227static int | 198 sc->et.et_start = a10_timer_timer_start; 199 sc->et.et_stop = a10_timer_timer_stop; 200 sc->et.et_priv = sc; 201 et_register(&sc->et); 202 203 if (device_get_unit(dev) == 0) 204 a10_timer_sc = sc; 205 --- 10 unchanged lines hidden (view full) --- 216 } 217 218 a10_timer_initialized = 1; 219 220 return (0); 221} 222 223static int |
| 228a10_timer_timer_start(struct eventtimer *et, struct bintime *first, 229 struct bintime *period) | 224a10_timer_timer_start(struct eventtimer *et, sbintime_t first, 225 sbintime_t period) |
| 230{ 231 struct a10_timer_softc *sc; 232 uint32_t count; 233 uint32_t val; 234 235 sc = (struct a10_timer_softc *)et->et_priv; 236 | 226{ 227 struct a10_timer_softc *sc; 228 uint32_t count; 229 uint32_t val; 230 231 sc = (struct a10_timer_softc *)et->et_priv; 232 |
| 237 sc->sc_period = 0; 238 239 if (period != NULL) { 240 sc->sc_period = (sc->et.et_frequency * (period->frac >> 32)) >> 32; 241 sc->sc_period += sc->et.et_frequency * period->sec; 242 } 243 if (first == NULL) | 233 if (period != 0) 234 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32; 235 else 236 sc->sc_period = 0; 237 if (first != 0) 238 count = ((uint32_t)et->et_frequency * first) >> 32; 239 else |
| 244 count = sc->sc_period; | 240 count = sc->sc_period; |
| 245 else { 246 count = (sc->et.et_frequency * (first->frac >> 32)) >> 32; 247 if (first->sec != 0) 248 count += sc->et.et_frequency * first->sec; 249 } | |
| 250 251 /* Update timer values */ 252 timer_write_4(sc, SW_TIMER0_INT_VALUE_REG, sc->sc_period); 253 timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, count); 254 255 val = timer_read_4(sc, SW_TIMER0_CTRL_REG); | 241 242 /* Update timer values */ 243 timer_write_4(sc, SW_TIMER0_INT_VALUE_REG, sc->sc_period); 244 timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, count); 245 246 val = timer_read_4(sc, SW_TIMER0_CTRL_REG); |
| 256 if (first == NULL) { | 247 if (period != 0) { |
| 257 /* periodic */ 258 val |= TIMER_AUTORELOAD; 259 } else { 260 /* oneshot */ 261 val &= ~TIMER_AUTORELOAD; 262 } 263 /* Enable timer0 */ 264 val |= TIMER_ENABLE; --- 115 unchanged lines hidden --- | 248 /* periodic */ 249 val |= TIMER_AUTORELOAD; 250 } else { 251 /* oneshot */ 252 val &= ~TIMER_AUTORELOAD; 253 } 254 /* Enable timer0 */ 255 val |= TIMER_ENABLE; --- 115 unchanged lines hidden --- |