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pci.c (279904) pci.c (280970)
1/*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 13 unchanged lines hidden (view full) ---

22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 13 unchanged lines hidden (view full) ---

22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD: stable/10/sys/dev/pci/pci.c 279904 2015-03-12 07:07:41Z scottl $");
30__FBSDID("$FreeBSD: stable/10/sys/dev/pci/pci.c 280970 2015-04-01 21:48:54Z jhb $");
31
32#include "opt_bus.h"
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/malloc.h>
37#include <sys/module.h>
38#include <sys/linker.h>

--- 48 unchanged lines hidden (view full) ---

87static int pci_porten(device_t dev);
88static int pci_memen(device_t dev);
89static void pci_assign_interrupt(device_t bus, device_t dev,
90 int force_route);
91static int pci_add_map(device_t bus, device_t dev, int reg,
92 struct resource_list *rl, int force, int prefetch);
93static int pci_probe(device_t dev);
94static int pci_attach(device_t dev);
31
32#include "opt_bus.h"
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/malloc.h>
37#include <sys/module.h>
38#include <sys/linker.h>

--- 48 unchanged lines hidden (view full) ---

87static int pci_porten(device_t dev);
88static int pci_memen(device_t dev);
89static void pci_assign_interrupt(device_t bus, device_t dev,
90 int force_route);
91static int pci_add_map(device_t bus, device_t dev, int reg,
92 struct resource_list *rl, int force, int prefetch);
93static int pci_probe(device_t dev);
94static int pci_attach(device_t dev);
95#ifdef PCI_RES_BUS
96static int pci_detach(device_t dev);
97#endif
95static void pci_load_vendor_data(void);
96static int pci_describe_parse_line(char **ptr, int *vendor,
97 int *device, char **desc);
98static char *pci_describe_device(device_t dev);
99static int pci_modevent(module_t mod, int what, void *arg);
100static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
101 pcicfgregs *cfg);
102static void pci_read_cap(device_t pcib, pcicfgregs *cfg);

--- 19 unchanged lines hidden (view full) ---

122 u_int irq);
123
124static uint16_t pci_get_rid_method(device_t dev, device_t child);
125
126static device_method_t pci_methods[] = {
127 /* Device interface */
128 DEVMETHOD(device_probe, pci_probe),
129 DEVMETHOD(device_attach, pci_attach),
98static void pci_load_vendor_data(void);
99static int pci_describe_parse_line(char **ptr, int *vendor,
100 int *device, char **desc);
101static char *pci_describe_device(device_t dev);
102static int pci_modevent(module_t mod, int what, void *arg);
103static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
104 pcicfgregs *cfg);
105static void pci_read_cap(device_t pcib, pcicfgregs *cfg);

--- 19 unchanged lines hidden (view full) ---

125 u_int irq);
126
127static uint16_t pci_get_rid_method(device_t dev, device_t child);
128
129static device_method_t pci_methods[] = {
130 /* Device interface */
131 DEVMETHOD(device_probe, pci_probe),
132 DEVMETHOD(device_attach, pci_attach),
133#ifdef PCI_RES_BUS
134 DEVMETHOD(device_detach, pci_detach),
135#else
130 DEVMETHOD(device_detach, bus_generic_detach),
136 DEVMETHOD(device_detach, bus_generic_detach),
137#endif
131 DEVMETHOD(device_shutdown, bus_generic_shutdown),
132 DEVMETHOD(device_suspend, pci_suspend),
133 DEVMETHOD(device_resume, pci_resume),
134
135 /* Bus interface */
136 DEVMETHOD(bus_print_child, pci_print_child),
137 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
138 DEVMETHOD(bus_read_ivar, pci_read_ivar),

--- 217 unchanged lines hidden (view full) ---

356Disable this if you depend on BIOS emulation of USB devices, that is\n\
357you use USB devices (like keyboard or mouse) but do not load USB drivers");
358
359static int pci_clear_bars;
360TUNABLE_INT("hw.pci.clear_bars", &pci_clear_bars);
361SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0,
362 "Ignore firmware-assigned resources for BARs.");
363
138 DEVMETHOD(device_shutdown, bus_generic_shutdown),
139 DEVMETHOD(device_suspend, pci_suspend),
140 DEVMETHOD(device_resume, pci_resume),
141
142 /* Bus interface */
143 DEVMETHOD(bus_print_child, pci_print_child),
144 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
145 DEVMETHOD(bus_read_ivar, pci_read_ivar),

--- 217 unchanged lines hidden (view full) ---

363Disable this if you depend on BIOS emulation of USB devices, that is\n\
364you use USB devices (like keyboard or mouse) but do not load USB drivers");
365
366static int pci_clear_bars;
367TUNABLE_INT("hw.pci.clear_bars", &pci_clear_bars);
368SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0,
369 "Ignore firmware-assigned resources for BARs.");
370
371#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
372static int pci_clear_buses;
373TUNABLE_INT("hw.pci.clear_buses", &pci_clear_buses);
374SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0,
375 "Ignore firmware-assigned bus numbers.");
376#endif
377
364static int pci_enable_ari = 1;
365TUNABLE_INT("hw.pci.enable_ari", &pci_enable_ari);
366SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari,
367 0, "Enable support for PCIe Alternative RID Interpretation");
368
369static int
370pci_has_quirk(uint32_t devid, int quirk)
371{

--- 2849 unchanged lines hidden (view full) ---

3221 /* Disable interrupts */
3222 offs = bus_read_1(res, XHCI_CAPLENGTH);
3223 bus_write_4(res, offs + XHCI_USBCMD, 0);
3224 bus_read_4(res, offs + XHCI_USBSTS);
3225 }
3226 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3227}
3228
378static int pci_enable_ari = 1;
379TUNABLE_INT("hw.pci.enable_ari", &pci_enable_ari);
380SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari,
381 0, "Enable support for PCIe Alternative RID Interpretation");
382
383static int
384pci_has_quirk(uint32_t devid, int quirk)
385{

--- 2849 unchanged lines hidden (view full) ---

3235 /* Disable interrupts */
3236 offs = bus_read_1(res, XHCI_CAPLENGTH);
3237 bus_write_4(res, offs + XHCI_USBCMD, 0);
3238 bus_read_4(res, offs + XHCI_USBSTS);
3239 }
3240 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3241}
3242
3243#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
3244static void
3245pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg,
3246 struct resource_list *rl)
3247{
3248 struct resource *res;
3249 char *cp;
3250 u_long start, end, count;
3251 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus;
3252
3253 switch (cfg->hdrtype & PCIM_HDRTYPE) {
3254 case PCIM_HDRTYPE_BRIDGE:
3255 sec_reg = PCIR_SECBUS_1;
3256 sub_reg = PCIR_SUBBUS_1;
3257 break;
3258 case PCIM_HDRTYPE_CARDBUS:
3259 sec_reg = PCIR_SECBUS_2;
3260 sub_reg = PCIR_SUBBUS_2;
3261 break;
3262 default:
3263 return;
3264 }
3265
3266 /*
3267 * If the existing bus range is valid, attempt to reserve it
3268 * from our parent. If this fails for any reason, clear the
3269 * secbus and subbus registers.
3270 *
3271 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus?
3272 * This would at least preserve the existing sec_bus if it is
3273 * valid.
3274 */
3275 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1);
3276 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1);
3277
3278 /* Quirk handling. */
3279 switch (pci_get_devid(dev)) {
3280 case 0x12258086: /* Intel 82454KX/GX (Orion) */
3281 sup_bus = pci_read_config(dev, 0x41, 1);
3282 if (sup_bus != 0xff) {
3283 sec_bus = sup_bus + 1;
3284 sub_bus = sup_bus + 1;
3285 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1);
3286 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1);
3287 }
3288 break;
3289
3290 case 0x00dd10de:
3291 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
3292 if ((cp = getenv("smbios.planar.maker")) == NULL)
3293 break;
3294 if (strncmp(cp, "Compal", 6) != 0) {
3295 freeenv(cp);
3296 break;
3297 }
3298 freeenv(cp);
3299 if ((cp = getenv("smbios.planar.product")) == NULL)
3300 break;
3301 if (strncmp(cp, "08A0", 4) != 0) {
3302 freeenv(cp);
3303 break;
3304 }
3305 freeenv(cp);
3306 if (sub_bus < 0xa) {
3307 sub_bus = 0xa;
3308 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1);
3309 }
3310 break;
3311 }
3312
3313 if (bootverbose)
3314 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus);
3315 if (sec_bus > 0 && sub_bus >= sec_bus) {
3316 start = sec_bus;
3317 end = sub_bus;
3318 count = end - start + 1;
3319
3320 resource_list_add(rl, PCI_RES_BUS, 0, 0ul, ~0ul, count);
3321
3322 /*
3323 * If requested, clear secondary bus registers in
3324 * bridge devices to force a complete renumbering
3325 * rather than reserving the existing range. However,
3326 * preserve the existing size.
3327 */
3328 if (pci_clear_buses)
3329 goto clear;
3330
3331 rid = 0;
3332 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid,
3333 start, end, count, 0);
3334 if (res != NULL)
3335 return;
3336
3337 if (bootverbose)
3338 device_printf(bus,
3339 "pci%d:%d:%d:%d secbus failed to allocate\n",
3340 pci_get_domain(dev), pci_get_bus(dev),
3341 pci_get_slot(dev), pci_get_function(dev));
3342 }
3343
3344clear:
3345 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1);
3346 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1);
3347}
3348
3349static struct resource *
3350pci_alloc_secbus(device_t dev, device_t child, int *rid, u_long start,
3351 u_long end, u_long count, u_int flags)
3352{
3353 struct pci_devinfo *dinfo;
3354 pcicfgregs *cfg;
3355 struct resource_list *rl;
3356 struct resource *res;
3357 int sec_reg, sub_reg;
3358
3359 dinfo = device_get_ivars(child);
3360 cfg = &dinfo->cfg;
3361 rl = &dinfo->resources;
3362 switch (cfg->hdrtype & PCIM_HDRTYPE) {
3363 case PCIM_HDRTYPE_BRIDGE:
3364 sec_reg = PCIR_SECBUS_1;
3365 sub_reg = PCIR_SUBBUS_1;
3366 break;
3367 case PCIM_HDRTYPE_CARDBUS:
3368 sec_reg = PCIR_SECBUS_2;
3369 sub_reg = PCIR_SUBBUS_2;
3370 break;
3371 default:
3372 return (NULL);
3373 }
3374
3375 if (*rid != 0)
3376 return (NULL);
3377
3378 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL)
3379 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count);
3380 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) {
3381 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid,
3382 start, end, count, flags & ~RF_ACTIVE);
3383 if (res == NULL) {
3384 resource_list_delete(rl, PCI_RES_BUS, *rid);
3385 device_printf(child, "allocating %lu bus%s failed\n",
3386 count, count == 1 ? "" : "es");
3387 return (NULL);
3388 }
3389 if (bootverbose)
3390 device_printf(child,
3391 "Lazy allocation of %lu bus%s at %lu\n", count,
3392 count == 1 ? "" : "es", rman_get_start(res));
3393 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1);
3394 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1);
3395 }
3396 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start,
3397 end, count, flags));
3398}
3399#endif
3400
3229void
3230pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
3231{
3232 struct pci_devinfo *dinfo;
3233 pcicfgregs *cfg;
3234 struct resource_list *rl;
3235 const struct pci_quirk *q;
3236 uint32_t devid;

--- 56 unchanged lines hidden (view full) ---

3293 xhci_early_takeover(dev);
3294 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
3295 ehci_early_takeover(dev);
3296 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
3297 ohci_early_takeover(dev);
3298 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
3299 uhci_early_takeover(dev);
3300 }
3401void
3402pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
3403{
3404 struct pci_devinfo *dinfo;
3405 pcicfgregs *cfg;
3406 struct resource_list *rl;
3407 const struct pci_quirk *q;
3408 uint32_t devid;

--- 56 unchanged lines hidden (view full) ---

3465 xhci_early_takeover(dev);
3466 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
3467 ehci_early_takeover(dev);
3468 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
3469 ohci_early_takeover(dev);
3470 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
3471 uhci_early_takeover(dev);
3472 }
3473
3474#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
3475 /*
3476 * Reserve resources for secondary bus ranges behind bridge
3477 * devices.
3478 */
3479 pci_reserve_secbus(bus, dev, cfg, rl);
3480#endif
3301}
3302
3303static struct pci_devinfo *
3304pci_identify_function(device_t pcib, device_t dev, int domain, int busno,
3305 int slot, int func, size_t dinfo_size)
3306{
3307 struct pci_devinfo *dinfo;
3308

--- 76 unchanged lines hidden (view full) ---

3385int
3386pci_attach_common(device_t dev)
3387{
3388 struct pci_softc *sc;
3389 int busno, domain;
3390#ifdef PCI_DMA_BOUNDARY
3391 int error, tag_valid;
3392#endif
3481}
3482
3483static struct pci_devinfo *
3484pci_identify_function(device_t pcib, device_t dev, int domain, int busno,
3485 int slot, int func, size_t dinfo_size)
3486{
3487 struct pci_devinfo *dinfo;
3488

--- 76 unchanged lines hidden (view full) ---

3565int
3566pci_attach_common(device_t dev)
3567{
3568 struct pci_softc *sc;
3569 int busno, domain;
3570#ifdef PCI_DMA_BOUNDARY
3571 int error, tag_valid;
3572#endif
3573#ifdef PCI_RES_BUS
3574 int rid;
3575#endif
3393
3394 sc = device_get_softc(dev);
3395 domain = pcib_get_domain(dev);
3396 busno = pcib_get_bus(dev);
3576
3577 sc = device_get_softc(dev);
3578 domain = pcib_get_domain(dev);
3579 busno = pcib_get_bus(dev);
3580#ifdef PCI_RES_BUS
3581 rid = 0;
3582 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno,
3583 1, 0);
3584 if (sc->sc_bus == NULL) {
3585 device_printf(dev, "failed to allocate bus number\n");
3586 return (ENXIO);
3587 }
3588#endif
3397 if (bootverbose)
3398 device_printf(dev, "domain=%d, physical bus=%d\n",
3399 domain, busno);
3400#ifdef PCI_DMA_BOUNDARY
3401 tag_valid = 0;
3402 if (device_get_devclass(device_get_parent(device_get_parent(dev))) !=
3403 devclass_find("pci")) {
3404 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1,

--- 28 unchanged lines hidden (view full) ---

3433 * the parent pcib what our domain and bus numbers are.
3434 */
3435 domain = pcib_get_domain(dev);
3436 busno = pcib_get_bus(dev);
3437 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
3438 return (bus_generic_attach(dev));
3439}
3440
3589 if (bootverbose)
3590 device_printf(dev, "domain=%d, physical bus=%d\n",
3591 domain, busno);
3592#ifdef PCI_DMA_BOUNDARY
3593 tag_valid = 0;
3594 if (device_get_devclass(device_get_parent(device_get_parent(dev))) !=
3595 devclass_find("pci")) {
3596 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1,

--- 28 unchanged lines hidden (view full) ---

3625 * the parent pcib what our domain and bus numbers are.
3626 */
3627 domain = pcib_get_domain(dev);
3628 busno = pcib_get_bus(dev);
3629 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
3630 return (bus_generic_attach(dev));
3631}
3632
3633#ifdef PCI_RES_BUS
3634static int
3635pci_detach(device_t dev)
3636{
3637 struct pci_softc *sc;
3638 int error;
3639
3640 error = bus_generic_detach(dev);
3641 if (error)
3642 return (error);
3643 sc = device_get_softc(dev);
3644 return (bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus));
3645}
3646#endif
3647
3441static void
3442pci_set_power_children(device_t dev, device_t *devlist, int numdevs,
3443 int state)
3444{
3445 device_t child, pcib;
3446 struct pci_devinfo *dinfo;
3447 int dstate, i;
3448

--- 499 unchanged lines hidden (view full) ---

3948 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) {
3949 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n");
3950 (void)pci_release_msi(child);
3951 }
3952 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0)
3953 pci_printf(&dinfo->cfg, "Device leaked memory resources\n");
3954 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0)
3955 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n");
3648static void
3649pci_set_power_children(device_t dev, device_t *devlist, int numdevs,
3650 int state)
3651{
3652 device_t child, pcib;
3653 struct pci_devinfo *dinfo;
3654 int dstate, i;
3655

--- 499 unchanged lines hidden (view full) ---

4155 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) {
4156 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n");
4157 (void)pci_release_msi(child);
4158 }
4159 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0)
4160 pci_printf(&dinfo->cfg, "Device leaked memory resources\n");
4161 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0)
4162 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n");
4163#ifdef PCI_RES_BUS
4164 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0)
4165 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n");
4166#endif
3956
3957 pci_cfg_save(child, dinfo, 1);
3958}
3959
3960/*
3961 * Parse the PCI device database, if loaded, and return a pointer to a
3962 * description of the device.
3963 *

--- 400 unchanged lines hidden (view full) ---

4364
4365 /*
4366 * Perform lazy resource allocation
4367 */
4368 dinfo = device_get_ivars(child);
4369 rl = &dinfo->resources;
4370 cfg = &dinfo->cfg;
4371 switch (type) {
4167
4168 pci_cfg_save(child, dinfo, 1);
4169}
4170
4171/*
4172 * Parse the PCI device database, if loaded, and return a pointer to a
4173 * description of the device.
4174 *

--- 400 unchanged lines hidden (view full) ---

4575
4576 /*
4577 * Perform lazy resource allocation
4578 */
4579 dinfo = device_get_ivars(child);
4580 rl = &dinfo->resources;
4581 cfg = &dinfo->cfg;
4582 switch (type) {
4583#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
4584 case PCI_RES_BUS:
4585 return (pci_alloc_secbus(dev, child, rid, start, end, count,
4586 flags));
4587#endif
4372 case SYS_RES_IRQ:
4373 /*
4374 * Can't alloc legacy interrupt once MSI messages have
4375 * been allocated.
4376 */
4377 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
4378 cfg->msix.msix_alloc > 0))
4379 return (NULL);

--- 543 unchanged lines hidden --- 		4588 case SYS_RES_IRQ:
4589 /*
4590 * Can't alloc legacy interrupt once MSI messages have
4591 * been allocated.
4592 */
4593 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
4594 cfg->msix.msix_alloc > 0))
4595 return (NULL);

--- 543 unchanged lines hidden ---