36
37/*
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
45 * frames, highly configurable RX filtering, and 16 RX and TX queues
46 * (which, along with RX filter rules, can be used for QOS applications).
47 * Other features, such as TCP segmentation, may be available as part
48 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
49 * firmware images can be stored in hardware and need not be compiled
50 * into the driver.
51 *
52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
54 *
55 * The BCM5701 is a single-chip solution incorporating both the BCM5700
56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
57 * does not support external SSRAM.
58 *
59 * Broadcom also produces a variation of the BCM5700 under the "Altima"
60 * brand name, which is functionally similar but lacks PCI-X support.
61 *
62 * Without external SSRAM, you can only have at most 4 TX rings,
63 * and the use of the mini RX ring is disabled. This seems to imply
64 * that these features are simply not available on the BCM5701. As a
65 * result, this driver does not implement any support for the mini RX
66 * ring.
67 */
68
69#ifdef HAVE_KERNEL_OPTION_HEADERS
70#include "opt_device_polling.h"
71#endif
72
73#include <sys/param.h>
74#include <sys/endian.h>
75#include <sys/systm.h>
76#include <sys/sockio.h>
77#include <sys/mbuf.h>
78#include <sys/malloc.h>
79#include <sys/kernel.h>
80#include <sys/module.h>
81#include <sys/socket.h>
82#include <sys/sysctl.h>
83
84#include <net/if.h>
85#include <net/if_arp.h>
86#include <net/ethernet.h>
87#include <net/if_dl.h>
88#include <net/if_media.h>
89
90#include <net/bpf.h>
91
92#include <net/if_types.h>
93#include <net/if_vlan_var.h>
94
95#include <netinet/in_systm.h>
96#include <netinet/in.h>
97#include <netinet/ip.h>
98
99#include <machine/bus.h>
100#include <machine/resource.h>
101#include <sys/bus.h>
102#include <sys/rman.h>
103
104#include <dev/mii/mii.h>
105#include <dev/mii/miivar.h>
106#include "miidevs.h"
107#include <dev/mii/brgphyreg.h>
108
109#ifdef __sparc64__
110#include <dev/ofw/ofw_bus.h>
111#include <dev/ofw/openfirm.h>
112#include <machine/ofw_machdep.h>
113#include <machine/ver.h>
114#endif
115
116#include <dev/pci/pcireg.h>
117#include <dev/pci/pcivar.h>
118
119#include <dev/bge/if_bgereg.h>
120
121#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
122#define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
123
124MODULE_DEPEND(bge, pci, 1, 1, 1);
125MODULE_DEPEND(bge, ether, 1, 1, 1);
126MODULE_DEPEND(bge, miibus, 1, 1, 1);
127
128/* "device miibus" required. See GENERIC if you get errors here. */
129#include "miibus_if.h"
130
131/*
132 * Various supported device vendors/types and their names. Note: the
133 * spec seems to indicate that the hardware still has Alteon's vendor
134 * ID burned into it, though it will always be overriden by the vendor
135 * ID in the EEPROM. Just to be safe, we cover all possibilities.
136 */
137static struct bge_type {
138 uint16_t bge_vid;
139 uint16_t bge_did;
140} bge_devs[] = {
141 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 },
142 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 },
143
144 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 },
145 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 },
146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 },
147
148 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 },
149
150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 },
151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 },
152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 },
153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT },
154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X },
155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT },
157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C },
159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT },
161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 },
173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },
177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 },
179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M },
180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 },
181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F },
182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M },
183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 },
184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M },
185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 },
186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M },
187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 },
190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 },
191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 },
192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 },
193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M },
194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 },
195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 },
196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 },
197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 },
198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M },
199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 },
200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M },
201
202 { SK_VENDORID, SK_DEVICEID_ALTIMA },
203
204 { TC_VENDORID, TC_DEVICEID_3C996 },
205
206 { 0, 0 }
207};
208
209static const struct bge_vendor {
210 uint16_t v_id;
211 const char *v_name;
212} bge_vendors[] = {
213 { ALTEON_VENDORID, "Alteon" },
214 { ALTIMA_VENDORID, "Altima" },
215 { APPLE_VENDORID, "Apple" },
216 { BCOM_VENDORID, "Broadcom" },
217 { SK_VENDORID, "SysKonnect" },
218 { TC_VENDORID, "3Com" },
219
220 { 0, NULL }
221};
222
223static const struct bge_revision {
224 uint32_t br_chipid;
225 const char *br_name;
226} bge_revisions[] = {
227 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
228 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
229 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
230 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
231 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
232 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
233 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
234 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
235 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
236 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
237 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
238 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
239 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
240 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
241 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
242 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
243 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
244 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
245 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
246 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
247 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
248 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
249 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
250 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
251 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
252 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
253 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
254 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
255 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
256 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
257 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
258 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
259 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
260 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
261 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
262 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
263 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
264 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
265 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
266 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
267 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
268 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
269 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
270 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
271 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
272 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
273 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
274 /* 5754 and 5787 share the same ASIC ID */
275 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
276 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
277 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
278 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
279 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
280
281 { 0, NULL }
282};
283
284/*
285 * Some defaults for major revisions, so that newer steppings
286 * that we don't know about have a shot at working.
287 */
288static const struct bge_revision bge_majorrevs[] = {
289 { BGE_ASICREV_BCM5700, "unknown BCM5700" },
290 { BGE_ASICREV_BCM5701, "unknown BCM5701" },
291 { BGE_ASICREV_BCM5703, "unknown BCM5703" },
292 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
293 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
294 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
295 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
296 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
297 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
298 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
299 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
300 /* 5754 and 5787 share the same ASIC ID */
301 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
302 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
303
304 { 0, NULL }
305};
306
307#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
308#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
309#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
310#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
311#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
312
313const struct bge_revision * bge_lookup_rev(uint32_t);
314const struct bge_vendor * bge_lookup_vendor(uint16_t);
315
316typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
317
318static int bge_probe(device_t);
319static int bge_attach(device_t);
320static int bge_detach(device_t);
321static int bge_suspend(device_t);
322static int bge_resume(device_t);
323static void bge_release_resources(struct bge_softc *);
324static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
325static int bge_dma_alloc(device_t);
326static void bge_dma_free(struct bge_softc *);
327
328static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
329static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
330static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
331static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
332static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
333
334static void bge_txeof(struct bge_softc *);
335static void bge_rxeof(struct bge_softc *);
336
337static void bge_asf_driver_up (struct bge_softc *);
338static void bge_tick(void *);
339static void bge_stats_update(struct bge_softc *);
340static void bge_stats_update_regs(struct bge_softc *);
341static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
342
343static void bge_intr(void *);
344static void bge_start_locked(struct ifnet *);
345static void bge_start(struct ifnet *);
346static int bge_ioctl(struct ifnet *, u_long, caddr_t);
347static void bge_init_locked(struct bge_softc *);
348static void bge_init(void *);
349static void bge_stop(struct bge_softc *);
350static void bge_watchdog(struct bge_softc *);
351static void bge_shutdown(device_t);
352static int bge_ifmedia_upd_locked(struct ifnet *);
353static int bge_ifmedia_upd(struct ifnet *);
354static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
355
356static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
357static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
358
359static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
360static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
361
362static void bge_setpromisc(struct bge_softc *);
363static void bge_setmulti(struct bge_softc *);
364static void bge_setvlan(struct bge_softc *);
365
366static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
367static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
368static int bge_init_rx_ring_std(struct bge_softc *);
369static void bge_free_rx_ring_std(struct bge_softc *);
370static int bge_init_rx_ring_jumbo(struct bge_softc *);
371static void bge_free_rx_ring_jumbo(struct bge_softc *);
372static void bge_free_tx_ring(struct bge_softc *);
373static int bge_init_tx_ring(struct bge_softc *);
374
375static int bge_chipinit(struct bge_softc *);
376static int bge_blockinit(struct bge_softc *);
377
378static int bge_has_eaddr(struct bge_softc *);
379static uint32_t bge_readmem_ind(struct bge_softc *, int);
380static void bge_writemem_ind(struct bge_softc *, int, int);
381static void bge_writembx(struct bge_softc *, int, int);
382#ifdef notdef
383static uint32_t bge_readreg_ind(struct bge_softc *, int);
384#endif
385static void bge_writemem_direct(struct bge_softc *, int, int);
386static void bge_writereg_ind(struct bge_softc *, int, int);
387
388static int bge_miibus_readreg(device_t, int, int);
389static int bge_miibus_writereg(device_t, int, int, int);
390static void bge_miibus_statchg(device_t);
391#ifdef DEVICE_POLLING
392static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
393#endif
394
395#define BGE_RESET_START 1
396#define BGE_RESET_STOP 2
397static void bge_sig_post_reset(struct bge_softc *, int);
398static void bge_sig_legacy(struct bge_softc *, int);
399static void bge_sig_pre_reset(struct bge_softc *, int);
400static int bge_reset(struct bge_softc *);
401static void bge_link_upd(struct bge_softc *);
402
403/*
404 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may
405 * leak information to untrusted users. It is also known to cause alignment
406 * traps on certain architectures.
407 */
408#ifdef BGE_REGISTER_DEBUG
409static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
410static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
411static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
412#endif
413static void bge_add_sysctls(struct bge_softc *);
414static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
415
416static device_method_t bge_methods[] = {
417 /* Device interface */
418 DEVMETHOD(device_probe, bge_probe),
419 DEVMETHOD(device_attach, bge_attach),
420 DEVMETHOD(device_detach, bge_detach),
421 DEVMETHOD(device_shutdown, bge_shutdown),
422 DEVMETHOD(device_suspend, bge_suspend),
423 DEVMETHOD(device_resume, bge_resume),
424
425 /* bus interface */
426 DEVMETHOD(bus_print_child, bus_generic_print_child),
427 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
428
429 /* MII interface */
430 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
431 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
432 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
433
434 { 0, 0 }
435};
436
437static driver_t bge_driver = {
438 "bge",
439 bge_methods,
440 sizeof(struct bge_softc)
441};
442
443static devclass_t bge_devclass;
444
445DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
446DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
447
448static int bge_allow_asf = 1;
449
450TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
451
452SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
453SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
454 "Allow ASF mode if available");
455
456#define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500"
457#define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2"
458#define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500"
459#define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3"
460#define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id"
461
462static int
463bge_has_eaddr(struct bge_softc *sc)
464{
465#ifdef __sparc64__
466 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
467 device_t dev;
468 uint32_t subvendor;
469
470 dev = sc->bge_dev;
471
472 /*
473 * The on-board BGEs found in sun4u machines aren't fitted with
474 * an EEPROM which means that we have to obtain the MAC address
475 * via OFW and that some tests will always fail. We distinguish
476 * such BGEs by the subvendor ID, which also has to be obtained
477 * from OFW instead of the PCI configuration space as the latter
478 * indicates Broadcom as the subvendor of the netboot interface.
479 * For early Blade 1500 and 2500 we even have to check the OFW
480 * device path as the subvendor ID always defaults to Broadcom
481 * there.
482 */
483 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
484 &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
485 subvendor == SUN_VENDORID)
486 return (0);
487 memset(buf, 0, sizeof(buf));
488 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
489 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
490 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
491 return (0);
492 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
493 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
494 return (0);
495 }
496#endif
497 return (1);
498}
499
500static uint32_t
501bge_readmem_ind(struct bge_softc *sc, int off)
502{
503 device_t dev;
504 uint32_t val;
505
506 dev = sc->bge_dev;
507
508 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
509 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
510 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
511 return (val);
512}
513
514static void
515bge_writemem_ind(struct bge_softc *sc, int off, int val)
516{
517 device_t dev;
518
519 dev = sc->bge_dev;
520
521 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
522 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
523 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
524}
525
526#ifdef notdef
527static uint32_t
528bge_readreg_ind(struct bge_softc *sc, int off)
529{
530 device_t dev;
531
532 dev = sc->bge_dev;
533
534 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
535 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
536}
537#endif
538
539static void
540bge_writereg_ind(struct bge_softc *sc, int off, int val)
541{
542 device_t dev;
543
544 dev = sc->bge_dev;
545
546 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
547 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
548}
549
550static void
551bge_writemem_direct(struct bge_softc *sc, int off, int val)
552{
553 CSR_WRITE_4(sc, off, val);
554}
555
556static void
557bge_writembx(struct bge_softc *sc, int off, int val)
558{
559 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
560 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
561
562 CSR_WRITE_4(sc, off, val);
563}
564
565/*
566 * Map a single buffer address.
567 */
568
569static void
570bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
571{
572 struct bge_dmamap_arg *ctx;
573
574 if (error)
575 return;
576
577 ctx = arg;
578
579 if (nseg > ctx->bge_maxsegs) {
580 ctx->bge_maxsegs = 0;
581 return;
582 }
583
584 ctx->bge_busaddr = segs->ds_addr;
585}
586
587static uint8_t
588bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
589{
590 uint32_t access, byte = 0;
591 int i;
592
593 /* Lock. */
594 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
595 for (i = 0; i < 8000; i++) {
596 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
597 break;
598 DELAY(20);
599 }
600 if (i == 8000)
601 return (1);
602
603 /* Enable access. */
604 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
605 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
606
607 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
608 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
609 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
610 DELAY(10);
611 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
612 DELAY(10);
613 break;
614 }
615 }
616
617 if (i == BGE_TIMEOUT * 10) {
618 if_printf(sc->bge_ifp, "nvram read timed out\n");
619 return (1);
620 }
621
622 /* Get result. */
623 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
624
625 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
626
627 /* Disable access. */
628 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
629
630 /* Unlock. */
631 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
632 CSR_READ_4(sc, BGE_NVRAM_SWARB);
633
634 return (0);
635}
636
637/*
638 * Read a sequence of bytes from NVRAM.
639 */
640static int
641bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
642{
643 int err = 0, i;
644 uint8_t byte = 0;
645
646 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
647 return (1);
648
649 for (i = 0; i < cnt; i++) {
650 err = bge_nvram_getbyte(sc, off + i, &byte);
651 if (err)
652 break;
653 *(dest + i) = byte;
654 }
655
656 return (err ? 1 : 0);
657}
658
659/*
660 * Read a byte of data stored in the EEPROM at address 'addr.' The
661 * BCM570x supports both the traditional bitbang interface and an
662 * auto access interface for reading the EEPROM. We use the auto
663 * access method.
664 */
665static uint8_t
666bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
667{
668 int i;
669 uint32_t byte = 0;
670
671 /*
672 * Enable use of auto EEPROM access so we can avoid
673 * having to use the bitbang method.
674 */
675 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
676
677 /* Reset the EEPROM, load the clock period. */
678 CSR_WRITE_4(sc, BGE_EE_ADDR,
679 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
680 DELAY(20);
681
682 /* Issue the read EEPROM command. */
683 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
684
685 /* Wait for completion */
686 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
687 DELAY(10);
688 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
689 break;
690 }
691
692 if (i == BGE_TIMEOUT * 10) {
693 device_printf(sc->bge_dev, "EEPROM read timed out\n");
694 return (1);
695 }
696
697 /* Get result. */
698 byte = CSR_READ_4(sc, BGE_EE_DATA);
699
700 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
701
702 return (0);
703}
704
705/*
706 * Read a sequence of bytes from the EEPROM.
707 */
708static int
709bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
710{
711 int i, error = 0;
712 uint8_t byte = 0;
713
714 for (i = 0; i < cnt; i++) {
715 error = bge_eeprom_getbyte(sc, off + i, &byte);
716 if (error)
717 break;
718 *(dest + i) = byte;
719 }
720
721 return (error ? 1 : 0);
722}
723
724static int
725bge_miibus_readreg(device_t dev, int phy, int reg)
726{
727 struct bge_softc *sc;
728 uint32_t val, autopoll;
729 int i;
730
731 sc = device_get_softc(dev);
732
733 /*
734 * Broadcom's own driver always assumes the internal
735 * PHY is at GMII address 1. On some chips, the PHY responds
736 * to accesses at all addresses, which could cause us to
737 * bogusly attach the PHY 32 times at probe type. Always
738 * restricting the lookup to address 1 is simpler than
739 * trying to figure out which chips revisions should be
740 * special-cased.
741 */
742 if (phy != 1)
743 return (0);
744
745 /* Reading with autopolling on may trigger PCI errors */
746 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
747 if (autopoll & BGE_MIMODE_AUTOPOLL) {
748 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
749 DELAY(40);
750 }
751
752 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
753 BGE_MIPHY(phy) | BGE_MIREG(reg));
754
755 for (i = 0; i < BGE_TIMEOUT; i++) {
756 DELAY(10);
757 val = CSR_READ_4(sc, BGE_MI_COMM);
758 if (!(val & BGE_MICOMM_BUSY))
759 break;
760 }
761
762 if (i == BGE_TIMEOUT) {
763 device_printf(sc->bge_dev,
764 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
765 phy, reg, val);
766 val = 0;
767 goto done;
768 }
769
770 DELAY(5);
771 val = CSR_READ_4(sc, BGE_MI_COMM);
772
773done:
774 if (autopoll & BGE_MIMODE_AUTOPOLL) {
775 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
776 DELAY(40);
777 }
778
779 if (val & BGE_MICOMM_READFAIL)
780 return (0);
781
782 return (val & 0xFFFF);
783}
784
785static int
786bge_miibus_writereg(device_t dev, int phy, int reg, int val)
787{
788 struct bge_softc *sc;
789 uint32_t autopoll;
790 int i;
791
792 sc = device_get_softc(dev);
793
794 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
795 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
796 return(0);
797
798 /* Reading with autopolling on may trigger PCI errors */
799 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
800 if (autopoll & BGE_MIMODE_AUTOPOLL) {
801 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
802 DELAY(40);
803 }
804
805 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
806 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
807
808 for (i = 0; i < BGE_TIMEOUT; i++) {
809 DELAY(10);
810 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
811 DELAY(5);
812 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
813 break;
814 }
815 }
816
817 if (i == BGE_TIMEOUT) {
818 device_printf(sc->bge_dev,
819 "PHY write timed out (phy %d, reg %d, val %d)\n",
820 phy, reg, val);
821 return (0);
822 }
823
824 if (autopoll & BGE_MIMODE_AUTOPOLL) {
825 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
826 DELAY(40);
827 }
828
829 return (0);
830}
831
832static void
833bge_miibus_statchg(device_t dev)
834{
835 struct bge_softc *sc;
836 struct mii_data *mii;
837 sc = device_get_softc(dev);
838 mii = device_get_softc(sc->bge_miibus);
839
840 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
841 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
842 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
843 else
844 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
845
846 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
847 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
848 else
849 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
850}
851
852/*
853 * Intialize a standard receive ring descriptor.
854 */
855static int
856bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
857{
858 struct mbuf *m_new = NULL;
859 struct bge_rx_bd *r;
860 struct bge_dmamap_arg ctx;
861 int error;
862
863 if (m == NULL) {
864 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
865 if (m_new == NULL)
866 return (ENOBUFS);
867 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
868 } else {
869 m_new = m;
870 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
871 m_new->m_data = m_new->m_ext.ext_buf;
872 }
873
874 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
875 m_adj(m_new, ETHER_ALIGN);
876 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
877 r = &sc->bge_ldata.bge_rx_std_ring[i];
878 ctx.bge_maxsegs = 1;
879 ctx.sc = sc;
880 error = bus_dmamap_load(sc->bge_cdata.bge_mtag,
881 sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *),
882 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
883 if (error || ctx.bge_maxsegs == 0) {
884 if (m == NULL) {
885 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
886 m_freem(m_new);
887 }
888 return (ENOMEM);
889 }
890 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_busaddr);
891 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_busaddr);
892 r->bge_flags = BGE_RXBDFLAG_END;
893 r->bge_len = m_new->m_len;
894 r->bge_idx = i;
895
896 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
897 sc->bge_cdata.bge_rx_std_dmamap[i],
898 BUS_DMASYNC_PREREAD);
899
900 return (0);
901}
902
903/*
904 * Initialize a jumbo receive ring descriptor. This allocates
905 * a jumbo buffer from the pool managed internally by the driver.
906 */
907static int
908bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
909{
910 bus_dma_segment_t segs[BGE_NSEG_JUMBO];
911 struct bge_extrx_bd *r;
912 struct mbuf *m_new = NULL;
913 int nsegs;
914 int error;
915
916 if (m == NULL) {
917 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
918 if (m_new == NULL)
919 return (ENOBUFS);
920
921 m_cljget(m_new, M_DONTWAIT, MJUM9BYTES);
922 if (!(m_new->m_flags & M_EXT)) {
923 m_freem(m_new);
924 return (ENOBUFS);
925 }
926 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES;
927 } else {
928 m_new = m;
929 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES;
930 m_new->m_data = m_new->m_ext.ext_buf;
931 }
932
933 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
934 m_adj(m_new, ETHER_ALIGN);
935
936 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
937 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
938 m_new, segs, &nsegs, BUS_DMA_NOWAIT);
939 if (error) {
940 if (m == NULL)
941 m_freem(m_new);
942 return (error);
943 }
944 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
945
946 /*
947 * Fill in the extended RX buffer descriptor.
948 */
949 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
950 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
951 r->bge_idx = i;
952 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
953 switch (nsegs) {
954 case 4:
955 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
956 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
957 r->bge_len3 = segs[3].ds_len;
958 case 3:
959 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
960 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
961 r->bge_len2 = segs[2].ds_len;
962 case 2:
963 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
964 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
965 r->bge_len1 = segs[1].ds_len;
966 case 1:
967 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
968 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
969 r->bge_len0 = segs[0].ds_len;
970 break;
971 default:
972 panic("%s: %d segments\n", __func__, nsegs);
973 }
974
975 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
976 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
977 BUS_DMASYNC_PREREAD);
978
979 return (0);
980}
981
982/*
983 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
984 * that's 1MB or memory, which is a lot. For now, we fill only the first
985 * 256 ring entries and hope that our CPU is fast enough to keep up with
986 * the NIC.
987 */
988static int
989bge_init_rx_ring_std(struct bge_softc *sc)
990{
991 int i;
992
993 for (i = 0; i < BGE_SSLOTS; i++) {
994 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
995 return (ENOBUFS);
996 };
997
998 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
999 sc->bge_cdata.bge_rx_std_ring_map,
1000 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1001
1002 sc->bge_std = i - 1;
1003 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1004
1005 return (0);
1006}
1007
1008static void
1009bge_free_rx_ring_std(struct bge_softc *sc)
1010{
1011 int i;
1012
1013 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1014 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1015 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
1016 sc->bge_cdata.bge_rx_std_dmamap[i],
1017 BUS_DMASYNC_POSTREAD);
1018 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1019 sc->bge_cdata.bge_rx_std_dmamap[i]);
1020 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1021 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1022 }
1023 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1024 sizeof(struct bge_rx_bd));
1025 }
1026}
1027
1028static int
1029bge_init_rx_ring_jumbo(struct bge_softc *sc)
1030{
1031 struct bge_rcb *rcb;
1032 int i;
1033
1034 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1035 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1036 return (ENOBUFS);
1037 };
1038
1039 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1040 sc->bge_cdata.bge_rx_jumbo_ring_map,
1041 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1042
1043 sc->bge_jumbo = i - 1;
1044
1045 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1046 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1047 BGE_RCB_FLAG_USE_EXT_RX_BD);
1048 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1049
1050 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1051
1052 return (0);
1053}
1054
1055static void
1056bge_free_rx_ring_jumbo(struct bge_softc *sc)
1057{
1058 int i;
1059
1060 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1061 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1062 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1063 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1064 BUS_DMASYNC_POSTREAD);
1065 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1066 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1067 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1068 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1069 }
1070 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1071 sizeof(struct bge_extrx_bd));
1072 }
1073}
1074
1075static void
1076bge_free_tx_ring(struct bge_softc *sc)
1077{
1078 int i;
1079
1080 if (sc->bge_ldata.bge_tx_ring == NULL)
1081 return;
1082
1083 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1084 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1085 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
1086 sc->bge_cdata.bge_tx_dmamap[i],
1087 BUS_DMASYNC_POSTWRITE);
1088 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1089 sc->bge_cdata.bge_tx_dmamap[i]);
1090 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1091 sc->bge_cdata.bge_tx_chain[i] = NULL;
1092 }
1093 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1094 sizeof(struct bge_tx_bd));
1095 }
1096}
1097
1098static int
1099bge_init_tx_ring(struct bge_softc *sc)
1100{
1101 sc->bge_txcnt = 0;
1102 sc->bge_tx_saved_considx = 0;
1103
1104 /* Initialize transmit producer index for host-memory send ring. */
1105 sc->bge_tx_prodidx = 0;
1106 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1107
1108 /* 5700 b2 errata */
1109 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1110 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1111
1112 /* NIC-memory send ring not used; initialize to zero. */
1113 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1114 /* 5700 b2 errata */
1115 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1116 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1117
1118 return (0);
1119}
1120
1121static void
1122bge_setpromisc(struct bge_softc *sc)
1123{
1124 struct ifnet *ifp;
1125
1126 BGE_LOCK_ASSERT(sc);
1127
1128 ifp = sc->bge_ifp;
1129
1130 /* Enable or disable promiscuous mode as needed. */
1131 if (ifp->if_flags & IFF_PROMISC)
1132 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1133 else
1134 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1135}
1136
1137static void
1138bge_setmulti(struct bge_softc *sc)
1139{
1140 struct ifnet *ifp;
1141 struct ifmultiaddr *ifma;
1142 uint32_t hashes[4] = { 0, 0, 0, 0 };
1143 int h, i;
1144
1145 BGE_LOCK_ASSERT(sc);
1146
1147 ifp = sc->bge_ifp;
1148
1149 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1150 for (i = 0; i < 4; i++)
1151 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1152 return;
1153 }
1154
1155 /* First, zot all the existing filters. */
1156 for (i = 0; i < 4; i++)
1157 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1158
1159 /* Now program new ones. */
1160 IF_ADDR_LOCK(ifp);
1161 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1162 if (ifma->ifma_addr->sa_family != AF_LINK)
1163 continue;
1164 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1165 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1166 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1167 }
1168 IF_ADDR_UNLOCK(ifp);
1169
1170 for (i = 0; i < 4; i++)
1171 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1172}
1173
1174static void
1175bge_setvlan(struct bge_softc *sc)
1176{
1177 struct ifnet *ifp;
1178
1179 BGE_LOCK_ASSERT(sc);
1180
1181 ifp = sc->bge_ifp;
1182
1183 /* Enable or disable VLAN tag stripping as needed. */
1184 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1185 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1186 else
1187 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1188}
1189
1190static void
1191bge_sig_pre_reset(sc, type)
1192 struct bge_softc *sc;
1193 int type;
1194{
1195 /*
1196 * Some chips don't like this so only do this if ASF is enabled
1197 */
1198 if (sc->bge_asf_mode)
1199 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1200
1201 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1202 switch (type) {
1203 case BGE_RESET_START:
1204 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1205 break;
1206 case BGE_RESET_STOP:
1207 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1208 break;
1209 }
1210 }
1211}
1212
1213static void
1214bge_sig_post_reset(sc, type)
1215 struct bge_softc *sc;
1216 int type;
1217{
1218 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1219 switch (type) {
1220 case BGE_RESET_START:
1221 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
1222 /* START DONE */
1223 break;
1224 case BGE_RESET_STOP:
1225 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
1226 break;
1227 }
1228 }
1229}
1230
1231static void
1232bge_sig_legacy(sc, type)
1233 struct bge_softc *sc;
1234 int type;
1235{
1236 if (sc->bge_asf_mode) {
1237 switch (type) {
1238 case BGE_RESET_START:
1239 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1240 break;
1241 case BGE_RESET_STOP:
1242 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1243 break;
1244 }
1245 }
1246}
1247
1248void bge_stop_fw(struct bge_softc *);
1249void
1250bge_stop_fw(sc)
1251 struct bge_softc *sc;
1252{
1253 int i;
1254
1255 if (sc->bge_asf_mode) {
1256 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
1257 CSR_WRITE_4(sc, BGE_CPU_EVENT,
1258 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
1259
1260 for (i = 0; i < 100; i++ ) {
1261 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
1262 break;
1263 DELAY(10);
1264 }
1265 }
1266}
1267
1268/*
1269 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1270 * self-test results.
1271 */
1272static int
1273bge_chipinit(struct bge_softc *sc)
1274{
1275 uint32_t dma_rw_ctl;
1276 int i;
1277
1278 /* Set endianness before we access any non-PCI registers. */
1279 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1280
1281 /*
1282 * Check the 'ROM failed' bit on the RX CPU to see if
1283 * self-tests passed. Skip this check when there's no
1284 * chip containing the Ethernet address fitted, since
1285 * in that case it will always fail.
1286 */
1287 if ((sc->bge_flags & BGE_FLAG_EADDR) &&
1288 CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1289 device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n");
1290 return (ENODEV);
1291 }
1292
1293 /* Clear the MAC control register */
1294 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1295
1296 /*
1297 * Clear the MAC statistics block in the NIC's
1298 * internal memory.
1299 */
1300 for (i = BGE_STATS_BLOCK;
1301 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1302 BGE_MEMWIN_WRITE(sc, i, 0);
1303
1304 for (i = BGE_STATUS_BLOCK;
1305 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1306 BGE_MEMWIN_WRITE(sc, i, 0);
1307
1308 /*
1309 * Set up the PCI DMA control register.
1310 */
1311 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1312 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1313 if (sc->bge_flags & BGE_FLAG_PCIE) {
1314 /* Read watermark not used, 128 bytes for write. */
1315 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1316 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1317 if (BGE_IS_5714_FAMILY(sc)) {
1318 /* 256 bytes for read and write. */
1319 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1320 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1321 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1322 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1323 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1324 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1325 /* 1536 bytes for read, 384 bytes for write. */
1326 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1327 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1328 } else {
1329 /* 384 bytes for read and write. */
1330 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1331 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1332 0x0F;
1333 }
1334 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1335 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1336 uint32_t tmp;
1337
1338 /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1339 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1340 if (tmp == 6 || tmp == 7)
1341 dma_rw_ctl |=
1342 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1343
1344 /* Set PCI-X DMA write workaround. */
1345 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1346 }
1347 } else {
1348 /* Conventional PCI bus: 256 bytes for read and write. */
1349 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1350 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1351
1352 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1353 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1354 dma_rw_ctl |= 0x0F;
1355 }
1356 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1357 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1358 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1359 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1360 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1361 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1362 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1363 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1364
1365 /*
1366 * Set up general mode register.
1367 */
1368 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1369 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1370 BGE_MODECTL_TX_NO_PHDR_CSUM);
1371
1372 /*
1373 * Tell the firmware the driver is running
1374 */
1375 if (sc->bge_asf_mode & ASF_STACKUP)
1376 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1377
1378 /*
1379 * Disable memory write invalidate. Apparently it is not supported
1380 * properly by these devices.
1381 */
1382 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1383
1384 /* Set the timer prescaler (always 66Mhz) */
1385 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1386
1387 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1388 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1389 DELAY(40); /* XXX */
1390
1391 /* Put PHY into ready state */
1392 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1393 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1394 DELAY(40);
1395 }
1396
1397 return (0);
1398}
1399
1400static int
1401bge_blockinit(struct bge_softc *sc)
1402{
1403 struct bge_rcb *rcb;
1404 bus_size_t vrcb;
1405 bge_hostaddr taddr;
1406 uint32_t val;
1407 int i;
1408
1409 /*
1410 * Initialize the memory window pointer register so that
1411 * we can access the first 32K of internal NIC RAM. This will
1412 * allow us to set up the TX send ring RCBs and the RX return
1413 * ring RCBs, plus other things which live in NIC memory.
1414 */
1415 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1416
1417 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1418
1419 if (!(BGE_IS_5705_PLUS(sc))) {
1420 /* Configure mbuf memory pool */
1421 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1422 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1423 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1424 else
1425 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1426
1427 /* Configure DMA resource pool */
1428 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1429 BGE_DMA_DESCRIPTORS);
1430 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1431 }
1432
1433 /* Configure mbuf pool watermarks */
1434 if (!BGE_IS_5705_PLUS(sc)) {
1435 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1436 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1437 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1438 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1439 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1440 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1441 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1442 } else {
1443 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1444 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1445 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1446 }
1447
1448 /* Configure DMA resource watermarks */
1449 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1450 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1451
1452 /* Enable buffer manager */
1453 if (!(BGE_IS_5705_PLUS(sc))) {
1454 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1455 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN);
1456
1457 /* Poll for buffer manager start indication */
1458 for (i = 0; i < BGE_TIMEOUT; i++) {
1459 DELAY(10);
1460 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1461 break;
1462 }
1463
1464 if (i == BGE_TIMEOUT) {
1465 device_printf(sc->bge_dev,
1466 "buffer manager failed to start\n");
1467 return (ENXIO);
1468 }
1469 }
1470
1471 /* Enable flow-through queues */
1472 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1473 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1474
1475 /* Wait until queue initialization is complete */
1476 for (i = 0; i < BGE_TIMEOUT; i++) {
1477 DELAY(10);
1478 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1479 break;
1480 }
1481
1482 if (i == BGE_TIMEOUT) {
1483 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1484 return (ENXIO);
1485 }
1486
1487 /* Initialize the standard RX ring control block */
1488 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1489 rcb->bge_hostaddr.bge_addr_lo =
1490 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1491 rcb->bge_hostaddr.bge_addr_hi =
1492 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1493 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1494 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1495 if (BGE_IS_5705_PLUS(sc))
1496 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1497 else
1498 rcb->bge_maxlen_flags =
1499 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1500 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1501 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1502 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1503
1504 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1505 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1506
1507 /*
1508 * Initialize the jumbo RX ring control block
1509 * We set the 'ring disabled' bit in the flags
1510 * field until we're actually ready to start
1511 * using this ring (i.e. once we set the MTU
1512 * high enough to require it).
1513 */
1514 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1515 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1516
1517 rcb->bge_hostaddr.bge_addr_lo =
1518 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1519 rcb->bge_hostaddr.bge_addr_hi =
1520 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1521 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1522 sc->bge_cdata.bge_rx_jumbo_ring_map,
1523 BUS_DMASYNC_PREREAD);
1524 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1525 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1526 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1527 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1528 rcb->bge_hostaddr.bge_addr_hi);
1529 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1530 rcb->bge_hostaddr.bge_addr_lo);
1531
1532 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1533 rcb->bge_maxlen_flags);
1534 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1535
1536 /* Set up dummy disabled mini ring RCB */
1537 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1538 rcb->bge_maxlen_flags =
1539 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1540 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1541 rcb->bge_maxlen_flags);
1542 }
1543
1544 /*
1545 * Set the BD ring replentish thresholds. The recommended
1546 * values are 1/8th the number of descriptors allocated to
1547 * each ring.
1548 * XXX The 5754 requires a lower threshold, so it might be a
1549 * requirement of all 575x family chips. The Linux driver sets
1550 * the lower threshold for all 5705 family chips as well, but there
1551 * are reports that it might not need to be so strict.
1552 *
1553 * XXX Linux does some extra fiddling here for the 5906 parts as
1554 * well.
1555 */
1556 if (BGE_IS_5705_PLUS(sc))
1557 val = 8;
1558 else
1559 val = BGE_STD_RX_RING_CNT / 8;
1560 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1561 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1562
1563 /*
1564 * Disable all unused send rings by setting the 'ring disabled'
1565 * bit in the flags field of all the TX send ring control blocks.
1566 * These are located in NIC memory.
1567 */
1568 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1569 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1570 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1571 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1572 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1573 vrcb += sizeof(struct bge_rcb);
1574 }
1575
1576 /* Configure TX RCB 0 (we use only the first ring) */
1577 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1578 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1579 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1580 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1581 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1582 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1583 if (!(BGE_IS_5705_PLUS(sc)))
1584 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1585 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1586
1587 /* Disable all unused RX return rings */
1588 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1589 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1590 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1591 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1592 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1593 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1594 BGE_RCB_FLAG_RING_DISABLED));
1595 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1596 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1597 (i * (sizeof(uint64_t))), 0);
1598 vrcb += sizeof(struct bge_rcb);
1599 }
1600
1601 /* Initialize RX ring indexes */
1602 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1603 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1604 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1605
1606 /*
1607 * Set up RX return ring 0
1608 * Note that the NIC address for RX return rings is 0x00000000.
1609 * The return rings live entirely within the host, so the
1610 * nicaddr field in the RCB isn't used.
1611 */
1612 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1613 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1614 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1615 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1616 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1617 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1618 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1619
1620 /* Set random backoff seed for TX */
1621 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1622 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1623 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1624 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1625 BGE_TX_BACKOFF_SEED_MASK);
1626
1627 /* Set inter-packet gap */
1628 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1629
1630 /*
1631 * Specify which ring to use for packets that don't match
1632 * any RX rules.
1633 */
1634 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1635
1636 /*
1637 * Configure number of RX lists. One interrupt distribution
1638 * list, sixteen active lists, one bad frames class.
1639 */
1640 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1641
1642 /* Inialize RX list placement stats mask. */
1643 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1644 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1645
1646 /* Disable host coalescing until we get it set up */
1647 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1648
1649 /* Poll to make sure it's shut down. */
1650 for (i = 0; i < BGE_TIMEOUT; i++) {
1651 DELAY(10);
1652 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1653 break;
1654 }
1655
1656 if (i == BGE_TIMEOUT) {
1657 device_printf(sc->bge_dev,
1658 "host coalescing engine failed to idle\n");
1659 return (ENXIO);
1660 }
1661
1662 /* Set up host coalescing defaults */
1663 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1664 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1665 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1666 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1667 if (!(BGE_IS_5705_PLUS(sc))) {
1668 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1669 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1670 }
1671 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1672 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1673
1674 /* Set up address of statistics block */
1675 if (!(BGE_IS_5705_PLUS(sc))) {
1676 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1677 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1678 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1679 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1680 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1681 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1682 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1683 }
1684
1685 /* Set up address of status block */
1686 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1687 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1688 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1689 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1690 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1691 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1692
1693 /* Turn on host coalescing state machine */
1694 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1695
1696 /* Turn on RX BD completion state machine and enable attentions */
1697 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1698 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
1699
1700 /* Turn on RX list placement state machine */
1701 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1702
1703 /* Turn on RX list selector state machine. */
1704 if (!(BGE_IS_5705_PLUS(sc)))
1705 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1706
1707 /* Turn on DMA, clear stats */
1708 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB |
1709 BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR |
1710 BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB |
1711 BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB |
1712 ((sc->bge_flags & BGE_FLAG_TBI) ?
1713 BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1714
1715 /* Set misc. local control, enable interrupts on attentions */
1716 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1717
1718#ifdef notdef
1719 /* Assert GPIO pins for PHY reset */
1720 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
1721 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
1722 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
1723 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
1724#endif
1725
1726 /* Turn on DMA completion state machine */
1727 if (!(BGE_IS_5705_PLUS(sc)))
1728 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1729
1730 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
1731
1732 /* Enable host coalescing bug fix. */
1733 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1734 sc->bge_asicrev == BGE_ASICREV_BCM5787)
1735 val |= 1 << 29;
1736
1737 /* Turn on write DMA state machine */
1738 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1739
1740 /* Turn on read DMA state machine */
1741 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1742 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS);
1743
1744 /* Turn on RX data completion state machine */
1745 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1746
1747 /* Turn on RX BD initiator state machine */
1748 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1749
1750 /* Turn on RX data and RX BD initiator state machine */
1751 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1752
1753 /* Turn on Mbuf cluster free state machine */
1754 if (!(BGE_IS_5705_PLUS(sc)))
1755 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1756
1757 /* Turn on send BD completion state machine */
1758 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1759
1760 /* Turn on send data completion state machine */
1761 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1762
1763 /* Turn on send data initiator state machine */
1764 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1765
1766 /* Turn on send BD initiator state machine */
1767 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1768
1769 /* Turn on send BD selector state machine */
1770 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1771
1772 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1773 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1774 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
1775
1776 /* ack/clear link change events */
1777 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1778 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1779 BGE_MACSTAT_LINK_CHANGED);
1780 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1781
1782 /* Enable PHY auto polling (for MII/GMII only) */
1783 if (sc->bge_flags & BGE_FLAG_TBI) {
1784 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1785 } else {
1786 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16));
1787 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1788 sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
1789 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1790 BGE_EVTENB_MI_INTERRUPT);
1791 }
1792
1793 /*
1794 * Clear any pending link state attention.
1795 * Otherwise some link state change events may be lost until attention
1796 * is cleared by bge_intr() -> bge_link_upd() sequence.
1797 * It's not necessary on newer BCM chips - perhaps enabling link
1798 * state change attentions implies clearing pending attention.
1799 */
1800 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1801 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1802 BGE_MACSTAT_LINK_CHANGED);
1803
1804 /* Enable link state change attentions. */
1805 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1806
1807 return (0);
1808}
1809
1810const struct bge_revision *
1811bge_lookup_rev(uint32_t chipid)
1812{
1813 const struct bge_revision *br;
1814
1815 for (br = bge_revisions; br->br_name != NULL; br++) {
1816 if (br->br_chipid == chipid)
1817 return (br);
1818 }
1819
1820 for (br = bge_majorrevs; br->br_name != NULL; br++) {
1821 if (br->br_chipid == BGE_ASICREV(chipid))
1822 return (br);
1823 }
1824
1825 return (NULL);
1826}
1827
1828const struct bge_vendor *
1829bge_lookup_vendor(uint16_t vid)
1830{
1831 const struct bge_vendor *v;
1832
1833 for (v = bge_vendors; v->v_name != NULL; v++)
1834 if (v->v_id == vid)
1835 return (v);
1836
1837 panic("%s: unknown vendor %d", __func__, vid);
1838 return (NULL);
1839}
1840
1841/*
1842 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1843 * against our list and return its name if we find a match.
1844 *
1845 * Note that since the Broadcom controller contains VPD support, we
1846 * try to get the device name string from the controller itself instead
1847 * of the compiled-in string. It guarantees we'll always announce the
1848 * right product name. We fall back to the compiled-in string when
1849 * VPD is unavailable or corrupt.
1850 */
1851static int
1852bge_probe(device_t dev)
1853{
1854 struct bge_type *t = bge_devs;
1855 struct bge_softc *sc = device_get_softc(dev);
1856 uint16_t vid, did;
1857
1858 sc->bge_dev = dev;
1859 vid = pci_get_vendor(dev);
1860 did = pci_get_device(dev);
1861 while(t->bge_vid != 0) {
1862 if ((vid == t->bge_vid) && (did == t->bge_did)) {
1863 char model[64], buf[96];
1864 const struct bge_revision *br;
1865 const struct bge_vendor *v;
1866 uint32_t id;
1867
1868 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1869 BGE_PCIMISCCTL_ASICREV;
1870 br = bge_lookup_rev(id);
1871 v = bge_lookup_vendor(vid);
1872 {
1873#if __FreeBSD_version > 700024
1874 const char *pname;
1875
1876 if (pci_get_vpd_ident(dev, &pname) == 0)
1877 snprintf(model, 64, "%s", pname);
1878 else
1879#endif
1880 snprintf(model, 64, "%s %s",
1881 v->v_name,
1882 br != NULL ? br->br_name :
1883 "NetXtreme Ethernet Controller");
1884 }
1885 snprintf(buf, 96, "%s, %sASIC rev. %#04x", model,
1886 br != NULL ? "" : "unknown ", id >> 16);
1887 device_set_desc_copy(dev, buf);
1888 if (pci_get_subvendor(dev) == DELL_VENDORID)
1889 sc->bge_flags |= BGE_FLAG_NO_3LED;
1890 if (did == BCOM_DEVICEID_BCM5755M)
1891 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1892 return (0);
1893 }
1894 t++;
1895 }
1896
1897 return (ENXIO);
1898}
1899
1900static void
1901bge_dma_free(struct bge_softc *sc)
1902{
1903 int i;
1904
1905 /* Destroy DMA maps for RX buffers. */
1906 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1907 if (sc->bge_cdata.bge_rx_std_dmamap[i])
1908 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
1909 sc->bge_cdata.bge_rx_std_dmamap[i]);
1910 }
1911
1912 /* Destroy DMA maps for jumbo RX buffers. */
1913 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1914 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
1915 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
1916 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1917 }
1918
1919 /* Destroy DMA maps for TX buffers. */
1920 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1921 if (sc->bge_cdata.bge_tx_dmamap[i])
1922 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
1923 sc->bge_cdata.bge_tx_dmamap[i]);
1924 }
1925
1926 if (sc->bge_cdata.bge_mtag)
1927 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
1928
1929
1930 /* Destroy standard RX ring. */
1931 if (sc->bge_cdata.bge_rx_std_ring_map)
1932 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
1933 sc->bge_cdata.bge_rx_std_ring_map);
1934 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
1935 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
1936 sc->bge_ldata.bge_rx_std_ring,
1937 sc->bge_cdata.bge_rx_std_ring_map);
1938
1939 if (sc->bge_cdata.bge_rx_std_ring_tag)
1940 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
1941
1942 /* Destroy jumbo RX ring. */
1943 if (sc->bge_cdata.bge_rx_jumbo_ring_map)
1944 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1945 sc->bge_cdata.bge_rx_jumbo_ring_map);
1946
1947 if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
1948 sc->bge_ldata.bge_rx_jumbo_ring)
1949 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1950 sc->bge_ldata.bge_rx_jumbo_ring,
1951 sc->bge_cdata.bge_rx_jumbo_ring_map);
1952
1953 if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
1954 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
1955
1956 /* Destroy RX return ring. */
1957 if (sc->bge_cdata.bge_rx_return_ring_map)
1958 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
1959 sc->bge_cdata.bge_rx_return_ring_map);
1960
1961 if (sc->bge_cdata.bge_rx_return_ring_map &&
1962 sc->bge_ldata.bge_rx_return_ring)
1963 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
1964 sc->bge_ldata.bge_rx_return_ring,
1965 sc->bge_cdata.bge_rx_return_ring_map);
1966
1967 if (sc->bge_cdata.bge_rx_return_ring_tag)
1968 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
1969
1970 /* Destroy TX ring. */
1971 if (sc->bge_cdata.bge_tx_ring_map)
1972 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
1973 sc->bge_cdata.bge_tx_ring_map);
1974
1975 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
1976 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
1977 sc->bge_ldata.bge_tx_ring,
1978 sc->bge_cdata.bge_tx_ring_map);
1979
1980 if (sc->bge_cdata.bge_tx_ring_tag)
1981 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
1982
1983 /* Destroy status block. */
1984 if (sc->bge_cdata.bge_status_map)
1985 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
1986 sc->bge_cdata.bge_status_map);
1987
1988 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
1989 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
1990 sc->bge_ldata.bge_status_block,
1991 sc->bge_cdata.bge_status_map);
1992
1993 if (sc->bge_cdata.bge_status_tag)
1994 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
1995
1996 /* Destroy statistics block. */
1997 if (sc->bge_cdata.bge_stats_map)
1998 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
1999 sc->bge_cdata.bge_stats_map);
2000
2001 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2002 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2003 sc->bge_ldata.bge_stats,
2004 sc->bge_cdata.bge_stats_map);
2005
2006 if (sc->bge_cdata.bge_stats_tag)
2007 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2008
2009 /* Destroy the parent tag. */
2010 if (sc->bge_cdata.bge_parent_tag)
2011 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2012}
2013
2014static int
2015bge_dma_alloc(device_t dev)
2016{
2017 struct bge_dmamap_arg ctx;
2018 struct bge_softc *sc;
2019 int i, error;
2020
2021 sc = device_get_softc(dev);
2022
2023 /*
2024 * Allocate the parent bus DMA tag appropriate for PCI.
2025 */
2026 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2027 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2028 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2029 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2030
2031 if (error != 0) {
2032 device_printf(sc->bge_dev,
2033 "could not allocate parent dma tag\n");
2034 return (ENOMEM);
2035 }
2036
2037 /*
2038 * Create tag for mbufs.
2039 */
2040 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,
2041 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2042 NULL, MCLBYTES * BGE_NSEG_NEW, BGE_NSEG_NEW, MCLBYTES,
2043 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->bge_cdata.bge_mtag);
2044
2045 if (error) {
2046 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2047 return (ENOMEM);
2048 }
2049
2050 /* Create DMA maps for RX buffers. */
2051 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2052 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
2053 &sc->bge_cdata.bge_rx_std_dmamap[i]);
2054 if (error) {
2055 device_printf(sc->bge_dev,
2056 "can't create DMA map for RX\n");
2057 return (ENOMEM);
2058 }
2059 }
2060
2061 /* Create DMA maps for TX buffers. */
2062 for (i = 0; i < BGE_TX_RING_CNT; i++) {
2063 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
2064 &sc->bge_cdata.bge_tx_dmamap[i]);
2065 if (error) {
2066 device_printf(sc->bge_dev,
2067 "can't create DMA map for RX\n");
2068 return (ENOMEM);
2069 }
2070 }
2071
2072 /* Create tag for standard RX ring. */
2073 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2074 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2075 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
2076 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);
2077
2078 if (error) {
2079 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2080 return (ENOMEM);
2081 }
2082
2083 /* Allocate DMA'able memory for standard RX ring. */
2084 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
2085 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
2086 &sc->bge_cdata.bge_rx_std_ring_map);
2087 if (error)
2088 return (ENOMEM);
2089
2090 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
2091
2092 /* Load the address of the standard RX ring. */
2093 ctx.bge_maxsegs = 1;
2094 ctx.sc = sc;
2095
2096 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,
2097 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
2098 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2099
2100 if (error)
2101 return (ENOMEM);
2102
2103 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
2104
2105 /* Create tags for jumbo mbufs. */
2106 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2107 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2108 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2109 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
2110 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2111 if (error) {
2112 device_printf(sc->bge_dev,
2113 "could not allocate jumbo dma tag\n");
2114 return (ENOMEM);
2115 }
2116
2117 /* Create tag for jumbo RX ring. */
2118 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2119 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2120 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
2121 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);
2122
2123 if (error) {
2124 device_printf(sc->bge_dev,
2125 "could not allocate jumbo ring dma tag\n");
2126 return (ENOMEM);
2127 }
2128
2129 /* Allocate DMA'able memory for jumbo RX ring. */
2130 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2131 (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
2132 BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2133 &sc->bge_cdata.bge_rx_jumbo_ring_map);
2134 if (error)
2135 return (ENOMEM);
2136
2137 /* Load the address of the jumbo RX ring. */
2138 ctx.bge_maxsegs = 1;
2139 ctx.sc = sc;
2140
2141 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2142 sc->bge_cdata.bge_rx_jumbo_ring_map,
2143 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,
2144 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2145
2146 if (error)
2147 return (ENOMEM);
2148
2149 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
2150
2151 /* Create DMA maps for jumbo RX buffers. */
2152 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2153 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2154 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2155 if (error) {
2156 device_printf(sc->bge_dev,
2157 "can't create DMA map for jumbo RX\n");
2158 return (ENOMEM);
2159 }
2160 }
2161
2162 }
2163
2164 /* Create tag for RX return ring. */
2165 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2166 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2167 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
2168 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);
2169
2170 if (error) {
2171 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2172 return (ENOMEM);
2173 }
2174
2175 /* Allocate DMA'able memory for RX return ring. */
2176 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
2177 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
2178 &sc->bge_cdata.bge_rx_return_ring_map);
2179 if (error)
2180 return (ENOMEM);
2181
2182 bzero((char *)sc->bge_ldata.bge_rx_return_ring,
2183 BGE_RX_RTN_RING_SZ(sc));
2184
2185 /* Load the address of the RX return ring. */
2186 ctx.bge_maxsegs = 1;
2187 ctx.sc = sc;
2188
2189 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,
2190 sc->bge_cdata.bge_rx_return_ring_map,
2191 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),
2192 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2193
2194 if (error)
2195 return (ENOMEM);
2196
2197 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
2198
2199 /* Create tag for TX ring. */
2200 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2201 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2202 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
2203 &sc->bge_cdata.bge_tx_ring_tag);
2204
2205 if (error) {
2206 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2207 return (ENOMEM);
2208 }
2209
2210 /* Allocate DMA'able memory for TX ring. */
2211 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
2212 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
2213 &sc->bge_cdata.bge_tx_ring_map);
2214 if (error)
2215 return (ENOMEM);
2216
2217 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
2218
2219 /* Load the address of the TX ring. */
2220 ctx.bge_maxsegs = 1;
2221 ctx.sc = sc;
2222
2223 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,
2224 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,
2225 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2226
2227 if (error)
2228 return (ENOMEM);
2229
2230 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
2231
2232 /* Create tag for status block. */
2233 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2234 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2235 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0,
2236 NULL, NULL, &sc->bge_cdata.bge_status_tag);
2237
2238 if (error) {
2239 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2240 return (ENOMEM);
2241 }
2242
2243 /* Allocate DMA'able memory for status block. */
2244 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
2245 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
2246 &sc->bge_cdata.bge_status_map);
2247 if (error)
2248 return (ENOMEM);
2249
2250 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2251
2252 /* Load the address of the status block. */
2253 ctx.sc = sc;
2254 ctx.bge_maxsegs = 1;
2255
2256 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag,
2257 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,
2258 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2259
2260 if (error)
2261 return (ENOMEM);
2262
2263 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
2264
2265 /* Create tag for statistics block. */
2266 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2267 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2268 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
2269 &sc->bge_cdata.bge_stats_tag);
2270
2271 if (error) {
2272 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2273 return (ENOMEM);
2274 }
2275
2276 /* Allocate DMA'able memory for statistics block. */
2277 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
2278 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
2279 &sc->bge_cdata.bge_stats_map);
2280 if (error)
2281 return (ENOMEM);
2282
2283 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
2284
2285 /* Load the address of the statstics block. */
2286 ctx.sc = sc;
2287 ctx.bge_maxsegs = 1;
2288
2289 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag,
2290 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,
2291 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2292
2293 if (error)
2294 return (ENOMEM);
2295
2296 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
2297
2298 return (0);
2299}
2300
2301#if __FreeBSD_version > 602105
2302/*
2303 * Return true if this device has more than one port.
2304 */
2305static int
2306bge_has_multiple_ports(struct bge_softc *sc)
2307{
2308 device_t dev = sc->bge_dev;
2309 u_int b, d, f, fscan, s;
2310
2311 d = pci_get_domain(dev);
2312 b = pci_get_bus(dev);
2313 s = pci_get_slot(dev);
2314 f = pci_get_function(dev);
2315 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2316 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
2317 return (1);
2318 return (0);
2319}
2320
2321/*
2322 * Return true if MSI can be used with this device.
2323 */
2324static int
2325bge_can_use_msi(struct bge_softc *sc)
2326{
2327 int can_use_msi = 0;
2328
2329 switch (sc->bge_asicrev) {
2330 case BGE_ASICREV_BCM5714:
2331 /*
2332 * Apparently, MSI doesn't work when this chip is configured
2333 * in single-port mode.
2334 */
2335 if (bge_has_multiple_ports(sc))
2336 can_use_msi = 1;
2337 break;
2338 case BGE_ASICREV_BCM5750:
2339 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2340 sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2341 can_use_msi = 1;
2342 break;
2343 case BGE_ASICREV_BCM5752:
2344 case BGE_ASICREV_BCM5780:
2345 can_use_msi = 1;
2346 break;
2347 }
2348 return (can_use_msi);
2349}
2350#endif
2351
2352static int
2353bge_attach(device_t dev)
2354{
2355 struct ifnet *ifp;
2356 struct bge_softc *sc;
2357 uint32_t hwcfg = 0, misccfg;
2358 u_char eaddr[ETHER_ADDR_LEN];
2359 int error, reg, rid, trys;
2360
2361 sc = device_get_softc(dev);
2362 sc->bge_dev = dev;
2363
2364 /*
2365 * Map control/status registers.
2366 */
2367 pci_enable_busmaster(dev);
2368
2369 rid = BGE_PCI_BAR0;
2370 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2371 RF_ACTIVE);
2372
2373 if (sc->bge_res == NULL) {
2374 device_printf (sc->bge_dev, "couldn't map memory\n");
2375 error = ENXIO;
2376 goto fail;
2377 }
2378
2379 sc->bge_btag = rman_get_bustag(sc->bge_res);
2380 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
2381
2382 /* Save ASIC rev. */
2383
2384 sc->bge_chipid =
2385 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
2386 BGE_PCIMISCCTL_ASICREV;
2387 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2388 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2389
2390 /*
2391 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2392 * 5705 A0 and A1 chips.
2393 */
2394 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
2395 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2396 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2397 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)
2398 sc->bge_flags |= BGE_FLAG_WIRESPEED;
2399
2400 if (bge_has_eaddr(sc))
2401 sc->bge_flags |= BGE_FLAG_EADDR;
2402
2403 /* Save chipset family. */
2404 switch (sc->bge_asicrev) {
2405 case BGE_ASICREV_BCM5700:
2406 case BGE_ASICREV_BCM5701:
2407 case BGE_ASICREV_BCM5703:
2408 case BGE_ASICREV_BCM5704:
2409 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2410 break;
2411 case BGE_ASICREV_BCM5714_A0:
2412 case BGE_ASICREV_BCM5780:
2413 case BGE_ASICREV_BCM5714:
2414 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */;
2415 /* FALLTHRU */
2416 case BGE_ASICREV_BCM5750:
2417 case BGE_ASICREV_BCM5752:
2418 case BGE_ASICREV_BCM5755:
2419 case BGE_ASICREV_BCM5787:
2420 case BGE_ASICREV_BCM5906:
2421 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2422 /* FALLTHRU */
2423 case BGE_ASICREV_BCM5705:
2424 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2425 break;
2426 }
2427
2428 /* Set various bug flags. */
2429 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2430 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2431 sc->bge_flags |= BGE_FLAG_CRC_BUG;
2432 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2433 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2434 sc->bge_flags |= BGE_FLAG_ADC_BUG;
2435 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2436 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
2437 if (BGE_IS_5705_PLUS(sc) &&
2438 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
2439 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2440 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2441 if (sc->bge_chipid != BGE_CHIPID_BCM5722_A0)
2442 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
2443 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
2444 sc->bge_flags |= BGE_FLAG_BER_BUG;
2445 }
2446
2447
2448 /*
2449 * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe()
2450 * but I do not know the DEVICEID for the 5788M.
2451 */
2452 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID;
2453 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2454 misccfg == BGE_MISCCFG_BOARD_ID_5788M)
2455 sc->bge_flags |= BGE_FLAG_5788;
2456
2457 /*
2458 * Check if this is a PCI-X or PCI Express device.
2459 */
2460#if __FreeBSD_version > 602101
2461 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
2462 /*
2463 * Found a PCI Express capabilities register, this
2464 * must be a PCI Express device.
2465 */
2466 if (reg != 0)
2467 sc->bge_flags |= BGE_FLAG_PCIE;
2468 } else if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) {
2469 if (reg != 0)
2470 sc->bge_flags |= BGE_FLAG_PCIX;
2471 }
2472
2473#else
2474 if (BGE_IS_5705_PLUS(sc)) {
2475 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
2476 if ((reg & 0xFF) == BGE_PCIE_CAPID)
2477 sc->bge_flags |= BGE_FLAG_PCIE;
2478 } else {
2479 /*
2480 * Check if the device is in PCI-X Mode.
2481 * (This bit is not valid on PCI Express controllers.)
2482 */
2483 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2484 BGE_PCISTATE_PCI_BUSMODE) == 0)
2485 sc->bge_flags |= BGE_FLAG_PCIX;
2486 }
2487#endif
2488
2489#if __FreeBSD_version > 602105
2490 {
2491 int msicount;
2492
2493 /*
2494 * Allocate the interrupt, using MSI if possible. These devices
2495 * support 8 MSI messages, but only the first one is used in
2496 * normal operation.
2497 */
2498 if (bge_can_use_msi(sc)) {
2499 msicount = pci_msi_count(dev);
2500 if (msicount > 1)
2501 msicount = 1;
2502 } else
2503 msicount = 0;
2504 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
2505 rid = 1;
2506 sc->bge_flags |= BGE_FLAG_MSI;
2507 } else
2508 rid = 0;
2509 }
2510#else
2511 rid = 0;
2512#endif
2513
2514 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2515 RF_SHAREABLE | RF_ACTIVE);
2516
2517 if (sc->bge_irq == NULL) {
2518 device_printf(sc->bge_dev, "couldn't map interrupt\n");
2519 error = ENXIO;
2520 goto fail;
2521 }
2522
2523 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
2524
2525 /* Try to reset the chip. */
2526 if (bge_reset(sc)) {
2527 device_printf(sc->bge_dev, "chip reset failed\n");
2528 error = ENXIO;
2529 goto fail;
2530 }
2531
2532 sc->bge_asf_mode = 0;
2533 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
2534 == BGE_MAGIC_NUMBER)) {
2535 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
2536 & BGE_HWCFG_ASF) {
2537 sc->bge_asf_mode |= ASF_ENABLE;
2538 sc->bge_asf_mode |= ASF_STACKUP;
2539 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
2540 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
2541 }
2542 }
2543 }
2544
2545 /* Try to reset the chip again the nice way. */
2546 bge_stop_fw(sc);
2547 bge_sig_pre_reset(sc, BGE_RESET_STOP);
2548 if (bge_reset(sc)) {
2549 device_printf(sc->bge_dev, "chip reset failed\n");
2550 error = ENXIO;
2551 goto fail;
2552 }
2553
2554 bge_sig_legacy(sc, BGE_RESET_STOP);
2555 bge_sig_post_reset(sc, BGE_RESET_STOP);
2556
2557 if (bge_chipinit(sc)) {
2558 device_printf(sc->bge_dev, "chip initialization failed\n");
2559 error = ENXIO;
2560 goto fail;
2561 }
2562
2563 error = bge_get_eaddr(sc, eaddr);
2564 if (error) {
2565 device_printf(sc->bge_dev,
2566 "failed to read station address\n");
2567 error = ENXIO;
2568 goto fail;
2569 }
2570
2571 /* 5705 limits RX return ring to 512 entries. */
2572 if (BGE_IS_5705_PLUS(sc))
2573 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2574 else
2575 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2576
2577 if (bge_dma_alloc(dev)) {
2578 device_printf(sc->bge_dev,
2579 "failed to allocate DMA resources\n");
2580 error = ENXIO;
2581 goto fail;
2582 }
2583
2584 /* Set default tuneable values. */
2585 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2586 sc->bge_rx_coal_ticks = 150;
2587 sc->bge_tx_coal_ticks = 150;
2588 sc->bge_rx_max_coal_bds = 10;
2589 sc->bge_tx_max_coal_bds = 10;
2590
2591 /* Set up ifnet structure */
2592 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
2593 if (ifp == NULL) {
2594 device_printf(sc->bge_dev, "failed to if_alloc()\n");
2595 error = ENXIO;
2596 goto fail;
2597 }
2598 ifp->if_softc = sc;
2599 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2600 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2601 ifp->if_ioctl = bge_ioctl;
2602 ifp->if_start = bge_start;
2603 ifp->if_init = bge_init;
2604 ifp->if_mtu = ETHERMTU;
2605 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
2606 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2607 IFQ_SET_READY(&ifp->if_snd);
2608 ifp->if_hwassist = BGE_CSUM_FEATURES;
2609 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
2610 IFCAP_VLAN_MTU;
2611#ifdef IFCAP_VLAN_HWCSUM
2612 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2613#endif
2614 ifp->if_capenable = ifp->if_capabilities;
2615#ifdef DEVICE_POLLING
2616 ifp->if_capabilities |= IFCAP_POLLING;
2617#endif
2618
2619 /*
2620 * 5700 B0 chips do not support checksumming correctly due
2621 * to hardware bugs.
2622 */
2623 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
2624 ifp->if_capabilities &= ~IFCAP_HWCSUM;
2625 ifp->if_capenable &= IFCAP_HWCSUM;
2626 ifp->if_hwassist = 0;
2627 }
2628
2629 /*
2630 * Figure out what sort of media we have by checking the
2631 * hardware config word in the first 32k of NIC internal memory,
2632 * or fall back to examining the EEPROM if necessary.
2633 * Note: on some BCM5700 cards, this value appears to be unset.
2634 * If that's the case, we have to rely on identifying the NIC
2635 * by its PCI subsystem ID, as we do below for the SysKonnect
2636 * SK-9D41.
2637 */
2638 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2639 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2640 else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
2641 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
2642 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2643 sizeof(hwcfg))) {
2644 device_printf(sc->bge_dev, "failed to read EEPROM\n");
2645 error = ENXIO;
2646 goto fail;
2647 }
2648 hwcfg = ntohl(hwcfg);
2649 }
2650
2651 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2652 sc->bge_flags |= BGE_FLAG_TBI;
2653
2654 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2655 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41)
2656 sc->bge_flags |= BGE_FLAG_TBI;
2657
2658 if (sc->bge_flags & BGE_FLAG_TBI) {
2659 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2660 bge_ifmedia_sts);
2661 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
2662 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2663 0, NULL);
2664 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
2665 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
2666 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2667 } else {
2668 /*
2669 * Do transceiver setup and tell the firmware the
2670 * driver is down so we can try to get access the
2671 * probe if ASF is running. Retry a couple of times
2672 * if we get a conflict with the ASF firmware accessing
2673 * the PHY.
2674 */
2675 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2676again:
2677 bge_asf_driver_up(sc);
2678
2679 trys = 0;
2680 if (mii_phy_probe(dev, &sc->bge_miibus,
2681 bge_ifmedia_upd, bge_ifmedia_sts)) {
2682 if (trys++ < 4) {
2683 device_printf(sc->bge_dev, "Try again\n");
2684 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
2685 BMCR_RESET);
2686 goto again;
2687 }
2688
2689 device_printf(sc->bge_dev, "MII without any PHY!\n");
2690 error = ENXIO;
2691 goto fail;
2692 }
2693
2694 /*
2695 * Now tell the firmware we are going up after probing the PHY
2696 */
2697 if (sc->bge_asf_mode & ASF_STACKUP)
2698 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2699 }
2700
2701 /*
2702 * When using the BCM5701 in PCI-X mode, data corruption has
2703 * been observed in the first few bytes of some received packets.
2704 * Aligning the packet buffer in memory eliminates the corruption.
2705 * Unfortunately, this misaligns the packet payloads. On platforms
2706 * which do not support unaligned accesses, we will realign the
2707 * payloads by copying the received packets.
2708 */
2709 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2710 sc->bge_flags & BGE_FLAG_PCIX)
2711 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2712
2713 /*
2714 * Call MI attach routine.
2715 */
2716 ether_ifattach(ifp, eaddr);
2717 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
2718
2719 /*
2720 * Hookup IRQ last.
2721 */
2722#if __FreeBSD_version > 700030
2723 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2724 NULL, bge_intr, sc, &sc->bge_intrhand);
2725#else
2726 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2727 bge_intr, sc, &sc->bge_intrhand);
2728#endif
2729
2730 if (error) {
2731 bge_detach(dev);
2732 device_printf(sc->bge_dev, "couldn't set up irq\n");
2733 }
2734
2735 bge_add_sysctls(sc);
2736
2737 return (0);
2738
2739fail:
2740 bge_release_resources(sc);
2741
2742 return (error);
2743}
2744
2745static int
2746bge_detach(device_t dev)
2747{
2748 struct bge_softc *sc;
2749 struct ifnet *ifp;
2750
2751 sc = device_get_softc(dev);
2752 ifp = sc->bge_ifp;
2753
2754#ifdef DEVICE_POLLING
2755 if (ifp->if_capenable & IFCAP_POLLING)
2756 ether_poll_deregister(ifp);
2757#endif
2758
2759 BGE_LOCK(sc);
2760 bge_stop(sc);
2761 bge_reset(sc);
2762 BGE_UNLOCK(sc);
2763
2764 callout_drain(&sc->bge_stat_ch);
2765
2766 ether_ifdetach(ifp);
2767
2768 if (sc->bge_flags & BGE_FLAG_TBI) {
2769 ifmedia_removeall(&sc->bge_ifmedia);
2770 } else {
2771 bus_generic_detach(dev);
2772 device_delete_child(dev, sc->bge_miibus);
2773 }
2774
2775 bge_release_resources(sc);
2776
2777 return (0);
2778}
2779
2780static void
2781bge_release_resources(struct bge_softc *sc)
2782{
2783 device_t dev;
2784
2785 dev = sc->bge_dev;
2786
2787 if (sc->bge_intrhand != NULL)
2788 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2789
2790 if (sc->bge_irq != NULL)
2791 bus_release_resource(dev, SYS_RES_IRQ,
2792 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
2793
2794#if __FreeBSD_version > 602105
2795 if (sc->bge_flags & BGE_FLAG_MSI)
2796 pci_release_msi(dev);
2797#endif
2798
2799 if (sc->bge_res != NULL)
2800 bus_release_resource(dev, SYS_RES_MEMORY,
2801 BGE_PCI_BAR0, sc->bge_res);
2802
2803 if (sc->bge_ifp != NULL)
2804 if_free(sc->bge_ifp);
2805
2806 bge_dma_free(sc);
2807
2808 if (mtx_initialized(&sc->bge_mtx)) /* XXX */
2809 BGE_LOCK_DESTROY(sc);
2810}
2811
2812static int
2813bge_reset(struct bge_softc *sc)
2814{
2815 device_t dev;
2816 uint32_t cachesize, command, pcistate, reset, val;
2817 void (*write_op)(struct bge_softc *, int, int);
2818 int i;
2819
2820 dev = sc->bge_dev;
2821
2822 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2823 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
2824 if (sc->bge_flags & BGE_FLAG_PCIE)
2825 write_op = bge_writemem_direct;
2826 else
2827 write_op = bge_writemem_ind;
2828 } else
2829 write_op = bge_writereg_ind;
2830
2831 /* Save some important PCI state. */
2832 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2833 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2834 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2835
2836 pci_write_config(dev, BGE_PCI_MISC_CTL,
2837 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
2838 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
2839
2840 /* Disable fastboot on controllers that support it. */
2841 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2842 sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2843 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2844 if (bootverbose)
2845 device_printf(sc->bge_dev, "Disabling fastboot\n");
2846 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2847 }
2848
2849 /*
2850 * Write the magic number to SRAM at offset 0xB50.
2851 * When firmware finishes its initialization it will
2852 * write ~BGE_MAGIC_NUMBER to the same location.
2853 */
2854 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2855
2856 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
2857
2858 /* XXX: Broadcom Linux driver. */
2859 if (sc->bge_flags & BGE_FLAG_PCIE) {
2860 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
2861 CSR_WRITE_4(sc, 0x7E2C, 0x20);
2862 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2863 /* Prevent PCIE link training during global reset */
2864 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
2865 reset |= 1 << 29;
2866 }
2867 }
2868
2869 /*
2870 * Set GPHY Power Down Override to leave GPHY
2871 * powered up in D0 uninitialized.
2872 */
2873 if (BGE_IS_5705_PLUS(sc))
2874 reset |= 0x04000000;
2875
2876 /* Issue global reset */
2877 write_op(sc, BGE_MISC_CFG, reset);
2878
2879 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2880 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2881 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2882 val | BGE_VCPU_STATUS_DRV_RESET);
2883 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2884 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2885 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2886 }
2887
2888 DELAY(1000);
2889
2890 /* XXX: Broadcom Linux driver. */
2891 if (sc->bge_flags & BGE_FLAG_PCIE) {
2892 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2893 DELAY(500000); /* wait for link training to complete */
2894 val = pci_read_config(dev, 0xC4, 4);
2895 pci_write_config(dev, 0xC4, val | (1 << 15), 4);
2896 }
2897 /*
2898 * Set PCIE max payload size to 128 bytes and clear error
2899 * status.
2900 */
2901 pci_write_config(dev, 0xD8, 0xF5000, 4);
2902 }
2903
2904 /* Reset some of the PCI state that got zapped by reset. */
2905 pci_write_config(dev, BGE_PCI_MISC_CTL,
2906 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
2907 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
2908 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2909 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2910 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
2911
2912 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */
2913 if (BGE_IS_5714_FAMILY(sc)) {
2914 /* This chip disables MSI on reset. */
2915 if (sc->bge_flags & BGE_FLAG_MSI) {
2916 val = pci_read_config(dev, BGE_PCI_MSI_CTL, 2);
2917 pci_write_config(dev, BGE_PCI_MSI_CTL,
2918 val | PCIM_MSICTRL_MSI_ENABLE, 2);
2919 val = CSR_READ_4(sc, BGE_MSI_MODE);
2920 CSR_WRITE_4(sc, BGE_MSI_MODE,
2921 val | BGE_MSIMODE_ENABLE);
2922 }
2923 val = CSR_READ_4(sc, BGE_MARB_MODE);
2924 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2925 } else
2926 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2927
2928 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2929 for (i = 0; i < BGE_TIMEOUT; i++) {
2930 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2931 if (val & BGE_VCPU_STATUS_INIT_DONE)
2932 break;
2933 DELAY(100);
2934 }
2935 if (i == BGE_TIMEOUT) {
2936 device_printf(sc->bge_dev, "reset timed out\n");
2937 return (1);
2938 }
2939 } else {
2940 /*
2941 * Poll until we see the 1's complement of the magic number.
2942 * This indicates that the firmware initialization is complete.
2943 * We expect this to fail if no chip containing the Ethernet
2944 * address is fitted though.
2945 */
2946 for (i = 0; i < BGE_TIMEOUT; i++) {
2947 DELAY(10);
2948 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2949 if (val == ~BGE_MAGIC_NUMBER)
2950 break;
2951 }
2952
2953 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
2954 device_printf(sc->bge_dev, "firmware handshake timed out, "
2955 "found 0x%08x\n", val);
2956 }
2957
2958 /*
2959 * XXX Wait for the value of the PCISTATE register to
2960 * return to its original pre-reset state. This is a
2961 * fairly good indicator of reset completion. If we don't
2962 * wait for the reset to fully complete, trying to read
2963 * from the device's non-PCI registers may yield garbage
2964 * results.
2965 */
2966 for (i = 0; i < BGE_TIMEOUT; i++) {
2967 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2968 break;
2969 DELAY(10);
2970 }
2971
2972 if (sc->bge_flags & BGE_FLAG_PCIE) {
2973 reset = bge_readmem_ind(sc, 0x7C00);
2974 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25));
2975 }
2976
2977 /* Fix up byte swapping. */
2978 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2979 BGE_MODECTL_BYTESWAP_DATA);
2980
2981 /* Tell the ASF firmware we are up */
2982 if (sc->bge_asf_mode & ASF_STACKUP)
2983 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2984
2985 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2986
2987 /*
2988 * The 5704 in TBI mode apparently needs some special
2989 * adjustment to insure the SERDES drive level is set
2990 * to 1.2V.
2991 */
2992 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2993 sc->bge_flags & BGE_FLAG_TBI) {
2994 val = CSR_READ_4(sc, BGE_SERDES_CFG);
2995 val = (val & ~0xFFF) | 0x880;
2996 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
2997 }
2998
2999 /* XXX: Broadcom Linux driver. */
3000 if (sc->bge_flags & BGE_FLAG_PCIE &&
3001 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3002 val = CSR_READ_4(sc, 0x7C00);
3003 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3004 }
3005 DELAY(10000);
3006
3007 return(0);
3008}
3009
3010/*
3011 * Frame reception handling. This is called if there's a frame
3012 * on the receive return list.
3013 *
3014 * Note: we have to be able to handle two possibilities here:
3015 * 1) the frame is from the jumbo receive ring
3016 * 2) the frame is from the standard receive ring
3017 */
3018
3019static void
3020bge_rxeof(struct bge_softc *sc)
3021{
3022 struct ifnet *ifp;
3023 int stdcnt = 0, jumbocnt = 0;
3024
3025 BGE_LOCK_ASSERT(sc);
3026
3027 /* Nothing to do. */
3028 if (sc->bge_rx_saved_considx ==
3029 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
3030 return;
3031
3032 ifp = sc->bge_ifp;
3033
3034 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3035 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3036 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3037 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD);
3038 if (BGE_IS_JUMBO_CAPABLE(sc))
3039 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3040 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTREAD);
3041
3042 while(sc->bge_rx_saved_considx !=
3043 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
3044 struct bge_rx_bd *cur_rx;
3045 uint32_t rxidx;
3046 struct mbuf *m = NULL;
3047 uint16_t vlan_tag = 0;
3048 int have_tag = 0;
3049
3050#ifdef DEVICE_POLLING
3051 if (ifp->if_capenable & IFCAP_POLLING) {
3052 if (sc->rxcycles <= 0)
3053 break;
3054 sc->rxcycles--;
3055 }
3056#endif
3057
3058 cur_rx =
3059 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
3060
3061 rxidx = cur_rx->bge_idx;
3062 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
3063
3064 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
3065 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3066 have_tag = 1;
3067 vlan_tag = cur_rx->bge_vlan_tag;
3068 }
3069
3070 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3071 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3072 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
3073 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx],
3074 BUS_DMASYNC_POSTREAD);
3075 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
3076 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]);
3077 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3078 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
3079 jumbocnt++;
3080 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3081 ifp->if_ierrors++;
3082 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
3083 continue;
3084 }
3085 if (bge_newbuf_jumbo(sc,
3086 sc->bge_jumbo, NULL) == ENOBUFS) {
3087 ifp->if_ierrors++;
3088 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
3089 continue;
3090 }
3091 } else {
3092 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3093 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
3094 sc->bge_cdata.bge_rx_std_dmamap[rxidx],
3095 BUS_DMASYNC_POSTREAD);
3096 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
3097 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
3098 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3099 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
3100 stdcnt++;
3101 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3102 ifp->if_ierrors++;
3103 bge_newbuf_std(sc, sc->bge_std, m);
3104 continue;
3105 }
3106 if (bge_newbuf_std(sc, sc->bge_std,
3107 NULL) == ENOBUFS) {
3108 ifp->if_ierrors++;
3109 bge_newbuf_std(sc, sc->bge_std, m);
3110 continue;
3111 }
3112 }
3113
3114 ifp->if_ipackets++;
3115#ifndef __NO_STRICT_ALIGNMENT
3116 /*
3117 * For architectures with strict alignment we must make sure
3118 * the payload is aligned.
3119 */
3120 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3121 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3122 cur_rx->bge_len);
3123 m->m_data += ETHER_ALIGN;
3124 }
3125#endif
3126 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3127 m->m_pkthdr.rcvif = ifp;
3128
3129 if (ifp->if_capenable & IFCAP_RXCSUM) {
3130 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3131 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3132 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3133 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3134 }
3135 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3136 m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3137 m->m_pkthdr.csum_data =
3138 cur_rx->bge_tcp_udp_csum;
3139 m->m_pkthdr.csum_flags |=
3140 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3141 }
3142 }
3143
3144 /*
3145 * If we received a packet with a vlan tag,
3146 * attach that information to the packet.
3147 */
3148 if (have_tag) {
3149#if __FreeBSD_version > 700022
3150 m->m_pkthdr.ether_vtag = vlan_tag;
3151 m->m_flags |= M_VLANTAG;
3152#else
3153 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag);
3154 if (m == NULL)
3155 continue;
3156#endif
3157 }
3158
3159 BGE_UNLOCK(sc);
3160 (*ifp->if_input)(ifp, m);
3161 BGE_LOCK(sc);
3162 }
3163
3164 if (stdcnt > 0)
3165 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3166 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3167
3168 if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0)
3169 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3170 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3171
3172 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3173 if (stdcnt)
3174 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3175 if (jumbocnt)
3176 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3177#ifdef notyet
3178 /*
3179 * This register wraps very quickly under heavy packet drops.
3180 * If you need correct statistics, you can enable this check.
3181 */
3182 if (BGE_IS_5705_PLUS(sc))
3183 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3184#endif
3185}
3186
3187static void
3188bge_txeof(struct bge_softc *sc)
3189{
3190 struct bge_tx_bd *cur_tx = NULL;
3191 struct ifnet *ifp;
3192
3193 BGE_LOCK_ASSERT(sc);
3194
3195 /* Nothing to do. */
3196 if (sc->bge_tx_saved_considx ==
3197 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
3198 return;
3199
3200 ifp = sc->bge_ifp;
3201
3202 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3203 sc->bge_cdata.bge_tx_ring_map,
3204 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3205 /*
3206 * Go through our tx ring and free mbufs for those
3207 * frames that have been sent.
3208 */
3209 while (sc->bge_tx_saved_considx !=
3210 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
3211 uint32_t idx = 0;
3212
3213 idx = sc->bge_tx_saved_considx;
3214 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3215 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3216 ifp->if_opackets++;
3217 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3218 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
3219 sc->bge_cdata.bge_tx_dmamap[idx],
3220 BUS_DMASYNC_POSTWRITE);
3221 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
3222 sc->bge_cdata.bge_tx_dmamap[idx]);
3223 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3224 sc->bge_cdata.bge_tx_chain[idx] = NULL;
3225 }
3226 sc->bge_txcnt--;
3227 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3228 }
3229
3230 if (cur_tx != NULL)
3231 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3232 if (sc->bge_txcnt == 0)
3233 sc->bge_timer = 0;
3234}
3235
3236#ifdef DEVICE_POLLING
3237static void
3238bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3239{
3240 struct bge_softc *sc = ifp->if_softc;
3241 uint32_t statusword;
3242
3243 BGE_LOCK(sc);
3244 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3245 BGE_UNLOCK(sc);
3246 return;
3247 }
3248
3249 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3250 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD);
3251
3252 statusword = atomic_readandclear_32(
3253 &sc->bge_ldata.bge_status_block->bge_status);
3254
3255 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3256 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD);
3257
3258 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3259 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3260 sc->bge_link_evt++;
3261
3262 if (cmd == POLL_AND_CHECK_STATUS)
3263 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3264 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3265 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3266 bge_link_upd(sc);
3267
3268 sc->rxcycles = count;
3269 bge_rxeof(sc);
3270 bge_txeof(sc);
3271 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3272 bge_start_locked(ifp);
3273
3274 BGE_UNLOCK(sc);
3275}
3276#endif /* DEVICE_POLLING */
3277
3278static void
3279bge_intr(void *xsc)
3280{
3281 struct bge_softc *sc;
3282 struct ifnet *ifp;
3283 uint32_t statusword;
3284
3285 sc = xsc;
3286
3287 BGE_LOCK(sc);
3288
3289 ifp = sc->bge_ifp;
3290
3291#ifdef DEVICE_POLLING
3292 if (ifp->if_capenable & IFCAP_POLLING) {
3293 BGE_UNLOCK(sc);
3294 return;
3295 }
3296#endif
3297
3298 /*
3299 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
3300 * disable interrupts by writing nonzero like we used to, since with
3301 * our current organization this just gives complications and
3302 * pessimizations for re-enabling interrupts. We used to have races
3303 * instead of the necessary complications. Disabling interrupts
3304 * would just reduce the chance of a status update while we are
3305 * running (by switching to the interrupt-mode coalescence
3306 * parameters), but this chance is already very low so it is more
3307 * efficient to get another interrupt than prevent it.
3308 *
3309 * We do the ack first to ensure another interrupt if there is a
3310 * status update after the ack. We don't check for the status
3311 * changing later because it is more efficient to get another
3312 * interrupt than prevent it, not quite as above (not checking is
3313 * a smaller optimization than not toggling the interrupt enable,
3314 * since checking doesn't involve PCI accesses and toggling require
3315 * the status check). So toggling would probably be a pessimization
3316 * even with MSI. It would only be needed for using a task queue.
3317 */
3318 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3319
3320 /*
3321 * Do the mandatory PCI flush as well as get the link status.
3322 */
3323 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
3324
3325 /* Make sure the descriptor ring indexes are coherent. */
3326 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3327 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD);
3328 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3329 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD);
3330
3331 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3332 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3333 statusword || sc->bge_link_evt)
3334 bge_link_upd(sc);
3335
3336 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3337 /* Check RX return ring producer/consumer. */
3338 bge_rxeof(sc);
3339
3340 /* Check TX ring producer/consumer. */
3341 bge_txeof(sc);
3342 }
3343
3344 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3345 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3346 bge_start_locked(ifp);
3347
3348 BGE_UNLOCK(sc);
3349}
3350
3351static void
3352bge_asf_driver_up(struct bge_softc *sc)
3353{
3354 if (sc->bge_asf_mode & ASF_STACKUP) {
3355 /* Send ASF heartbeat aprox. every 2s */
3356 if (sc->bge_asf_count)
3357 sc->bge_asf_count --;
3358 else {
3359 sc->bge_asf_count = 5;
3360 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
3361 BGE_FW_DRV_ALIVE);
3362 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
3363 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
3364 CSR_WRITE_4(sc, BGE_CPU_EVENT,
3365 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
3366 }
3367 }
3368}
3369
3370static void
3371bge_tick(void *xsc)
3372{
3373 struct bge_softc *sc = xsc;
3374 struct mii_data *mii = NULL;
3375
3376 BGE_LOCK_ASSERT(sc);
3377
3378 /* Synchronize with possible callout reset/stop. */
3379 if (callout_pending(&sc->bge_stat_ch) ||
3380 !callout_active(&sc->bge_stat_ch))
3381 return;
3382
3383 if (BGE_IS_5705_PLUS(sc))
3384 bge_stats_update_regs(sc);
3385 else
3386 bge_stats_update(sc);
3387
3388 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3389 mii = device_get_softc(sc->bge_miibus);
| 36
37/*
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
45 * frames, highly configurable RX filtering, and 16 RX and TX queues
46 * (which, along with RX filter rules, can be used for QOS applications).
47 * Other features, such as TCP segmentation, may be available as part
48 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
49 * firmware images can be stored in hardware and need not be compiled
50 * into the driver.
51 *
52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
54 *
55 * The BCM5701 is a single-chip solution incorporating both the BCM5700
56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
57 * does not support external SSRAM.
58 *
59 * Broadcom also produces a variation of the BCM5700 under the "Altima"
60 * brand name, which is functionally similar but lacks PCI-X support.
61 *
62 * Without external SSRAM, you can only have at most 4 TX rings,
63 * and the use of the mini RX ring is disabled. This seems to imply
64 * that these features are simply not available on the BCM5701. As a
65 * result, this driver does not implement any support for the mini RX
66 * ring.
67 */
68
69#ifdef HAVE_KERNEL_OPTION_HEADERS
70#include "opt_device_polling.h"
71#endif
72
73#include <sys/param.h>
74#include <sys/endian.h>
75#include <sys/systm.h>
76#include <sys/sockio.h>
77#include <sys/mbuf.h>
78#include <sys/malloc.h>
79#include <sys/kernel.h>
80#include <sys/module.h>
81#include <sys/socket.h>
82#include <sys/sysctl.h>
83
84#include <net/if.h>
85#include <net/if_arp.h>
86#include <net/ethernet.h>
87#include <net/if_dl.h>
88#include <net/if_media.h>
89
90#include <net/bpf.h>
91
92#include <net/if_types.h>
93#include <net/if_vlan_var.h>
94
95#include <netinet/in_systm.h>
96#include <netinet/in.h>
97#include <netinet/ip.h>
98
99#include <machine/bus.h>
100#include <machine/resource.h>
101#include <sys/bus.h>
102#include <sys/rman.h>
103
104#include <dev/mii/mii.h>
105#include <dev/mii/miivar.h>
106#include "miidevs.h"
107#include <dev/mii/brgphyreg.h>
108
109#ifdef __sparc64__
110#include <dev/ofw/ofw_bus.h>
111#include <dev/ofw/openfirm.h>
112#include <machine/ofw_machdep.h>
113#include <machine/ver.h>
114#endif
115
116#include <dev/pci/pcireg.h>
117#include <dev/pci/pcivar.h>
118
119#include <dev/bge/if_bgereg.h>
120
121#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
122#define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
123
124MODULE_DEPEND(bge, pci, 1, 1, 1);
125MODULE_DEPEND(bge, ether, 1, 1, 1);
126MODULE_DEPEND(bge, miibus, 1, 1, 1);
127
128/* "device miibus" required. See GENERIC if you get errors here. */
129#include "miibus_if.h"
130
131/*
132 * Various supported device vendors/types and their names. Note: the
133 * spec seems to indicate that the hardware still has Alteon's vendor
134 * ID burned into it, though it will always be overriden by the vendor
135 * ID in the EEPROM. Just to be safe, we cover all possibilities.
136 */
137static struct bge_type {
138 uint16_t bge_vid;
139 uint16_t bge_did;
140} bge_devs[] = {
141 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 },
142 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 },
143
144 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 },
145 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 },
146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 },
147
148 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 },
149
150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 },
151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 },
152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 },
153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT },
154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X },
155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT },
157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C },
159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT },
161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 },
173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },
177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 },
179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M },
180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 },
181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F },
182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M },
183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 },
184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M },
185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 },
186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M },
187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 },
190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 },
191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 },
192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 },
193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M },
194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 },
195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 },
196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 },
197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 },
198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M },
199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 },
200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M },
201
202 { SK_VENDORID, SK_DEVICEID_ALTIMA },
203
204 { TC_VENDORID, TC_DEVICEID_3C996 },
205
206 { 0, 0 }
207};
208
209static const struct bge_vendor {
210 uint16_t v_id;
211 const char *v_name;
212} bge_vendors[] = {
213 { ALTEON_VENDORID, "Alteon" },
214 { ALTIMA_VENDORID, "Altima" },
215 { APPLE_VENDORID, "Apple" },
216 { BCOM_VENDORID, "Broadcom" },
217 { SK_VENDORID, "SysKonnect" },
218 { TC_VENDORID, "3Com" },
219
220 { 0, NULL }
221};
222
223static const struct bge_revision {
224 uint32_t br_chipid;
225 const char *br_name;
226} bge_revisions[] = {
227 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
228 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
229 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
230 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
231 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
232 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
233 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
234 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
235 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
236 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
237 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
238 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
239 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
240 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
241 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
242 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
243 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
244 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
245 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
246 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
247 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
248 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
249 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
250 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
251 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
252 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
253 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
254 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
255 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
256 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
257 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
258 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
259 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
260 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
261 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
262 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
263 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
264 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
265 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
266 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
267 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
268 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
269 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
270 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
271 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
272 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
273 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
274 /* 5754 and 5787 share the same ASIC ID */
275 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
276 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
277 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
278 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
279 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
280
281 { 0, NULL }
282};
283
284/*
285 * Some defaults for major revisions, so that newer steppings
286 * that we don't know about have a shot at working.
287 */
288static const struct bge_revision bge_majorrevs[] = {
289 { BGE_ASICREV_BCM5700, "unknown BCM5700" },
290 { BGE_ASICREV_BCM5701, "unknown BCM5701" },
291 { BGE_ASICREV_BCM5703, "unknown BCM5703" },
292 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
293 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
294 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
295 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
296 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
297 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
298 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
299 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
300 /* 5754 and 5787 share the same ASIC ID */
301 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
302 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
303
304 { 0, NULL }
305};
306
307#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
308#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
309#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
310#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
311#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
312
313const struct bge_revision * bge_lookup_rev(uint32_t);
314const struct bge_vendor * bge_lookup_vendor(uint16_t);
315
316typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
317
318static int bge_probe(device_t);
319static int bge_attach(device_t);
320static int bge_detach(device_t);
321static int bge_suspend(device_t);
322static int bge_resume(device_t);
323static void bge_release_resources(struct bge_softc *);
324static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
325static int bge_dma_alloc(device_t);
326static void bge_dma_free(struct bge_softc *);
327
328static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
329static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
330static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
331static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
332static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
333
334static void bge_txeof(struct bge_softc *);
335static void bge_rxeof(struct bge_softc *);
336
337static void bge_asf_driver_up (struct bge_softc *);
338static void bge_tick(void *);
339static void bge_stats_update(struct bge_softc *);
340static void bge_stats_update_regs(struct bge_softc *);
341static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
342
343static void bge_intr(void *);
344static void bge_start_locked(struct ifnet *);
345static void bge_start(struct ifnet *);
346static int bge_ioctl(struct ifnet *, u_long, caddr_t);
347static void bge_init_locked(struct bge_softc *);
348static void bge_init(void *);
349static void bge_stop(struct bge_softc *);
350static void bge_watchdog(struct bge_softc *);
351static void bge_shutdown(device_t);
352static int bge_ifmedia_upd_locked(struct ifnet *);
353static int bge_ifmedia_upd(struct ifnet *);
354static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
355
356static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
357static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
358
359static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
360static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
361
362static void bge_setpromisc(struct bge_softc *);
363static void bge_setmulti(struct bge_softc *);
364static void bge_setvlan(struct bge_softc *);
365
366static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
367static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
368static int bge_init_rx_ring_std(struct bge_softc *);
369static void bge_free_rx_ring_std(struct bge_softc *);
370static int bge_init_rx_ring_jumbo(struct bge_softc *);
371static void bge_free_rx_ring_jumbo(struct bge_softc *);
372static void bge_free_tx_ring(struct bge_softc *);
373static int bge_init_tx_ring(struct bge_softc *);
374
375static int bge_chipinit(struct bge_softc *);
376static int bge_blockinit(struct bge_softc *);
377
378static int bge_has_eaddr(struct bge_softc *);
379static uint32_t bge_readmem_ind(struct bge_softc *, int);
380static void bge_writemem_ind(struct bge_softc *, int, int);
381static void bge_writembx(struct bge_softc *, int, int);
382#ifdef notdef
383static uint32_t bge_readreg_ind(struct bge_softc *, int);
384#endif
385static void bge_writemem_direct(struct bge_softc *, int, int);
386static void bge_writereg_ind(struct bge_softc *, int, int);
387
388static int bge_miibus_readreg(device_t, int, int);
389static int bge_miibus_writereg(device_t, int, int, int);
390static void bge_miibus_statchg(device_t);
391#ifdef DEVICE_POLLING
392static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
393#endif
394
395#define BGE_RESET_START 1
396#define BGE_RESET_STOP 2
397static void bge_sig_post_reset(struct bge_softc *, int);
398static void bge_sig_legacy(struct bge_softc *, int);
399static void bge_sig_pre_reset(struct bge_softc *, int);
400static int bge_reset(struct bge_softc *);
401static void bge_link_upd(struct bge_softc *);
402
403/*
404 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may
405 * leak information to untrusted users. It is also known to cause alignment
406 * traps on certain architectures.
407 */
408#ifdef BGE_REGISTER_DEBUG
409static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
410static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
411static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
412#endif
413static void bge_add_sysctls(struct bge_softc *);
414static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
415
416static device_method_t bge_methods[] = {
417 /* Device interface */
418 DEVMETHOD(device_probe, bge_probe),
419 DEVMETHOD(device_attach, bge_attach),
420 DEVMETHOD(device_detach, bge_detach),
421 DEVMETHOD(device_shutdown, bge_shutdown),
422 DEVMETHOD(device_suspend, bge_suspend),
423 DEVMETHOD(device_resume, bge_resume),
424
425 /* bus interface */
426 DEVMETHOD(bus_print_child, bus_generic_print_child),
427 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
428
429 /* MII interface */
430 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
431 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
432 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
433
434 { 0, 0 }
435};
436
437static driver_t bge_driver = {
438 "bge",
439 bge_methods,
440 sizeof(struct bge_softc)
441};
442
443static devclass_t bge_devclass;
444
445DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
446DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
447
448static int bge_allow_asf = 1;
449
450TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
451
452SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
453SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
454 "Allow ASF mode if available");
455
456#define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500"
457#define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2"
458#define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500"
459#define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3"
460#define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id"
461
462static int
463bge_has_eaddr(struct bge_softc *sc)
464{
465#ifdef __sparc64__
466 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
467 device_t dev;
468 uint32_t subvendor;
469
470 dev = sc->bge_dev;
471
472 /*
473 * The on-board BGEs found in sun4u machines aren't fitted with
474 * an EEPROM which means that we have to obtain the MAC address
475 * via OFW and that some tests will always fail. We distinguish
476 * such BGEs by the subvendor ID, which also has to be obtained
477 * from OFW instead of the PCI configuration space as the latter
478 * indicates Broadcom as the subvendor of the netboot interface.
479 * For early Blade 1500 and 2500 we even have to check the OFW
480 * device path as the subvendor ID always defaults to Broadcom
481 * there.
482 */
483 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
484 &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
485 subvendor == SUN_VENDORID)
486 return (0);
487 memset(buf, 0, sizeof(buf));
488 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
489 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
490 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
491 return (0);
492 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
493 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
494 return (0);
495 }
496#endif
497 return (1);
498}
499
500static uint32_t
501bge_readmem_ind(struct bge_softc *sc, int off)
502{
503 device_t dev;
504 uint32_t val;
505
506 dev = sc->bge_dev;
507
508 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
509 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
510 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
511 return (val);
512}
513
514static void
515bge_writemem_ind(struct bge_softc *sc, int off, int val)
516{
517 device_t dev;
518
519 dev = sc->bge_dev;
520
521 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
522 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
523 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
524}
525
526#ifdef notdef
527static uint32_t
528bge_readreg_ind(struct bge_softc *sc, int off)
529{
530 device_t dev;
531
532 dev = sc->bge_dev;
533
534 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
535 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
536}
537#endif
538
539static void
540bge_writereg_ind(struct bge_softc *sc, int off, int val)
541{
542 device_t dev;
543
544 dev = sc->bge_dev;
545
546 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
547 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
548}
549
550static void
551bge_writemem_direct(struct bge_softc *sc, int off, int val)
552{
553 CSR_WRITE_4(sc, off, val);
554}
555
556static void
557bge_writembx(struct bge_softc *sc, int off, int val)
558{
559 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
560 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
561
562 CSR_WRITE_4(sc, off, val);
563}
564
565/*
566 * Map a single buffer address.
567 */
568
569static void
570bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
571{
572 struct bge_dmamap_arg *ctx;
573
574 if (error)
575 return;
576
577 ctx = arg;
578
579 if (nseg > ctx->bge_maxsegs) {
580 ctx->bge_maxsegs = 0;
581 return;
582 }
583
584 ctx->bge_busaddr = segs->ds_addr;
585}
586
587static uint8_t
588bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
589{
590 uint32_t access, byte = 0;
591 int i;
592
593 /* Lock. */
594 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
595 for (i = 0; i < 8000; i++) {
596 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
597 break;
598 DELAY(20);
599 }
600 if (i == 8000)
601 return (1);
602
603 /* Enable access. */
604 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
605 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
606
607 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
608 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
609 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
610 DELAY(10);
611 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
612 DELAY(10);
613 break;
614 }
615 }
616
617 if (i == BGE_TIMEOUT * 10) {
618 if_printf(sc->bge_ifp, "nvram read timed out\n");
619 return (1);
620 }
621
622 /* Get result. */
623 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
624
625 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
626
627 /* Disable access. */
628 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
629
630 /* Unlock. */
631 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
632 CSR_READ_4(sc, BGE_NVRAM_SWARB);
633
634 return (0);
635}
636
637/*
638 * Read a sequence of bytes from NVRAM.
639 */
640static int
641bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
642{
643 int err = 0, i;
644 uint8_t byte = 0;
645
646 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
647 return (1);
648
649 for (i = 0; i < cnt; i++) {
650 err = bge_nvram_getbyte(sc, off + i, &byte);
651 if (err)
652 break;
653 *(dest + i) = byte;
654 }
655
656 return (err ? 1 : 0);
657}
658
659/*
660 * Read a byte of data stored in the EEPROM at address 'addr.' The
661 * BCM570x supports both the traditional bitbang interface and an
662 * auto access interface for reading the EEPROM. We use the auto
663 * access method.
664 */
665static uint8_t
666bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
667{
668 int i;
669 uint32_t byte = 0;
670
671 /*
672 * Enable use of auto EEPROM access so we can avoid
673 * having to use the bitbang method.
674 */
675 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
676
677 /* Reset the EEPROM, load the clock period. */
678 CSR_WRITE_4(sc, BGE_EE_ADDR,
679 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
680 DELAY(20);
681
682 /* Issue the read EEPROM command. */
683 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
684
685 /* Wait for completion */
686 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
687 DELAY(10);
688 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
689 break;
690 }
691
692 if (i == BGE_TIMEOUT * 10) {
693 device_printf(sc->bge_dev, "EEPROM read timed out\n");
694 return (1);
695 }
696
697 /* Get result. */
698 byte = CSR_READ_4(sc, BGE_EE_DATA);
699
700 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
701
702 return (0);
703}
704
705/*
706 * Read a sequence of bytes from the EEPROM.
707 */
708static int
709bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
710{
711 int i, error = 0;
712 uint8_t byte = 0;
713
714 for (i = 0; i < cnt; i++) {
715 error = bge_eeprom_getbyte(sc, off + i, &byte);
716 if (error)
717 break;
718 *(dest + i) = byte;
719 }
720
721 return (error ? 1 : 0);
722}
723
724static int
725bge_miibus_readreg(device_t dev, int phy, int reg)
726{
727 struct bge_softc *sc;
728 uint32_t val, autopoll;
729 int i;
730
731 sc = device_get_softc(dev);
732
733 /*
734 * Broadcom's own driver always assumes the internal
735 * PHY is at GMII address 1. On some chips, the PHY responds
736 * to accesses at all addresses, which could cause us to
737 * bogusly attach the PHY 32 times at probe type. Always
738 * restricting the lookup to address 1 is simpler than
739 * trying to figure out which chips revisions should be
740 * special-cased.
741 */
742 if (phy != 1)
743 return (0);
744
745 /* Reading with autopolling on may trigger PCI errors */
746 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
747 if (autopoll & BGE_MIMODE_AUTOPOLL) {
748 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
749 DELAY(40);
750 }
751
752 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
753 BGE_MIPHY(phy) | BGE_MIREG(reg));
754
755 for (i = 0; i < BGE_TIMEOUT; i++) {
756 DELAY(10);
757 val = CSR_READ_4(sc, BGE_MI_COMM);
758 if (!(val & BGE_MICOMM_BUSY))
759 break;
760 }
761
762 if (i == BGE_TIMEOUT) {
763 device_printf(sc->bge_dev,
764 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
765 phy, reg, val);
766 val = 0;
767 goto done;
768 }
769
770 DELAY(5);
771 val = CSR_READ_4(sc, BGE_MI_COMM);
772
773done:
774 if (autopoll & BGE_MIMODE_AUTOPOLL) {
775 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
776 DELAY(40);
777 }
778
779 if (val & BGE_MICOMM_READFAIL)
780 return (0);
781
782 return (val & 0xFFFF);
783}
784
785static int
786bge_miibus_writereg(device_t dev, int phy, int reg, int val)
787{
788 struct bge_softc *sc;
789 uint32_t autopoll;
790 int i;
791
792 sc = device_get_softc(dev);
793
794 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
795 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
796 return(0);
797
798 /* Reading with autopolling on may trigger PCI errors */
799 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
800 if (autopoll & BGE_MIMODE_AUTOPOLL) {
801 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
802 DELAY(40);
803 }
804
805 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
806 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
807
808 for (i = 0; i < BGE_TIMEOUT; i++) {
809 DELAY(10);
810 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
811 DELAY(5);
812 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
813 break;
814 }
815 }
816
817 if (i == BGE_TIMEOUT) {
818 device_printf(sc->bge_dev,
819 "PHY write timed out (phy %d, reg %d, val %d)\n",
820 phy, reg, val);
821 return (0);
822 }
823
824 if (autopoll & BGE_MIMODE_AUTOPOLL) {
825 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
826 DELAY(40);
827 }
828
829 return (0);
830}
831
832static void
833bge_miibus_statchg(device_t dev)
834{
835 struct bge_softc *sc;
836 struct mii_data *mii;
837 sc = device_get_softc(dev);
838 mii = device_get_softc(sc->bge_miibus);
839
840 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
841 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
842 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
843 else
844 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
845
846 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
847 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
848 else
849 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
850}
851
852/*
853 * Intialize a standard receive ring descriptor.
854 */
855static int
856bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
857{
858 struct mbuf *m_new = NULL;
859 struct bge_rx_bd *r;
860 struct bge_dmamap_arg ctx;
861 int error;
862
863 if (m == NULL) {
864 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
865 if (m_new == NULL)
866 return (ENOBUFS);
867 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
868 } else {
869 m_new = m;
870 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
871 m_new->m_data = m_new->m_ext.ext_buf;
872 }
873
874 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
875 m_adj(m_new, ETHER_ALIGN);
876 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
877 r = &sc->bge_ldata.bge_rx_std_ring[i];
878 ctx.bge_maxsegs = 1;
879 ctx.sc = sc;
880 error = bus_dmamap_load(sc->bge_cdata.bge_mtag,
881 sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *),
882 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
883 if (error || ctx.bge_maxsegs == 0) {
884 if (m == NULL) {
885 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
886 m_freem(m_new);
887 }
888 return (ENOMEM);
889 }
890 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_busaddr);
891 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_busaddr);
892 r->bge_flags = BGE_RXBDFLAG_END;
893 r->bge_len = m_new->m_len;
894 r->bge_idx = i;
895
896 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
897 sc->bge_cdata.bge_rx_std_dmamap[i],
898 BUS_DMASYNC_PREREAD);
899
900 return (0);
901}
902
903/*
904 * Initialize a jumbo receive ring descriptor. This allocates
905 * a jumbo buffer from the pool managed internally by the driver.
906 */
907static int
908bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
909{
910 bus_dma_segment_t segs[BGE_NSEG_JUMBO];
911 struct bge_extrx_bd *r;
912 struct mbuf *m_new = NULL;
913 int nsegs;
914 int error;
915
916 if (m == NULL) {
917 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
918 if (m_new == NULL)
919 return (ENOBUFS);
920
921 m_cljget(m_new, M_DONTWAIT, MJUM9BYTES);
922 if (!(m_new->m_flags & M_EXT)) {
923 m_freem(m_new);
924 return (ENOBUFS);
925 }
926 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES;
927 } else {
928 m_new = m;
929 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES;
930 m_new->m_data = m_new->m_ext.ext_buf;
931 }
932
933 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
934 m_adj(m_new, ETHER_ALIGN);
935
936 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
937 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
938 m_new, segs, &nsegs, BUS_DMA_NOWAIT);
939 if (error) {
940 if (m == NULL)
941 m_freem(m_new);
942 return (error);
943 }
944 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
945
946 /*
947 * Fill in the extended RX buffer descriptor.
948 */
949 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
950 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
951 r->bge_idx = i;
952 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
953 switch (nsegs) {
954 case 4:
955 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
956 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
957 r->bge_len3 = segs[3].ds_len;
958 case 3:
959 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
960 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
961 r->bge_len2 = segs[2].ds_len;
962 case 2:
963 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
964 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
965 r->bge_len1 = segs[1].ds_len;
966 case 1:
967 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
968 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
969 r->bge_len0 = segs[0].ds_len;
970 break;
971 default:
972 panic("%s: %d segments\n", __func__, nsegs);
973 }
974
975 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
976 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
977 BUS_DMASYNC_PREREAD);
978
979 return (0);
980}
981
982/*
983 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
984 * that's 1MB or memory, which is a lot. For now, we fill only the first
985 * 256 ring entries and hope that our CPU is fast enough to keep up with
986 * the NIC.
987 */
988static int
989bge_init_rx_ring_std(struct bge_softc *sc)
990{
991 int i;
992
993 for (i = 0; i < BGE_SSLOTS; i++) {
994 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
995 return (ENOBUFS);
996 };
997
998 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
999 sc->bge_cdata.bge_rx_std_ring_map,
1000 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1001
1002 sc->bge_std = i - 1;
1003 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1004
1005 return (0);
1006}
1007
1008static void
1009bge_free_rx_ring_std(struct bge_softc *sc)
1010{
1011 int i;
1012
1013 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1014 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1015 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
1016 sc->bge_cdata.bge_rx_std_dmamap[i],
1017 BUS_DMASYNC_POSTREAD);
1018 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1019 sc->bge_cdata.bge_rx_std_dmamap[i]);
1020 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1021 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1022 }
1023 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1024 sizeof(struct bge_rx_bd));
1025 }
1026}
1027
1028static int
1029bge_init_rx_ring_jumbo(struct bge_softc *sc)
1030{
1031 struct bge_rcb *rcb;
1032 int i;
1033
1034 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1035 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1036 return (ENOBUFS);
1037 };
1038
1039 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1040 sc->bge_cdata.bge_rx_jumbo_ring_map,
1041 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1042
1043 sc->bge_jumbo = i - 1;
1044
1045 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1046 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1047 BGE_RCB_FLAG_USE_EXT_RX_BD);
1048 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1049
1050 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1051
1052 return (0);
1053}
1054
1055static void
1056bge_free_rx_ring_jumbo(struct bge_softc *sc)
1057{
1058 int i;
1059
1060 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1061 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1062 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1063 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1064 BUS_DMASYNC_POSTREAD);
1065 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1066 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1067 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1068 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1069 }
1070 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1071 sizeof(struct bge_extrx_bd));
1072 }
1073}
1074
1075static void
1076bge_free_tx_ring(struct bge_softc *sc)
1077{
1078 int i;
1079
1080 if (sc->bge_ldata.bge_tx_ring == NULL)
1081 return;
1082
1083 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1084 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1085 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
1086 sc->bge_cdata.bge_tx_dmamap[i],
1087 BUS_DMASYNC_POSTWRITE);
1088 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1089 sc->bge_cdata.bge_tx_dmamap[i]);
1090 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1091 sc->bge_cdata.bge_tx_chain[i] = NULL;
1092 }
1093 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1094 sizeof(struct bge_tx_bd));
1095 }
1096}
1097
1098static int
1099bge_init_tx_ring(struct bge_softc *sc)
1100{
1101 sc->bge_txcnt = 0;
1102 sc->bge_tx_saved_considx = 0;
1103
1104 /* Initialize transmit producer index for host-memory send ring. */
1105 sc->bge_tx_prodidx = 0;
1106 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1107
1108 /* 5700 b2 errata */
1109 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1110 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1111
1112 /* NIC-memory send ring not used; initialize to zero. */
1113 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1114 /* 5700 b2 errata */
1115 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1116 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1117
1118 return (0);
1119}
1120
1121static void
1122bge_setpromisc(struct bge_softc *sc)
1123{
1124 struct ifnet *ifp;
1125
1126 BGE_LOCK_ASSERT(sc);
1127
1128 ifp = sc->bge_ifp;
1129
1130 /* Enable or disable promiscuous mode as needed. */
1131 if (ifp->if_flags & IFF_PROMISC)
1132 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1133 else
1134 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1135}
1136
1137static void
1138bge_setmulti(struct bge_softc *sc)
1139{
1140 struct ifnet *ifp;
1141 struct ifmultiaddr *ifma;
1142 uint32_t hashes[4] = { 0, 0, 0, 0 };
1143 int h, i;
1144
1145 BGE_LOCK_ASSERT(sc);
1146
1147 ifp = sc->bge_ifp;
1148
1149 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1150 for (i = 0; i < 4; i++)
1151 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1152 return;
1153 }
1154
1155 /* First, zot all the existing filters. */
1156 for (i = 0; i < 4; i++)
1157 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1158
1159 /* Now program new ones. */
1160 IF_ADDR_LOCK(ifp);
1161 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1162 if (ifma->ifma_addr->sa_family != AF_LINK)
1163 continue;
1164 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1165 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1166 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1167 }
1168 IF_ADDR_UNLOCK(ifp);
1169
1170 for (i = 0; i < 4; i++)
1171 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1172}
1173
1174static void
1175bge_setvlan(struct bge_softc *sc)
1176{
1177 struct ifnet *ifp;
1178
1179 BGE_LOCK_ASSERT(sc);
1180
1181 ifp = sc->bge_ifp;
1182
1183 /* Enable or disable VLAN tag stripping as needed. */
1184 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1185 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1186 else
1187 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1188}
1189
1190static void
1191bge_sig_pre_reset(sc, type)
1192 struct bge_softc *sc;
1193 int type;
1194{
1195 /*
1196 * Some chips don't like this so only do this if ASF is enabled
1197 */
1198 if (sc->bge_asf_mode)
1199 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1200
1201 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1202 switch (type) {
1203 case BGE_RESET_START:
1204 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1205 break;
1206 case BGE_RESET_STOP:
1207 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1208 break;
1209 }
1210 }
1211}
1212
1213static void
1214bge_sig_post_reset(sc, type)
1215 struct bge_softc *sc;
1216 int type;
1217{
1218 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1219 switch (type) {
1220 case BGE_RESET_START:
1221 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
1222 /* START DONE */
1223 break;
1224 case BGE_RESET_STOP:
1225 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
1226 break;
1227 }
1228 }
1229}
1230
1231static void
1232bge_sig_legacy(sc, type)
1233 struct bge_softc *sc;
1234 int type;
1235{
1236 if (sc->bge_asf_mode) {
1237 switch (type) {
1238 case BGE_RESET_START:
1239 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1240 break;
1241 case BGE_RESET_STOP:
1242 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1243 break;
1244 }
1245 }
1246}
1247
1248void bge_stop_fw(struct bge_softc *);
1249void
1250bge_stop_fw(sc)
1251 struct bge_softc *sc;
1252{
1253 int i;
1254
1255 if (sc->bge_asf_mode) {
1256 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
1257 CSR_WRITE_4(sc, BGE_CPU_EVENT,
1258 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
1259
1260 for (i = 0; i < 100; i++ ) {
1261 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
1262 break;
1263 DELAY(10);
1264 }
1265 }
1266}
1267
1268/*
1269 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1270 * self-test results.
1271 */
1272static int
1273bge_chipinit(struct bge_softc *sc)
1274{
1275 uint32_t dma_rw_ctl;
1276 int i;
1277
1278 /* Set endianness before we access any non-PCI registers. */
1279 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1280
1281 /*
1282 * Check the 'ROM failed' bit on the RX CPU to see if
1283 * self-tests passed. Skip this check when there's no
1284 * chip containing the Ethernet address fitted, since
1285 * in that case it will always fail.
1286 */
1287 if ((sc->bge_flags & BGE_FLAG_EADDR) &&
1288 CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1289 device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n");
1290 return (ENODEV);
1291 }
1292
1293 /* Clear the MAC control register */
1294 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1295
1296 /*
1297 * Clear the MAC statistics block in the NIC's
1298 * internal memory.
1299 */
1300 for (i = BGE_STATS_BLOCK;
1301 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1302 BGE_MEMWIN_WRITE(sc, i, 0);
1303
1304 for (i = BGE_STATUS_BLOCK;
1305 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1306 BGE_MEMWIN_WRITE(sc, i, 0);
1307
1308 /*
1309 * Set up the PCI DMA control register.
1310 */
1311 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1312 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1313 if (sc->bge_flags & BGE_FLAG_PCIE) {
1314 /* Read watermark not used, 128 bytes for write. */
1315 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1316 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1317 if (BGE_IS_5714_FAMILY(sc)) {
1318 /* 256 bytes for read and write. */
1319 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1320 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1321 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1322 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1323 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1324 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1325 /* 1536 bytes for read, 384 bytes for write. */
1326 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1327 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1328 } else {
1329 /* 384 bytes for read and write. */
1330 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1331 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1332 0x0F;
1333 }
1334 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1335 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1336 uint32_t tmp;
1337
1338 /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1339 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1340 if (tmp == 6 || tmp == 7)
1341 dma_rw_ctl |=
1342 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1343
1344 /* Set PCI-X DMA write workaround. */
1345 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1346 }
1347 } else {
1348 /* Conventional PCI bus: 256 bytes for read and write. */
1349 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1350 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1351
1352 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1353 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1354 dma_rw_ctl |= 0x0F;
1355 }
1356 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1357 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1358 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1359 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1360 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1361 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1362 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1363 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1364
1365 /*
1366 * Set up general mode register.
1367 */
1368 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1369 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1370 BGE_MODECTL_TX_NO_PHDR_CSUM);
1371
1372 /*
1373 * Tell the firmware the driver is running
1374 */
1375 if (sc->bge_asf_mode & ASF_STACKUP)
1376 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1377
1378 /*
1379 * Disable memory write invalidate. Apparently it is not supported
1380 * properly by these devices.
1381 */
1382 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1383
1384 /* Set the timer prescaler (always 66Mhz) */
1385 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1386
1387 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1388 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1389 DELAY(40); /* XXX */
1390
1391 /* Put PHY into ready state */
1392 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1393 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1394 DELAY(40);
1395 }
1396
1397 return (0);
1398}
1399
1400static int
1401bge_blockinit(struct bge_softc *sc)
1402{
1403 struct bge_rcb *rcb;
1404 bus_size_t vrcb;
1405 bge_hostaddr taddr;
1406 uint32_t val;
1407 int i;
1408
1409 /*
1410 * Initialize the memory window pointer register so that
1411 * we can access the first 32K of internal NIC RAM. This will
1412 * allow us to set up the TX send ring RCBs and the RX return
1413 * ring RCBs, plus other things which live in NIC memory.
1414 */
1415 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1416
1417 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1418
1419 if (!(BGE_IS_5705_PLUS(sc))) {
1420 /* Configure mbuf memory pool */
1421 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1422 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1423 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1424 else
1425 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1426
1427 /* Configure DMA resource pool */
1428 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1429 BGE_DMA_DESCRIPTORS);
1430 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1431 }
1432
1433 /* Configure mbuf pool watermarks */
1434 if (!BGE_IS_5705_PLUS(sc)) {
1435 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1436 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1437 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1438 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1439 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1440 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1441 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1442 } else {
1443 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1444 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1445 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1446 }
1447
1448 /* Configure DMA resource watermarks */
1449 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1450 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1451
1452 /* Enable buffer manager */
1453 if (!(BGE_IS_5705_PLUS(sc))) {
1454 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1455 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN);
1456
1457 /* Poll for buffer manager start indication */
1458 for (i = 0; i < BGE_TIMEOUT; i++) {
1459 DELAY(10);
1460 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1461 break;
1462 }
1463
1464 if (i == BGE_TIMEOUT) {
1465 device_printf(sc->bge_dev,
1466 "buffer manager failed to start\n");
1467 return (ENXIO);
1468 }
1469 }
1470
1471 /* Enable flow-through queues */
1472 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1473 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1474
1475 /* Wait until queue initialization is complete */
1476 for (i = 0; i < BGE_TIMEOUT; i++) {
1477 DELAY(10);
1478 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1479 break;
1480 }
1481
1482 if (i == BGE_TIMEOUT) {
1483 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1484 return (ENXIO);
1485 }
1486
1487 /* Initialize the standard RX ring control block */
1488 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1489 rcb->bge_hostaddr.bge_addr_lo =
1490 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1491 rcb->bge_hostaddr.bge_addr_hi =
1492 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1493 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1494 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1495 if (BGE_IS_5705_PLUS(sc))
1496 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1497 else
1498 rcb->bge_maxlen_flags =
1499 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1500 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1501 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1502 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1503
1504 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1505 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1506
1507 /*
1508 * Initialize the jumbo RX ring control block
1509 * We set the 'ring disabled' bit in the flags
1510 * field until we're actually ready to start
1511 * using this ring (i.e. once we set the MTU
1512 * high enough to require it).
1513 */
1514 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1515 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1516
1517 rcb->bge_hostaddr.bge_addr_lo =
1518 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1519 rcb->bge_hostaddr.bge_addr_hi =
1520 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1521 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1522 sc->bge_cdata.bge_rx_jumbo_ring_map,
1523 BUS_DMASYNC_PREREAD);
1524 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1525 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1526 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1527 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1528 rcb->bge_hostaddr.bge_addr_hi);
1529 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1530 rcb->bge_hostaddr.bge_addr_lo);
1531
1532 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1533 rcb->bge_maxlen_flags);
1534 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1535
1536 /* Set up dummy disabled mini ring RCB */
1537 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1538 rcb->bge_maxlen_flags =
1539 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1540 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1541 rcb->bge_maxlen_flags);
1542 }
1543
1544 /*
1545 * Set the BD ring replentish thresholds. The recommended
1546 * values are 1/8th the number of descriptors allocated to
1547 * each ring.
1548 * XXX The 5754 requires a lower threshold, so it might be a
1549 * requirement of all 575x family chips. The Linux driver sets
1550 * the lower threshold for all 5705 family chips as well, but there
1551 * are reports that it might not need to be so strict.
1552 *
1553 * XXX Linux does some extra fiddling here for the 5906 parts as
1554 * well.
1555 */
1556 if (BGE_IS_5705_PLUS(sc))
1557 val = 8;
1558 else
1559 val = BGE_STD_RX_RING_CNT / 8;
1560 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1561 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1562
1563 /*
1564 * Disable all unused send rings by setting the 'ring disabled'
1565 * bit in the flags field of all the TX send ring control blocks.
1566 * These are located in NIC memory.
1567 */
1568 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1569 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1570 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1571 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1572 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1573 vrcb += sizeof(struct bge_rcb);
1574 }
1575
1576 /* Configure TX RCB 0 (we use only the first ring) */
1577 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1578 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1579 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1580 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1581 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1582 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1583 if (!(BGE_IS_5705_PLUS(sc)))
1584 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1585 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1586
1587 /* Disable all unused RX return rings */
1588 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1589 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1590 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1591 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1592 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1593 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1594 BGE_RCB_FLAG_RING_DISABLED));
1595 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1596 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1597 (i * (sizeof(uint64_t))), 0);
1598 vrcb += sizeof(struct bge_rcb);
1599 }
1600
1601 /* Initialize RX ring indexes */
1602 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1603 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1604 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1605
1606 /*
1607 * Set up RX return ring 0
1608 * Note that the NIC address for RX return rings is 0x00000000.
1609 * The return rings live entirely within the host, so the
1610 * nicaddr field in the RCB isn't used.
1611 */
1612 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1613 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1614 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1615 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1616 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1617 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1618 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1619
1620 /* Set random backoff seed for TX */
1621 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1622 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1623 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1624 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1625 BGE_TX_BACKOFF_SEED_MASK);
1626
1627 /* Set inter-packet gap */
1628 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1629
1630 /*
1631 * Specify which ring to use for packets that don't match
1632 * any RX rules.
1633 */
1634 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1635
1636 /*
1637 * Configure number of RX lists. One interrupt distribution
1638 * list, sixteen active lists, one bad frames class.
1639 */
1640 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1641
1642 /* Inialize RX list placement stats mask. */
1643 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1644 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1645
1646 /* Disable host coalescing until we get it set up */
1647 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1648
1649 /* Poll to make sure it's shut down. */
1650 for (i = 0; i < BGE_TIMEOUT; i++) {
1651 DELAY(10);
1652 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1653 break;
1654 }
1655
1656 if (i == BGE_TIMEOUT) {
1657 device_printf(sc->bge_dev,
1658 "host coalescing engine failed to idle\n");
1659 return (ENXIO);
1660 }
1661
1662 /* Set up host coalescing defaults */
1663 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1664 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1665 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1666 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1667 if (!(BGE_IS_5705_PLUS(sc))) {
1668 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1669 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1670 }
1671 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1672 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1673
1674 /* Set up address of statistics block */
1675 if (!(BGE_IS_5705_PLUS(sc))) {
1676 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1677 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1678 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1679 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1680 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1681 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1682 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1683 }
1684
1685 /* Set up address of status block */
1686 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1687 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1688 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1689 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1690 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1691 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1692
1693 /* Turn on host coalescing state machine */
1694 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1695
1696 /* Turn on RX BD completion state machine and enable attentions */
1697 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1698 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
1699
1700 /* Turn on RX list placement state machine */
1701 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1702
1703 /* Turn on RX list selector state machine. */
1704 if (!(BGE_IS_5705_PLUS(sc)))
1705 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1706
1707 /* Turn on DMA, clear stats */
1708 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB |
1709 BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR |
1710 BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB |
1711 BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB |
1712 ((sc->bge_flags & BGE_FLAG_TBI) ?
1713 BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1714
1715 /* Set misc. local control, enable interrupts on attentions */
1716 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1717
1718#ifdef notdef
1719 /* Assert GPIO pins for PHY reset */
1720 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
1721 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
1722 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
1723 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
1724#endif
1725
1726 /* Turn on DMA completion state machine */
1727 if (!(BGE_IS_5705_PLUS(sc)))
1728 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1729
1730 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
1731
1732 /* Enable host coalescing bug fix. */
1733 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1734 sc->bge_asicrev == BGE_ASICREV_BCM5787)
1735 val |= 1 << 29;
1736
1737 /* Turn on write DMA state machine */
1738 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1739
1740 /* Turn on read DMA state machine */
1741 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1742 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS);
1743
1744 /* Turn on RX data completion state machine */
1745 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1746
1747 /* Turn on RX BD initiator state machine */
1748 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1749
1750 /* Turn on RX data and RX BD initiator state machine */
1751 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1752
1753 /* Turn on Mbuf cluster free state machine */
1754 if (!(BGE_IS_5705_PLUS(sc)))
1755 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1756
1757 /* Turn on send BD completion state machine */
1758 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1759
1760 /* Turn on send data completion state machine */
1761 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1762
1763 /* Turn on send data initiator state machine */
1764 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1765
1766 /* Turn on send BD initiator state machine */
1767 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1768
1769 /* Turn on send BD selector state machine */
1770 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1771
1772 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1773 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1774 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
1775
1776 /* ack/clear link change events */
1777 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1778 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1779 BGE_MACSTAT_LINK_CHANGED);
1780 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1781
1782 /* Enable PHY auto polling (for MII/GMII only) */
1783 if (sc->bge_flags & BGE_FLAG_TBI) {
1784 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1785 } else {
1786 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16));
1787 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1788 sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
1789 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1790 BGE_EVTENB_MI_INTERRUPT);
1791 }
1792
1793 /*
1794 * Clear any pending link state attention.
1795 * Otherwise some link state change events may be lost until attention
1796 * is cleared by bge_intr() -> bge_link_upd() sequence.
1797 * It's not necessary on newer BCM chips - perhaps enabling link
1798 * state change attentions implies clearing pending attention.
1799 */
1800 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1801 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1802 BGE_MACSTAT_LINK_CHANGED);
1803
1804 /* Enable link state change attentions. */
1805 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1806
1807 return (0);
1808}
1809
1810const struct bge_revision *
1811bge_lookup_rev(uint32_t chipid)
1812{
1813 const struct bge_revision *br;
1814
1815 for (br = bge_revisions; br->br_name != NULL; br++) {
1816 if (br->br_chipid == chipid)
1817 return (br);
1818 }
1819
1820 for (br = bge_majorrevs; br->br_name != NULL; br++) {
1821 if (br->br_chipid == BGE_ASICREV(chipid))
1822 return (br);
1823 }
1824
1825 return (NULL);
1826}
1827
1828const struct bge_vendor *
1829bge_lookup_vendor(uint16_t vid)
1830{
1831 const struct bge_vendor *v;
1832
1833 for (v = bge_vendors; v->v_name != NULL; v++)
1834 if (v->v_id == vid)
1835 return (v);
1836
1837 panic("%s: unknown vendor %d", __func__, vid);
1838 return (NULL);
1839}
1840
1841/*
1842 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1843 * against our list and return its name if we find a match.
1844 *
1845 * Note that since the Broadcom controller contains VPD support, we
1846 * try to get the device name string from the controller itself instead
1847 * of the compiled-in string. It guarantees we'll always announce the
1848 * right product name. We fall back to the compiled-in string when
1849 * VPD is unavailable or corrupt.
1850 */
1851static int
1852bge_probe(device_t dev)
1853{
1854 struct bge_type *t = bge_devs;
1855 struct bge_softc *sc = device_get_softc(dev);
1856 uint16_t vid, did;
1857
1858 sc->bge_dev = dev;
1859 vid = pci_get_vendor(dev);
1860 did = pci_get_device(dev);
1861 while(t->bge_vid != 0) {
1862 if ((vid == t->bge_vid) && (did == t->bge_did)) {
1863 char model[64], buf[96];
1864 const struct bge_revision *br;
1865 const struct bge_vendor *v;
1866 uint32_t id;
1867
1868 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1869 BGE_PCIMISCCTL_ASICREV;
1870 br = bge_lookup_rev(id);
1871 v = bge_lookup_vendor(vid);
1872 {
1873#if __FreeBSD_version > 700024
1874 const char *pname;
1875
1876 if (pci_get_vpd_ident(dev, &pname) == 0)
1877 snprintf(model, 64, "%s", pname);
1878 else
1879#endif
1880 snprintf(model, 64, "%s %s",
1881 v->v_name,
1882 br != NULL ? br->br_name :
1883 "NetXtreme Ethernet Controller");
1884 }
1885 snprintf(buf, 96, "%s, %sASIC rev. %#04x", model,
1886 br != NULL ? "" : "unknown ", id >> 16);
1887 device_set_desc_copy(dev, buf);
1888 if (pci_get_subvendor(dev) == DELL_VENDORID)
1889 sc->bge_flags |= BGE_FLAG_NO_3LED;
1890 if (did == BCOM_DEVICEID_BCM5755M)
1891 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1892 return (0);
1893 }
1894 t++;
1895 }
1896
1897 return (ENXIO);
1898}
1899
1900static void
1901bge_dma_free(struct bge_softc *sc)
1902{
1903 int i;
1904
1905 /* Destroy DMA maps for RX buffers. */
1906 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1907 if (sc->bge_cdata.bge_rx_std_dmamap[i])
1908 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
1909 sc->bge_cdata.bge_rx_std_dmamap[i]);
1910 }
1911
1912 /* Destroy DMA maps for jumbo RX buffers. */
1913 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1914 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
1915 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
1916 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1917 }
1918
1919 /* Destroy DMA maps for TX buffers. */
1920 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1921 if (sc->bge_cdata.bge_tx_dmamap[i])
1922 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
1923 sc->bge_cdata.bge_tx_dmamap[i]);
1924 }
1925
1926 if (sc->bge_cdata.bge_mtag)
1927 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
1928
1929
1930 /* Destroy standard RX ring. */
1931 if (sc->bge_cdata.bge_rx_std_ring_map)
1932 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
1933 sc->bge_cdata.bge_rx_std_ring_map);
1934 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
1935 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
1936 sc->bge_ldata.bge_rx_std_ring,
1937 sc->bge_cdata.bge_rx_std_ring_map);
1938
1939 if (sc->bge_cdata.bge_rx_std_ring_tag)
1940 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
1941
1942 /* Destroy jumbo RX ring. */
1943 if (sc->bge_cdata.bge_rx_jumbo_ring_map)
1944 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1945 sc->bge_cdata.bge_rx_jumbo_ring_map);
1946
1947 if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
1948 sc->bge_ldata.bge_rx_jumbo_ring)
1949 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1950 sc->bge_ldata.bge_rx_jumbo_ring,
1951 sc->bge_cdata.bge_rx_jumbo_ring_map);
1952
1953 if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
1954 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
1955
1956 /* Destroy RX return ring. */
1957 if (sc->bge_cdata.bge_rx_return_ring_map)
1958 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
1959 sc->bge_cdata.bge_rx_return_ring_map);
1960
1961 if (sc->bge_cdata.bge_rx_return_ring_map &&
1962 sc->bge_ldata.bge_rx_return_ring)
1963 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
1964 sc->bge_ldata.bge_rx_return_ring,
1965 sc->bge_cdata.bge_rx_return_ring_map);
1966
1967 if (sc->bge_cdata.bge_rx_return_ring_tag)
1968 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
1969
1970 /* Destroy TX ring. */
1971 if (sc->bge_cdata.bge_tx_ring_map)
1972 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
1973 sc->bge_cdata.bge_tx_ring_map);
1974
1975 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
1976 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
1977 sc->bge_ldata.bge_tx_ring,
1978 sc->bge_cdata.bge_tx_ring_map);
1979
1980 if (sc->bge_cdata.bge_tx_ring_tag)
1981 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
1982
1983 /* Destroy status block. */
1984 if (sc->bge_cdata.bge_status_map)
1985 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
1986 sc->bge_cdata.bge_status_map);
1987
1988 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
1989 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
1990 sc->bge_ldata.bge_status_block,
1991 sc->bge_cdata.bge_status_map);
1992
1993 if (sc->bge_cdata.bge_status_tag)
1994 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
1995
1996 /* Destroy statistics block. */
1997 if (sc->bge_cdata.bge_stats_map)
1998 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
1999 sc->bge_cdata.bge_stats_map);
2000
2001 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2002 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2003 sc->bge_ldata.bge_stats,
2004 sc->bge_cdata.bge_stats_map);
2005
2006 if (sc->bge_cdata.bge_stats_tag)
2007 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2008
2009 /* Destroy the parent tag. */
2010 if (sc->bge_cdata.bge_parent_tag)
2011 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2012}
2013
2014static int
2015bge_dma_alloc(device_t dev)
2016{
2017 struct bge_dmamap_arg ctx;
2018 struct bge_softc *sc;
2019 int i, error;
2020
2021 sc = device_get_softc(dev);
2022
2023 /*
2024 * Allocate the parent bus DMA tag appropriate for PCI.
2025 */
2026 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2027 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2028 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2029 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2030
2031 if (error != 0) {
2032 device_printf(sc->bge_dev,
2033 "could not allocate parent dma tag\n");
2034 return (ENOMEM);
2035 }
2036
2037 /*
2038 * Create tag for mbufs.
2039 */
2040 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,
2041 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2042 NULL, MCLBYTES * BGE_NSEG_NEW, BGE_NSEG_NEW, MCLBYTES,
2043 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->bge_cdata.bge_mtag);
2044
2045 if (error) {
2046 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2047 return (ENOMEM);
2048 }
2049
2050 /* Create DMA maps for RX buffers. */
2051 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2052 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
2053 &sc->bge_cdata.bge_rx_std_dmamap[i]);
2054 if (error) {
2055 device_printf(sc->bge_dev,
2056 "can't create DMA map for RX\n");
2057 return (ENOMEM);
2058 }
2059 }
2060
2061 /* Create DMA maps for TX buffers. */
2062 for (i = 0; i < BGE_TX_RING_CNT; i++) {
2063 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
2064 &sc->bge_cdata.bge_tx_dmamap[i]);
2065 if (error) {
2066 device_printf(sc->bge_dev,
2067 "can't create DMA map for RX\n");
2068 return (ENOMEM);
2069 }
2070 }
2071
2072 /* Create tag for standard RX ring. */
2073 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2074 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2075 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
2076 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);
2077
2078 if (error) {
2079 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2080 return (ENOMEM);
2081 }
2082
2083 /* Allocate DMA'able memory for standard RX ring. */
2084 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
2085 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
2086 &sc->bge_cdata.bge_rx_std_ring_map);
2087 if (error)
2088 return (ENOMEM);
2089
2090 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
2091
2092 /* Load the address of the standard RX ring. */
2093 ctx.bge_maxsegs = 1;
2094 ctx.sc = sc;
2095
2096 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,
2097 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
2098 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2099
2100 if (error)
2101 return (ENOMEM);
2102
2103 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
2104
2105 /* Create tags for jumbo mbufs. */
2106 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2107 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2108 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2109 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
2110 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2111 if (error) {
2112 device_printf(sc->bge_dev,
2113 "could not allocate jumbo dma tag\n");
2114 return (ENOMEM);
2115 }
2116
2117 /* Create tag for jumbo RX ring. */
2118 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2119 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2120 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
2121 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);
2122
2123 if (error) {
2124 device_printf(sc->bge_dev,
2125 "could not allocate jumbo ring dma tag\n");
2126 return (ENOMEM);
2127 }
2128
2129 /* Allocate DMA'able memory for jumbo RX ring. */
2130 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2131 (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
2132 BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2133 &sc->bge_cdata.bge_rx_jumbo_ring_map);
2134 if (error)
2135 return (ENOMEM);
2136
2137 /* Load the address of the jumbo RX ring. */
2138 ctx.bge_maxsegs = 1;
2139 ctx.sc = sc;
2140
2141 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2142 sc->bge_cdata.bge_rx_jumbo_ring_map,
2143 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,
2144 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2145
2146 if (error)
2147 return (ENOMEM);
2148
2149 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
2150
2151 /* Create DMA maps for jumbo RX buffers. */
2152 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2153 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2154 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2155 if (error) {
2156 device_printf(sc->bge_dev,
2157 "can't create DMA map for jumbo RX\n");
2158 return (ENOMEM);
2159 }
2160 }
2161
2162 }
2163
2164 /* Create tag for RX return ring. */
2165 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2166 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2167 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
2168 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);
2169
2170 if (error) {
2171 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2172 return (ENOMEM);
2173 }
2174
2175 /* Allocate DMA'able memory for RX return ring. */
2176 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
2177 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
2178 &sc->bge_cdata.bge_rx_return_ring_map);
2179 if (error)
2180 return (ENOMEM);
2181
2182 bzero((char *)sc->bge_ldata.bge_rx_return_ring,
2183 BGE_RX_RTN_RING_SZ(sc));
2184
2185 /* Load the address of the RX return ring. */
2186 ctx.bge_maxsegs = 1;
2187 ctx.sc = sc;
2188
2189 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,
2190 sc->bge_cdata.bge_rx_return_ring_map,
2191 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),
2192 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2193
2194 if (error)
2195 return (ENOMEM);
2196
2197 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
2198
2199 /* Create tag for TX ring. */
2200 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2201 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2202 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
2203 &sc->bge_cdata.bge_tx_ring_tag);
2204
2205 if (error) {
2206 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2207 return (ENOMEM);
2208 }
2209
2210 /* Allocate DMA'able memory for TX ring. */
2211 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
2212 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
2213 &sc->bge_cdata.bge_tx_ring_map);
2214 if (error)
2215 return (ENOMEM);
2216
2217 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
2218
2219 /* Load the address of the TX ring. */
2220 ctx.bge_maxsegs = 1;
2221 ctx.sc = sc;
2222
2223 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,
2224 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,
2225 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2226
2227 if (error)
2228 return (ENOMEM);
2229
2230 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
2231
2232 /* Create tag for status block. */
2233 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2234 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2235 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0,
2236 NULL, NULL, &sc->bge_cdata.bge_status_tag);
2237
2238 if (error) {
2239 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2240 return (ENOMEM);
2241 }
2242
2243 /* Allocate DMA'able memory for status block. */
2244 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
2245 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
2246 &sc->bge_cdata.bge_status_map);
2247 if (error)
2248 return (ENOMEM);
2249
2250 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2251
2252 /* Load the address of the status block. */
2253 ctx.sc = sc;
2254 ctx.bge_maxsegs = 1;
2255
2256 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag,
2257 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,
2258 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2259
2260 if (error)
2261 return (ENOMEM);
2262
2263 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
2264
2265 /* Create tag for statistics block. */
2266 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2267 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2268 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
2269 &sc->bge_cdata.bge_stats_tag);
2270
2271 if (error) {
2272 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2273 return (ENOMEM);
2274 }
2275
2276 /* Allocate DMA'able memory for statistics block. */
2277 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
2278 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
2279 &sc->bge_cdata.bge_stats_map);
2280 if (error)
2281 return (ENOMEM);
2282
2283 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
2284
2285 /* Load the address of the statstics block. */
2286 ctx.sc = sc;
2287 ctx.bge_maxsegs = 1;
2288
2289 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag,
2290 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,
2291 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2292
2293 if (error)
2294 return (ENOMEM);
2295
2296 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
2297
2298 return (0);
2299}
2300
2301#if __FreeBSD_version > 602105
2302/*
2303 * Return true if this device has more than one port.
2304 */
2305static int
2306bge_has_multiple_ports(struct bge_softc *sc)
2307{
2308 device_t dev = sc->bge_dev;
2309 u_int b, d, f, fscan, s;
2310
2311 d = pci_get_domain(dev);
2312 b = pci_get_bus(dev);
2313 s = pci_get_slot(dev);
2314 f = pci_get_function(dev);
2315 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2316 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
2317 return (1);
2318 return (0);
2319}
2320
2321/*
2322 * Return true if MSI can be used with this device.
2323 */
2324static int
2325bge_can_use_msi(struct bge_softc *sc)
2326{
2327 int can_use_msi = 0;
2328
2329 switch (sc->bge_asicrev) {
2330 case BGE_ASICREV_BCM5714:
2331 /*
2332 * Apparently, MSI doesn't work when this chip is configured
2333 * in single-port mode.
2334 */
2335 if (bge_has_multiple_ports(sc))
2336 can_use_msi = 1;
2337 break;
2338 case BGE_ASICREV_BCM5750:
2339 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2340 sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2341 can_use_msi = 1;
2342 break;
2343 case BGE_ASICREV_BCM5752:
2344 case BGE_ASICREV_BCM5780:
2345 can_use_msi = 1;
2346 break;
2347 }
2348 return (can_use_msi);
2349}
2350#endif
2351
2352static int
2353bge_attach(device_t dev)
2354{
2355 struct ifnet *ifp;
2356 struct bge_softc *sc;
2357 uint32_t hwcfg = 0, misccfg;
2358 u_char eaddr[ETHER_ADDR_LEN];
2359 int error, reg, rid, trys;
2360
2361 sc = device_get_softc(dev);
2362 sc->bge_dev = dev;
2363
2364 /*
2365 * Map control/status registers.
2366 */
2367 pci_enable_busmaster(dev);
2368
2369 rid = BGE_PCI_BAR0;
2370 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2371 RF_ACTIVE);
2372
2373 if (sc->bge_res == NULL) {
2374 device_printf (sc->bge_dev, "couldn't map memory\n");
2375 error = ENXIO;
2376 goto fail;
2377 }
2378
2379 sc->bge_btag = rman_get_bustag(sc->bge_res);
2380 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
2381
2382 /* Save ASIC rev. */
2383
2384 sc->bge_chipid =
2385 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
2386 BGE_PCIMISCCTL_ASICREV;
2387 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2388 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2389
2390 /*
2391 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2392 * 5705 A0 and A1 chips.
2393 */
2394 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
2395 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2396 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2397 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)
2398 sc->bge_flags |= BGE_FLAG_WIRESPEED;
2399
2400 if (bge_has_eaddr(sc))
2401 sc->bge_flags |= BGE_FLAG_EADDR;
2402
2403 /* Save chipset family. */
2404 switch (sc->bge_asicrev) {
2405 case BGE_ASICREV_BCM5700:
2406 case BGE_ASICREV_BCM5701:
2407 case BGE_ASICREV_BCM5703:
2408 case BGE_ASICREV_BCM5704:
2409 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2410 break;
2411 case BGE_ASICREV_BCM5714_A0:
2412 case BGE_ASICREV_BCM5780:
2413 case BGE_ASICREV_BCM5714:
2414 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */;
2415 /* FALLTHRU */
2416 case BGE_ASICREV_BCM5750:
2417 case BGE_ASICREV_BCM5752:
2418 case BGE_ASICREV_BCM5755:
2419 case BGE_ASICREV_BCM5787:
2420 case BGE_ASICREV_BCM5906:
2421 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2422 /* FALLTHRU */
2423 case BGE_ASICREV_BCM5705:
2424 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2425 break;
2426 }
2427
2428 /* Set various bug flags. */
2429 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2430 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2431 sc->bge_flags |= BGE_FLAG_CRC_BUG;
2432 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2433 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2434 sc->bge_flags |= BGE_FLAG_ADC_BUG;
2435 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2436 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
2437 if (BGE_IS_5705_PLUS(sc) &&
2438 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
2439 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2440 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2441 if (sc->bge_chipid != BGE_CHIPID_BCM5722_A0)
2442 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
2443 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
2444 sc->bge_flags |= BGE_FLAG_BER_BUG;
2445 }
2446
2447
2448 /*
2449 * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe()
2450 * but I do not know the DEVICEID for the 5788M.
2451 */
2452 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID;
2453 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2454 misccfg == BGE_MISCCFG_BOARD_ID_5788M)
2455 sc->bge_flags |= BGE_FLAG_5788;
2456
2457 /*
2458 * Check if this is a PCI-X or PCI Express device.
2459 */
2460#if __FreeBSD_version > 602101
2461 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
2462 /*
2463 * Found a PCI Express capabilities register, this
2464 * must be a PCI Express device.
2465 */
2466 if (reg != 0)
2467 sc->bge_flags |= BGE_FLAG_PCIE;
2468 } else if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) {
2469 if (reg != 0)
2470 sc->bge_flags |= BGE_FLAG_PCIX;
2471 }
2472
2473#else
2474 if (BGE_IS_5705_PLUS(sc)) {
2475 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
2476 if ((reg & 0xFF) == BGE_PCIE_CAPID)
2477 sc->bge_flags |= BGE_FLAG_PCIE;
2478 } else {
2479 /*
2480 * Check if the device is in PCI-X Mode.
2481 * (This bit is not valid on PCI Express controllers.)
2482 */
2483 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2484 BGE_PCISTATE_PCI_BUSMODE) == 0)
2485 sc->bge_flags |= BGE_FLAG_PCIX;
2486 }
2487#endif
2488
2489#if __FreeBSD_version > 602105
2490 {
2491 int msicount;
2492
2493 /*
2494 * Allocate the interrupt, using MSI if possible. These devices
2495 * support 8 MSI messages, but only the first one is used in
2496 * normal operation.
2497 */
2498 if (bge_can_use_msi(sc)) {
2499 msicount = pci_msi_count(dev);
2500 if (msicount > 1)
2501 msicount = 1;
2502 } else
2503 msicount = 0;
2504 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
2505 rid = 1;
2506 sc->bge_flags |= BGE_FLAG_MSI;
2507 } else
2508 rid = 0;
2509 }
2510#else
2511 rid = 0;
2512#endif
2513
2514 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2515 RF_SHAREABLE | RF_ACTIVE);
2516
2517 if (sc->bge_irq == NULL) {
2518 device_printf(sc->bge_dev, "couldn't map interrupt\n");
2519 error = ENXIO;
2520 goto fail;
2521 }
2522
2523 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
2524
2525 /* Try to reset the chip. */
2526 if (bge_reset(sc)) {
2527 device_printf(sc->bge_dev, "chip reset failed\n");
2528 error = ENXIO;
2529 goto fail;
2530 }
2531
2532 sc->bge_asf_mode = 0;
2533 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
2534 == BGE_MAGIC_NUMBER)) {
2535 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
2536 & BGE_HWCFG_ASF) {
2537 sc->bge_asf_mode |= ASF_ENABLE;
2538 sc->bge_asf_mode |= ASF_STACKUP;
2539 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
2540 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
2541 }
2542 }
2543 }
2544
2545 /* Try to reset the chip again the nice way. */
2546 bge_stop_fw(sc);
2547 bge_sig_pre_reset(sc, BGE_RESET_STOP);
2548 if (bge_reset(sc)) {
2549 device_printf(sc->bge_dev, "chip reset failed\n");
2550 error = ENXIO;
2551 goto fail;
2552 }
2553
2554 bge_sig_legacy(sc, BGE_RESET_STOP);
2555 bge_sig_post_reset(sc, BGE_RESET_STOP);
2556
2557 if (bge_chipinit(sc)) {
2558 device_printf(sc->bge_dev, "chip initialization failed\n");
2559 error = ENXIO;
2560 goto fail;
2561 }
2562
2563 error = bge_get_eaddr(sc, eaddr);
2564 if (error) {
2565 device_printf(sc->bge_dev,
2566 "failed to read station address\n");
2567 error = ENXIO;
2568 goto fail;
2569 }
2570
2571 /* 5705 limits RX return ring to 512 entries. */
2572 if (BGE_IS_5705_PLUS(sc))
2573 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2574 else
2575 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2576
2577 if (bge_dma_alloc(dev)) {
2578 device_printf(sc->bge_dev,
2579 "failed to allocate DMA resources\n");
2580 error = ENXIO;
2581 goto fail;
2582 }
2583
2584 /* Set default tuneable values. */
2585 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2586 sc->bge_rx_coal_ticks = 150;
2587 sc->bge_tx_coal_ticks = 150;
2588 sc->bge_rx_max_coal_bds = 10;
2589 sc->bge_tx_max_coal_bds = 10;
2590
2591 /* Set up ifnet structure */
2592 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
2593 if (ifp == NULL) {
2594 device_printf(sc->bge_dev, "failed to if_alloc()\n");
2595 error = ENXIO;
2596 goto fail;
2597 }
2598 ifp->if_softc = sc;
2599 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2600 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2601 ifp->if_ioctl = bge_ioctl;
2602 ifp->if_start = bge_start;
2603 ifp->if_init = bge_init;
2604 ifp->if_mtu = ETHERMTU;
2605 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
2606 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2607 IFQ_SET_READY(&ifp->if_snd);
2608 ifp->if_hwassist = BGE_CSUM_FEATURES;
2609 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
2610 IFCAP_VLAN_MTU;
2611#ifdef IFCAP_VLAN_HWCSUM
2612 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2613#endif
2614 ifp->if_capenable = ifp->if_capabilities;
2615#ifdef DEVICE_POLLING
2616 ifp->if_capabilities |= IFCAP_POLLING;
2617#endif
2618
2619 /*
2620 * 5700 B0 chips do not support checksumming correctly due
2621 * to hardware bugs.
2622 */
2623 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
2624 ifp->if_capabilities &= ~IFCAP_HWCSUM;
2625 ifp->if_capenable &= IFCAP_HWCSUM;
2626 ifp->if_hwassist = 0;
2627 }
2628
2629 /*
2630 * Figure out what sort of media we have by checking the
2631 * hardware config word in the first 32k of NIC internal memory,
2632 * or fall back to examining the EEPROM if necessary.
2633 * Note: on some BCM5700 cards, this value appears to be unset.
2634 * If that's the case, we have to rely on identifying the NIC
2635 * by its PCI subsystem ID, as we do below for the SysKonnect
2636 * SK-9D41.
2637 */
2638 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2639 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2640 else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
2641 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
2642 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2643 sizeof(hwcfg))) {
2644 device_printf(sc->bge_dev, "failed to read EEPROM\n");
2645 error = ENXIO;
2646 goto fail;
2647 }
2648 hwcfg = ntohl(hwcfg);
2649 }
2650
2651 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2652 sc->bge_flags |= BGE_FLAG_TBI;
2653
2654 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2655 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41)
2656 sc->bge_flags |= BGE_FLAG_TBI;
2657
2658 if (sc->bge_flags & BGE_FLAG_TBI) {
2659 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2660 bge_ifmedia_sts);
2661 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
2662 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2663 0, NULL);
2664 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
2665 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
2666 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2667 } else {
2668 /*
2669 * Do transceiver setup and tell the firmware the
2670 * driver is down so we can try to get access the
2671 * probe if ASF is running. Retry a couple of times
2672 * if we get a conflict with the ASF firmware accessing
2673 * the PHY.
2674 */
2675 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2676again:
2677 bge_asf_driver_up(sc);
2678
2679 trys = 0;
2680 if (mii_phy_probe(dev, &sc->bge_miibus,
2681 bge_ifmedia_upd, bge_ifmedia_sts)) {
2682 if (trys++ < 4) {
2683 device_printf(sc->bge_dev, "Try again\n");
2684 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
2685 BMCR_RESET);
2686 goto again;
2687 }
2688
2689 device_printf(sc->bge_dev, "MII without any PHY!\n");
2690 error = ENXIO;
2691 goto fail;
2692 }
2693
2694 /*
2695 * Now tell the firmware we are going up after probing the PHY
2696 */
2697 if (sc->bge_asf_mode & ASF_STACKUP)
2698 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2699 }
2700
2701 /*
2702 * When using the BCM5701 in PCI-X mode, data corruption has
2703 * been observed in the first few bytes of some received packets.
2704 * Aligning the packet buffer in memory eliminates the corruption.
2705 * Unfortunately, this misaligns the packet payloads. On platforms
2706 * which do not support unaligned accesses, we will realign the
2707 * payloads by copying the received packets.
2708 */
2709 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2710 sc->bge_flags & BGE_FLAG_PCIX)
2711 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2712
2713 /*
2714 * Call MI attach routine.
2715 */
2716 ether_ifattach(ifp, eaddr);
2717 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
2718
2719 /*
2720 * Hookup IRQ last.
2721 */
2722#if __FreeBSD_version > 700030
2723 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2724 NULL, bge_intr, sc, &sc->bge_intrhand);
2725#else
2726 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2727 bge_intr, sc, &sc->bge_intrhand);
2728#endif
2729
2730 if (error) {
2731 bge_detach(dev);
2732 device_printf(sc->bge_dev, "couldn't set up irq\n");
2733 }
2734
2735 bge_add_sysctls(sc);
2736
2737 return (0);
2738
2739fail:
2740 bge_release_resources(sc);
2741
2742 return (error);
2743}
2744
2745static int
2746bge_detach(device_t dev)
2747{
2748 struct bge_softc *sc;
2749 struct ifnet *ifp;
2750
2751 sc = device_get_softc(dev);
2752 ifp = sc->bge_ifp;
2753
2754#ifdef DEVICE_POLLING
2755 if (ifp->if_capenable & IFCAP_POLLING)
2756 ether_poll_deregister(ifp);
2757#endif
2758
2759 BGE_LOCK(sc);
2760 bge_stop(sc);
2761 bge_reset(sc);
2762 BGE_UNLOCK(sc);
2763
2764 callout_drain(&sc->bge_stat_ch);
2765
2766 ether_ifdetach(ifp);
2767
2768 if (sc->bge_flags & BGE_FLAG_TBI) {
2769 ifmedia_removeall(&sc->bge_ifmedia);
2770 } else {
2771 bus_generic_detach(dev);
2772 device_delete_child(dev, sc->bge_miibus);
2773 }
2774
2775 bge_release_resources(sc);
2776
2777 return (0);
2778}
2779
2780static void
2781bge_release_resources(struct bge_softc *sc)
2782{
2783 device_t dev;
2784
2785 dev = sc->bge_dev;
2786
2787 if (sc->bge_intrhand != NULL)
2788 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2789
2790 if (sc->bge_irq != NULL)
2791 bus_release_resource(dev, SYS_RES_IRQ,
2792 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
2793
2794#if __FreeBSD_version > 602105
2795 if (sc->bge_flags & BGE_FLAG_MSI)
2796 pci_release_msi(dev);
2797#endif
2798
2799 if (sc->bge_res != NULL)
2800 bus_release_resource(dev, SYS_RES_MEMORY,
2801 BGE_PCI_BAR0, sc->bge_res);
2802
2803 if (sc->bge_ifp != NULL)
2804 if_free(sc->bge_ifp);
2805
2806 bge_dma_free(sc);
2807
2808 if (mtx_initialized(&sc->bge_mtx)) /* XXX */
2809 BGE_LOCK_DESTROY(sc);
2810}
2811
2812static int
2813bge_reset(struct bge_softc *sc)
2814{
2815 device_t dev;
2816 uint32_t cachesize, command, pcistate, reset, val;
2817 void (*write_op)(struct bge_softc *, int, int);
2818 int i;
2819
2820 dev = sc->bge_dev;
2821
2822 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2823 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
2824 if (sc->bge_flags & BGE_FLAG_PCIE)
2825 write_op = bge_writemem_direct;
2826 else
2827 write_op = bge_writemem_ind;
2828 } else
2829 write_op = bge_writereg_ind;
2830
2831 /* Save some important PCI state. */
2832 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2833 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2834 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2835
2836 pci_write_config(dev, BGE_PCI_MISC_CTL,
2837 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
2838 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
2839
2840 /* Disable fastboot on controllers that support it. */
2841 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2842 sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2843 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2844 if (bootverbose)
2845 device_printf(sc->bge_dev, "Disabling fastboot\n");
2846 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2847 }
2848
2849 /*
2850 * Write the magic number to SRAM at offset 0xB50.
2851 * When firmware finishes its initialization it will
2852 * write ~BGE_MAGIC_NUMBER to the same location.
2853 */
2854 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2855
2856 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
2857
2858 /* XXX: Broadcom Linux driver. */
2859 if (sc->bge_flags & BGE_FLAG_PCIE) {
2860 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
2861 CSR_WRITE_4(sc, 0x7E2C, 0x20);
2862 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2863 /* Prevent PCIE link training during global reset */
2864 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
2865 reset |= 1 << 29;
2866 }
2867 }
2868
2869 /*
2870 * Set GPHY Power Down Override to leave GPHY
2871 * powered up in D0 uninitialized.
2872 */
2873 if (BGE_IS_5705_PLUS(sc))
2874 reset |= 0x04000000;
2875
2876 /* Issue global reset */
2877 write_op(sc, BGE_MISC_CFG, reset);
2878
2879 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2880 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2881 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2882 val | BGE_VCPU_STATUS_DRV_RESET);
2883 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2884 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2885 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2886 }
2887
2888 DELAY(1000);
2889
2890 /* XXX: Broadcom Linux driver. */
2891 if (sc->bge_flags & BGE_FLAG_PCIE) {
2892 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2893 DELAY(500000); /* wait for link training to complete */
2894 val = pci_read_config(dev, 0xC4, 4);
2895 pci_write_config(dev, 0xC4, val | (1 << 15), 4);
2896 }
2897 /*
2898 * Set PCIE max payload size to 128 bytes and clear error
2899 * status.
2900 */
2901 pci_write_config(dev, 0xD8, 0xF5000, 4);
2902 }
2903
2904 /* Reset some of the PCI state that got zapped by reset. */
2905 pci_write_config(dev, BGE_PCI_MISC_CTL,
2906 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
2907 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
2908 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2909 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2910 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
2911
2912 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */
2913 if (BGE_IS_5714_FAMILY(sc)) {
2914 /* This chip disables MSI on reset. */
2915 if (sc->bge_flags & BGE_FLAG_MSI) {
2916 val = pci_read_config(dev, BGE_PCI_MSI_CTL, 2);
2917 pci_write_config(dev, BGE_PCI_MSI_CTL,
2918 val | PCIM_MSICTRL_MSI_ENABLE, 2);
2919 val = CSR_READ_4(sc, BGE_MSI_MODE);
2920 CSR_WRITE_4(sc, BGE_MSI_MODE,
2921 val | BGE_MSIMODE_ENABLE);
2922 }
2923 val = CSR_READ_4(sc, BGE_MARB_MODE);
2924 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2925 } else
2926 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2927
2928 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2929 for (i = 0; i < BGE_TIMEOUT; i++) {
2930 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2931 if (val & BGE_VCPU_STATUS_INIT_DONE)
2932 break;
2933 DELAY(100);
2934 }
2935 if (i == BGE_TIMEOUT) {
2936 device_printf(sc->bge_dev, "reset timed out\n");
2937 return (1);
2938 }
2939 } else {
2940 /*
2941 * Poll until we see the 1's complement of the magic number.
2942 * This indicates that the firmware initialization is complete.
2943 * We expect this to fail if no chip containing the Ethernet
2944 * address is fitted though.
2945 */
2946 for (i = 0; i < BGE_TIMEOUT; i++) {
2947 DELAY(10);
2948 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2949 if (val == ~BGE_MAGIC_NUMBER)
2950 break;
2951 }
2952
2953 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
2954 device_printf(sc->bge_dev, "firmware handshake timed out, "
2955 "found 0x%08x\n", val);
2956 }
2957
2958 /*
2959 * XXX Wait for the value of the PCISTATE register to
2960 * return to its original pre-reset state. This is a
2961 * fairly good indicator of reset completion. If we don't
2962 * wait for the reset to fully complete, trying to read
2963 * from the device's non-PCI registers may yield garbage
2964 * results.
2965 */
2966 for (i = 0; i < BGE_TIMEOUT; i++) {
2967 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2968 break;
2969 DELAY(10);
2970 }
2971
2972 if (sc->bge_flags & BGE_FLAG_PCIE) {
2973 reset = bge_readmem_ind(sc, 0x7C00);
2974 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25));
2975 }
2976
2977 /* Fix up byte swapping. */
2978 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2979 BGE_MODECTL_BYTESWAP_DATA);
2980
2981 /* Tell the ASF firmware we are up */
2982 if (sc->bge_asf_mode & ASF_STACKUP)
2983 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2984
2985 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2986
2987 /*
2988 * The 5704 in TBI mode apparently needs some special
2989 * adjustment to insure the SERDES drive level is set
2990 * to 1.2V.
2991 */
2992 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2993 sc->bge_flags & BGE_FLAG_TBI) {
2994 val = CSR_READ_4(sc, BGE_SERDES_CFG);
2995 val = (val & ~0xFFF) | 0x880;
2996 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
2997 }
2998
2999 /* XXX: Broadcom Linux driver. */
3000 if (sc->bge_flags & BGE_FLAG_PCIE &&
3001 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3002 val = CSR_READ_4(sc, 0x7C00);
3003 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3004 }
3005 DELAY(10000);
3006
3007 return(0);
3008}
3009
3010/*
3011 * Frame reception handling. This is called if there's a frame
3012 * on the receive return list.
3013 *
3014 * Note: we have to be able to handle two possibilities here:
3015 * 1) the frame is from the jumbo receive ring
3016 * 2) the frame is from the standard receive ring
3017 */
3018
3019static void
3020bge_rxeof(struct bge_softc *sc)
3021{
3022 struct ifnet *ifp;
3023 int stdcnt = 0, jumbocnt = 0;
3024
3025 BGE_LOCK_ASSERT(sc);
3026
3027 /* Nothing to do. */
3028 if (sc->bge_rx_saved_considx ==
3029 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
3030 return;
3031
3032 ifp = sc->bge_ifp;
3033
3034 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3035 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3036 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3037 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD);
3038 if (BGE_IS_JUMBO_CAPABLE(sc))
3039 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3040 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTREAD);
3041
3042 while(sc->bge_rx_saved_considx !=
3043 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
3044 struct bge_rx_bd *cur_rx;
3045 uint32_t rxidx;
3046 struct mbuf *m = NULL;
3047 uint16_t vlan_tag = 0;
3048 int have_tag = 0;
3049
3050#ifdef DEVICE_POLLING
3051 if (ifp->if_capenable & IFCAP_POLLING) {
3052 if (sc->rxcycles <= 0)
3053 break;
3054 sc->rxcycles--;
3055 }
3056#endif
3057
3058 cur_rx =
3059 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
3060
3061 rxidx = cur_rx->bge_idx;
3062 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
3063
3064 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
3065 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3066 have_tag = 1;
3067 vlan_tag = cur_rx->bge_vlan_tag;
3068 }
3069
3070 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3071 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3072 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
3073 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx],
3074 BUS_DMASYNC_POSTREAD);
3075 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
3076 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]);
3077 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3078 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
3079 jumbocnt++;
3080 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3081 ifp->if_ierrors++;
3082 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
3083 continue;
3084 }
3085 if (bge_newbuf_jumbo(sc,
3086 sc->bge_jumbo, NULL) == ENOBUFS) {
3087 ifp->if_ierrors++;
3088 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
3089 continue;
3090 }
3091 } else {
3092 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3093 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
3094 sc->bge_cdata.bge_rx_std_dmamap[rxidx],
3095 BUS_DMASYNC_POSTREAD);
3096 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
3097 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
3098 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3099 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
3100 stdcnt++;
3101 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3102 ifp->if_ierrors++;
3103 bge_newbuf_std(sc, sc->bge_std, m);
3104 continue;
3105 }
3106 if (bge_newbuf_std(sc, sc->bge_std,
3107 NULL) == ENOBUFS) {
3108 ifp->if_ierrors++;
3109 bge_newbuf_std(sc, sc->bge_std, m);
3110 continue;
3111 }
3112 }
3113
3114 ifp->if_ipackets++;
3115#ifndef __NO_STRICT_ALIGNMENT
3116 /*
3117 * For architectures with strict alignment we must make sure
3118 * the payload is aligned.
3119 */
3120 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3121 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3122 cur_rx->bge_len);
3123 m->m_data += ETHER_ALIGN;
3124 }
3125#endif
3126 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3127 m->m_pkthdr.rcvif = ifp;
3128
3129 if (ifp->if_capenable & IFCAP_RXCSUM) {
3130 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3131 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3132 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3133 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3134 }
3135 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3136 m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3137 m->m_pkthdr.csum_data =
3138 cur_rx->bge_tcp_udp_csum;
3139 m->m_pkthdr.csum_flags |=
3140 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3141 }
3142 }
3143
3144 /*
3145 * If we received a packet with a vlan tag,
3146 * attach that information to the packet.
3147 */
3148 if (have_tag) {
3149#if __FreeBSD_version > 700022
3150 m->m_pkthdr.ether_vtag = vlan_tag;
3151 m->m_flags |= M_VLANTAG;
3152#else
3153 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag);
3154 if (m == NULL)
3155 continue;
3156#endif
3157 }
3158
3159 BGE_UNLOCK(sc);
3160 (*ifp->if_input)(ifp, m);
3161 BGE_LOCK(sc);
3162 }
3163
3164 if (stdcnt > 0)
3165 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3166 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3167
3168 if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0)
3169 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3170 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3171
3172 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3173 if (stdcnt)
3174 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3175 if (jumbocnt)
3176 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3177#ifdef notyet
3178 /*
3179 * This register wraps very quickly under heavy packet drops.
3180 * If you need correct statistics, you can enable this check.
3181 */
3182 if (BGE_IS_5705_PLUS(sc))
3183 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3184#endif
3185}
3186
3187static void
3188bge_txeof(struct bge_softc *sc)
3189{
3190 struct bge_tx_bd *cur_tx = NULL;
3191 struct ifnet *ifp;
3192
3193 BGE_LOCK_ASSERT(sc);
3194
3195 /* Nothing to do. */
3196 if (sc->bge_tx_saved_considx ==
3197 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
3198 return;
3199
3200 ifp = sc->bge_ifp;
3201
3202 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3203 sc->bge_cdata.bge_tx_ring_map,
3204 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3205 /*
3206 * Go through our tx ring and free mbufs for those
3207 * frames that have been sent.
3208 */
3209 while (sc->bge_tx_saved_considx !=
3210 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
3211 uint32_t idx = 0;
3212
3213 idx = sc->bge_tx_saved_considx;
3214 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3215 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3216 ifp->if_opackets++;
3217 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3218 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
3219 sc->bge_cdata.bge_tx_dmamap[idx],
3220 BUS_DMASYNC_POSTWRITE);
3221 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
3222 sc->bge_cdata.bge_tx_dmamap[idx]);
3223 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3224 sc->bge_cdata.bge_tx_chain[idx] = NULL;
3225 }
3226 sc->bge_txcnt--;
3227 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3228 }
3229
3230 if (cur_tx != NULL)
3231 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3232 if (sc->bge_txcnt == 0)
3233 sc->bge_timer = 0;
3234}
3235
3236#ifdef DEVICE_POLLING
3237static void
3238bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3239{
3240 struct bge_softc *sc = ifp->if_softc;
3241 uint32_t statusword;
3242
3243 BGE_LOCK(sc);
3244 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3245 BGE_UNLOCK(sc);
3246 return;
3247 }
3248
3249 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3250 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD);
3251
3252 statusword = atomic_readandclear_32(
3253 &sc->bge_ldata.bge_status_block->bge_status);
3254
3255 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3256 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD);
3257
3258 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3259 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3260 sc->bge_link_evt++;
3261
3262 if (cmd == POLL_AND_CHECK_STATUS)
3263 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3264 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3265 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3266 bge_link_upd(sc);
3267
3268 sc->rxcycles = count;
3269 bge_rxeof(sc);
3270 bge_txeof(sc);
3271 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3272 bge_start_locked(ifp);
3273
3274 BGE_UNLOCK(sc);
3275}
3276#endif /* DEVICE_POLLING */
3277
3278static void
3279bge_intr(void *xsc)
3280{
3281 struct bge_softc *sc;
3282 struct ifnet *ifp;
3283 uint32_t statusword;
3284
3285 sc = xsc;
3286
3287 BGE_LOCK(sc);
3288
3289 ifp = sc->bge_ifp;
3290
3291#ifdef DEVICE_POLLING
3292 if (ifp->if_capenable & IFCAP_POLLING) {
3293 BGE_UNLOCK(sc);
3294 return;
3295 }
3296#endif
3297
3298 /*
3299 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
3300 * disable interrupts by writing nonzero like we used to, since with
3301 * our current organization this just gives complications and
3302 * pessimizations for re-enabling interrupts. We used to have races
3303 * instead of the necessary complications. Disabling interrupts
3304 * would just reduce the chance of a status update while we are
3305 * running (by switching to the interrupt-mode coalescence
3306 * parameters), but this chance is already very low so it is more
3307 * efficient to get another interrupt than prevent it.
3308 *
3309 * We do the ack first to ensure another interrupt if there is a
3310 * status update after the ack. We don't check for the status
3311 * changing later because it is more efficient to get another
3312 * interrupt than prevent it, not quite as above (not checking is
3313 * a smaller optimization than not toggling the interrupt enable,
3314 * since checking doesn't involve PCI accesses and toggling require
3315 * the status check). So toggling would probably be a pessimization
3316 * even with MSI. It would only be needed for using a task queue.
3317 */
3318 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3319
3320 /*
3321 * Do the mandatory PCI flush as well as get the link status.
3322 */
3323 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
3324
3325 /* Make sure the descriptor ring indexes are coherent. */
3326 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3327 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD);
3328 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3329 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD);
3330
3331 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3332 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3333 statusword || sc->bge_link_evt)
3334 bge_link_upd(sc);
3335
3336 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3337 /* Check RX return ring producer/consumer. */
3338 bge_rxeof(sc);
3339
3340 /* Check TX ring producer/consumer. */
3341 bge_txeof(sc);
3342 }
3343
3344 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3345 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3346 bge_start_locked(ifp);
3347
3348 BGE_UNLOCK(sc);
3349}
3350
3351static void
3352bge_asf_driver_up(struct bge_softc *sc)
3353{
3354 if (sc->bge_asf_mode & ASF_STACKUP) {
3355 /* Send ASF heartbeat aprox. every 2s */
3356 if (sc->bge_asf_count)
3357 sc->bge_asf_count --;
3358 else {
3359 sc->bge_asf_count = 5;
3360 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
3361 BGE_FW_DRV_ALIVE);
3362 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
3363 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
3364 CSR_WRITE_4(sc, BGE_CPU_EVENT,
3365 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
3366 }
3367 }
3368}
3369
3370static void
3371bge_tick(void *xsc)
3372{
3373 struct bge_softc *sc = xsc;
3374 struct mii_data *mii = NULL;
3375
3376 BGE_LOCK_ASSERT(sc);
3377
3378 /* Synchronize with possible callout reset/stop. */
3379 if (callout_pending(&sc->bge_stat_ch) ||
3380 !callout_active(&sc->bge_stat_ch))
3381 return;
3382
3383 if (BGE_IS_5705_PLUS(sc))
3384 bge_stats_update_regs(sc);
3385 else
3386 bge_stats_update(sc);
3387
3388 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3389 mii = device_get_softc(sc->bge_miibus);
|
3392 mii_tick(mii);
3393 } else {
3394 /*
3395 * Since in TBI mode auto-polling can't be used we should poll
3396 * link status manually. Here we register pending link event
3397 * and trigger interrupt.
3398 */
3399#ifdef DEVICE_POLLING
3400 /* In polling mode we poll link state in bge_poll(). */
3401 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
3402#endif
3403 {
3404 sc->bge_link_evt++;
3405 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3406 sc->bge_flags & BGE_FLAG_5788)
3407 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3408 else
3409 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3410 }
3411 }
3412
3413 bge_asf_driver_up(sc);
3414 bge_watchdog(sc);
3415
3416 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3417}
3418
3419static void
3420bge_stats_update_regs(struct bge_softc *sc)
3421{
3422 struct ifnet *ifp;
3423
3424 ifp = sc->bge_ifp;
3425
3426 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
3427 offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
3428
3429 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3430}
3431
3432static void
3433bge_stats_update(struct bge_softc *sc)
3434{
3435 struct ifnet *ifp;
3436 bus_size_t stats;
3437 uint32_t cnt; /* current register value */
3438
3439 ifp = sc->bge_ifp;
3440
3441 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3442
3443#define READ_STAT(sc, stats, stat) \
3444 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3445
3446 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
3447 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
3448 sc->bge_tx_collisions = cnt;
3449
3450 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
3451 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
3452 sc->bge_rx_discards = cnt;
3453
3454 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
3455 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
3456 sc->bge_tx_discards = cnt;
3457
3458#undef READ_STAT
3459}
3460
3461/*
3462 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
3463 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
3464 * but when such padded frames employ the bge IP/TCP checksum offload,
3465 * the hardware checksum assist gives incorrect results (possibly
3466 * from incorporating its own padding into the UDP/TCP checksum; who knows).
3467 * If we pad such runts with zeros, the onboard checksum comes out correct.
3468 */
3469static __inline int
3470bge_cksum_pad(struct mbuf *m)
3471{
3472 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
3473 struct mbuf *last;
3474
3475 /* If there's only the packet-header and we can pad there, use it. */
3476 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
3477 M_TRAILINGSPACE(m) >= padlen) {
3478 last = m;
3479 } else {
3480 /*
3481 * Walk packet chain to find last mbuf. We will either
3482 * pad there, or append a new mbuf and pad it.
3483 */
3484 for (last = m; last->m_next != NULL; last = last->m_next);
3485 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
3486 /* Allocate new empty mbuf, pad it. Compact later. */
3487 struct mbuf *n;
3488
3489 MGET(n, M_DONTWAIT, MT_DATA);
3490 if (n == NULL)
3491 return (ENOBUFS);
3492 n->m_len = 0;
3493 last->m_next = n;
3494 last = n;
3495 }
3496 }
3497
3498 /* Now zero the pad area, to avoid the bge cksum-assist bug. */
3499 memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
3500 last->m_len += padlen;
3501 m->m_pkthdr.len += padlen;
3502
3503 return (0);
3504}
3505
3506/*
3507 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3508 * pointers to descriptors.
3509 */
3510static int
3511bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
3512{
3513 bus_dma_segment_t segs[BGE_NSEG_NEW];
3514 bus_dmamap_t map;
3515 struct bge_tx_bd *d;
3516 struct mbuf *m = *m_head;
3517 uint32_t idx = *txidx;
3518 uint16_t csum_flags;
3519 int nsegs, i, error;
3520
3521 csum_flags = 0;
3522 if (m->m_pkthdr.csum_flags) {
3523 if (m->m_pkthdr.csum_flags & CSUM_IP)
3524 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3525 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
3526 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3527 if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
3528 (error = bge_cksum_pad(m)) != 0) {
3529 m_freem(m);
3530 *m_head = NULL;
3531 return (error);
3532 }
3533 }
3534 if (m->m_flags & M_LASTFRAG)
3535 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3536 else if (m->m_flags & M_FRAG)
3537 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3538 }
3539
3540 map = sc->bge_cdata.bge_tx_dmamap[idx];
3541 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, segs,
3542 &nsegs, BUS_DMA_NOWAIT);
3543 if (error == EFBIG) {
3544 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
3545 if (m == NULL) {
3546 m_freem(*m_head);
3547 *m_head = NULL;
3548 return (ENOBUFS);
3549 }
3550 *m_head = m;
3551 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m,
3552 segs, &nsegs, BUS_DMA_NOWAIT);
3553 if (error) {
3554 m_freem(m);
3555 *m_head = NULL;
3556 return (error);
3557 }
3558 } else if (error != 0)
3559 return (error);
3560
3561 /*
3562 * Sanity check: avoid coming within 16 descriptors
3563 * of the end of the ring.
3564 */
3565 if (nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) {
3566 bus_dmamap_unload(sc->bge_cdata.bge_mtag, map);
3567 return (ENOBUFS);
3568 }
3569
3570 bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
3571
3572 for (i = 0; ; i++) {
3573 d = &sc->bge_ldata.bge_tx_ring[idx];
3574 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3575 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3576 d->bge_len = segs[i].ds_len;
3577 d->bge_flags = csum_flags;
3578 if (i == nsegs - 1)
3579 break;
3580 BGE_INC(idx, BGE_TX_RING_CNT);
3581 }
3582
3583 /* Mark the last segment as end of packet... */
3584 d->bge_flags |= BGE_TXBDFLAG_END;
3585
3586 /* ... and put VLAN tag into first segment. */
3587 d = &sc->bge_ldata.bge_tx_ring[*txidx];
3588#if __FreeBSD_version > 700022
3589 if (m->m_flags & M_VLANTAG) {
3590 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3591 d->bge_vlan_tag = m->m_pkthdr.ether_vtag;
3592 } else
3593 d->bge_vlan_tag = 0;
3594#else
3595 {
3596 struct m_tag *mtag;
3597
3598 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) {
3599 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3600 d->bge_vlan_tag = VLAN_TAG_VALUE(mtag);
3601 } else
3602 d->bge_vlan_tag = 0;
3603 }
3604#endif
3605
3606 /*
3607 * Insure that the map for this transmission
3608 * is placed at the array index of the last descriptor
3609 * in this chain.
3610 */
3611 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3612 sc->bge_cdata.bge_tx_dmamap[idx] = map;
3613 sc->bge_cdata.bge_tx_chain[idx] = m;
3614 sc->bge_txcnt += nsegs;
3615
3616 BGE_INC(idx, BGE_TX_RING_CNT);
3617 *txidx = idx;
3618
3619 return (0);
3620}
3621
3622/*
3623 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3624 * to the mbuf data regions directly in the transmit descriptors.
3625 */
3626static void
3627bge_start_locked(struct ifnet *ifp)
3628{
3629 struct bge_softc *sc;
3630 struct mbuf *m_head = NULL;
3631 uint32_t prodidx;
3632 int count = 0;
3633
3634 sc = ifp->if_softc;
3635
3636 if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3637 return;
3638
3639 prodidx = sc->bge_tx_prodidx;
3640
3641 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3642 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3643 if (m_head == NULL)
3644 break;
3645
3646 /*
3647 * XXX
3648 * The code inside the if() block is never reached since we
3649 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3650 * requests to checksum TCP/UDP in a fragmented packet.
3651 *
3652 * XXX
3653 * safety overkill. If this is a fragmented packet chain
3654 * with delayed TCP/UDP checksums, then only encapsulate
3655 * it if we have enough descriptors to handle the entire
3656 * chain at once.
3657 * (paranoia -- may not actually be needed)
3658 */
3659 if (m_head->m_flags & M_FIRSTFRAG &&
3660 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
3661 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3662 m_head->m_pkthdr.csum_data + 16) {
3663 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3664 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3665 break;
3666 }
3667 }
3668
3669 /*
3670 * Pack the data into the transmit ring. If we
3671 * don't have room, set the OACTIVE flag and wait
3672 * for the NIC to drain the ring.
3673 */
3674 if (bge_encap(sc, &m_head, &prodidx)) {
3675 if (m_head == NULL)
3676 break;
3677 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3678 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3679 break;
3680 }
3681 ++count;
3682
3683 /*
3684 * If there's a BPF listener, bounce a copy of this frame
3685 * to him.
3686 */
3687#ifdef ETHER_BPF_MTAP
3688 ETHER_BPF_MTAP(ifp, m_head);
3689#else
3690 BPF_MTAP(ifp, m_head);
3691#endif
3692 }
3693
3694 if (count == 0)
3695 /* No packets were dequeued. */
3696 return;
3697
3698 /* Transmit. */
3699 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3700 /* 5700 b2 errata */
3701 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3702 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3703
3704 sc->bge_tx_prodidx = prodidx;
3705
3706 /*
3707 * Set a timeout in case the chip goes out to lunch.
3708 */
3709 sc->bge_timer = 5;
3710}
3711
3712/*
3713 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3714 * to the mbuf data regions directly in the transmit descriptors.
3715 */
3716static void
3717bge_start(struct ifnet *ifp)
3718{
3719 struct bge_softc *sc;
3720
3721 sc = ifp->if_softc;
3722 BGE_LOCK(sc);
3723 bge_start_locked(ifp);
3724 BGE_UNLOCK(sc);
3725}
3726
3727static void
3728bge_init_locked(struct bge_softc *sc)
3729{
3730 struct ifnet *ifp;
3731 uint16_t *m;
3732
3733 BGE_LOCK_ASSERT(sc);
3734
3735 ifp = sc->bge_ifp;
3736
3737 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3738 return;
3739
3740 /* Cancel pending I/O and flush buffers. */
3741 bge_stop(sc);
3742
3743 bge_stop_fw(sc);
3744 bge_sig_pre_reset(sc, BGE_RESET_START);
3745 bge_reset(sc);
3746 bge_sig_legacy(sc, BGE_RESET_START);
3747 bge_sig_post_reset(sc, BGE_RESET_START);
3748
3749 bge_chipinit(sc);
3750
3751 /*
3752 * Init the various state machines, ring
3753 * control blocks and firmware.
3754 */
3755 if (bge_blockinit(sc)) {
3756 device_printf(sc->bge_dev, "initialization failure\n");
3757 return;
3758 }
3759
3760 ifp = sc->bge_ifp;
3761
3762 /* Specify MTU. */
3763 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3764 ETHER_HDR_LEN + ETHER_CRC_LEN +
3765 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
3766
3767 /* Load our MAC address. */
3768 m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
3769 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3770 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3771
3772 /* Program promiscuous mode. */
3773 bge_setpromisc(sc);
3774
3775 /* Program multicast filter. */
3776 bge_setmulti(sc);
3777
3778 /* Program VLAN tag stripping. */
3779 bge_setvlan(sc);
3780
3781 /* Init RX ring. */
3782 bge_init_rx_ring_std(sc);
3783
3784 /*
3785 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3786 * memory to insure that the chip has in fact read the first
3787 * entry of the ring.
3788 */
3789 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3790 uint32_t v, i;
3791 for (i = 0; i < 10; i++) {
3792 DELAY(20);
3793 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3794 if (v == (MCLBYTES - ETHER_ALIGN))
3795 break;
3796 }
3797 if (i == 10)
3798 device_printf (sc->bge_dev,
3799 "5705 A0 chip failed to load RX ring\n");
3800 }
3801
3802 /* Init jumbo RX ring. */
3803 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
3804 bge_init_rx_ring_jumbo(sc);
3805
3806 /* Init our RX return ring index. */
3807 sc->bge_rx_saved_considx = 0;
3808
3809 /* Init our RX/TX stat counters. */
3810 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
3811
3812 /* Init TX ring. */
3813 bge_init_tx_ring(sc);
3814
3815 /* Turn on transmitter. */
3816 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3817
3818 /* Turn on receiver. */
3819 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3820
3821 /* Tell firmware we're alive. */
3822 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3823
3824#ifdef DEVICE_POLLING
3825 /* Disable interrupts if we are polling. */
3826 if (ifp->if_capenable & IFCAP_POLLING) {
3827 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
3828 BGE_PCIMISCCTL_MASK_PCI_INTR);
3829 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3830 } else
3831#endif
3832
3833 /* Enable host interrupts. */
3834 {
3835 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3836 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3837 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3838 }
3839
3840 bge_ifmedia_upd_locked(ifp);
3841
3842 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3843 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3844
3845 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3846}
3847
3848static void
3849bge_init(void *xsc)
3850{
3851 struct bge_softc *sc = xsc;
3852
3853 BGE_LOCK(sc);
3854 bge_init_locked(sc);
3855 BGE_UNLOCK(sc);
3856}
3857
3858/*
3859 * Set media options.
3860 */
3861static int
3862bge_ifmedia_upd(struct ifnet *ifp)
3863{
3864 struct bge_softc *sc = ifp->if_softc;
3865 int res;
3866
3867 BGE_LOCK(sc);
3868 res = bge_ifmedia_upd_locked(ifp);
3869 BGE_UNLOCK(sc);
3870
3871 return (res);
3872}
3873
3874static int
3875bge_ifmedia_upd_locked(struct ifnet *ifp)
3876{
3877 struct bge_softc *sc = ifp->if_softc;
3878 struct mii_data *mii;
3879 struct ifmedia *ifm;
3880
3881 BGE_LOCK_ASSERT(sc);
3882
3883 ifm = &sc->bge_ifmedia;
3884
3885 /* If this is a 1000baseX NIC, enable the TBI port. */
3886 if (sc->bge_flags & BGE_FLAG_TBI) {
3887 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3888 return (EINVAL);
3889 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3890 case IFM_AUTO:
3891 /*
3892 * The BCM5704 ASIC appears to have a special
3893 * mechanism for programming the autoneg
3894 * advertisement registers in TBI mode.
3895 */
3896 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3897 uint32_t sgdig;
3898 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
3899 if (sgdig & BGE_SGDIGSTS_DONE) {
3900 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3901 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3902 sgdig |= BGE_SGDIGCFG_AUTO |
3903 BGE_SGDIGCFG_PAUSE_CAP |
3904 BGE_SGDIGCFG_ASYM_PAUSE;
3905 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3906 sgdig | BGE_SGDIGCFG_SEND);
3907 DELAY(5);
3908 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3909 }
3910 }
3911 break;
3912 case IFM_1000_SX:
3913 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3914 BGE_CLRBIT(sc, BGE_MAC_MODE,
3915 BGE_MACMODE_HALF_DUPLEX);
3916 } else {
3917 BGE_SETBIT(sc, BGE_MAC_MODE,
3918 BGE_MACMODE_HALF_DUPLEX);
3919 }
3920 break;
3921 default:
3922 return (EINVAL);
3923 }
3924 return (0);
3925 }
3926
3927 sc->bge_link_evt++;
3928 mii = device_get_softc(sc->bge_miibus);
3929 if (mii->mii_instance) {
3930 struct mii_softc *miisc;
3931 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
3932 miisc = LIST_NEXT(miisc, mii_list))
3933 mii_phy_reset(miisc);
3934 }
3935 mii_mediachg(mii);
3936
3937 /*
3938 * Force an interrupt so that we will call bge_link_upd
3939 * if needed and clear any pending link state attention.
3940 * Without this we are not getting any further interrupts
3941 * for link state changes and thus will not UP the link and
3942 * not be able to send in bge_start_locked. The only
3943 * way to get things working was to receive a packet and
3944 * get an RX intr.
3945 * bge_tick should help for fiber cards and we might not
3946 * need to do this here if BGE_FLAG_TBI is set but as
3947 * we poll for fiber anyway it should not harm.
3948 */
3949 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3950 sc->bge_flags & BGE_FLAG_5788)
3951 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3952 else
3953 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3954
3955 return (0);
3956}
3957
3958/*
3959 * Report current media status.
3960 */
3961static void
3962bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3963{
3964 struct bge_softc *sc = ifp->if_softc;
3965 struct mii_data *mii;
3966
3967 BGE_LOCK(sc);
3968
3969 if (sc->bge_flags & BGE_FLAG_TBI) {
3970 ifmr->ifm_status = IFM_AVALID;
3971 ifmr->ifm_active = IFM_ETHER;
3972 if (CSR_READ_4(sc, BGE_MAC_STS) &
3973 BGE_MACSTAT_TBI_PCS_SYNCHED)
3974 ifmr->ifm_status |= IFM_ACTIVE;
3975 else {
3976 ifmr->ifm_active |= IFM_NONE;
3977 BGE_UNLOCK(sc);
3978 return;
3979 }
3980 ifmr->ifm_active |= IFM_1000_SX;
3981 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3982 ifmr->ifm_active |= IFM_HDX;
3983 else
3984 ifmr->ifm_active |= IFM_FDX;
3985 BGE_UNLOCK(sc);
3986 return;
3987 }
3988
3989 mii = device_get_softc(sc->bge_miibus);
3990 mii_pollstat(mii);
3991 ifmr->ifm_active = mii->mii_media_active;
3992 ifmr->ifm_status = mii->mii_media_status;
3993
3994 BGE_UNLOCK(sc);
3995}
3996
3997static int
3998bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3999{
4000 struct bge_softc *sc = ifp->if_softc;
4001 struct ifreq *ifr = (struct ifreq *) data;
4002 struct mii_data *mii;
4003 int flags, mask, error = 0;
4004
4005 switch (command) {
4006 case SIOCSIFMTU:
4007 if (ifr->ifr_mtu < ETHERMIN ||
4008 ((BGE_IS_JUMBO_CAPABLE(sc)) &&
4009 ifr->ifr_mtu > BGE_JUMBO_MTU) ||
4010 ((!BGE_IS_JUMBO_CAPABLE(sc)) &&
4011 ifr->ifr_mtu > ETHERMTU))
4012 error = EINVAL;
4013 else if (ifp->if_mtu != ifr->ifr_mtu) {
4014 ifp->if_mtu = ifr->ifr_mtu;
4015 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4016 bge_init(sc);
4017 }
4018 break;
4019 case SIOCSIFFLAGS:
4020 BGE_LOCK(sc);
4021 if (ifp->if_flags & IFF_UP) {
4022 /*
4023 * If only the state of the PROMISC flag changed,
4024 * then just use the 'set promisc mode' command
4025 * instead of reinitializing the entire NIC. Doing
4026 * a full re-init means reloading the firmware and
4027 * waiting for it to start up, which may take a
4028 * second or two. Similarly for ALLMULTI.
4029 */
4030 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4031 flags = ifp->if_flags ^ sc->bge_if_flags;
4032 if (flags & IFF_PROMISC)
4033 bge_setpromisc(sc);
4034 if (flags & IFF_ALLMULTI)
4035 bge_setmulti(sc);
4036 } else
4037 bge_init_locked(sc);
4038 } else {
4039 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4040 bge_stop(sc);
4041 }
4042 }
4043 sc->bge_if_flags = ifp->if_flags;
4044 BGE_UNLOCK(sc);
4045 error = 0;
4046 break;
4047 case SIOCADDMULTI:
4048 case SIOCDELMULTI:
4049 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4050 BGE_LOCK(sc);
4051 bge_setmulti(sc);
4052 BGE_UNLOCK(sc);
4053 error = 0;
4054 }
4055 break;
4056 case SIOCSIFMEDIA:
4057 case SIOCGIFMEDIA:
4058 if (sc->bge_flags & BGE_FLAG_TBI) {
4059 error = ifmedia_ioctl(ifp, ifr,
4060 &sc->bge_ifmedia, command);
4061 } else {
4062 mii = device_get_softc(sc->bge_miibus);
4063 error = ifmedia_ioctl(ifp, ifr,
4064 &mii->mii_media, command);
4065 }
4066 break;
4067 case SIOCSIFCAP:
4068 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4069#ifdef DEVICE_POLLING
4070 if (mask & IFCAP_POLLING) {
4071 if (ifr->ifr_reqcap & IFCAP_POLLING) {
4072 error = ether_poll_register(bge_poll, ifp);
4073 if (error)
4074 return (error);
4075 BGE_LOCK(sc);
4076 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4077 BGE_PCIMISCCTL_MASK_PCI_INTR);
4078 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4079 ifp->if_capenable |= IFCAP_POLLING;
4080 BGE_UNLOCK(sc);
4081 } else {
4082 error = ether_poll_deregister(ifp);
4083 /* Enable interrupt even in error case */
4084 BGE_LOCK(sc);
4085 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
4086 BGE_PCIMISCCTL_MASK_PCI_INTR);
4087 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4088 ifp->if_capenable &= ~IFCAP_POLLING;
4089 BGE_UNLOCK(sc);
4090 }
4091 }
4092#endif
4093 if (mask & IFCAP_HWCSUM) {
4094 ifp->if_capenable ^= IFCAP_HWCSUM;
4095 if (IFCAP_HWCSUM & ifp->if_capenable &&
4096 IFCAP_HWCSUM & ifp->if_capabilities)
4097 ifp->if_hwassist = BGE_CSUM_FEATURES;
4098 else
4099 ifp->if_hwassist = 0;
4100#ifdef VLAN_CAPABILITIES
4101 VLAN_CAPABILITIES(ifp);
4102#endif
4103 }
4104
4105 if (mask & IFCAP_VLAN_MTU) {
4106 ifp->if_capenable ^= IFCAP_VLAN_MTU;
4107 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4108 bge_init(sc);
4109 }
4110
4111 if (mask & IFCAP_VLAN_HWTAGGING) {
4112 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
4113 BGE_LOCK(sc);
4114 bge_setvlan(sc);
4115 BGE_UNLOCK(sc);
4116#ifdef VLAN_CAPABILITIES
4117 VLAN_CAPABILITIES(ifp);
4118#endif
4119 }
4120
4121 break;
4122 default:
4123 error = ether_ioctl(ifp, command, data);
4124 break;
4125 }
4126
4127 return (error);
4128}
4129
4130static void
4131bge_watchdog(struct bge_softc *sc)
4132{
4133 struct ifnet *ifp;
4134
4135 BGE_LOCK_ASSERT(sc);
4136
4137 if (sc->bge_timer == 0 || --sc->bge_timer)
4138 return;
4139
4140 ifp = sc->bge_ifp;
4141
4142 if_printf(ifp, "watchdog timeout -- resetting\n");
4143
4144 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4145 bge_init_locked(sc);
4146
4147 ifp->if_oerrors++;
4148}
4149
4150/*
4151 * Stop the adapter and free any mbufs allocated to the
4152 * RX and TX lists.
4153 */
4154static void
4155bge_stop(struct bge_softc *sc)
4156{
4157 struct ifnet *ifp;
4158 struct ifmedia_entry *ifm;
4159 struct mii_data *mii = NULL;
4160 int mtmp, itmp;
4161
4162 BGE_LOCK_ASSERT(sc);
4163
4164 ifp = sc->bge_ifp;
4165
4166 if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
4167 mii = device_get_softc(sc->bge_miibus);
4168
4169 callout_stop(&sc->bge_stat_ch);
4170
4171 /*
4172 * Disable all of the receiver blocks.
4173 */
4174 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4175 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
4176 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
4177 if (!(BGE_IS_5705_PLUS(sc)))
4178 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
4179 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
4180 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
4181 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
4182
4183 /*
4184 * Disable all of the transmit blocks.
4185 */
4186 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
4187 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
4188 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
4189 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
4190 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
4191 if (!(BGE_IS_5705_PLUS(sc)))
4192 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
4193 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
4194
4195 /*
4196 * Shut down all of the memory managers and related
4197 * state machines.
4198 */
4199 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4200 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4201 if (!(BGE_IS_5705_PLUS(sc)))
4202 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4203 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4204 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4205 if (!(BGE_IS_5705_PLUS(sc))) {
4206 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4207 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4208 }
4209
4210 /* Disable host interrupts. */
4211 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4212 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4213
4214 /*
4215 * Tell firmware we're shutting down.
4216 */
4217
4218 bge_stop_fw(sc);
4219 bge_sig_pre_reset(sc, BGE_RESET_STOP);
4220 bge_reset(sc);
4221 bge_sig_legacy(sc, BGE_RESET_STOP);
4222 bge_sig_post_reset(sc, BGE_RESET_STOP);
4223
4224 /*
4225 * Keep the ASF firmware running if up.
4226 */
4227 if (sc->bge_asf_mode & ASF_STACKUP)
4228 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4229 else
4230 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4231
4232 /* Free the RX lists. */
4233 bge_free_rx_ring_std(sc);
4234
4235 /* Free jumbo RX list. */
4236 if (BGE_IS_JUMBO_CAPABLE(sc))
4237 bge_free_rx_ring_jumbo(sc);
4238
4239 /* Free TX buffers. */
4240 bge_free_tx_ring(sc);
4241
4242 /*
4243 * Isolate/power down the PHY, but leave the media selection
4244 * unchanged so that things will be put back to normal when
4245 * we bring the interface back up.
4246 */
4247 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4248 itmp = ifp->if_flags;
4249 ifp->if_flags |= IFF_UP;
4250 /*
4251 * If we are called from bge_detach(), mii is already NULL.
4252 */
4253 if (mii != NULL) {
4254 ifm = mii->mii_media.ifm_cur;
4255 mtmp = ifm->ifm_media;
4256 ifm->ifm_media = IFM_ETHER | IFM_NONE;
4257 mii_mediachg(mii);
4258 ifm->ifm_media = mtmp;
4259 }
4260 ifp->if_flags = itmp;
4261 }
4262
4263 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4264
4265 /* Clear MAC's link state (PHY may still have link UP). */
4266 if (bootverbose && sc->bge_link)
4267 if_printf(sc->bge_ifp, "link DOWN\n");
4268 sc->bge_link = 0;
4269
4270 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4271}
4272
4273/*
4274 * Stop all chip I/O so that the kernel's probe routines don't
4275 * get confused by errant DMAs when rebooting.
4276 */
4277static void
4278bge_shutdown(device_t dev)
4279{
4280 struct bge_softc *sc;
4281
4282 sc = device_get_softc(dev);
4283
4284 BGE_LOCK(sc);
4285 bge_stop(sc);
4286 bge_reset(sc);
4287 BGE_UNLOCK(sc);
4288}
4289
4290static int
4291bge_suspend(device_t dev)
4292{
4293 struct bge_softc *sc;
4294
4295 sc = device_get_softc(dev);
4296 BGE_LOCK(sc);
4297 bge_stop(sc);
4298 BGE_UNLOCK(sc);
4299
4300 return (0);
4301}
4302
4303static int
4304bge_resume(device_t dev)
4305{
4306 struct bge_softc *sc;
4307 struct ifnet *ifp;
4308
4309 sc = device_get_softc(dev);
4310 BGE_LOCK(sc);
4311 ifp = sc->bge_ifp;
4312 if (ifp->if_flags & IFF_UP) {
4313 bge_init_locked(sc);
4314 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4315 bge_start_locked(ifp);
4316 }
4317 BGE_UNLOCK(sc);
4318
4319 return (0);
4320}
4321
4322static void
4323bge_link_upd(struct bge_softc *sc)
4324{
4325 struct mii_data *mii;
4326 uint32_t link, status;
4327
4328 BGE_LOCK_ASSERT(sc);
4329
4330 /* Clear 'pending link event' flag. */
4331 sc->bge_link_evt = 0;
4332
4333 /*
4334 * Process link state changes.
4335 * Grrr. The link status word in the status block does
4336 * not work correctly on the BCM5700 rev AX and BX chips,
4337 * according to all available information. Hence, we have
4338 * to enable MII interrupts in order to properly obtain
4339 * async link changes. Unfortunately, this also means that
4340 * we have to read the MAC status register to detect link
4341 * changes, thereby adding an additional register access to
4342 * the interrupt handler.
4343 *
4344 * XXX: perhaps link state detection procedure used for
4345 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4346 */
4347
4348 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4349 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
4350 status = CSR_READ_4(sc, BGE_MAC_STS);
4351 if (status & BGE_MACSTAT_MI_INTERRUPT) {
4352 mii = device_get_softc(sc->bge_miibus);
4353 mii_pollstat(mii);
4354 if (!sc->bge_link &&
4355 mii->mii_media_status & IFM_ACTIVE &&
4356 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4357 sc->bge_link++;
4358 if (bootverbose)
4359 if_printf(sc->bge_ifp, "link UP\n");
4360 } else if (sc->bge_link &&
4361 (!(mii->mii_media_status & IFM_ACTIVE) ||
4362 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4363 sc->bge_link = 0;
4364 if (bootverbose)
4365 if_printf(sc->bge_ifp, "link DOWN\n");
4366 }
4367
4368 /* Clear the interrupt. */
4369 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
4370 BGE_EVTENB_MI_INTERRUPT);
4371 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4372 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
4373 BRGPHY_INTRS);
4374 }
4375 return;
4376 }
4377
4378 if (sc->bge_flags & BGE_FLAG_TBI) {
4379 status = CSR_READ_4(sc, BGE_MAC_STS);
4380 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4381 if (!sc->bge_link) {
4382 sc->bge_link++;
4383 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
4384 BGE_CLRBIT(sc, BGE_MAC_MODE,
4385 BGE_MACMODE_TBI_SEND_CFGS);
4386 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4387 if (bootverbose)
4388 if_printf(sc->bge_ifp, "link UP\n");
4389 if_link_state_change(sc->bge_ifp,
4390 LINK_STATE_UP);
4391 }
4392 } else if (sc->bge_link) {
4393 sc->bge_link = 0;
4394 if (bootverbose)
4395 if_printf(sc->bge_ifp, "link DOWN\n");
4396 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
4397 }
4398 } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
4399 /*
4400 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
4401 * in status word always set. Workaround this bug by reading
4402 * PHY link status directly.
4403 */
4404 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
4405
4406 if (link != sc->bge_link ||
4407 sc->bge_asicrev == BGE_ASICREV_BCM5700) {
4408 mii = device_get_softc(sc->bge_miibus);
4409 mii_pollstat(mii);
4410 if (!sc->bge_link &&
4411 mii->mii_media_status & IFM_ACTIVE &&
4412 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4413 sc->bge_link++;
4414 if (bootverbose)
4415 if_printf(sc->bge_ifp, "link UP\n");
4416 } else if (sc->bge_link &&
4417 (!(mii->mii_media_status & IFM_ACTIVE) ||
4418 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4419 sc->bge_link = 0;
4420 if (bootverbose)
4421 if_printf(sc->bge_ifp, "link DOWN\n");
4422 }
4423 }
4424 } else {
4425 /*
4426 * Discard link events for MII/GMII controllers
4427 * if MI auto-polling is disabled.
4428 */
4429 }
4430
4431 /* Clear the attention. */
4432 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4433 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4434 BGE_MACSTAT_LINK_CHANGED);
4435}
4436
4437#define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
4438 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
4439 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
4440 desc)
4441
4442static void
4443bge_add_sysctls(struct bge_softc *sc)
4444{
4445 struct sysctl_ctx_list *ctx;
4446 struct sysctl_oid_list *children, *schildren;
4447 struct sysctl_oid *tree;
4448
4449 ctx = device_get_sysctl_ctx(sc->bge_dev);
4450 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
4451
4452#ifdef BGE_REGISTER_DEBUG
4453 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
4454 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
4455 "Debug Information");
4456
4457 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
4458 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
4459 "Register Read");
4460
4461 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
4462 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
4463 "Memory Read");
4464
4465#endif
4466
4467 if (BGE_IS_5705_PLUS(sc))
4468 return;
4469
4470 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4471 NULL, "BGE Statistics");
4472 schildren = children = SYSCTL_CHILDREN(tree);
4473 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
4474 children, COSFramesDroppedDueToFilters,
4475 "FramesDroppedDueToFilters");
4476 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
4477 children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
4478 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
4479 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
4480 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
4481 children, nicNoMoreRxBDs, "NoMoreRxBDs");
4482 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
4483 children, ifInDiscards, "InputDiscards");
4484 BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
4485 children, ifInErrors, "InputErrors");
4486 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
4487 children, nicRecvThresholdHit, "RecvThresholdHit");
4488 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
4489 children, nicDmaReadQueueFull, "DmaReadQueueFull");
4490 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
4491 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
4492 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
4493 children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
4494 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
4495 children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
4496 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
4497 children, nicRingStatusUpdate, "RingStatusUpdate");
4498 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
4499 children, nicInterrupts, "Interrupts");
4500 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
4501 children, nicAvoidedInterrupts, "AvoidedInterrupts");
4502 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
4503 children, nicSendThresholdHit, "SendThresholdHit");
4504
4505 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
4506 NULL, "BGE RX Statistics");
4507 children = SYSCTL_CHILDREN(tree);
4508 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
4509 children, rxstats.ifHCInOctets, "Octets");
4510 BGE_SYSCTL_STAT(sc, ctx, "Fragments",
4511 children, rxstats.etherStatsFragments, "Fragments");
4512 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
4513 children, rxstats.ifHCInUcastPkts, "UcastPkts");
4514 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
4515 children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
4516 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
4517 children, rxstats.dot3StatsFCSErrors, "FCSErrors");
4518 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
4519 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
4520 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
4521 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
4522 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
4523 children, rxstats.xoffPauseFramesReceived,
4524 "xoffPauseFramesReceived");
4525 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
4526 children, rxstats.macControlFramesReceived,
4527 "ControlFramesReceived");
4528 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
4529 children, rxstats.xoffStateEntered, "xoffStateEntered");
4530 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
4531 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
4532 BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
4533 children, rxstats.etherStatsJabbers, "Jabbers");
4534 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
4535 children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
4536 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
4537 children, rxstats.inRangeLengthError, "inRangeLengthError");
4538 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
4539 children, rxstats.outRangeLengthError, "outRangeLengthError");
4540
4541 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
4542 NULL, "BGE TX Statistics");
4543 children = SYSCTL_CHILDREN(tree);
4544 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
4545 children, txstats.ifHCOutOctets, "Octets");
4546 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
4547 children, txstats.etherStatsCollisions, "Collisions");
4548 BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
4549 children, txstats.outXonSent, "XonSent");
4550 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
4551 children, txstats.outXoffSent, "XoffSent");
4552 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
4553 children, txstats.flowControlDone, "flowControlDone");
4554 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
4555 children, txstats.dot3StatsInternalMacTransmitErrors,
4556 "InternalMacTransmitErrors");
4557 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
4558 children, txstats.dot3StatsSingleCollisionFrames,
4559 "SingleCollisionFrames");
4560 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
4561 children, txstats.dot3StatsMultipleCollisionFrames,
4562 "MultipleCollisionFrames");
4563 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
4564 children, txstats.dot3StatsDeferredTransmissions,
4565 "DeferredTransmissions");
4566 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
4567 children, txstats.dot3StatsExcessiveCollisions,
4568 "ExcessiveCollisions");
4569 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
4570 children, txstats.dot3StatsLateCollisions,
4571 "LateCollisions");
4572 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
4573 children, txstats.ifHCOutUcastPkts, "UcastPkts");
4574 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
4575 children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
4576 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
4577 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
4578 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
4579 children, txstats.dot3StatsCarrierSenseErrors,
4580 "CarrierSenseErrors");
4581 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
4582 children, txstats.ifOutDiscards, "Discards");
4583 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
4584 children, txstats.ifOutErrors, "Errors");
4585}
4586
4587static int
4588bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
4589{
4590 struct bge_softc *sc;
4591 uint32_t result;
4592 int offset;
4593
4594 sc = (struct bge_softc *)arg1;
4595 offset = arg2;
4596 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
4597 offsetof(bge_hostaddr, bge_addr_lo));
4598 return (sysctl_handle_int(oidp, &result, 0, req));
4599}
4600
4601#ifdef BGE_REGISTER_DEBUG
4602static int
4603bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4604{
4605 struct bge_softc *sc;
4606 uint16_t *sbdata;
4607 int error;
4608 int result;
4609 int i, j;
4610
4611 result = -1;
4612 error = sysctl_handle_int(oidp, &result, 0, req);
4613 if (error || (req->newptr == NULL))
4614 return (error);
4615
4616 if (result == 1) {
4617 sc = (struct bge_softc *)arg1;
4618
4619 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
4620 printf("Status Block:\n");
4621 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
4622 printf("%06x:", i);
4623 for (j = 0; j < 8; j++) {
4624 printf(" %04x", sbdata[i]);
4625 i += 4;
4626 }
4627 printf("\n");
4628 }
4629
4630 printf("Registers:\n");
4631 for (i = 0x800; i < 0xA00; ) {
4632 printf("%06x:", i);
4633 for (j = 0; j < 8; j++) {
4634 printf(" %08x", CSR_READ_4(sc, i));
4635 i += 4;
4636 }
4637 printf("\n");
4638 }
4639
4640 printf("Hardware Flags:\n");
4641 if (BGE_IS_575X_PLUS(sc))
4642 printf(" - 575X Plus\n");
4643 if (BGE_IS_5705_PLUS(sc))
4644 printf(" - 5705 Plus\n");
4645 if (BGE_IS_5714_FAMILY(sc))
4646 printf(" - 5714 Family\n");
4647 if (BGE_IS_5700_FAMILY(sc))
4648 printf(" - 5700 Family\n");
4649 if (sc->bge_flags & BGE_FLAG_JUMBO)
4650 printf(" - Supports Jumbo Frames\n");
4651 if (sc->bge_flags & BGE_FLAG_PCIX)
4652 printf(" - PCI-X Bus\n");
4653 if (sc->bge_flags & BGE_FLAG_PCIE)
4654 printf(" - PCI Express Bus\n");
4655 if (sc->bge_flags & BGE_FLAG_NO_3LED)
4656 printf(" - No 3 LEDs\n");
4657 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
4658 printf(" - RX Alignment Bug\n");
4659 }
4660
4661 return (error);
4662}
4663
4664static int
4665bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
4666{
4667 struct bge_softc *sc;
4668 int error;
4669 uint16_t result;
4670 uint32_t val;
4671
4672 result = -1;
4673 error = sysctl_handle_int(oidp, &result, 0, req);
4674 if (error || (req->newptr == NULL))
4675 return (error);
4676
4677 if (result < 0x8000) {
4678 sc = (struct bge_softc *)arg1;
4679 val = CSR_READ_4(sc, result);
4680 printf("reg 0x%06X = 0x%08X\n", result, val);
4681 }
4682
4683 return (error);
4684}
4685
4686static int
4687bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
4688{
4689 struct bge_softc *sc;
4690 int error;
4691 uint16_t result;
4692 uint32_t val;
4693
4694 result = -1;
4695 error = sysctl_handle_int(oidp, &result, 0, req);
4696 if (error || (req->newptr == NULL))
4697 return (error);
4698
4699 if (result < 0x8000) {
4700 sc = (struct bge_softc *)arg1;
4701 val = bge_readmem_ind(sc, result);
4702 printf("mem 0x%06X = 0x%08X\n", result, val);
4703 }
4704
4705 return (error);
4706}
4707#endif
4708
4709static int
4710bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
4711{
4712
4713 if (sc->bge_flags & BGE_FLAG_EADDR)
4714 return (1);
4715
4716#ifdef __sparc64__
4717 OF_getetheraddr(sc->bge_dev, ether_addr);
4718 return (0);
4719#endif
4720 return (1);
4721}
4722
4723static int
4724bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
4725{
4726 uint32_t mac_addr;
4727
4728 mac_addr = bge_readmem_ind(sc, 0x0c14);
4729 if ((mac_addr >> 16) == 0x484b) {
4730 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4731 ether_addr[1] = (uint8_t)mac_addr;
4732 mac_addr = bge_readmem_ind(sc, 0x0c18);
4733 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4734 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4735 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4736 ether_addr[5] = (uint8_t)mac_addr;
4737 return (0);
4738 }
4739 return (1);
4740}
4741
4742static int
4743bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
4744{
4745 int mac_offset = BGE_EE_MAC_OFFSET;
4746
4747 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4748 mac_offset = BGE_EE_MAC_OFFSET_5906;
4749
4750 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
4751 ETHER_ADDR_LEN));
4752}
4753
4754static int
4755bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4756{
4757
4758 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4759 return (1);
4760
4761 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4762 ETHER_ADDR_LEN));
4763}
4764
4765static int
4766bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4767{
4768 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4769 /* NOTE: Order is critical */
4770 bge_get_eaddr_fw,
4771 bge_get_eaddr_mem,
4772 bge_get_eaddr_nvram,
4773 bge_get_eaddr_eeprom,
4774 NULL
4775 };
4776 const bge_eaddr_fcn_t *func;
4777
4778 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4779 if ((*func)(sc, eaddr) == 0)
4780 break;
4781 }
4782 return (*func == NULL ? ENXIO : 0);
4783}
| 3396 mii_tick(mii);
3397 } else {
3398 /*
3399 * Since in TBI mode auto-polling can't be used we should poll
3400 * link status manually. Here we register pending link event
3401 * and trigger interrupt.
3402 */
3403#ifdef DEVICE_POLLING
3404 /* In polling mode we poll link state in bge_poll(). */
3405 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
3406#endif
3407 {
3408 sc->bge_link_evt++;
3409 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3410 sc->bge_flags & BGE_FLAG_5788)
3411 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3412 else
3413 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3414 }
3415 }
3416
3417 bge_asf_driver_up(sc);
3418 bge_watchdog(sc);
3419
3420 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3421}
3422
3423static void
3424bge_stats_update_regs(struct bge_softc *sc)
3425{
3426 struct ifnet *ifp;
3427
3428 ifp = sc->bge_ifp;
3429
3430 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
3431 offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
3432
3433 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3434}
3435
3436static void
3437bge_stats_update(struct bge_softc *sc)
3438{
3439 struct ifnet *ifp;
3440 bus_size_t stats;
3441 uint32_t cnt; /* current register value */
3442
3443 ifp = sc->bge_ifp;
3444
3445 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3446
3447#define READ_STAT(sc, stats, stat) \
3448 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3449
3450 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
3451 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
3452 sc->bge_tx_collisions = cnt;
3453
3454 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
3455 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
3456 sc->bge_rx_discards = cnt;
3457
3458 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
3459 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
3460 sc->bge_tx_discards = cnt;
3461
3462#undef READ_STAT
3463}
3464
3465/*
3466 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
3467 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
3468 * but when such padded frames employ the bge IP/TCP checksum offload,
3469 * the hardware checksum assist gives incorrect results (possibly
3470 * from incorporating its own padding into the UDP/TCP checksum; who knows).
3471 * If we pad such runts with zeros, the onboard checksum comes out correct.
3472 */
3473static __inline int
3474bge_cksum_pad(struct mbuf *m)
3475{
3476 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
3477 struct mbuf *last;
3478
3479 /* If there's only the packet-header and we can pad there, use it. */
3480 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
3481 M_TRAILINGSPACE(m) >= padlen) {
3482 last = m;
3483 } else {
3484 /*
3485 * Walk packet chain to find last mbuf. We will either
3486 * pad there, or append a new mbuf and pad it.
3487 */
3488 for (last = m; last->m_next != NULL; last = last->m_next);
3489 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
3490 /* Allocate new empty mbuf, pad it. Compact later. */
3491 struct mbuf *n;
3492
3493 MGET(n, M_DONTWAIT, MT_DATA);
3494 if (n == NULL)
3495 return (ENOBUFS);
3496 n->m_len = 0;
3497 last->m_next = n;
3498 last = n;
3499 }
3500 }
3501
3502 /* Now zero the pad area, to avoid the bge cksum-assist bug. */
3503 memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
3504 last->m_len += padlen;
3505 m->m_pkthdr.len += padlen;
3506
3507 return (0);
3508}
3509
3510/*
3511 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3512 * pointers to descriptors.
3513 */
3514static int
3515bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
3516{
3517 bus_dma_segment_t segs[BGE_NSEG_NEW];
3518 bus_dmamap_t map;
3519 struct bge_tx_bd *d;
3520 struct mbuf *m = *m_head;
3521 uint32_t idx = *txidx;
3522 uint16_t csum_flags;
3523 int nsegs, i, error;
3524
3525 csum_flags = 0;
3526 if (m->m_pkthdr.csum_flags) {
3527 if (m->m_pkthdr.csum_flags & CSUM_IP)
3528 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3529 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
3530 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3531 if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
3532 (error = bge_cksum_pad(m)) != 0) {
3533 m_freem(m);
3534 *m_head = NULL;
3535 return (error);
3536 }
3537 }
3538 if (m->m_flags & M_LASTFRAG)
3539 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3540 else if (m->m_flags & M_FRAG)
3541 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3542 }
3543
3544 map = sc->bge_cdata.bge_tx_dmamap[idx];
3545 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, segs,
3546 &nsegs, BUS_DMA_NOWAIT);
3547 if (error == EFBIG) {
3548 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
3549 if (m == NULL) {
3550 m_freem(*m_head);
3551 *m_head = NULL;
3552 return (ENOBUFS);
3553 }
3554 *m_head = m;
3555 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m,
3556 segs, &nsegs, BUS_DMA_NOWAIT);
3557 if (error) {
3558 m_freem(m);
3559 *m_head = NULL;
3560 return (error);
3561 }
3562 } else if (error != 0)
3563 return (error);
3564
3565 /*
3566 * Sanity check: avoid coming within 16 descriptors
3567 * of the end of the ring.
3568 */
3569 if (nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) {
3570 bus_dmamap_unload(sc->bge_cdata.bge_mtag, map);
3571 return (ENOBUFS);
3572 }
3573
3574 bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
3575
3576 for (i = 0; ; i++) {
3577 d = &sc->bge_ldata.bge_tx_ring[idx];
3578 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3579 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3580 d->bge_len = segs[i].ds_len;
3581 d->bge_flags = csum_flags;
3582 if (i == nsegs - 1)
3583 break;
3584 BGE_INC(idx, BGE_TX_RING_CNT);
3585 }
3586
3587 /* Mark the last segment as end of packet... */
3588 d->bge_flags |= BGE_TXBDFLAG_END;
3589
3590 /* ... and put VLAN tag into first segment. */
3591 d = &sc->bge_ldata.bge_tx_ring[*txidx];
3592#if __FreeBSD_version > 700022
3593 if (m->m_flags & M_VLANTAG) {
3594 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3595 d->bge_vlan_tag = m->m_pkthdr.ether_vtag;
3596 } else
3597 d->bge_vlan_tag = 0;
3598#else
3599 {
3600 struct m_tag *mtag;
3601
3602 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) {
3603 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3604 d->bge_vlan_tag = VLAN_TAG_VALUE(mtag);
3605 } else
3606 d->bge_vlan_tag = 0;
3607 }
3608#endif
3609
3610 /*
3611 * Insure that the map for this transmission
3612 * is placed at the array index of the last descriptor
3613 * in this chain.
3614 */
3615 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3616 sc->bge_cdata.bge_tx_dmamap[idx] = map;
3617 sc->bge_cdata.bge_tx_chain[idx] = m;
3618 sc->bge_txcnt += nsegs;
3619
3620 BGE_INC(idx, BGE_TX_RING_CNT);
3621 *txidx = idx;
3622
3623 return (0);
3624}
3625
3626/*
3627 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3628 * to the mbuf data regions directly in the transmit descriptors.
3629 */
3630static void
3631bge_start_locked(struct ifnet *ifp)
3632{
3633 struct bge_softc *sc;
3634 struct mbuf *m_head = NULL;
3635 uint32_t prodidx;
3636 int count = 0;
3637
3638 sc = ifp->if_softc;
3639
3640 if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3641 return;
3642
3643 prodidx = sc->bge_tx_prodidx;
3644
3645 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3646 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3647 if (m_head == NULL)
3648 break;
3649
3650 /*
3651 * XXX
3652 * The code inside the if() block is never reached since we
3653 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3654 * requests to checksum TCP/UDP in a fragmented packet.
3655 *
3656 * XXX
3657 * safety overkill. If this is a fragmented packet chain
3658 * with delayed TCP/UDP checksums, then only encapsulate
3659 * it if we have enough descriptors to handle the entire
3660 * chain at once.
3661 * (paranoia -- may not actually be needed)
3662 */
3663 if (m_head->m_flags & M_FIRSTFRAG &&
3664 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
3665 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3666 m_head->m_pkthdr.csum_data + 16) {
3667 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3668 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3669 break;
3670 }
3671 }
3672
3673 /*
3674 * Pack the data into the transmit ring. If we
3675 * don't have room, set the OACTIVE flag and wait
3676 * for the NIC to drain the ring.
3677 */
3678 if (bge_encap(sc, &m_head, &prodidx)) {
3679 if (m_head == NULL)
3680 break;
3681 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3682 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3683 break;
3684 }
3685 ++count;
3686
3687 /*
3688 * If there's a BPF listener, bounce a copy of this frame
3689 * to him.
3690 */
3691#ifdef ETHER_BPF_MTAP
3692 ETHER_BPF_MTAP(ifp, m_head);
3693#else
3694 BPF_MTAP(ifp, m_head);
3695#endif
3696 }
3697
3698 if (count == 0)
3699 /* No packets were dequeued. */
3700 return;
3701
3702 /* Transmit. */
3703 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3704 /* 5700 b2 errata */
3705 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3706 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3707
3708 sc->bge_tx_prodidx = prodidx;
3709
3710 /*
3711 * Set a timeout in case the chip goes out to lunch.
3712 */
3713 sc->bge_timer = 5;
3714}
3715
3716/*
3717 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3718 * to the mbuf data regions directly in the transmit descriptors.
3719 */
3720static void
3721bge_start(struct ifnet *ifp)
3722{
3723 struct bge_softc *sc;
3724
3725 sc = ifp->if_softc;
3726 BGE_LOCK(sc);
3727 bge_start_locked(ifp);
3728 BGE_UNLOCK(sc);
3729}
3730
3731static void
3732bge_init_locked(struct bge_softc *sc)
3733{
3734 struct ifnet *ifp;
3735 uint16_t *m;
3736
3737 BGE_LOCK_ASSERT(sc);
3738
3739 ifp = sc->bge_ifp;
3740
3741 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3742 return;
3743
3744 /* Cancel pending I/O and flush buffers. */
3745 bge_stop(sc);
3746
3747 bge_stop_fw(sc);
3748 bge_sig_pre_reset(sc, BGE_RESET_START);
3749 bge_reset(sc);
3750 bge_sig_legacy(sc, BGE_RESET_START);
3751 bge_sig_post_reset(sc, BGE_RESET_START);
3752
3753 bge_chipinit(sc);
3754
3755 /*
3756 * Init the various state machines, ring
3757 * control blocks and firmware.
3758 */
3759 if (bge_blockinit(sc)) {
3760 device_printf(sc->bge_dev, "initialization failure\n");
3761 return;
3762 }
3763
3764 ifp = sc->bge_ifp;
3765
3766 /* Specify MTU. */
3767 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3768 ETHER_HDR_LEN + ETHER_CRC_LEN +
3769 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
3770
3771 /* Load our MAC address. */
3772 m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
3773 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3774 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3775
3776 /* Program promiscuous mode. */
3777 bge_setpromisc(sc);
3778
3779 /* Program multicast filter. */
3780 bge_setmulti(sc);
3781
3782 /* Program VLAN tag stripping. */
3783 bge_setvlan(sc);
3784
3785 /* Init RX ring. */
3786 bge_init_rx_ring_std(sc);
3787
3788 /*
3789 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3790 * memory to insure that the chip has in fact read the first
3791 * entry of the ring.
3792 */
3793 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3794 uint32_t v, i;
3795 for (i = 0; i < 10; i++) {
3796 DELAY(20);
3797 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3798 if (v == (MCLBYTES - ETHER_ALIGN))
3799 break;
3800 }
3801 if (i == 10)
3802 device_printf (sc->bge_dev,
3803 "5705 A0 chip failed to load RX ring\n");
3804 }
3805
3806 /* Init jumbo RX ring. */
3807 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
3808 bge_init_rx_ring_jumbo(sc);
3809
3810 /* Init our RX return ring index. */
3811 sc->bge_rx_saved_considx = 0;
3812
3813 /* Init our RX/TX stat counters. */
3814 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
3815
3816 /* Init TX ring. */
3817 bge_init_tx_ring(sc);
3818
3819 /* Turn on transmitter. */
3820 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3821
3822 /* Turn on receiver. */
3823 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3824
3825 /* Tell firmware we're alive. */
3826 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3827
3828#ifdef DEVICE_POLLING
3829 /* Disable interrupts if we are polling. */
3830 if (ifp->if_capenable & IFCAP_POLLING) {
3831 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
3832 BGE_PCIMISCCTL_MASK_PCI_INTR);
3833 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3834 } else
3835#endif
3836
3837 /* Enable host interrupts. */
3838 {
3839 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3840 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3841 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3842 }
3843
3844 bge_ifmedia_upd_locked(ifp);
3845
3846 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3847 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3848
3849 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3850}
3851
3852static void
3853bge_init(void *xsc)
3854{
3855 struct bge_softc *sc = xsc;
3856
3857 BGE_LOCK(sc);
3858 bge_init_locked(sc);
3859 BGE_UNLOCK(sc);
3860}
3861
3862/*
3863 * Set media options.
3864 */
3865static int
3866bge_ifmedia_upd(struct ifnet *ifp)
3867{
3868 struct bge_softc *sc = ifp->if_softc;
3869 int res;
3870
3871 BGE_LOCK(sc);
3872 res = bge_ifmedia_upd_locked(ifp);
3873 BGE_UNLOCK(sc);
3874
3875 return (res);
3876}
3877
3878static int
3879bge_ifmedia_upd_locked(struct ifnet *ifp)
3880{
3881 struct bge_softc *sc = ifp->if_softc;
3882 struct mii_data *mii;
3883 struct ifmedia *ifm;
3884
3885 BGE_LOCK_ASSERT(sc);
3886
3887 ifm = &sc->bge_ifmedia;
3888
3889 /* If this is a 1000baseX NIC, enable the TBI port. */
3890 if (sc->bge_flags & BGE_FLAG_TBI) {
3891 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3892 return (EINVAL);
3893 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3894 case IFM_AUTO:
3895 /*
3896 * The BCM5704 ASIC appears to have a special
3897 * mechanism for programming the autoneg
3898 * advertisement registers in TBI mode.
3899 */
3900 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3901 uint32_t sgdig;
3902 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
3903 if (sgdig & BGE_SGDIGSTS_DONE) {
3904 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3905 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3906 sgdig |= BGE_SGDIGCFG_AUTO |
3907 BGE_SGDIGCFG_PAUSE_CAP |
3908 BGE_SGDIGCFG_ASYM_PAUSE;
3909 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3910 sgdig | BGE_SGDIGCFG_SEND);
3911 DELAY(5);
3912 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3913 }
3914 }
3915 break;
3916 case IFM_1000_SX:
3917 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3918 BGE_CLRBIT(sc, BGE_MAC_MODE,
3919 BGE_MACMODE_HALF_DUPLEX);
3920 } else {
3921 BGE_SETBIT(sc, BGE_MAC_MODE,
3922 BGE_MACMODE_HALF_DUPLEX);
3923 }
3924 break;
3925 default:
3926 return (EINVAL);
3927 }
3928 return (0);
3929 }
3930
3931 sc->bge_link_evt++;
3932 mii = device_get_softc(sc->bge_miibus);
3933 if (mii->mii_instance) {
3934 struct mii_softc *miisc;
3935 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
3936 miisc = LIST_NEXT(miisc, mii_list))
3937 mii_phy_reset(miisc);
3938 }
3939 mii_mediachg(mii);
3940
3941 /*
3942 * Force an interrupt so that we will call bge_link_upd
3943 * if needed and clear any pending link state attention.
3944 * Without this we are not getting any further interrupts
3945 * for link state changes and thus will not UP the link and
3946 * not be able to send in bge_start_locked. The only
3947 * way to get things working was to receive a packet and
3948 * get an RX intr.
3949 * bge_tick should help for fiber cards and we might not
3950 * need to do this here if BGE_FLAG_TBI is set but as
3951 * we poll for fiber anyway it should not harm.
3952 */
3953 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3954 sc->bge_flags & BGE_FLAG_5788)
3955 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3956 else
3957 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3958
3959 return (0);
3960}
3961
3962/*
3963 * Report current media status.
3964 */
3965static void
3966bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3967{
3968 struct bge_softc *sc = ifp->if_softc;
3969 struct mii_data *mii;
3970
3971 BGE_LOCK(sc);
3972
3973 if (sc->bge_flags & BGE_FLAG_TBI) {
3974 ifmr->ifm_status = IFM_AVALID;
3975 ifmr->ifm_active = IFM_ETHER;
3976 if (CSR_READ_4(sc, BGE_MAC_STS) &
3977 BGE_MACSTAT_TBI_PCS_SYNCHED)
3978 ifmr->ifm_status |= IFM_ACTIVE;
3979 else {
3980 ifmr->ifm_active |= IFM_NONE;
3981 BGE_UNLOCK(sc);
3982 return;
3983 }
3984 ifmr->ifm_active |= IFM_1000_SX;
3985 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3986 ifmr->ifm_active |= IFM_HDX;
3987 else
3988 ifmr->ifm_active |= IFM_FDX;
3989 BGE_UNLOCK(sc);
3990 return;
3991 }
3992
3993 mii = device_get_softc(sc->bge_miibus);
3994 mii_pollstat(mii);
3995 ifmr->ifm_active = mii->mii_media_active;
3996 ifmr->ifm_status = mii->mii_media_status;
3997
3998 BGE_UNLOCK(sc);
3999}
4000
4001static int
4002bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
4003{
4004 struct bge_softc *sc = ifp->if_softc;
4005 struct ifreq *ifr = (struct ifreq *) data;
4006 struct mii_data *mii;
4007 int flags, mask, error = 0;
4008
4009 switch (command) {
4010 case SIOCSIFMTU:
4011 if (ifr->ifr_mtu < ETHERMIN ||
4012 ((BGE_IS_JUMBO_CAPABLE(sc)) &&
4013 ifr->ifr_mtu > BGE_JUMBO_MTU) ||
4014 ((!BGE_IS_JUMBO_CAPABLE(sc)) &&
4015 ifr->ifr_mtu > ETHERMTU))
4016 error = EINVAL;
4017 else if (ifp->if_mtu != ifr->ifr_mtu) {
4018 ifp->if_mtu = ifr->ifr_mtu;
4019 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4020 bge_init(sc);
4021 }
4022 break;
4023 case SIOCSIFFLAGS:
4024 BGE_LOCK(sc);
4025 if (ifp->if_flags & IFF_UP) {
4026 /*
4027 * If only the state of the PROMISC flag changed,
4028 * then just use the 'set promisc mode' command
4029 * instead of reinitializing the entire NIC. Doing
4030 * a full re-init means reloading the firmware and
4031 * waiting for it to start up, which may take a
4032 * second or two. Similarly for ALLMULTI.
4033 */
4034 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4035 flags = ifp->if_flags ^ sc->bge_if_flags;
4036 if (flags & IFF_PROMISC)
4037 bge_setpromisc(sc);
4038 if (flags & IFF_ALLMULTI)
4039 bge_setmulti(sc);
4040 } else
4041 bge_init_locked(sc);
4042 } else {
4043 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4044 bge_stop(sc);
4045 }
4046 }
4047 sc->bge_if_flags = ifp->if_flags;
4048 BGE_UNLOCK(sc);
4049 error = 0;
4050 break;
4051 case SIOCADDMULTI:
4052 case SIOCDELMULTI:
4053 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4054 BGE_LOCK(sc);
4055 bge_setmulti(sc);
4056 BGE_UNLOCK(sc);
4057 error = 0;
4058 }
4059 break;
4060 case SIOCSIFMEDIA:
4061 case SIOCGIFMEDIA:
4062 if (sc->bge_flags & BGE_FLAG_TBI) {
4063 error = ifmedia_ioctl(ifp, ifr,
4064 &sc->bge_ifmedia, command);
4065 } else {
4066 mii = device_get_softc(sc->bge_miibus);
4067 error = ifmedia_ioctl(ifp, ifr,
4068 &mii->mii_media, command);
4069 }
4070 break;
4071 case SIOCSIFCAP:
4072 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4073#ifdef DEVICE_POLLING
4074 if (mask & IFCAP_POLLING) {
4075 if (ifr->ifr_reqcap & IFCAP_POLLING) {
4076 error = ether_poll_register(bge_poll, ifp);
4077 if (error)
4078 return (error);
4079 BGE_LOCK(sc);
4080 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4081 BGE_PCIMISCCTL_MASK_PCI_INTR);
4082 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4083 ifp->if_capenable |= IFCAP_POLLING;
4084 BGE_UNLOCK(sc);
4085 } else {
4086 error = ether_poll_deregister(ifp);
4087 /* Enable interrupt even in error case */
4088 BGE_LOCK(sc);
4089 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
4090 BGE_PCIMISCCTL_MASK_PCI_INTR);
4091 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4092 ifp->if_capenable &= ~IFCAP_POLLING;
4093 BGE_UNLOCK(sc);
4094 }
4095 }
4096#endif
4097 if (mask & IFCAP_HWCSUM) {
4098 ifp->if_capenable ^= IFCAP_HWCSUM;
4099 if (IFCAP_HWCSUM & ifp->if_capenable &&
4100 IFCAP_HWCSUM & ifp->if_capabilities)
4101 ifp->if_hwassist = BGE_CSUM_FEATURES;
4102 else
4103 ifp->if_hwassist = 0;
4104#ifdef VLAN_CAPABILITIES
4105 VLAN_CAPABILITIES(ifp);
4106#endif
4107 }
4108
4109 if (mask & IFCAP_VLAN_MTU) {
4110 ifp->if_capenable ^= IFCAP_VLAN_MTU;
4111 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4112 bge_init(sc);
4113 }
4114
4115 if (mask & IFCAP_VLAN_HWTAGGING) {
4116 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
4117 BGE_LOCK(sc);
4118 bge_setvlan(sc);
4119 BGE_UNLOCK(sc);
4120#ifdef VLAN_CAPABILITIES
4121 VLAN_CAPABILITIES(ifp);
4122#endif
4123 }
4124
4125 break;
4126 default:
4127 error = ether_ioctl(ifp, command, data);
4128 break;
4129 }
4130
4131 return (error);
4132}
4133
4134static void
4135bge_watchdog(struct bge_softc *sc)
4136{
4137 struct ifnet *ifp;
4138
4139 BGE_LOCK_ASSERT(sc);
4140
4141 if (sc->bge_timer == 0 || --sc->bge_timer)
4142 return;
4143
4144 ifp = sc->bge_ifp;
4145
4146 if_printf(ifp, "watchdog timeout -- resetting\n");
4147
4148 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4149 bge_init_locked(sc);
4150
4151 ifp->if_oerrors++;
4152}
4153
4154/*
4155 * Stop the adapter and free any mbufs allocated to the
4156 * RX and TX lists.
4157 */
4158static void
4159bge_stop(struct bge_softc *sc)
4160{
4161 struct ifnet *ifp;
4162 struct ifmedia_entry *ifm;
4163 struct mii_data *mii = NULL;
4164 int mtmp, itmp;
4165
4166 BGE_LOCK_ASSERT(sc);
4167
4168 ifp = sc->bge_ifp;
4169
4170 if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
4171 mii = device_get_softc(sc->bge_miibus);
4172
4173 callout_stop(&sc->bge_stat_ch);
4174
4175 /*
4176 * Disable all of the receiver blocks.
4177 */
4178 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4179 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
4180 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
4181 if (!(BGE_IS_5705_PLUS(sc)))
4182 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
4183 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
4184 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
4185 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
4186
4187 /*
4188 * Disable all of the transmit blocks.
4189 */
4190 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
4191 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
4192 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
4193 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
4194 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
4195 if (!(BGE_IS_5705_PLUS(sc)))
4196 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
4197 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
4198
4199 /*
4200 * Shut down all of the memory managers and related
4201 * state machines.
4202 */
4203 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4204 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4205 if (!(BGE_IS_5705_PLUS(sc)))
4206 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4207 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4208 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4209 if (!(BGE_IS_5705_PLUS(sc))) {
4210 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4211 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4212 }
4213
4214 /* Disable host interrupts. */
4215 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4216 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4217
4218 /*
4219 * Tell firmware we're shutting down.
4220 */
4221
4222 bge_stop_fw(sc);
4223 bge_sig_pre_reset(sc, BGE_RESET_STOP);
4224 bge_reset(sc);
4225 bge_sig_legacy(sc, BGE_RESET_STOP);
4226 bge_sig_post_reset(sc, BGE_RESET_STOP);
4227
4228 /*
4229 * Keep the ASF firmware running if up.
4230 */
4231 if (sc->bge_asf_mode & ASF_STACKUP)
4232 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4233 else
4234 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4235
4236 /* Free the RX lists. */
4237 bge_free_rx_ring_std(sc);
4238
4239 /* Free jumbo RX list. */
4240 if (BGE_IS_JUMBO_CAPABLE(sc))
4241 bge_free_rx_ring_jumbo(sc);
4242
4243 /* Free TX buffers. */
4244 bge_free_tx_ring(sc);
4245
4246 /*
4247 * Isolate/power down the PHY, but leave the media selection
4248 * unchanged so that things will be put back to normal when
4249 * we bring the interface back up.
4250 */
4251 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4252 itmp = ifp->if_flags;
4253 ifp->if_flags |= IFF_UP;
4254 /*
4255 * If we are called from bge_detach(), mii is already NULL.
4256 */
4257 if (mii != NULL) {
4258 ifm = mii->mii_media.ifm_cur;
4259 mtmp = ifm->ifm_media;
4260 ifm->ifm_media = IFM_ETHER | IFM_NONE;
4261 mii_mediachg(mii);
4262 ifm->ifm_media = mtmp;
4263 }
4264 ifp->if_flags = itmp;
4265 }
4266
4267 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4268
4269 /* Clear MAC's link state (PHY may still have link UP). */
4270 if (bootverbose && sc->bge_link)
4271 if_printf(sc->bge_ifp, "link DOWN\n");
4272 sc->bge_link = 0;
4273
4274 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4275}
4276
4277/*
4278 * Stop all chip I/O so that the kernel's probe routines don't
4279 * get confused by errant DMAs when rebooting.
4280 */
4281static void
4282bge_shutdown(device_t dev)
4283{
4284 struct bge_softc *sc;
4285
4286 sc = device_get_softc(dev);
4287
4288 BGE_LOCK(sc);
4289 bge_stop(sc);
4290 bge_reset(sc);
4291 BGE_UNLOCK(sc);
4292}
4293
4294static int
4295bge_suspend(device_t dev)
4296{
4297 struct bge_softc *sc;
4298
4299 sc = device_get_softc(dev);
4300 BGE_LOCK(sc);
4301 bge_stop(sc);
4302 BGE_UNLOCK(sc);
4303
4304 return (0);
4305}
4306
4307static int
4308bge_resume(device_t dev)
4309{
4310 struct bge_softc *sc;
4311 struct ifnet *ifp;
4312
4313 sc = device_get_softc(dev);
4314 BGE_LOCK(sc);
4315 ifp = sc->bge_ifp;
4316 if (ifp->if_flags & IFF_UP) {
4317 bge_init_locked(sc);
4318 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4319 bge_start_locked(ifp);
4320 }
4321 BGE_UNLOCK(sc);
4322
4323 return (0);
4324}
4325
4326static void
4327bge_link_upd(struct bge_softc *sc)
4328{
4329 struct mii_data *mii;
4330 uint32_t link, status;
4331
4332 BGE_LOCK_ASSERT(sc);
4333
4334 /* Clear 'pending link event' flag. */
4335 sc->bge_link_evt = 0;
4336
4337 /*
4338 * Process link state changes.
4339 * Grrr. The link status word in the status block does
4340 * not work correctly on the BCM5700 rev AX and BX chips,
4341 * according to all available information. Hence, we have
4342 * to enable MII interrupts in order to properly obtain
4343 * async link changes. Unfortunately, this also means that
4344 * we have to read the MAC status register to detect link
4345 * changes, thereby adding an additional register access to
4346 * the interrupt handler.
4347 *
4348 * XXX: perhaps link state detection procedure used for
4349 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4350 */
4351
4352 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4353 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
4354 status = CSR_READ_4(sc, BGE_MAC_STS);
4355 if (status & BGE_MACSTAT_MI_INTERRUPT) {
4356 mii = device_get_softc(sc->bge_miibus);
4357 mii_pollstat(mii);
4358 if (!sc->bge_link &&
4359 mii->mii_media_status & IFM_ACTIVE &&
4360 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4361 sc->bge_link++;
4362 if (bootverbose)
4363 if_printf(sc->bge_ifp, "link UP\n");
4364 } else if (sc->bge_link &&
4365 (!(mii->mii_media_status & IFM_ACTIVE) ||
4366 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4367 sc->bge_link = 0;
4368 if (bootverbose)
4369 if_printf(sc->bge_ifp, "link DOWN\n");
4370 }
4371
4372 /* Clear the interrupt. */
4373 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
4374 BGE_EVTENB_MI_INTERRUPT);
4375 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4376 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
4377 BRGPHY_INTRS);
4378 }
4379 return;
4380 }
4381
4382 if (sc->bge_flags & BGE_FLAG_TBI) {
4383 status = CSR_READ_4(sc, BGE_MAC_STS);
4384 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4385 if (!sc->bge_link) {
4386 sc->bge_link++;
4387 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
4388 BGE_CLRBIT(sc, BGE_MAC_MODE,
4389 BGE_MACMODE_TBI_SEND_CFGS);
4390 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4391 if (bootverbose)
4392 if_printf(sc->bge_ifp, "link UP\n");
4393 if_link_state_change(sc->bge_ifp,
4394 LINK_STATE_UP);
4395 }
4396 } else if (sc->bge_link) {
4397 sc->bge_link = 0;
4398 if (bootverbose)
4399 if_printf(sc->bge_ifp, "link DOWN\n");
4400 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
4401 }
4402 } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
4403 /*
4404 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
4405 * in status word always set. Workaround this bug by reading
4406 * PHY link status directly.
4407 */
4408 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
4409
4410 if (link != sc->bge_link ||
4411 sc->bge_asicrev == BGE_ASICREV_BCM5700) {
4412 mii = device_get_softc(sc->bge_miibus);
4413 mii_pollstat(mii);
4414 if (!sc->bge_link &&
4415 mii->mii_media_status & IFM_ACTIVE &&
4416 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4417 sc->bge_link++;
4418 if (bootverbose)
4419 if_printf(sc->bge_ifp, "link UP\n");
4420 } else if (sc->bge_link &&
4421 (!(mii->mii_media_status & IFM_ACTIVE) ||
4422 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4423 sc->bge_link = 0;
4424 if (bootverbose)
4425 if_printf(sc->bge_ifp, "link DOWN\n");
4426 }
4427 }
4428 } else {
4429 /*
4430 * Discard link events for MII/GMII controllers
4431 * if MI auto-polling is disabled.
4432 */
4433 }
4434
4435 /* Clear the attention. */
4436 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4437 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4438 BGE_MACSTAT_LINK_CHANGED);
4439}
4440
4441#define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
4442 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
4443 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
4444 desc)
4445
4446static void
4447bge_add_sysctls(struct bge_softc *sc)
4448{
4449 struct sysctl_ctx_list *ctx;
4450 struct sysctl_oid_list *children, *schildren;
4451 struct sysctl_oid *tree;
4452
4453 ctx = device_get_sysctl_ctx(sc->bge_dev);
4454 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
4455
4456#ifdef BGE_REGISTER_DEBUG
4457 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
4458 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
4459 "Debug Information");
4460
4461 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
4462 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
4463 "Register Read");
4464
4465 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
4466 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
4467 "Memory Read");
4468
4469#endif
4470
4471 if (BGE_IS_5705_PLUS(sc))
4472 return;
4473
4474 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4475 NULL, "BGE Statistics");
4476 schildren = children = SYSCTL_CHILDREN(tree);
4477 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
4478 children, COSFramesDroppedDueToFilters,
4479 "FramesDroppedDueToFilters");
4480 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
4481 children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
4482 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
4483 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
4484 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
4485 children, nicNoMoreRxBDs, "NoMoreRxBDs");
4486 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
4487 children, ifInDiscards, "InputDiscards");
4488 BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
4489 children, ifInErrors, "InputErrors");
4490 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
4491 children, nicRecvThresholdHit, "RecvThresholdHit");
4492 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
4493 children, nicDmaReadQueueFull, "DmaReadQueueFull");
4494 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
4495 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
4496 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
4497 children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
4498 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
4499 children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
4500 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
4501 children, nicRingStatusUpdate, "RingStatusUpdate");
4502 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
4503 children, nicInterrupts, "Interrupts");
4504 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
4505 children, nicAvoidedInterrupts, "AvoidedInterrupts");
4506 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
4507 children, nicSendThresholdHit, "SendThresholdHit");
4508
4509 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
4510 NULL, "BGE RX Statistics");
4511 children = SYSCTL_CHILDREN(tree);
4512 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
4513 children, rxstats.ifHCInOctets, "Octets");
4514 BGE_SYSCTL_STAT(sc, ctx, "Fragments",
4515 children, rxstats.etherStatsFragments, "Fragments");
4516 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
4517 children, rxstats.ifHCInUcastPkts, "UcastPkts");
4518 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
4519 children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
4520 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
4521 children, rxstats.dot3StatsFCSErrors, "FCSErrors");
4522 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
4523 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
4524 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
4525 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
4526 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
4527 children, rxstats.xoffPauseFramesReceived,
4528 "xoffPauseFramesReceived");
4529 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
4530 children, rxstats.macControlFramesReceived,
4531 "ControlFramesReceived");
4532 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
4533 children, rxstats.xoffStateEntered, "xoffStateEntered");
4534 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
4535 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
4536 BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
4537 children, rxstats.etherStatsJabbers, "Jabbers");
4538 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
4539 children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
4540 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
4541 children, rxstats.inRangeLengthError, "inRangeLengthError");
4542 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
4543 children, rxstats.outRangeLengthError, "outRangeLengthError");
4544
4545 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
4546 NULL, "BGE TX Statistics");
4547 children = SYSCTL_CHILDREN(tree);
4548 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
4549 children, txstats.ifHCOutOctets, "Octets");
4550 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
4551 children, txstats.etherStatsCollisions, "Collisions");
4552 BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
4553 children, txstats.outXonSent, "XonSent");
4554 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
4555 children, txstats.outXoffSent, "XoffSent");
4556 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
4557 children, txstats.flowControlDone, "flowControlDone");
4558 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
4559 children, txstats.dot3StatsInternalMacTransmitErrors,
4560 "InternalMacTransmitErrors");
4561 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
4562 children, txstats.dot3StatsSingleCollisionFrames,
4563 "SingleCollisionFrames");
4564 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
4565 children, txstats.dot3StatsMultipleCollisionFrames,
4566 "MultipleCollisionFrames");
4567 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
4568 children, txstats.dot3StatsDeferredTransmissions,
4569 "DeferredTransmissions");
4570 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
4571 children, txstats.dot3StatsExcessiveCollisions,
4572 "ExcessiveCollisions");
4573 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
4574 children, txstats.dot3StatsLateCollisions,
4575 "LateCollisions");
4576 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
4577 children, txstats.ifHCOutUcastPkts, "UcastPkts");
4578 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
4579 children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
4580 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
4581 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
4582 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
4583 children, txstats.dot3StatsCarrierSenseErrors,
4584 "CarrierSenseErrors");
4585 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
4586 children, txstats.ifOutDiscards, "Discards");
4587 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
4588 children, txstats.ifOutErrors, "Errors");
4589}
4590
4591static int
4592bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
4593{
4594 struct bge_softc *sc;
4595 uint32_t result;
4596 int offset;
4597
4598 sc = (struct bge_softc *)arg1;
4599 offset = arg2;
4600 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
4601 offsetof(bge_hostaddr, bge_addr_lo));
4602 return (sysctl_handle_int(oidp, &result, 0, req));
4603}
4604
4605#ifdef BGE_REGISTER_DEBUG
4606static int
4607bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4608{
4609 struct bge_softc *sc;
4610 uint16_t *sbdata;
4611 int error;
4612 int result;
4613 int i, j;
4614
4615 result = -1;
4616 error = sysctl_handle_int(oidp, &result, 0, req);
4617 if (error || (req->newptr == NULL))
4618 return (error);
4619
4620 if (result == 1) {
4621 sc = (struct bge_softc *)arg1;
4622
4623 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
4624 printf("Status Block:\n");
4625 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
4626 printf("%06x:", i);
4627 for (j = 0; j < 8; j++) {
4628 printf(" %04x", sbdata[i]);
4629 i += 4;
4630 }
4631 printf("\n");
4632 }
4633
4634 printf("Registers:\n");
4635 for (i = 0x800; i < 0xA00; ) {
4636 printf("%06x:", i);
4637 for (j = 0; j < 8; j++) {
4638 printf(" %08x", CSR_READ_4(sc, i));
4639 i += 4;
4640 }
4641 printf("\n");
4642 }
4643
4644 printf("Hardware Flags:\n");
4645 if (BGE_IS_575X_PLUS(sc))
4646 printf(" - 575X Plus\n");
4647 if (BGE_IS_5705_PLUS(sc))
4648 printf(" - 5705 Plus\n");
4649 if (BGE_IS_5714_FAMILY(sc))
4650 printf(" - 5714 Family\n");
4651 if (BGE_IS_5700_FAMILY(sc))
4652 printf(" - 5700 Family\n");
4653 if (sc->bge_flags & BGE_FLAG_JUMBO)
4654 printf(" - Supports Jumbo Frames\n");
4655 if (sc->bge_flags & BGE_FLAG_PCIX)
4656 printf(" - PCI-X Bus\n");
4657 if (sc->bge_flags & BGE_FLAG_PCIE)
4658 printf(" - PCI Express Bus\n");
4659 if (sc->bge_flags & BGE_FLAG_NO_3LED)
4660 printf(" - No 3 LEDs\n");
4661 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
4662 printf(" - RX Alignment Bug\n");
4663 }
4664
4665 return (error);
4666}
4667
4668static int
4669bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
4670{
4671 struct bge_softc *sc;
4672 int error;
4673 uint16_t result;
4674 uint32_t val;
4675
4676 result = -1;
4677 error = sysctl_handle_int(oidp, &result, 0, req);
4678 if (error || (req->newptr == NULL))
4679 return (error);
4680
4681 if (result < 0x8000) {
4682 sc = (struct bge_softc *)arg1;
4683 val = CSR_READ_4(sc, result);
4684 printf("reg 0x%06X = 0x%08X\n", result, val);
4685 }
4686
4687 return (error);
4688}
4689
4690static int
4691bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
4692{
4693 struct bge_softc *sc;
4694 int error;
4695 uint16_t result;
4696 uint32_t val;
4697
4698 result = -1;
4699 error = sysctl_handle_int(oidp, &result, 0, req);
4700 if (error || (req->newptr == NULL))
4701 return (error);
4702
4703 if (result < 0x8000) {
4704 sc = (struct bge_softc *)arg1;
4705 val = bge_readmem_ind(sc, result);
4706 printf("mem 0x%06X = 0x%08X\n", result, val);
4707 }
4708
4709 return (error);
4710}
4711#endif
4712
4713static int
4714bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
4715{
4716
4717 if (sc->bge_flags & BGE_FLAG_EADDR)
4718 return (1);
4719
4720#ifdef __sparc64__
4721 OF_getetheraddr(sc->bge_dev, ether_addr);
4722 return (0);
4723#endif
4724 return (1);
4725}
4726
4727static int
4728bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
4729{
4730 uint32_t mac_addr;
4731
4732 mac_addr = bge_readmem_ind(sc, 0x0c14);
4733 if ((mac_addr >> 16) == 0x484b) {
4734 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4735 ether_addr[1] = (uint8_t)mac_addr;
4736 mac_addr = bge_readmem_ind(sc, 0x0c18);
4737 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4738 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4739 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4740 ether_addr[5] = (uint8_t)mac_addr;
4741 return (0);
4742 }
4743 return (1);
4744}
4745
4746static int
4747bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
4748{
4749 int mac_offset = BGE_EE_MAC_OFFSET;
4750
4751 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4752 mac_offset = BGE_EE_MAC_OFFSET_5906;
4753
4754 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
4755 ETHER_ADDR_LEN));
4756}
4757
4758static int
4759bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4760{
4761
4762 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4763 return (1);
4764
4765 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4766 ETHER_ADDR_LEN));
4767}
4768
4769static int
4770bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4771{
4772 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4773 /* NOTE: Order is critical */
4774 bge_get_eaddr_fw,
4775 bge_get_eaddr_mem,
4776 bge_get_eaddr_nvram,
4777 bge_get_eaddr_eeprom,
4778 NULL
4779 };
4780 const bge_eaddr_fcn_t *func;
4781
4782 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4783 if ((*func)(sc, eaddr) == 0)
4784 break;
4785 }
4786 return (*func == NULL ? ENXIO : 0);
4787}
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