1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: head/sys/dev/bge/if_bge.c 88114 2001-12-18 08:03:25Z peter $
34 */
35
36/*
37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Engineer, Wind River Systems
41 */
42
43/*
44 * The Broadcom BCM5700 is based on technology originally developed by
45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
49 * frames, highly configurable RX filtering, and 16 RX and TX queues
50 * (which, along with RX filter rules, can be used for QOS applications).
51 * Other features, such as TCP segmentation, may be available as part
52 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
53 * firmware images can be stored in hardware and need not be compiled
54 * into the driver.
55 *
56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
58 *
59 * The BCM5701 is a single-chip solution incorporating both the BCM5700
60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5700
61 * does not support external SSRAM.
62 *
63 * Broadcom also produces a variation of the BCM5700 under the "Altima"
64 * brand name, which is functionally similar but lacks PCI-X support.
65 *
66 * Without external SSRAM, you can only have at most 4 TX rings,
67 * and the use of the mini RX ring is disabled. This seems to imply
68 * that these features are simply not available on the BCM5701. As a
69 * result, this driver does not implement any support for the mini RX
70 * ring.
71 */
72
73#include <sys/param.h>
74#include <sys/systm.h>
75#include <sys/sockio.h>
76#include <sys/mbuf.h>
77#include <sys/malloc.h>
78#include <sys/kernel.h>
79#include <sys/socket.h>
80#include <sys/queue.h>
81
82#include <net/if.h>
83#include <net/if_arp.h>
84#include <net/ethernet.h>
85#include <net/if_dl.h>
86#include <net/if_media.h>
87
88#include <net/bpf.h>
89
90#include <net/if_types.h>
91#include <net/if_vlan_var.h>
92
93#include <netinet/in_systm.h>
94#include <netinet/in.h>
95#include <netinet/ip.h>
96
97#include <vm/vm.h> /* for vtophys */
98#include <vm/pmap.h> /* for vtophys */
99#include <machine/clock.h> /* for DELAY */
100#include <machine/bus_memio.h>
101#include <machine/bus.h>
102#include <machine/resource.h>
103#include <sys/bus.h>
104#include <sys/rman.h>
105
106#include <dev/mii/mii.h>
107#include <dev/mii/miivar.h>
108#include <dev/mii/miidevs.h>
109#include <dev/mii/brgphyreg.h>
110
111#include <pci/pcireg.h>
112#include <pci/pcivar.h>
113
114#include <dev/bge/if_bgereg.h>
115
116#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
117
118MODULE_DEPEND(bge, miibus, 1, 1, 1);
119
120/* "controller miibus0" required. See GENERIC if you get errors here. */
121#include "miibus_if.h"
122
123#if !defined(lint)
124static const char rcsid[] =
125 "$FreeBSD: head/sys/dev/bge/if_bge.c 88114 2001-12-18 08:03:25Z peter $";
126#endif
127
128/*
129 * Various supported device vendors/types and their names. Note: the
130 * spec seems to indicate that the hardware still has Alteon's vendor
131 * ID burned into it, though it will always be overriden by the vendor
132 * ID in the EEPROM. Just to be safe, we cover all possibilities.
133 */
134
135static struct bge_type bge_devs[] = {
136 { ALT_VENDORID, ALT_DEVICEID_BCM5700,
137 "Broadcom BCM5700 Gigabit Ethernet" },
138 { ALT_VENDORID, ALT_DEVICEID_BCM5701,
139 "Broadcom BCM5701 Gigabit Ethernet" },
140 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700,
141 "Broadcom BCM5700 Gigabit Ethernet" },
142 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701,
143 "Broadcom BCM5701 Gigabit Ethernet" },
144 { SK_VENDORID, SK_DEVICEID_ALTIMA,
145 "SysKonnect Gigabit Ethernet" },
146 { 0, 0, NULL }
147};
148
149static int bge_probe __P((device_t));
150static int bge_attach __P((device_t));
151static int bge_detach __P((device_t));
152static void bge_release_resources
153 __P((struct bge_softc *));
154static void bge_txeof __P((struct bge_softc *));
155static void bge_rxeof __P((struct bge_softc *));
156
157static void bge_tick __P((void *));
158static void bge_stats_update __P((struct bge_softc *));
159static int bge_encap __P((struct bge_softc *, struct mbuf *,
160 u_int32_t *));
161
162static void bge_intr __P((void *));
163static void bge_start __P((struct ifnet *));
164static int bge_ioctl __P((struct ifnet *, u_long, caddr_t));
165static void bge_init __P((void *));
166static void bge_stop __P((struct bge_softc *));
167static void bge_watchdog __P((struct ifnet *));
168static void bge_shutdown __P((device_t));
169static int bge_ifmedia_upd __P((struct ifnet *));
170static void bge_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
171
172static u_int8_t bge_eeprom_getbyte __P((struct bge_softc *,
173 int, u_int8_t *));
174static int bge_read_eeprom __P((struct bge_softc *, caddr_t, int, int));
175
176static u_int32_t bge_crc __P((caddr_t));
177static void bge_setmulti __P((struct bge_softc *));
178
179static void bge_handle_events __P((struct bge_softc *));
180static int bge_alloc_jumbo_mem __P((struct bge_softc *));
181static void bge_free_jumbo_mem __P((struct bge_softc *));
182static void *bge_jalloc __P((struct bge_softc *));
183static void bge_jfree __P((caddr_t, void *));
184static int bge_newbuf_std __P((struct bge_softc *, int, struct mbuf *));
185static int bge_newbuf_jumbo __P((struct bge_softc *, int, struct mbuf *));
186static int bge_init_rx_ring_std __P((struct bge_softc *));
187static void bge_free_rx_ring_std __P((struct bge_softc *));
188static int bge_init_rx_ring_jumbo __P((struct bge_softc *));
189static void bge_free_rx_ring_jumbo __P((struct bge_softc *));
190static void bge_free_tx_ring __P((struct bge_softc *));
191static int bge_init_tx_ring __P((struct bge_softc *));
192
193static int bge_chipinit __P((struct bge_softc *));
194static int bge_blockinit __P((struct bge_softc *));
195
196#ifdef notdef
197static u_int8_t bge_vpd_readbyte __P((struct bge_softc *, int));
198static void bge_vpd_read_res __P((struct bge_softc *,
199 struct vpd_res *, int));
200static void bge_vpd_read __P((struct bge_softc *));
201#endif
202
203static u_int32_t bge_readmem_ind
204 __P((struct bge_softc *, int));
205static void bge_writemem_ind __P((struct bge_softc *, int, int));
206#ifdef notdef
207static u_int32_t bge_readreg_ind
208 __P((struct bge_softc *, int));
209#endif
210static void bge_writereg_ind __P((struct bge_softc *, int, int));
211
212static int bge_miibus_readreg __P((device_t, int, int));
213static int bge_miibus_writereg __P((device_t, int, int, int));
214static void bge_miibus_statchg __P((device_t));
215
216static void bge_reset __P((struct bge_softc *));
217static void bge_phy_hack __P((struct bge_softc *));
218
219static device_method_t bge_methods[] = {
220 /* Device interface */
221 DEVMETHOD(device_probe, bge_probe),
222 DEVMETHOD(device_attach, bge_attach),
223 DEVMETHOD(device_detach, bge_detach),
224 DEVMETHOD(device_shutdown, bge_shutdown),
225
226 /* bus interface */
227 DEVMETHOD(bus_print_child, bus_generic_print_child),
228 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
229
230 /* MII interface */
231 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
232 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
233 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
234
235 { 0, 0 }
236};
237
238static driver_t bge_driver = {
239 "bge",
240 bge_methods,
241 sizeof(struct bge_softc)
242};
243
244static devclass_t bge_devclass;
245
246DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
247DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
248
249static u_int32_t
250bge_readmem_ind(sc, off)
251 struct bge_softc *sc;
252 int off;
253{
254 device_t dev;
255
256 dev = sc->bge_dev;
257
258 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
259 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
260}
261
262static void
263bge_writemem_ind(sc, off, val)
264 struct bge_softc *sc;
265 int off, val;
266{
267 device_t dev;
268
269 dev = sc->bge_dev;
270
271 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
272 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
273
274 return;
275}
276
277#ifdef notdef
278static u_int32_t
279bge_readreg_ind(sc, off)
280 struct bge_softc *sc;
281 int off;
282{
283 device_t dev;
284
285 dev = sc->bge_dev;
286
287 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
288 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
289}
290#endif
291
292static void
293bge_writereg_ind(sc, off, val)
294 struct bge_softc *sc;
295 int off, val;
296{
297 device_t dev;
298
299 dev = sc->bge_dev;
300
301 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
302 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
303
304 return;
305}
306
307#ifdef notdef
308static u_int8_t
309bge_vpd_readbyte(sc, addr)
310 struct bge_softc *sc;
311 int addr;
312{
313 int i;
314 device_t dev;
315 u_int32_t val;
316
317 dev = sc->bge_dev;
318 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
319 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
320 DELAY(10);
321 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
322 break;
323 }
324
325 if (i == BGE_TIMEOUT) {
326 printf("bge%d: VPD read timed out\n", sc->bge_unit);
327 return(0);
328 }
329
330 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
331
332 return((val >> ((addr % 4) * 8)) & 0xFF);
333}
334
335static void
336bge_vpd_read_res(sc, res, addr)
337 struct bge_softc *sc;
338 struct vpd_res *res;
339 int addr;
340{
341 int i;
342 u_int8_t *ptr;
343
344 ptr = (u_int8_t *)res;
345 for (i = 0; i < sizeof(struct vpd_res); i++)
346 ptr[i] = bge_vpd_readbyte(sc, i + addr);
347
348 return;
349}
350
351static void
352bge_vpd_read(sc)
353 struct bge_softc *sc;
354{
355 int pos = 0, i;
356 struct vpd_res res;
357
358 if (sc->bge_vpd_prodname != NULL)
359 free(sc->bge_vpd_prodname, M_DEVBUF);
360 if (sc->bge_vpd_readonly != NULL)
361 free(sc->bge_vpd_readonly, M_DEVBUF);
362 sc->bge_vpd_prodname = NULL;
363 sc->bge_vpd_readonly = NULL;
364
365 bge_vpd_read_res(sc, &res, pos);
366
367 if (res.vr_id != VPD_RES_ID) {
368 printf("bge%d: bad VPD resource id: expected %x got %x\n",
369 sc->bge_unit, VPD_RES_ID, res.vr_id);
370 return;
371 }
372
373 pos += sizeof(res);
374 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
375 for (i = 0; i < res.vr_len; i++)
376 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
377 sc->bge_vpd_prodname[i] = '\0';
378 pos += i;
379
380 bge_vpd_read_res(sc, &res, pos);
381
382 if (res.vr_id != VPD_RES_READ) {
383 printf("bge%d: bad VPD resource id: expected %x got %x\n",
384 sc->bge_unit, VPD_RES_READ, res.vr_id);
385 return;
386 }
387
388 pos += sizeof(res);
389 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
390 for (i = 0; i < res.vr_len + 1; i++)
391 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
392
393 return;
394}
395#endif
396
397/*
398 * Read a byte of data stored in the EEPROM at address 'addr.' The
399 * BCM570x supports both the traditional bitbang interface and an
400 * auto access interface for reading the EEPROM. We use the auto
401 * access method.
402 */
403static u_int8_t
404bge_eeprom_getbyte(sc, addr, dest)
405 struct bge_softc *sc;
406 int addr;
407 u_int8_t *dest;
408{
409 int i;
410 u_int32_t byte = 0;
411
412 /*
413 * Enable use of auto EEPROM access so we can avoid
414 * having to use the bitbang method.
415 */
416 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
417
418 /* Reset the EEPROM, load the clock period. */
419 CSR_WRITE_4(sc, BGE_EE_ADDR,
420 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
421 DELAY(20);
422
423 /* Issue the read EEPROM command. */
424 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
425
426 /* Wait for completion */
427 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
428 DELAY(10);
429 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
430 break;
431 }
432
433 if (i == BGE_TIMEOUT) {
434 printf("bge%d: eeprom read timed out\n", sc->bge_unit);
435 return(0);
436 }
437
438 /* Get result. */
439 byte = CSR_READ_4(sc, BGE_EE_DATA);
440
441 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
442
443 return(0);
444}
445
446/*
447 * Read a sequence of bytes from the EEPROM.
448 */
449static int
450bge_read_eeprom(sc, dest, off, cnt)
451 struct bge_softc *sc;
452 caddr_t dest;
453 int off;
454 int cnt;
455{
456 int err = 0, i;
457 u_int8_t byte = 0;
458
459 for (i = 0; i < cnt; i++) {
460 err = bge_eeprom_getbyte(sc, off + i, &byte);
461 if (err)
462 break;
463 *(dest + i) = byte;
464 }
465
466 return(err ? 1 : 0);
467}
468
469static int
470bge_miibus_readreg(dev, phy, reg)
471 device_t dev;
472 int phy, reg;
473{
474 struct bge_softc *sc;
475 struct ifnet *ifp;
476 u_int32_t val;
477 int i;
478
479 sc = device_get_softc(dev);
480 ifp = &sc->arpcom.ac_if;
481
482 if (ifp->if_flags & IFF_RUNNING)
483 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
484
485 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
486 BGE_MIPHY(phy)|BGE_MIREG(reg));
487
488 for (i = 0; i < BGE_TIMEOUT; i++) {
489 val = CSR_READ_4(sc, BGE_MI_COMM);
490 if (!(val & BGE_MICOMM_BUSY))
491 break;
492 }
493
494 if (i == BGE_TIMEOUT) {
495 printf("bge%d: PHY read timed out\n", sc->bge_unit);
496 return(0);
497 }
498
499 val = CSR_READ_4(sc, BGE_MI_COMM);
500
501 if (ifp->if_flags & IFF_RUNNING)
502 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
503
504 if (val & BGE_MICOMM_READFAIL)
505 return(0);
506
507 return(val & 0xFFFF);
508}
509
510static int
511bge_miibus_writereg(dev, phy, reg, val)
512 device_t dev;
513 int phy, reg, val;
514{
515 struct bge_softc *sc;
516 int i;
517
518 sc = device_get_softc(dev);
519
520 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
521 BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
522
523 for (i = 0; i < BGE_TIMEOUT; i++) {
524 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
525 break;
526 }
527
528 if (i == BGE_TIMEOUT) {
529 printf("bge%d: PHY read timed out\n", sc->bge_unit);
530 return(0);
531 }
532
533 return(0);
534}
535
536static void
537bge_miibus_statchg(dev)
538 device_t dev;
539{
540 struct bge_softc *sc;
541 struct mii_data *mii;
542
543 sc = device_get_softc(dev);
544 mii = device_get_softc(sc->bge_miibus);
545
546 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
547 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) {
548 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
549 } else {
550 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
551 }
552
553 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
554 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
555 } else {
556 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
557 }
558
559 bge_phy_hack(sc);
560
561 return;
562}
563
564/*
565 * Handle events that have triggered interrupts.
566 */
567static void
568bge_handle_events(sc)
569 struct bge_softc *sc;
570{
571
572 return;
573}
574
575/*
576 * Memory management for jumbo frames.
577 */
578
579static int
580bge_alloc_jumbo_mem(sc)
581 struct bge_softc *sc;
582{
583 caddr_t ptr;
584 register int i;
585 struct bge_jpool_entry *entry;
586
587 /* Grab a big chunk o' storage. */
588 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF,
589 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
590
591 if (sc->bge_cdata.bge_jumbo_buf == NULL) {
592 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit);
593 return(ENOBUFS);
594 }
595
596 SLIST_INIT(&sc->bge_jfree_listhead);
597 SLIST_INIT(&sc->bge_jinuse_listhead);
598
599 /*
600 * Now divide it up into 9K pieces and save the addresses
601 * in an array.
602 */
603 ptr = sc->bge_cdata.bge_jumbo_buf;
604 for (i = 0; i < BGE_JSLOTS; i++) {
605 sc->bge_cdata.bge_jslots[i] = ptr;
606 ptr += BGE_JLEN;
607 entry = malloc(sizeof(struct bge_jpool_entry),
608 M_DEVBUF, M_NOWAIT);
609 if (entry == NULL) {
610 contigfree(sc->bge_cdata.bge_jumbo_buf,
611 BGE_JMEM, M_DEVBUF);
612 sc->bge_cdata.bge_jumbo_buf = NULL;
613 printf("bge%d: no memory for jumbo "
614 "buffer queue!\n", sc->bge_unit);
615 return(ENOBUFS);
616 }
617 entry->slot = i;
618 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
619 entry, jpool_entries);
620 }
621
622 return(0);
623}
624
625static void
626bge_free_jumbo_mem(sc)
627 struct bge_softc *sc;
628{
629 int i;
630 struct bge_jpool_entry *entry;
631
632 for (i = 0; i < BGE_JSLOTS; i++) {
633 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
634 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
635 free(entry, M_DEVBUF);
636 }
637
638 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF);
639
640 return;
641}
642
643/*
644 * Allocate a jumbo buffer.
645 */
646static void *
647bge_jalloc(sc)
648 struct bge_softc *sc;
649{
650 struct bge_jpool_entry *entry;
651
652 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
653
654 if (entry == NULL) {
655 printf("bge%d: no free jumbo buffers\n", sc->bge_unit);
656 return(NULL);
657 }
658
659 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
660 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries);
661 return(sc->bge_cdata.bge_jslots[entry->slot]);
662}
663
664/*
665 * Release a jumbo buffer.
666 */
667static void
668bge_jfree(buf, args)
669 caddr_t buf;
670 void *args;
671{
672 struct bge_jpool_entry *entry;
673 struct bge_softc *sc;
674 int i;
675
676 /* Extract the softc struct pointer. */
677 sc = (struct bge_softc *)args;
678
679 if (sc == NULL)
680 panic("bge_jfree: can't find softc pointer!");
681
682 /* calculate the slot this buffer belongs to */
683
684 i = ((vm_offset_t)buf
685 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
686
687 if ((i < 0) || (i >= BGE_JSLOTS))
688 panic("bge_jfree: asked to free buffer that we don't manage!");
689
690 entry = SLIST_FIRST(&sc->bge_jinuse_listhead);
691 if (entry == NULL)
692 panic("bge_jfree: buffer not in use!");
693 entry->slot = i;
694 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries);
695 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries);
696
697 return;
698}
699
700
701/*
702 * Intialize a standard receive ring descriptor.
703 */
704static int
705bge_newbuf_std(sc, i, m)
706 struct bge_softc *sc;
707 int i;
708 struct mbuf *m;
709{
710 struct mbuf *m_new = NULL;
711 struct bge_rx_bd *r;
712
713 if (m == NULL) {
714 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
715 if (m_new == NULL) {
716 printf("bge%d: mbuf allocation failed "
717 "-- packet dropped!\n", sc->bge_unit);
718 return(ENOBUFS);
719 }
720
721 MCLGET(m_new, M_DONTWAIT);
722 if (!(m_new->m_flags & M_EXT)) {
723 printf("bge%d: cluster allocation failed "
724 "-- packet dropped!\n", sc->bge_unit);
725 m_freem(m_new);
726 return(ENOBUFS);
727 }
728 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
729 } else {
730 m_new = m;
731 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
732 m_new->m_data = m_new->m_ext.ext_buf;
733 }
734
735 m_adj(m_new, ETHER_ALIGN);
736 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
737 r = &sc->bge_rdata->bge_rx_std_ring[i];
738 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t));
739 r->bge_flags = BGE_RXBDFLAG_END;
740 r->bge_len = m_new->m_len;
741 r->bge_idx = i;
742
743 return(0);
744}
745
746/*
747 * Initialize a jumbo receive ring descriptor. This allocates
748 * a jumbo buffer from the pool managed internally by the driver.
749 */
750static int
751bge_newbuf_jumbo(sc, i, m)
752 struct bge_softc *sc;
753 int i;
754 struct mbuf *m;
755{
756 struct mbuf *m_new = NULL;
757 struct bge_rx_bd *r;
758
759 if (m == NULL) {
760 caddr_t *buf = NULL;
761
762 /* Allocate the mbuf. */
763 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
764 if (m_new == NULL) {
765 printf("bge%d: mbuf allocation failed "
766 "-- packet dropped!\n", sc->bge_unit);
767 return(ENOBUFS);
768 }
769
770 /* Allocate the jumbo buffer */
771 buf = bge_jalloc(sc);
772 if (buf == NULL) {
773 m_freem(m_new);
774 printf("bge%d: jumbo allocation failed "
775 "-- packet dropped!\n", sc->bge_unit);
776 return(ENOBUFS);
777 }
778
779 /* Attach the buffer to the mbuf. */
780 m_new->m_data = (void *) buf;
781 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN;
782 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree,
783 (struct bge_softc *)sc, 0, EXT_NET_DRV);
784 } else {
785 m_new = m;
786 m_new->m_data = m_new->m_ext.ext_buf;
787 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
788 }
789
790 m_adj(m_new, ETHER_ALIGN);
791 /* Set up the descriptor. */
792 r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
793 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
794 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t));
795 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
796 r->bge_len = m_new->m_len;
797 r->bge_idx = i;
798
799 return(0);
800}
801
802/*
803 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
804 * that's 1MB or memory, which is a lot. For now, we fill only the first
805 * 256 ring entries and hope that our CPU is fast enough to keep up with
806 * the NIC.
807 */
808static int
809bge_init_rx_ring_std(sc)
810 struct bge_softc *sc;
811{
812 int i;
813
814 for (i = 0; i < BGE_SSLOTS; i++) {
815 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
816 return(ENOBUFS);
817 };
818
819 sc->bge_std = i - 1;
820 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
821
822 return(0);
823}
824
825static void
826bge_free_rx_ring_std(sc)
827 struct bge_softc *sc;
828{
829 int i;
830
831 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
832 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
833 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
834 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
835 }
836 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i],
837 sizeof(struct bge_rx_bd));
838 }
839
840 return;
841}
842
843static int
844bge_init_rx_ring_jumbo(sc)
845 struct bge_softc *sc;
846{
847 int i;
848 struct bge_rcb *rcb;
849 struct bge_rcb_opaque *rcbo;
850
851 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
852 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
853 return(ENOBUFS);
854 };
855
856 sc->bge_jumbo = i - 1;
857
858 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
859 rcbo = (struct bge_rcb_opaque *)rcb;
860 rcb->bge_flags = 0;
861 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
862
863 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
864
865 return(0);
866}
867
868static void
869bge_free_rx_ring_jumbo(sc)
870 struct bge_softc *sc;
871{
872 int i;
873
874 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
875 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
876 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
877 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
878 }
879 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i],
880 sizeof(struct bge_rx_bd));
881 }
882
883 return;
884}
885
886static void
887bge_free_tx_ring(sc)
888 struct bge_softc *sc;
889{
890 int i;
891
892 if (sc->bge_rdata->bge_tx_ring == NULL)
893 return;
894
895 for (i = 0; i < BGE_TX_RING_CNT; i++) {
896 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
897 m_freem(sc->bge_cdata.bge_tx_chain[i]);
898 sc->bge_cdata.bge_tx_chain[i] = NULL;
899 }
900 bzero((char *)&sc->bge_rdata->bge_tx_ring[i],
901 sizeof(struct bge_tx_bd));
902 }
903
904 return;
905}
906
907static int
908bge_init_tx_ring(sc)
909 struct bge_softc *sc;
910{
911 sc->bge_txcnt = 0;
912 sc->bge_tx_saved_considx = 0;
913 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
914 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
915
916 return(0);
917}
918
919#define BGE_POLY 0xEDB88320
920
921static u_int32_t
922bge_crc(addr)
923 caddr_t addr;
924{
925 u_int32_t idx, bit, data, crc;
926
927 /* Compute CRC for the address value. */
928 crc = 0xFFFFFFFF; /* initial value */
929
930 for (idx = 0; idx < 6; idx++) {
931 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
932 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0);
933 }
934
935 return(crc & 0x7F);
936}
937
938static void
939bge_setmulti(sc)
940 struct bge_softc *sc;
941{
942 struct ifnet *ifp;
943 struct ifmultiaddr *ifma;
944 u_int32_t hashes[4] = { 0, 0, 0, 0 };
945 int h, i;
946
947 ifp = &sc->arpcom.ac_if;
948
949 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
950 for (i = 0; i < 4; i++)
951 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
952 return;
953 }
954
955 /* First, zot all the existing filters. */
956 for (i = 0; i < 4; i++)
957 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
958
959 /* Now program new ones. */
960 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
961 if (ifma->ifma_addr->sa_family != AF_LINK)
962 continue;
963 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
964 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
965 }
966
967 for (i = 0; i < 4; i++)
968 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
969
970 return;
971}
972
973/*
974 * Do endian, PCI and DMA initialization. Also check the on-board ROM
975 * self-test results.
976 */
977static int
978bge_chipinit(sc)
979 struct bge_softc *sc;
980{
981 u_int32_t cachesize;
982 int i;
983
984 /* Set endianness before we access any non-PCI registers. */
985#if BYTE_ORDER == BIG_ENDIAN
986 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
987 BGE_BIGENDIAN_INIT, 4);
988#else
989 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
990 BGE_LITTLEENDIAN_INIT, 4);
991#endif
992
993 /*
994 * Check the 'ROM failed' bit on the RX CPU to see if
995 * self-tests passed.
996 */
997 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
998 printf("bge%d: RX CPU self-diagnostics failed!\n",
999 sc->bge_unit);
1000 return(ENODEV);
1001 }
1002
1003 /* Clear the MAC control register */
1004 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1005
1006 /*
1007 * Clear the MAC statistics block in the NIC's
1008 * internal memory.
1009 */
1010 for (i = BGE_STATS_BLOCK;
1011 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t))
1012 BGE_MEMWIN_WRITE(sc, i, 0);
1013
1014 for (i = BGE_STATUS_BLOCK;
1015 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
1016 BGE_MEMWIN_WRITE(sc, i, 0);
1017
1018 /* Set up the PCI DMA control register. */
1019 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1020 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F, 4);
1021
1022 /*
1023 * Set up general mode register.
1024 */
1025 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1026 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1027 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1028 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM|
1029 BGE_MODECTL_RX_NO_PHDR_CSUM);
1030
1031 /* Get cache line size. */
1032 cachesize = pci_read_config(sc->bge_dev, BGE_PCI_CACHESZ, 1);
1033
1034 /*
1035 * Avoid violating PCI spec on certain chip revs.
1036 */
1037 if (pci_read_config(sc->bge_dev, BGE_PCI_CMD, 4) & PCIM_CMD_MWIEN) {
1038 switch(cachesize) {
1039 case 1:
1040 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1041 BGE_PCI_WRITE_BNDRY_16BYTES, 4);
1042 break;
1043 case 2:
1044 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1045 BGE_PCI_WRITE_BNDRY_32BYTES, 4);
1046 break;
1047 case 4:
1048 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1049 BGE_PCI_WRITE_BNDRY_64BYTES, 4);
1050 break;
1051 case 8:
1052 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1053 BGE_PCI_WRITE_BNDRY_128BYTES, 4);
1054 break;
1055 case 16:
1056 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1057 BGE_PCI_WRITE_BNDRY_256BYTES, 4);
1058 break;
1059 case 32:
1060 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1061 BGE_PCI_WRITE_BNDRY_512BYTES, 4);
1062 break;
1063 case 64:
1064 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1065 BGE_PCI_WRITE_BNDRY_1024BYTES, 4);
1066 break;
1067 default:
1068 /* Disable PCI memory write and invalidate. */
1069 if (bootverbose)
1070 printf("bge%d: cache line size %d not "
1071 "supported; disabling PCI MWI\n",
1072 sc->bge_unit, cachesize);
1073 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1074 PCIM_CMD_MWIEN, 4);
1075 break;
1076 }
1077 }
1078
1079#ifdef __brokenalpha__
1080 /*
1081 * Must insure that we do not cross an 8K (bytes) boundary
1082 * for DMA reads. Our highest limit is 1K bytes. This is a
1083 * restriction on some ALPHA platforms with early revision
1084 * 21174 PCI chipsets, such as the AlphaPC 164lx
1085 */
1086 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4);
1087#endif
1088
1089 /* Set the timer prescaler (always 66Mhz) */
1090 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1091
1092 return(0);
1093}
1094
1095static int
1096bge_blockinit(sc)
1097 struct bge_softc *sc;
1098{
1099 struct bge_rcb *rcb;
1100 struct bge_rcb_opaque *rcbo;
1101 int i;
1102
1103 /*
1104 * Initialize the memory window pointer register so that
1105 * we can access the first 32K of internal NIC RAM. This will
1106 * allow us to set up the TX send ring RCBs and the RX return
1107 * ring RCBs, plus other things which live in NIC memory.
1108 */
1109 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1110
1111 /* Configure mbuf memory pool */
1112 if (sc->bge_extram) {
1113 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM);
1114 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1115 } else {
1116 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1117 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1118 }
1119
1120 /* Configure DMA resource pool */
1121 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS);
1122 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1123
1124 /* Configure mbuf pool watermarks */
1125 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24);
1126 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24);
1127 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48);
1128
1129 /* Configure DMA resource watermarks */
1130 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1131 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1132
1133 /* Enable buffer manager */
1134 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1135 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1136
1137 /* Poll for buffer manager start indication */
1138 for (i = 0; i < BGE_TIMEOUT; i++) {
1139 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1140 break;
1141 DELAY(10);
1142 }
1143
1144 if (i == BGE_TIMEOUT) {
1145 printf("bge%d: buffer manager failed to start\n",
1146 sc->bge_unit);
1147 return(ENXIO);
1148 }
1149
1150 /* Enable flow-through queues */
1151 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1152 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1153
1154 /* Wait until queue initialization is complete */
1155 for (i = 0; i < BGE_TIMEOUT; i++) {
1156 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1157 break;
1158 DELAY(10);
1159 }
1160
1161 if (i == BGE_TIMEOUT) {
1162 printf("bge%d: flow-through queue init failed\n",
1163 sc->bge_unit);
1164 return(ENXIO);
1165 }
1166
1167 /* Initialize the standard RX ring control block */
1168 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
1169 BGE_HOSTADDR(rcb->bge_hostaddr) =
1170 vtophys(&sc->bge_rdata->bge_rx_std_ring);
1171 rcb->bge_max_len = BGE_MAX_FRAMELEN;
1172 if (sc->bge_extram)
1173 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1174 else
1175 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1176 rcb->bge_flags = 0;
1177 rcbo = (struct bge_rcb_opaque *)rcb;
1178 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0);
1179 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1);
1180 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
1181 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3);
1182
1183 /*
1184 * Initialize the jumbo RX ring control block
1185 * We set the 'ring disabled' bit in the flags
1186 * field until we're actually ready to start
1187 * using this ring (i.e. once we set the MTU
1188 * high enough to require it).
1189 */
1190 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1191 BGE_HOSTADDR(rcb->bge_hostaddr) =
1192 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring);
1193 rcb->bge_max_len = BGE_MAX_FRAMELEN;
1194 if (sc->bge_extram)
1195 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1196 else
1197 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1198 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
1199
1200 rcbo = (struct bge_rcb_opaque *)rcb;
1201 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0);
1202 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1);
1203 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
1204 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3);
1205
1206 /* Set up dummy disabled mini ring RCB */
1207 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1208 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
1209 rcbo = (struct bge_rcb_opaque *)rcb;
1210 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
1211
1212 /*
1213 * Set the BD ring replentish thresholds. The recommended
1214 * values are 1/8th the number of descriptors allocated to
1215 * each ring.
1216 */
1217 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1218 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1219
1220 /*
1221 * Disable all unused send rings by setting the 'ring disabled'
1222 * bit in the flags field of all the TX send ring control blocks.
1223 * These are located in NIC memory.
1224 */
1225 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1226 BGE_SEND_RING_RCB);
1227 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1228 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
1229 rcb->bge_max_len = 0;
1230 rcb->bge_nicaddr = 0;
1231 rcb++;
1232 }
1233
1234 /* Configure TX RCB 0 (we use only the first ring) */
1235 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1236 BGE_SEND_RING_RCB);
1237 rcb->bge_hostaddr.bge_addr_hi = 0;
1238 BGE_HOSTADDR(rcb->bge_hostaddr) =
1239 vtophys(&sc->bge_rdata->bge_tx_ring);
1240 rcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
1241 rcb->bge_max_len = BGE_TX_RING_CNT;
1242 rcb->bge_flags = 0;
1243
1244 /* Disable all unused RX return rings */
1245 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1246 BGE_RX_RETURN_RING_RCB);
1247 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1248 rcb->bge_hostaddr.bge_addr_hi = 0;
1249 rcb->bge_hostaddr.bge_addr_lo = 0;
1250 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
1251 rcb->bge_max_len = BGE_RETURN_RING_CNT;
1252 rcb->bge_nicaddr = 0;
1253 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1254 (i * (sizeof(u_int64_t))), 0);
1255 rcb++;
1256 }
1257
1258 /* Initialize RX ring indexes */
1259 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1260 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1261 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1262
1263 /*
1264 * Set up RX return ring 0
1265 * Note that the NIC address for RX return rings is 0x00000000.
1266 * The return rings live entirely within the host, so the
1267 * nicaddr field in the RCB isn't used.
1268 */
1269 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1270 BGE_RX_RETURN_RING_RCB);
1271 rcb->bge_hostaddr.bge_addr_hi = 0;
1272 BGE_HOSTADDR(rcb->bge_hostaddr) =
1273 vtophys(&sc->bge_rdata->bge_rx_return_ring);
1274 rcb->bge_nicaddr = 0x00000000;
1275 rcb->bge_max_len = BGE_RETURN_RING_CNT;
1276 rcb->bge_flags = 0;
1277
1278 /* Set random backoff seed for TX */
1279 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1280 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1281 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1282 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1283 BGE_TX_BACKOFF_SEED_MASK);
1284
1285 /* Set inter-packet gap */
1286 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1287
1288 /*
1289 * Specify which ring to use for packets that don't match
1290 * any RX rules.
1291 */
1292 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1293
1294 /*
1295 * Configure number of RX lists. One interrupt distribution
1296 * list, sixteen active lists, one bad frames class.
1297 */
1298 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1299
1300 /* Inialize RX list placement stats mask. */
1301 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1302 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1303
1304 /* Disable host coalescing until we get it set up */
1305 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1306
1307 /* Poll to make sure it's shut down. */
1308 for (i = 0; i < BGE_TIMEOUT; i++) {
1309 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1310 break;
1311 DELAY(10);
1312 }
1313
1314 if (i == BGE_TIMEOUT) {
1315 printf("bge%d: host coalescing engine failed to idle\n",
1316 sc->bge_unit);
1317 return(ENXIO);
1318 }
1319
1320 /* Set up host coalescing defaults */
1321 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1322 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1323 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1324 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1325 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1326 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1327 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1328 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1329 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1330
1331 /* Set up address of statistics block */
1332 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1333 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
1334 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1335 vtophys(&sc->bge_rdata->bge_info.bge_stats));
1336
1337 /* Set up address of status block */
1338 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1339 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0);
1340 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1341 vtophys(&sc->bge_rdata->bge_status_block));
1342 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1343 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1344
1345 /* Turn on host coalescing state machine */
1346 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1347
1348 /* Turn on RX BD completion state machine and enable attentions */
1349 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1350 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1351
1352 /* Turn on RX list placement state machine */
1353 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1354
1355 /* Turn on RX list selector state machine. */
1356 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1357
1358 /* Turn on DMA, clear stats */
1359 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1360 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1361 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1362 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1363 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1364
1365 /* Set misc. local control, enable interrupts on attentions */
1366 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1367
1368#ifdef notdef
1369 /* Assert GPIO pins for PHY reset */
1370 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1371 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1372 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1373 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1374#endif
1375
1376 /* Turn on DMA completion state machine */
1377 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1378
1379 /* Turn on write DMA state machine */
1380 CSR_WRITE_4(sc, BGE_WDMA_MODE,
1381 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1382
1383 /* Turn on read DMA state machine */
1384 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1385 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1386
1387 /* Turn on RX data completion state machine */
1388 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1389
1390 /* Turn on RX BD initiator state machine */
1391 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1392
1393 /* Turn on RX data and RX BD initiator state machine */
1394 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1395
1396 /* Turn on Mbuf cluster free state machine */
1397 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1398
1399 /* Turn on send BD completion state machine */
1400 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1401
1402 /* Turn on send data completion state machine */
1403 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1404
1405 /* Turn on send data initiator state machine */
1406 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1407
1408 /* Turn on send BD initiator state machine */
1409 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1410
1411 /* Turn on send BD selector state machine */
1412 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1413
1414 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1415 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1416 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1417
1418 /* init LED register */
1419 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000);
1420
1421 /* ack/clear link change events */
1422 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1423 BGE_MACSTAT_CFG_CHANGED);
1424 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1425
1426 /* Enable PHY auto polling (for MII/GMII only) */
1427 if (sc->bge_tbi) {
1428 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1429 } else
1430 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1431
1432 /* Enable link state change attentions. */
1433 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1434
1435 return(0);
1436}
1437
1438/*
1439 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1440 * against our list and return its name if we find a match. Note
1441 * that since the Broadcom controller contains VPD support, we
1442 * can get the device name string from the controller itself instead
1443 * of the compiled-in string. This is a little slow, but it guarantees
1444 * we'll always announce the right product name.
1445 */
1446static int
1447bge_probe(dev)
1448 device_t dev;
1449{
1450 struct bge_type *t;
1451 struct bge_softc *sc;
1452
1453 t = bge_devs;
1454
1455 sc = device_get_softc(dev);
1456 bzero(sc, sizeof(struct bge_softc));
1457 sc->bge_unit = device_get_unit(dev);
1458 sc->bge_dev = dev;
1459
1460 while(t->bge_name != NULL) {
1461 if ((pci_get_vendor(dev) == t->bge_vid) &&
1462 (pci_get_device(dev) == t->bge_did)) {
1463#ifdef notdef
1464 bge_vpd_read(sc);
1465 device_set_desc(dev, sc->bge_vpd_prodname);
1466#endif
1467 device_set_desc(dev, t->bge_name);
1468 return(0);
1469 }
1470 t++;
1471 }
1472
1473 return(ENXIO);
1474}
1475
1476static int
1477bge_attach(dev)
1478 device_t dev;
1479{
1480 int s;
1481 u_int32_t command;
1482 struct ifnet *ifp;
1483 struct bge_softc *sc;
1484 int unit, error = 0, rid;
1485
1486 s = splimp();
1487
1488 sc = device_get_softc(dev);
1489 unit = device_get_unit(dev);
1490 sc->bge_dev = dev;
1491 sc->bge_unit = unit;
1492
1493 /*
1494 * Map control/status registers.
1495 */
1496 pci_enable_busmaster(dev);
1497 pci_enable_io(dev, SYS_RES_MEMORY);
1498 command = pci_read_config(dev, PCIR_COMMAND, 4);
1499
1500 if (!(command & PCIM_CMD_MEMEN)) {
1501 printf("bge%d: failed to enable memory mapping!\n", unit);
1502 error = ENXIO;
1503 goto fail;
1504 }
1505
1506 rid = BGE_PCI_BAR0;
1507 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1508 0, ~0, 1, RF_ACTIVE);
1509
1510 if (sc->bge_res == NULL) {
1511 printf ("bge%d: couldn't map memory\n", unit);
1512 error = ENXIO;
1513 goto fail;
1514 }
1515
1516 sc->bge_btag = rman_get_bustag(sc->bge_res);
1517 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1518 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
1519
1520 /*
1521 * XXX FIXME: rman_get_virtual() on the alpha is currently
1522 * broken and returns a physical address instead of a kernel
1523 * virtual address. Consequently, we need to do a little
1524 * extra mangling of the vhandle on the alpha. This should
1525 * eventually be fixed! The whole idea here is to get rid
1526 * of platform dependencies.
1527 */
1528#ifdef __alpha__
1529 if (pci_cvt_to_bwx(sc->bge_vhandle))
1530 sc->bge_vhandle = pci_cvt_to_bwx(sc->bge_vhandle);
1531 else
1532 sc->bge_vhandle = pci_cvt_to_dense(sc->bge_vhandle);
1533 sc->bge_vhandle = ALPHA_PHYS_TO_K0SEG(sc->bge_vhandle);
1534#endif
1535
1536 /* Allocate interrupt */
1537 rid = 0;
1538
1539 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1540 RF_SHAREABLE | RF_ACTIVE);
1541
1542 if (sc->bge_irq == NULL) {
1543 printf("bge%d: couldn't map interrupt\n", unit);
1544 error = ENXIO;
1545 goto fail;
1546 }
1547
1548 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET,
1549 bge_intr, sc, &sc->bge_intrhand);
1550
1551 if (error) {
1552 bge_release_resources(sc);
1553 printf("bge%d: couldn't set up irq\n", unit);
1554 goto fail;
1555 }
1556
1557 sc->bge_unit = unit;
1558
1559 /* Try to reset the chip. */
1560 bge_reset(sc);
1561
1562 if (bge_chipinit(sc)) {
1563 printf("bge%d: chip initialization failed\n", sc->bge_unit);
1564 bge_release_resources(sc);
1565 error = ENXIO;
1566 goto fail;
1567 }
1568
1569 /*
1570 * Get station address from the EEPROM.
1571 */
1572 if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1573 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1574 printf("bge%d: failed to read station address\n", unit);
1575 bge_release_resources(sc);
1576 error = ENXIO;
1577 goto fail;
1578 }
1579
1580 /*
1581 * A Broadcom chip was detected. Inform the world.
1582 */
1583 printf("bge%d: Ethernet address: %6D\n", unit,
1584 sc->arpcom.ac_enaddr, ":");
1585
1586 /* Allocate the general information block and ring buffers. */
1587 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF,
1588 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1589
1590 if (sc->bge_rdata == NULL) {
1591 bge_release_resources(sc);
1592 error = ENXIO;
1593 printf("bge%d: no memory for list buffers!\n", sc->bge_unit);
1594 goto fail;
1595 }
1596
1597 bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
1598
1599 /* Try to allocate memory for jumbo buffers. */
1600 if (bge_alloc_jumbo_mem(sc)) {
1601 printf("bge%d: jumbo buffer allocation "
1602 "failed\n", sc->bge_unit);
1603 bge_release_resources(sc);
1604 error = ENXIO;
1605 goto fail;
1606 }
1607
1608 /* Set default tuneable values. */
1609 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1610 sc->bge_rx_coal_ticks = 150;
1611 sc->bge_tx_coal_ticks = 150;
1612 sc->bge_rx_max_coal_bds = 64;
1613 sc->bge_tx_max_coal_bds = 128;
1614
1615 /* Set up ifnet structure */
1616 ifp = &sc->arpcom.ac_if;
1617 ifp->if_softc = sc;
1618 ifp->if_unit = sc->bge_unit;
1619 ifp->if_name = "bge";
1620 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1621 ifp->if_ioctl = bge_ioctl;
1622 ifp->if_output = ether_output;
1623 ifp->if_start = bge_start;
1624 ifp->if_watchdog = bge_watchdog;
1625 ifp->if_init = bge_init;
1626 ifp->if_mtu = ETHERMTU;
1627 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1;
1628 ifp->if_hwassist = BGE_CSUM_FEATURES;
1629 ifp->if_capabilities = IFCAP_HWCSUM;
1630 ifp->if_capenable = ifp->if_capabilities;
1631
1632 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1633 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41)
1634 sc->bge_tbi = 1;
1635
1636 if (sc->bge_tbi) {
1637 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1638 bge_ifmedia_upd, bge_ifmedia_sts);
1639 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1640 ifmedia_add(&sc->bge_ifmedia,
1641 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1642 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1643 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1644 } else {
1645 /*
1646 * Do transceiver setup.
1647 */
1648 if (mii_phy_probe(dev, &sc->bge_miibus,
1649 bge_ifmedia_upd, bge_ifmedia_sts)) {
1650 printf("bge%d: MII without any PHY!\n", sc->bge_unit);
1651 bge_release_resources(sc);
1652 bge_free_jumbo_mem(sc);
1653 error = ENXIO;
1654 goto fail;
1655 }
1656 }
1657
1658 /*
1659 * Call MI attach routine.
1660 */
1661 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1662 callout_handle_init(&sc->bge_stat_ch);
1663
1664fail:
1665 splx(s);
1666
1667 return(error);
1668}
1669
1670static int
1671bge_detach(dev)
1672 device_t dev;
1673{
1674 struct bge_softc *sc;
1675 struct ifnet *ifp;
1676 int s;
1677
1678 s = splimp();
1679
1680 sc = device_get_softc(dev);
1681 ifp = &sc->arpcom.ac_if;
1682
1683 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1684 bge_stop(sc);
1685 bge_reset(sc);
1686
1687 if (sc->bge_tbi) {
1688 ifmedia_removeall(&sc->bge_ifmedia);
1689 } else {
1690 bus_generic_detach(dev);
1691 device_delete_child(dev, sc->bge_miibus);
1692 }
1693
1694 bge_release_resources(sc);
1695 bge_free_jumbo_mem(sc);
1696
1697 splx(s);
1698
1699 return(0);
1700}
1701
1702static void
1703bge_release_resources(sc)
1704 struct bge_softc *sc;
1705{
1706 device_t dev;
1707
1708 dev = sc->bge_dev;
1709
1710 if (sc->bge_vpd_prodname != NULL)
1711 free(sc->bge_vpd_prodname, M_DEVBUF);
1712
1713 if (sc->bge_vpd_readonly != NULL)
1714 free(sc->bge_vpd_readonly, M_DEVBUF);
1715
1716 if (sc->bge_intrhand != NULL)
1717 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1718
1719 if (sc->bge_irq != NULL)
1720 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1721
1722 if (sc->bge_res != NULL)
1723 bus_release_resource(dev, SYS_RES_MEMORY,
1724 BGE_PCI_BAR0, sc->bge_res);
1725
1726 if (sc->bge_rdata != NULL)
1727 contigfree(sc->bge_rdata,
1728 sizeof(struct bge_ring_data), M_DEVBUF);
1729
1730 return;
1731}
1732
1733static void
1734bge_reset(sc)
1735 struct bge_softc *sc;
1736{
1737 device_t dev;
1738 u_int32_t cachesize, command, pcistate;
1739 int i, val = 0;
1740
1741 dev = sc->bge_dev;
1742
1743 /* Save some important PCI state. */
1744 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
1745 command = pci_read_config(dev, BGE_PCI_CMD, 4);
1746 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
1747
1748 pci_write_config(dev, BGE_PCI_MISC_CTL,
1749 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1750 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1751
1752 /* Issue global reset */
1753 bge_writereg_ind(sc, BGE_MISC_CFG,
1754 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1));
1755
1756 DELAY(1000);
1757
1758 /* Reset some of the PCI state that got zapped by reset */
1759 pci_write_config(dev, BGE_PCI_MISC_CTL,
1760 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1761 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1762 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
1763 pci_write_config(dev, BGE_PCI_CMD, command, 4);
1764 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
1765
1766 /*
1767 * Prevent PXE restart: write a magic number to the
1768 * general communications memory at 0xB50.
1769 */
1770 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1771 /*
1772 * Poll the value location we just wrote until
1773 * we see the 1's complement of the magic number.
1774 * This indicates that the firmware initialization
1775 * is complete.
1776 */
1777 for (i = 0; i < BGE_TIMEOUT; i++) {
1778 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
1779 if (val == ~BGE_MAGIC_NUMBER)
1780 break;
1781 DELAY(10);
1782 }
1783
1784 if (i == BGE_TIMEOUT) {
1785 printf("bge%d: firmware handshake timed out\n", sc->bge_unit);
1786 return;
1787 }
1788
1789 /*
1790 * XXX Wait for the value of the PCISTATE register to
1791 * return to its original pre-reset state. This is a
1792 * fairly good indicator of reset completion. If we don't
1793 * wait for the reset to fully complete, trying to read
1794 * from the device's non-PCI registers may yield garbage
1795 * results.
1796 */
1797 for (i = 0; i < BGE_TIMEOUT; i++) {
1798 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
1799 break;
1800 DELAY(10);
1801 }
1802
1803 /* Enable memory arbiter. */
1804 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
1805
1806 /* Fix up byte swapping */
1807 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
1808 BGE_MODECTL_BYTESWAP_DATA);
1809
1810 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1811
1812 DELAY(10000);
1813
1814 return;
1815}
1816
1817/*
1818 * Frame reception handling. This is called if there's a frame
1819 * on the receive return list.
1820 *
1821 * Note: we have to be able to handle two possibilities here:
1822 * 1) the frame is from the jumbo recieve ring
1823 * 2) the frame is from the standard receive ring
1824 */
1825
1826static void
1827bge_rxeof(sc)
1828 struct bge_softc *sc;
1829{
1830 struct ifnet *ifp;
1831 int stdcnt = 0, jumbocnt = 0;
1832
1833 ifp = &sc->arpcom.ac_if;
1834
1835 while(sc->bge_rx_saved_considx !=
1836 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
1837 struct bge_rx_bd *cur_rx;
1838 u_int32_t rxidx;
1839 struct ether_header *eh;
1840 struct mbuf *m = NULL;
1841 u_int16_t vlan_tag = 0;
1842 int have_tag = 0;
1843
1844 cur_rx =
1845 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx];
1846
1847 rxidx = cur_rx->bge_idx;
1848 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT);
1849
1850 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
1851 have_tag = 1;
1852 vlan_tag = cur_rx->bge_vlan_tag;
1853 }
1854
1855 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
1856 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1857 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
1858 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
1859 jumbocnt++;
1860 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1861 ifp->if_ierrors++;
1862 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1863 continue;
1864 }
1865 if (bge_newbuf_jumbo(sc,
1866 sc->bge_jumbo, NULL) == ENOBUFS) {
1867 ifp->if_ierrors++;
1868 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1869 continue;
1870 }
1871 } else {
1872 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1873 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
1874 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
1875 stdcnt++;
1876 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1877 ifp->if_ierrors++;
1878 bge_newbuf_std(sc, sc->bge_std, m);
1879 continue;
1880 }
1881 if (bge_newbuf_std(sc, sc->bge_std,
1882 NULL) == ENOBUFS) {
1883 ifp->if_ierrors++;
1884 bge_newbuf_std(sc, sc->bge_std, m);
1885 continue;
1886 }
1887 }
1888
1889 ifp->if_ipackets++;
1890 eh = mtod(m, struct ether_header *);
1891 m->m_pkthdr.len = m->m_len = cur_rx->bge_len;
1892 m->m_pkthdr.rcvif = ifp;
1893
1894 /* Remove header from mbuf and pass it on. */
1895 m_adj(m, sizeof(struct ether_header));
1896
1897#if 0 /* currently broken for some packets, possibly related to TCP options */
1898 if (ifp->if_hwassist) {
1899 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1900 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
1901 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1902 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
1903 m->m_pkthdr.csum_data =
1904 cur_rx->bge_tcp_udp_csum;
1905 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1906 }
1907 }
1908#endif
1909
1910 /*
1911 * If we received a packet with a vlan tag, pass it
1912 * to vlan_input() instead of ether_input().
1913 */
1914 if (have_tag) {
1915 VLAN_INPUT_TAG(eh, m, vlan_tag);
1916 have_tag = vlan_tag = 0;
1917 continue;
1918 }
1919
1920 ether_input(ifp, eh, m);
1921 }
1922
1923 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
1924 if (stdcnt)
1925 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1926 if (jumbocnt)
1927 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1928
1929 return;
1930}
1931
1932static void
1933bge_txeof(sc)
1934 struct bge_softc *sc;
1935{
1936 struct bge_tx_bd *cur_tx = NULL;
1937 struct ifnet *ifp;
1938
1939 ifp = &sc->arpcom.ac_if;
1940
1941 /*
1942 * Go through our tx ring and free mbufs for those
1943 * frames that have been sent.
1944 */
1945 while (sc->bge_tx_saved_considx !=
1946 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
1947 u_int32_t idx = 0;
1948
1949 idx = sc->bge_tx_saved_considx;
1950 cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
1951 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
1952 ifp->if_opackets++;
1953 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
1954 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
1955 sc->bge_cdata.bge_tx_chain[idx] = NULL;
1956 }
1957 sc->bge_txcnt--;
1958 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
1959 ifp->if_timer = 0;
1960 }
1961
1962 if (cur_tx != NULL)
1963 ifp->if_flags &= ~IFF_OACTIVE;
1964
1965 return;
1966}
1967
1968static void
1969bge_intr(xsc)
1970 void *xsc;
1971{
1972 struct bge_softc *sc;
1973 struct ifnet *ifp;
1974
1975 sc = xsc;
1976 ifp = &sc->arpcom.ac_if;
1977
1978#ifdef notdef
1979 /* Avoid this for now -- checking this register is expensive. */
1980 /* Make sure this is really our interrupt. */
1981 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
1982 return;
1983#endif
1984 /* Ack interrupt and stop others from occuring. */
1985 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
1986
1987 /* Process link state changes. */
1988 if (sc->bge_rdata->bge_status_block.bge_status &
1989 BGE_STATFLAG_LINKSTATE_CHANGED) {
1990 sc->bge_link = 0;
1991 untimeout(bge_tick, sc, sc->bge_stat_ch);
1992 bge_tick(sc);
1993 /* ack the event to clear/reset it */
1994 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1995 BGE_MACSTAT_CFG_CHANGED);
1996 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1997 }
1998
1999 if (ifp->if_flags & IFF_RUNNING) {
2000 /* Check RX return ring producer/consumer */
2001 bge_rxeof(sc);
2002
2003 /* Check TX ring producer/consumer */
2004 bge_txeof(sc);
2005 }
2006
2007 bge_handle_events(sc);
2008
2009 /* Re-enable interrupts. */
2010 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2011
2012 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
2013 bge_start(ifp);
2014
2015 return;
2016}
2017
2018static void
2019bge_tick(xsc)
2020 void *xsc;
2021{
2022 struct bge_softc *sc;
2023 struct mii_data *mii = NULL;
2024 struct ifmedia *ifm = NULL;
2025 struct ifnet *ifp;
2026 int s;
2027
2028 sc = xsc;
2029 ifp = &sc->arpcom.ac_if;
2030
2031 s = splimp();
2032
2033 bge_stats_update(sc);
2034 sc->bge_stat_ch = timeout(bge_tick, sc, hz);
2035 if (sc->bge_link)
2036 return;
2037
2038 if (sc->bge_tbi) {
2039 ifm = &sc->bge_ifmedia;
2040 if (CSR_READ_4(sc, BGE_MAC_STS) &
2041 BGE_MACSTAT_TBI_PCS_SYNCHED) {
2042 sc->bge_link++;
2043 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
2044 printf("bge%d: gigabit link up\n", sc->bge_unit);
2045 if (ifp->if_snd.ifq_head != NULL)
2046 bge_start(ifp);
2047 }
2048 return;
2049 }
2050
2051 mii = device_get_softc(sc->bge_miibus);
2052 mii_tick(mii);
2053
2054 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE &&
2055 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2056 sc->bge_link++;
2057 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX ||
2058 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
2059 printf("bge%d: gigabit link up\n",
2060 sc->bge_unit);
2061 if (ifp->if_snd.ifq_head != NULL)
2062 bge_start(ifp);
2063 }
2064
2065 splx(s);
2066
2067 return;
2068}
2069
2070static void
2071bge_stats_update(sc)
2072 struct bge_softc *sc;
2073{
2074 struct ifnet *ifp;
2075 struct bge_stats *stats;
2076
2077 ifp = &sc->arpcom.ac_if;
2078
2079 stats = (struct bge_stats *)(sc->bge_vhandle +
2080 BGE_MEMWIN_START + BGE_STATS_BLOCK);
2081
2082 ifp->if_collisions +=
2083 (stats->dot3StatsSingleCollisionFrames.bge_addr_lo +
2084 stats->dot3StatsMultipleCollisionFrames.bge_addr_lo +
2085 stats->dot3StatsExcessiveCollisions.bge_addr_lo +
2086 stats->dot3StatsLateCollisions.bge_addr_lo) -
2087 ifp->if_collisions;
2088
2089#ifdef notdef
2090 ifp->if_collisions +=
2091 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2092 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2093 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2094 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2095 ifp->if_collisions;
2096#endif
2097
2098 return;
2099}
2100
2101/*
2102 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2103 * pointers to descriptors.
2104 */
2105static int
2106bge_encap(sc, m_head, txidx)
2107 struct bge_softc *sc;
2108 struct mbuf *m_head;
2109 u_int32_t *txidx;
2110{
2111 struct bge_tx_bd *f = NULL;
2112 struct mbuf *m;
2113 u_int32_t frag, cur, cnt = 0;
2114 u_int16_t csum_flags = 0;
2115 struct ifvlan *ifv = NULL;
2116
2117 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2118 m_head->m_pkthdr.rcvif != NULL &&
2119 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2120 ifv = m_head->m_pkthdr.rcvif->if_softc;
2121
2122 m = m_head;
2123 cur = frag = *txidx;
2124
2125 if (m_head->m_pkthdr.csum_flags) {
2126 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2127 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2128 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2129 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2130 if (m_head->m_flags & M_LASTFRAG)
2131 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2132 else if (m_head->m_flags & M_FRAG)
2133 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2134 }
2135
2136 /*
2137 * Start packing the mbufs in this chain into
2138 * the fragment pointers. Stop when we run out
2139 * of fragments or hit the end of the mbuf chain.
2140 */
2141 for (m = m_head; m != NULL; m = m->m_next) {
2142 if (m->m_len != 0) {
2143 f = &sc->bge_rdata->bge_tx_ring[frag];
2144 if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
2145 break;
2146 BGE_HOSTADDR(f->bge_addr) =
2147 vtophys(mtod(m, vm_offset_t));
2148 f->bge_len = m->m_len;
2149 f->bge_flags = csum_flags;
2150 if (ifv != NULL) {
2151 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2152 f->bge_vlan_tag = ifv->ifv_tag;
2153 } else {
2154 f->bge_vlan_tag = 0;
2155 }
2156 /*
2157 * Sanity check: avoid coming within 16 descriptors
2158 * of the end of the ring.
2159 */
2160 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
2161 return(ENOBUFS);
2162 cur = frag;
2163 BGE_INC(frag, BGE_TX_RING_CNT);
2164 cnt++;
2165 }
2166 }
2167
2168 if (m != NULL)
2169 return(ENOBUFS);
2170
2171 if (frag == sc->bge_tx_saved_considx)
2172 return(ENOBUFS);
2173
2174 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
2175 sc->bge_cdata.bge_tx_chain[cur] = m_head;
2176 sc->bge_txcnt += cnt;
2177
2178 *txidx = frag;
2179
2180 return(0);
2181}
2182
2183/*
2184 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2185 * to the mbuf data regions directly in the transmit descriptors.
2186 */
2187static void
2188bge_start(ifp)
2189 struct ifnet *ifp;
2190{
2191 struct bge_softc *sc;
2192 struct mbuf *m_head = NULL;
2193 u_int32_t prodidx = 0;
2194
2195 sc = ifp->if_softc;
2196
2197 if (!sc->bge_link && ifp->if_snd.ifq_len < 10)
2198 return;
2199
2200 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
2201
2202 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2203 IF_DEQUEUE(&ifp->if_snd, m_head);
2204 if (m_head == NULL)
2205 break;
2206
2207 /*
2208 * XXX
2209 * safety overkill. If this is a fragmented packet chain
2210 * with delayed TCP/UDP checksums, then only encapsulate
2211 * it if we have enough descriptors to handle the entire
2212 * chain at once.
2213 * (paranoia -- may not actually be needed)
2214 */
2215 if (m_head->m_flags & M_FIRSTFRAG &&
2216 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2217 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2218 m_head->m_pkthdr.csum_data + 16) {
2219 IF_PREPEND(&ifp->if_snd, m_head);
2220 ifp->if_flags |= IFF_OACTIVE;
2221 break;
2222 }
2223 }
2224
2225 /*
2226 * Pack the data into the transmit ring. If we
2227 * don't have room, set the OACTIVE flag and wait
2228 * for the NIC to drain the ring.
2229 */
2230 if (bge_encap(sc, m_head, &prodidx)) {
2231 IF_PREPEND(&ifp->if_snd, m_head);
2232 ifp->if_flags |= IFF_OACTIVE;
2233 break;
2234 }
2235
2236 /*
2237 * If there's a BPF listener, bounce a copy of this frame
2238 * to him.
2239 */
2240 if (ifp->if_bpf)
2241 bpf_mtap(ifp, m_head);
2242 }
2243
2244 /* Transmit */
2245 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2246
2247 /*
2248 * Set a timeout in case the chip goes out to lunch.
2249 */
2250 ifp->if_timer = 5;
2251
2252 return;
2253}
2254
2255/*
2256 * If we have a BCM5400 or BCM5401 PHY, we need to properly
2257 * program its internal DSP. Failing to do this can result in
2258 * massive packet loss at 1Gb speeds.
2259 */
2260static void
2261bge_phy_hack(sc)
2262 struct bge_softc *sc;
2263{
2264 struct bge_bcom_hack bhack[] = {
2265 { BRGPHY_MII_AUXCTL, 0x4C20 },
2266 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
2267 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
2268 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
2269 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
2270 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
2271 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
2272 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
2273 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
2274 { BRGPHY_MII_DSP_ADDR_REG, 0x201F },
2275 { BRGPHY_MII_DSP_RW_PORT, 0x0A20 },
2276 { 0, 0 } };
2277 u_int16_t vid, did;
2278 int i;
2279
2280 vid = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR1);
2281 did = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR2);
2282
2283 if (MII_OUI(vid, did) == MII_OUI_xxBROADCOM &&
2284 (MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5400 ||
2285 MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5401)) {
2286 i = 0;
2287 while(bhack[i].reg) {
2288 bge_miibus_writereg(sc->bge_dev, 1, bhack[i].reg,
2289 bhack[i].val);
2290 i++;
2291 }
2292 }
2293
2294 return;
2295}
2296
2297static void
2298bge_init(xsc)
2299 void *xsc;
2300{
2301 struct bge_softc *sc = xsc;
2302 struct ifnet *ifp;
2303 u_int16_t *m;
2304 int s;
2305
2306 s = splimp();
2307
2308 ifp = &sc->arpcom.ac_if;
2309
2310 if (ifp->if_flags & IFF_RUNNING)
2311 return;
2312
2313 /* Cancel pending I/O and flush buffers. */
2314 bge_stop(sc);
2315 bge_reset(sc);
2316 bge_chipinit(sc);
2317
2318 /*
2319 * Init the various state machines, ring
2320 * control blocks and firmware.
2321 */
2322 if (bge_blockinit(sc)) {
2323 printf("bge%d: initialization failure\n", sc->bge_unit);
2324 splx(s);
2325 return;
2326 }
2327
2328 ifp = &sc->arpcom.ac_if;
2329
2330 /* Specify MTU. */
2331 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2332 ETHER_HDR_LEN + ETHER_CRC_LEN);
2333
2334 /* Load our MAC address. */
2335 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2336 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2337 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2338
2339 /* Enable or disable promiscuous mode as needed. */
2340 if (ifp->if_flags & IFF_PROMISC) {
2341 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2342 } else {
2343 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2344 }
2345
2346 /* Program multicast filter. */
2347 bge_setmulti(sc);
2348
2349 /* Init RX ring. */
2350 bge_init_rx_ring_std(sc);
2351
2352 /* Init jumbo RX ring. */
2353 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2354 bge_init_rx_ring_jumbo(sc);
2355
2356 /* Init our RX return ring index */
2357 sc->bge_rx_saved_considx = 0;
2358
2359 /* Init TX ring. */
2360 bge_init_tx_ring(sc);
2361
2362 /* Turn on transmitter */
2363 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2364
2365 /* Turn on receiver */
2366 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2367
2368 /* Tell firmware we're alive. */
2369 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2370
2371 /* Enable host interrupts. */
2372 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2373 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2374 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2375
2376 bge_ifmedia_upd(ifp);
2377
2378 ifp->if_flags |= IFF_RUNNING;
2379 ifp->if_flags &= ~IFF_OACTIVE;
2380
2381 splx(s);
2382
2383 sc->bge_stat_ch = timeout(bge_tick, sc, hz);
2384
2385 return;
2386}
2387
2388/*
2389 * Set media options.
2390 */
2391static int
2392bge_ifmedia_upd(ifp)
2393 struct ifnet *ifp;
2394{
2395 struct bge_softc *sc;
2396 struct mii_data *mii;
2397 struct ifmedia *ifm;
2398
2399 sc = ifp->if_softc;
2400 ifm = &sc->bge_ifmedia;
2401
2402 /* If this is a 1000baseX NIC, enable the TBI port. */
2403 if (sc->bge_tbi) {
2404 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2405 return(EINVAL);
2406 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2407 case IFM_AUTO:
2408 break;
2409 case IFM_1000_SX:
2410 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2411 BGE_CLRBIT(sc, BGE_MAC_MODE,
2412 BGE_MACMODE_HALF_DUPLEX);
2413 } else {
2414 BGE_SETBIT(sc, BGE_MAC_MODE,
2415 BGE_MACMODE_HALF_DUPLEX);
2416 }
2417 break;
2418 default:
2419 return(EINVAL);
2420 }
2421 return(0);
2422 }
2423
2424 mii = device_get_softc(sc->bge_miibus);
2425 sc->bge_link = 0;
2426 if (mii->mii_instance) {
2427 struct mii_softc *miisc;
2428 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
2429 miisc = LIST_NEXT(miisc, mii_list))
2430 mii_phy_reset(miisc);
2431 }
2432 bge_phy_hack(sc);
2433 mii_mediachg(mii);
2434
2435 return(0);
2436}
2437
2438/*
2439 * Report current media status.
2440 */
2441static void
2442bge_ifmedia_sts(ifp, ifmr)
2443 struct ifnet *ifp;
2444 struct ifmediareq *ifmr;
2445{
2446 struct bge_softc *sc;
2447 struct mii_data *mii;
2448
2449 sc = ifp->if_softc;
2450
2451 if (sc->bge_tbi) {
2452 ifmr->ifm_status = IFM_AVALID;
2453 ifmr->ifm_active = IFM_ETHER;
2454 if (CSR_READ_4(sc, BGE_MAC_STS) &
2455 BGE_MACSTAT_TBI_PCS_SYNCHED)
2456 ifmr->ifm_status |= IFM_ACTIVE;
2457 ifmr->ifm_active |= IFM_1000_SX;
2458 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2459 ifmr->ifm_active |= IFM_HDX;
2460 else
2461 ifmr->ifm_active |= IFM_FDX;
2462 return;
2463 }
2464
2465 mii = device_get_softc(sc->bge_miibus);
2466 mii_pollstat(mii);
2467 ifmr->ifm_active = mii->mii_media_active;
2468 ifmr->ifm_status = mii->mii_media_status;
2469
2470 return;
2471}
2472
2473static int
2474bge_ioctl(ifp, command, data)
2475 struct ifnet *ifp;
2476 u_long command;
2477 caddr_t data;
2478{
2479 struct bge_softc *sc = ifp->if_softc;
2480 struct ifreq *ifr = (struct ifreq *) data;
2481 int s, mask, error = 0;
2482 struct mii_data *mii;
2483
2484 s = splimp();
2485
2486 switch(command) {
2487 case SIOCSIFADDR:
2488 case SIOCGIFADDR:
2489 error = ether_ioctl(ifp, command, data);
2490 break;
2491 case SIOCSIFMTU:
2492 if (ifr->ifr_mtu > BGE_JUMBO_MTU)
2493 error = EINVAL;
2494 else {
2495 ifp->if_mtu = ifr->ifr_mtu;
2496 ifp->if_flags &= ~IFF_RUNNING;
2497 bge_init(sc);
2498 }
2499 break;
2500 case SIOCSIFFLAGS:
2501 if (ifp->if_flags & IFF_UP) {
2502 /*
2503 * If only the state of the PROMISC flag changed,
2504 * then just use the 'set promisc mode' command
2505 * instead of reinitializing the entire NIC. Doing
2506 * a full re-init means reloading the firmware and
2507 * waiting for it to start up, which may take a
2508 * second or two.
2509 */
2510 if (ifp->if_flags & IFF_RUNNING &&
2511 ifp->if_flags & IFF_PROMISC &&
2512 !(sc->bge_if_flags & IFF_PROMISC)) {
2513 BGE_SETBIT(sc, BGE_RX_MODE,
2514 BGE_RXMODE_RX_PROMISC);
2515 } else if (ifp->if_flags & IFF_RUNNING &&
2516 !(ifp->if_flags & IFF_PROMISC) &&
2517 sc->bge_if_flags & IFF_PROMISC) {
2518 BGE_CLRBIT(sc, BGE_RX_MODE,
2519 BGE_RXMODE_RX_PROMISC);
2520 } else
2521 bge_init(sc);
2522 } else {
2523 if (ifp->if_flags & IFF_RUNNING) {
2524 bge_stop(sc);
2525 }
2526 }
2527 sc->bge_if_flags = ifp->if_flags;
2528 error = 0;
2529 break;
2530 case SIOCADDMULTI:
2531 case SIOCDELMULTI:
2532 if (ifp->if_flags & IFF_RUNNING) {
2533 bge_setmulti(sc);
2534 error = 0;
2535 }
2536 break;
2537 case SIOCSIFMEDIA:
2538 case SIOCGIFMEDIA:
2539 if (sc->bge_tbi) {
2540 error = ifmedia_ioctl(ifp, ifr,
2541 &sc->bge_ifmedia, command);
2542 } else {
2543 mii = device_get_softc(sc->bge_miibus);
2544 error = ifmedia_ioctl(ifp, ifr,
2545 &mii->mii_media, command);
2546 }
2547 break;
2548 case SIOCSIFCAP:
2549 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2550 if (mask & IFCAP_HWCSUM) {
2551 if (IFCAP_HWCSUM & ifp->if_capenable)
2552 ifp->if_capenable &= ~IFCAP_HWCSUM;
2553 else
2554 ifp->if_capenable |= IFCAP_HWCSUM;
2555 }
2556 error = 0;
2557 break;
2558 default:
2559 error = EINVAL;
2560 break;
2561 }
2562
2563 (void)splx(s);
2564
2565 return(error);
2566}
2567
2568static void
2569bge_watchdog(ifp)
2570 struct ifnet *ifp;
2571{
2572 struct bge_softc *sc;
2573
2574 sc = ifp->if_softc;
2575
2576 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit);
2577
2578 ifp->if_flags &= ~IFF_RUNNING;
2579 bge_init(sc);
2580
2581 ifp->if_oerrors++;
2582
2583 return;
2584}
2585
2586/*
2587 * Stop the adapter and free any mbufs allocated to the
2588 * RX and TX lists.
2589 */
2590static void
2591bge_stop(sc)
2592 struct bge_softc *sc;
2593{
2594 struct ifnet *ifp;
2595 struct ifmedia_entry *ifm;
2596 struct mii_data *mii = NULL;
2597 int mtmp, itmp;
2598
2599 ifp = &sc->arpcom.ac_if;
2600
2601 if (!sc->bge_tbi)
2602 mii = device_get_softc(sc->bge_miibus);
2603
2604 untimeout(bge_tick, sc, sc->bge_stat_ch);
2605
2606 /*
2607 * Disable all of the receiver blocks
2608 */
2609 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2610 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2611 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2612 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2613 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
2614 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2615 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
2616
2617 /*
2618 * Disable all of the transmit blocks
2619 */
2620 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2621 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2622 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2623 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
2624 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
2625 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2626 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2627
2628 /*
2629 * Shut down all of the memory managers and related
2630 * state machines.
2631 */
2632 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
2633 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
2634 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2635 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2636 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2637 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
2638 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2639
2640 /* Disable host interrupts. */
2641 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2642 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2643
2644 /*
2645 * Tell firmware we're shutting down.
2646 */
2647 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2648
2649 /* Free the RX lists. */
2650 bge_free_rx_ring_std(sc);
2651
2652 /* Free jumbo RX list. */
2653 bge_free_rx_ring_jumbo(sc);
2654
2655 /* Free TX buffers. */
2656 bge_free_tx_ring(sc);
2657
2658 /*
2659 * Isolate/power down the PHY, but leave the media selection
2660 * unchanged so that things will be put back to normal when
2661 * we bring the interface back up.
2662 */
2663 if (!sc->bge_tbi) {
2664 itmp = ifp->if_flags;
2665 ifp->if_flags |= IFF_UP;
2666 ifm = mii->mii_media.ifm_cur;
2667 mtmp = ifm->ifm_media;
2668 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2669 mii_mediachg(mii);
2670 ifm->ifm_media = mtmp;
2671 ifp->if_flags = itmp;
2672 }
2673
2674 sc->bge_link = 0;
2675
2676 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
2677
2678 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2679
2680 return;
2681}
2682
2683/*
2684 * Stop all chip I/O so that the kernel's probe routines don't
2685 * get confused by errant DMAs when rebooting.
2686 */
2687static void
2688bge_shutdown(dev)
2689 device_t dev;
2690{
2691 struct bge_softc *sc;
2692
2693 sc = device_get_softc(dev);
2694
2695 bge_stop(sc);
2696 bge_reset(sc);
2697
2698 return;
2699}