1.\" Copyright (c) 1998, Nicolas Souchu
2.\" All rights reserved.
3.\"
4.\" Redistribution and use in source and binary forms, with or without
5.\" modification, are permitted provided that the following conditions
6.\" are met:
7.\" 1. Redistributions of source code must retain the above copyright
8.\" notice, this list of conditions and the following disclaimer.
9.\" 2. Redistributions in binary form must reproduce the above copyright
10.\" notice, this list of conditions and the following disclaimer in the
11.\" documentation and/or other materials provided with the distribution.
12.\"
13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23.\" SUCH DAMAGE.
24.\"
25.\" $Id$
26.\"
27.Dd August 6, 1998
28.Dt IICBUS 4
29.Os FreeBSD
30.Sh NAME
31.Nm iicbus
32.Nd
33I2C bus system
34.Sh SYNOPSIS
35.Cd "controller iicbus0"
36.Cd "controller iicbb0"
37.Pp
38.Cd "device iic0 at iicbus?"
39.Cd "device ic0 at iicbus?"
40.Cd "device iicsmb0 at iicbus?"
41.Sh DESCRIPTION
42The
43.Em iicbus
44system provides a uniform, modular and architecture-independent
45system for the implementation of drivers to control various I2C devices
46and to utilize different I2C controllers.
47.Sh I2C
48I2C is an acronym for Inter Integrated Circuit bus. The I2C bus was developed
49in the early 1980's by Philips semiconductors. It's purpose was to provide an
50easy way to connect a CPU to peripheral chips in a TV-set.
51.Pp
52The BUS physically consists of 2 active wires and a ground connection.
53The active wires, SDA and SCL, are both bidirectional. Where SDA is the
54Serial DAta line and SCL is the Serial CLock line.
55
56Every component hooked up to the bus has its own unique address whether it
57is a CPU, LCD driver, memory, or complex function chip. Each of these chips
58can act as a receiver and/or transmitter depending on it's functionality.
59Obviously an LCD driver is only a receiver, while a memory or I/O chip can
60both be transmitter and receiver. Furthermore there may be one or
61more BUS MASTER's.
62
63The BUS MASTER is the chip issuing the commands on the BUS. In the I2C protocol
64specification it is stated that the IC that initiates a data transfer on the
65bus is considered the BUS MASTER. At that time all the others are regarded to
66as the BUS SLAVEs. As mentioned before, the IC bus is a Multi-MASTER BUS.
67This means that more than one IC capable of initiating data transfer can be
68connected to it.
69.Sh DEVICES
70Some I2C device drivers are available:
71.Pp
72.Bl -column "Device drivers" -compact
73.It Em Devices Ta Em Description
74.It Sy iic Ta "general i/o operation"
75.It Sy ic Ta "network IP interface"
76.It Sy iicsmb Ta "I2C to SMB software bridge"
77.El
78.Sh INTERFACES
79The I2C protocol may be implemented by hardware or software. Software
80interfaces rely on very simple hardware, usually two lines
81twiddled by 2 registers. Hardware interfaces are more intelligent and receive
828-bit characters they write to the bus according to the I2C protocol.
83
84I2C interfaces may act on the bus as slave devices, allowing spontaneous
85bidirectional communications, thanks to the mutli-master capabilities of the
86I2C protocol.
87
88Some I2C interfaces are available:
89.Pp
90.Bl -column "Interface drivers" -compact
91.It Em Interface Ta Em Description
92.It Sy pcf Ta "Philips PCF8584 master/slave interface"
93.It Sy iicbb Ta "generic bit-banging master-only driver"
94.It Sy lpbb Ta "parallel port specific bit-banging interface"
95.It Sy bktr Ta "Brooktree848 video chipset, hardware and software master-only interface"
96.El
97.Sh SEE ALSO
98.Xr pcf 4 ,
99.Xr iicbb 4 ,
100.Xr lpbb 4
101.Sh HISTORY
102The
103.Nm
104manual page first appeared in
105.Fx 3.0 .
106.Sh AUTHOR
107This
108manual page was written by
109.An Nicolas Souchu .
2.\" All rights reserved.
3.\"
4.\" Redistribution and use in source and binary forms, with or without
5.\" modification, are permitted provided that the following conditions
6.\" are met:
7.\" 1. Redistributions of source code must retain the above copyright
8.\" notice, this list of conditions and the following disclaimer.
9.\" 2. Redistributions in binary form must reproduce the above copyright
10.\" notice, this list of conditions and the following disclaimer in the
11.\" documentation and/or other materials provided with the distribution.
12.\"
13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23.\" SUCH DAMAGE.
24.\"
25.\" $Id$
26.\"
27.Dd August 6, 1998
28.Dt IICBUS 4
29.Os FreeBSD
30.Sh NAME
31.Nm iicbus
32.Nd
33I2C bus system
34.Sh SYNOPSIS
35.Cd "controller iicbus0"
36.Cd "controller iicbb0"
37.Pp
38.Cd "device iic0 at iicbus?"
39.Cd "device ic0 at iicbus?"
40.Cd "device iicsmb0 at iicbus?"
41.Sh DESCRIPTION
42The
43.Em iicbus
44system provides a uniform, modular and architecture-independent
45system for the implementation of drivers to control various I2C devices
46and to utilize different I2C controllers.
47.Sh I2C
48I2C is an acronym for Inter Integrated Circuit bus. The I2C bus was developed
49in the early 1980's by Philips semiconductors. It's purpose was to provide an
50easy way to connect a CPU to peripheral chips in a TV-set.
51.Pp
52The BUS physically consists of 2 active wires and a ground connection.
53The active wires, SDA and SCL, are both bidirectional. Where SDA is the
54Serial DAta line and SCL is the Serial CLock line.
55
56Every component hooked up to the bus has its own unique address whether it
57is a CPU, LCD driver, memory, or complex function chip. Each of these chips
58can act as a receiver and/or transmitter depending on it's functionality.
59Obviously an LCD driver is only a receiver, while a memory or I/O chip can
60both be transmitter and receiver. Furthermore there may be one or
61more BUS MASTER's.
62
63The BUS MASTER is the chip issuing the commands on the BUS. In the I2C protocol
64specification it is stated that the IC that initiates a data transfer on the
65bus is considered the BUS MASTER. At that time all the others are regarded to
66as the BUS SLAVEs. As mentioned before, the IC bus is a Multi-MASTER BUS.
67This means that more than one IC capable of initiating data transfer can be
68connected to it.
69.Sh DEVICES
70Some I2C device drivers are available:
71.Pp
72.Bl -column "Device drivers" -compact
73.It Em Devices Ta Em Description
74.It Sy iic Ta "general i/o operation"
75.It Sy ic Ta "network IP interface"
76.It Sy iicsmb Ta "I2C to SMB software bridge"
77.El
78.Sh INTERFACES
79The I2C protocol may be implemented by hardware or software. Software
80interfaces rely on very simple hardware, usually two lines
81twiddled by 2 registers. Hardware interfaces are more intelligent and receive
828-bit characters they write to the bus according to the I2C protocol.
83
84I2C interfaces may act on the bus as slave devices, allowing spontaneous
85bidirectional communications, thanks to the mutli-master capabilities of the
86I2C protocol.
87
88Some I2C interfaces are available:
89.Pp
90.Bl -column "Interface drivers" -compact
91.It Em Interface Ta Em Description
92.It Sy pcf Ta "Philips PCF8584 master/slave interface"
93.It Sy iicbb Ta "generic bit-banging master-only driver"
94.It Sy lpbb Ta "parallel port specific bit-banging interface"
95.It Sy bktr Ta "Brooktree848 video chipset, hardware and software master-only interface"
96.El
97.Sh SEE ALSO
98.Xr pcf 4 ,
99.Xr iicbb 4 ,
100.Xr lpbb 4
101.Sh HISTORY
102The
103.Nm
104manual page first appeared in
105.Fx 3.0 .
106.Sh AUTHOR
107This
108manual page was written by
109.An Nicolas Souchu .