| sb_asm.S (205363) | sb_asm.S (205675) |
|---|---|
| 1/*- 2 * Copyright (c) 2009 Neelkanth Natu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2009 Neelkanth Natu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/mips/sibyte/sb_asm.S 205363 2010-03-20 05:21:14Z neel $ | 26 * $FreeBSD: head/sys/mips/sibyte/sb_asm.S 205675 2010-03-26 07:15:27Z neel $ |
| 27 */ 28 29#include <machine/asm.h> 30#include <machine/cpuregs.h> | 27 */ 28 29#include <machine/asm.h> 30#include <machine/cpuregs.h> |
| 31#include <machine/endian.h> | |
| 32 | 31 |
| 33/* 34 * We compile a 32-bit kernel to run on the SB-1 processor which is a 64-bit 35 * processor. It has some registers that must be accessed using 64-bit load 36 * and store instructions. 37 * 38 * So we have to resort to assembly because the compiler does not emit the 39 * 'ld' and 'sd' instructions since it thinks that it is compiling for a 40 * 32-bit mips processor. 41 */ 42 | |
| 43.set mips64 44.set noat 45.set noreorder 46 | 32.set mips64 33.set noat 34.set noreorder 35 |
| 47/* 48 * Parameters: uint32_t ptr 49 * Return value: *(uint64_t *)ptr 50 */ 51LEAF(sb_load64) 52 ld v1, 0(a0) /* result = *(uint64_t *)ptr */ 53 move v0, v1 54#if _BYTE_ORDER == _BIG_ENDIAN 55 dsll32 v1, v1, 0 56 dsra32 v1, v1, 0 /* v1 = lower_uint32(result) */ 57 jr ra 58 dsra32 v0, v0, 0 /* v0 = upper_uint32(result) */ 59#else 60 dsll32 v0, v0, 0 61 dsra32 v0, v0, 0 /* v0 = lower_uint32(result) */ 62 jr ra 63 dsra32 v1, v1, 0 /* v1 = upper_uint32(result) */ 64#endif 65END(sb_load64) 66 67/* 68 * Parameters: uint32_t ptr, uint64_t val 69 * Return value: void 70 */ 71LEAF(sb_store64) 72#if _BYTE_ORDER == _BIG_ENDIAN 73 dsll32 a2, a2, 0 /* a2 = upper_uint32(val) */ 74 dsll32 a3, a3, 0 /* a3 = lower_uint32(val) */ 75 dsrl32 a3, a3, 0 76#else 77 dsll32 a3, a3, 0 /* a3 = upper_uint32(val) */ 78 dsll32 a2, a2, 0 /* a2 = lower_uint32(val) */ 79 dsrl32 a2, a2, 0 80#endif 81 or t0, a2, a3 82 jr ra 83 sd t0, 0(a0) 84END(sb_store64) 85 | |
| 86#ifdef SMP 87/* 88 * This function must be implemented in assembly because it is called early 89 * in AP boot without a valid stack. 90 * 91 * This cpu number is available in bits 25 to 27 of the coprocessor 0 PRID 92 * register. This is not documented in the BCM1250 user manual but can be 93 * gleaned from the CFE source code - see sb1250_altcpu.S 94 */ 95LEAF(platform_processor_id) 96 mfc0 v0, MIPS_COP_0_PRID 97 srl v0, v0, 25 98 jr ra 99 and v0, v0, 7 100END(platform_processor_id) 101#endif /* SMP */ | 36#ifdef SMP 37/* 38 * This function must be implemented in assembly because it is called early 39 * in AP boot without a valid stack. 40 * 41 * This cpu number is available in bits 25 to 27 of the coprocessor 0 PRID 42 * register. This is not documented in the BCM1250 user manual but can be 43 * gleaned from the CFE source code - see sb1250_altcpu.S 44 */ 45LEAF(platform_processor_id) 46 mfc0 v0, MIPS_COP_0_PRID 47 srl v0, v0, 25 48 jr ra 49 and v0, v0, 7 50END(platform_processor_id) 51#endif /* SMP */ |