1/*- 2 * Copyright (c) 1998,1999 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * |
28 * $FreeBSD: head/sys/dev/ata/ata-all.h 52067 1999-10-09 19:57:13Z sos $ |
29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0x00 /* data register */ 33#define ATA_ERROR 0x01 /* (R) error register */ |
34#define ATA_E_ABORT 0x04 /* command aborted */ 35 |
36#define ATA_FEATURE 0x01 /* (W) feature register */ 37#define ATA_F_DMA 0x01 /* enable DMA */ 38#define ATA_F_OVL 0x02 /* enable overlap */ 39 40#define ATA_COUNT 0x02 /* (W) sector count */ 41#define ATA_IREASON 0x02 /* (R) interrupt reason */ 42#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 43#define ATA_I_IN 0x02 /* read (1) | write (0) */ --- 23 unchanged lines hidden (view full) --- 67#define ATA_C_FEA_SETXFER 0x03 /* set transfer mode */ 68 69#define ATA_STATUS 0x07 /* status register */ 70#define ATA_S_ERROR 0x01 /* error */ 71#define ATA_S_INDEX 0x02 /* index */ 72#define ATA_S_CORR 0x04 /* data corrected */ 73#define ATA_S_DRQ 0x08 /* data request */ 74#define ATA_S_DSC 0x10 /* drive seek completed */ |
75#define ATA_S_SERVICE 0x10 /* drive needs service */ |
76#define ATA_S_DWF 0x20 /* drive write fault */ |
77#define ATA_S_DMA 0x20 /* DMA ready */ 78#define ATA_S_READY 0x40 /* drive ready */ 79#define ATA_S_BUSY 0x80 /* busy */ |
80 81#define ATA_ALTPORT 0x206 /* alternate Status register */ 82#define ATA_A_IDS 0x02 /* disable interrupts */ 83#define ATA_A_RESET 0x04 /* RESET controller */ 84#define ATA_A_4BIT 0x08 /* 4 head bits */ 85 86/* misc defines */ 87#define ATA_MASTER 0x00 --- 13 unchanged lines hidden (view full) --- 101 102#define ATA_BMSTAT_PORT 0x02 103#define ATA_BMSTAT_ACTIVE 0x01 104#define ATA_BMSTAT_ERROR 0x02 105#define ATA_BMSTAT_INTERRUPT 0x04 106#define ATA_BMSTAT_MASK 0x07 107#define ATA_BMSTAT_DMA_MASTER 0x20 108#define ATA_BMSTAT_DMA_SLAVE 0x40 |
109#define ATA_BMSTAT_DMA_SIMPLEX 0x80 |
110 111#define ATA_BMDTP_PORT 0x04 112 113/* structure for holding DMA address data */ 114struct ata_dmaentry { 115 u_int32_t base; 116 u_int32_t count; 117}; 118 119/* ATA device DMA access modes */ 120#define ATA_WDMA2 0x22 121#define ATA_UDMA2 0x42 |
122#define ATA_UDMA3 0x43 |
123#define ATA_UDMA4 0x44 124 125/* structure describing an ATA device */ 126struct ata_softc { 127 int32_t unit; /* unit on this controller */ 128 int32_t lun; /* logical unit # */ 129 struct device *dev; /* device handle */ 130 int32_t ioaddr; /* port addr */ 131 int32_t altioaddr; /* alternate port addr */ 132 int32_t bmaddr; /* bus master DMA port */ 133 void *dev_softc[2]; /* ptr to devices softc's */ 134 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */ 135 int32_t mode[2]; /* transfer mode for devices */ 136#define ATA_MODE_PIO 0x00 |
137#define ATA_MODE_WDMA2 0x01 138#define ATA_MODE_UDMA2 0x02 139#define ATA_MODE_UDMA3 0x04 140#define ATA_MODE_UDMA4 0x08 |
141 142 int32_t flags; /* controller flags */ |
143#define ATA_DMA_ACTIVE 0x01 144#define ATA_ATAPI_DMA_RO 0x02 |
145 146 int32_t devices; /* what is present */ 147#define ATA_ATA_MASTER 0x01 148#define ATA_ATA_SLAVE 0x02 149#define ATA_ATAPI_MASTER 0x04 150#define ATA_ATAPI_SLAVE 0x08 151 152 u_int8_t status; /* last controller status */ 153 u_int8_t error; /* last controller error */ 154 int32_t active; /* active processing request */ 155#define ATA_IDLE 0x0 156#define ATA_IMMEDIATE 0x0 157#define ATA_WAIT_INTR 0x1 158#define ATA_IGNORE_INTR 0x2 159#define ATA_ACTIVE_ATA 0x3 160#define ATA_ACTIVE_ATAPI 0x4 |
161#define ATA_REINITING 0x5 |
162 163 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */ 164 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */ 165 void *running; /* currently running request */ 166#if NAPM > 0 167 struct apmhook resume_hook; /* hook for apm */ 168#endif 169 170}; 171 |
172/* array to hold all ata softc's */ |
173extern struct ata_softc *atadevices[]; |
174#define MAXATA 16 |
175 176/* public prototypes */ 177void ata_start(struct ata_softc *); 178void ata_reset(struct ata_softc *, int32_t *); 179int32_t ata_reinit(struct ata_softc *); 180int32_t ata_wait(struct ata_softc *, int32_t, u_int8_t); 181int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t); 182int32_t ata_dmainit(struct ata_softc *, int32_t, int32_t, int32_t, int32_t); 183int32_t ata_dmasetup(struct ata_softc *, int32_t, int8_t *, int32_t, int32_t); |
184void ata_dmastart(struct ata_softc *); 185int32_t ata_dmastatus(struct ata_softc *); 186int32_t ata_dmadone(struct ata_softc *); |
187int8_t *ata_mode2str(int32_t); 188void bswap(int8_t *, int32_t); 189void btrim(int8_t *, int32_t); 190void bpack(int8_t *, int8_t *, int32_t); |